JP2007249134A - Electro-optical device and electronic apparatus provided with the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent the generation of image defects such as ghosts in an electro-optical device. <P>SOLUTION: The electro-optical device is provided with: an enable circuit 101b arranged near to one side of a TFT array substrate 10 along the array direction of a plurality of data lines 6a rather than a shift register 101a in a peripheral area on the TFT array substrate 10; a plurality of enable signal terminals 102e1 to 102e4 arrayed along the direction intersecting with the one-side; and a plurality of enable signal lines respectively having portions wired so as to be extended in the one-side direction, electrically connected to respective enable signal terminals 102e1 to 102e4 and capable of supplying enable signals of a plurality of series to the enable circuit 101b. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a technical field of an electro-optical device such as a liquid crystal device, and an electronic apparatus such as a liquid crystal projector including the electro-optical device.

  In this type of electro-optical device, a plurality of data lines and a plurality of scanning lines are provided so as to intersect each other in a pixel region on a substrate, and a pixel portion is formed corresponding to the intersection of the data lines and the scanning lines. Further, as disclosed in Patent Document 1, a data line driving circuit and a sampling circuit for driving each data line are provided in a peripheral region located around the pixel region on the substrate.

  More specifically, the data line driving circuit includes an enable circuit that shapes each pulse width of the transfer signal sequentially output from the shift register based on each pulse width of the plurality of series of enable signals. It is. The sampling circuit samples the image signal in the data line driving circuit according to the sampling circuit driving signal that is sequentially generated and output based on the transfer signal after the pulse width is shaped in the enable circuit. Supply to multiple data lines.

  Based on such a signal processing order, in the electro-optical device, a shift register, an enable circuit, and a sampling circuit are arranged along one side along the arrangement direction of the plurality of data lines in the pixel region as viewed in plan on the substrate. Each is arranged, and in this order, arranged so as to approach the one side.

  Here, a plurality of series of enable signals are supplied to the enable circuit via a plurality of enable signal lines from the external circuit connection terminals arranged along one side of the substrate along the one side in the peripheral region on the substrate. The The plurality of enable signal lines are routed around the shift register from the external circuit connection terminal to the enable circuit.

Japanese Patent No. 3589005

  However, according to the configuration of the enable signal line as described above, the wiring length of each enable signal line becomes relatively large, and when a plurality of wirings bypass the shift register, a route is routed between the outer wiring and the inner wiring. A difference occurs, and the wiring length varies among the plurality of enable signal lines. As a result, the delay amount of the enable signal in each enable signal line also becomes relatively large, and the delay amount varies in each of a plurality of series.

  Here, an image signal is supplied to the sampling circuit in synchronization with the input timing of each sampling circuit drive signal. As described above, the input timing of the sampling circuit drive signal to the sampling circuit is defined by each of a plurality of series of enable signals. Therefore, the input timings of the sampling circuit drive signals based on the different series of enable signals are delayed with respect to the corresponding image signal supply timings, and the delay amounts also vary. As a result, in the image display of the electro-optical device, an image defect such as a ghost occurs and the image quality is deteriorated.

  SUMMARY An advantage of some aspects of the invention is that it provides an electro-optical device that can perform high-quality image display and an electronic apparatus including the electro-optical device. And

  In order to solve the above-described problem, an electro-optical device according to an aspect of the invention includes a plurality of pixel portions and a plurality of scanning lines wired on the substrate so as to intersect with a pixel region in which the plurality of pixel portions are arranged. A shift register that is arranged along one side of the substrate along the array direction of the plurality of data lines and sequentially outputs a transfer signal in a plurality of data lines and a peripheral region located around the pixel region, and the peripheral An enable circuit that is arranged in a region and outputs the sampling signal as a sampling circuit driving signal by limiting the transfer signal with a pulse width of each of a plurality of series of enabling signals, and the image signal is output according to the sampling circuit driving signal. A sampling circuit including a plurality of sampling switches respectively supplied to the data lines, and in the peripheral region, arranged along the direction intersecting the one side, A plurality of enable signal terminals to which a plurality of series of enable signals are supplied from an external circuit, and a portion wired in the peripheral region so as to extend in the direction of the one side, And a plurality of enable signal lines that are electrically connected to each other and supply the plurality of series of enable signals to the enable circuit.

  According to the electro-optical device of the present invention, in the peripheral area on the substrate, each pulse width of the transfer signal sequentially output from the shift register is limited based on each pulse width of the plurality of series of enable signals in the enable circuit. Or it is shaped. The sampling circuit supplies an image signal to a plurality of data lines according to the sampling circuit drive signal (that is, the transfer signal after the pulse width is shaped) output from the enable circuit. In other words, the sampling circuit An image signal is sampled based on the drive signal and supplied to a plurality of data lines.

  When the data line is driven in this way, each pixel unit is in a selected state based on, for example, a scanning signal supplied from the scanning line driving circuit via the scanning line, and an image signal is supplied from the data line, An image display based on the signal is performed.

  In plan view on the substrate, the shift register, the enable circuit, and the sampling circuit are typically arranged in this order with respect to one side along the arrangement direction of the data lines in the pixel region. Are arranged along the one side, that is, along the arrangement direction of the plurality of data lines. Here, the “data line arrangement direction” according to the present invention means a direction intersecting with a direction in which each data line extends or a direction “X direction” in which each scanning line extends.

  In addition, a plurality of enable signal lines for supplying a plurality of series of enable signals to the enable circuit are respectively wired along a portion (that is, an arrangement direction of a plurality of data lines (that is, an X direction)) along the one side. Part). The portion wired along the one side is disposed closer to the one side than the shift register, typically between the shift register and the sampling circuit.

  In the electro-optical device according to the aspect of the invention, each enable signal terminal intersects the direction (that is, one side) that avoids the arrangement (that is, the arrangement along one side of the pixel region) of the shift register, the enable circuit, and the sampling circuit. In the direction or Y direction, in other words, the direction along the other side adjacent to one side of the pixel region).

  Therefore, even if the portion wired along the one side of each enable signal line between the shift register and the sampling circuit is extended to the side as it is on the extension line, the shift register is avoided. The pattern can be obtained naturally. Therefore, it is possible to wire from the enable signal terminal to the enable circuit without forming each enable signal line as a pattern that bypasses the periphery of the shift register as already described. Therefore, the wiring length of each enable signal line can be reduced as compared with the case where the enable signal line is routed around the shift register.

  Here, when each enable signal line is routed so as to bypass the periphery of the shift register, for example, in each of the plurality of enable signal lines, around the shift register, along one side of the pixel region (that is, X One enable signal line in which the bent portion is wired near the shift register and one enable signal line in which the bent portion is bent in the direction intersecting with the crossed portion from the wired portion) In other enable signal lines wired farther away from the shift register than the shift register, the wiring length of each other will vary greatly.

  However, according to the present invention, since the positional relationship of each enable signal line with respect to the shift register or the sampling circuit does not particularly affect the wiring length, it is possible to suppress the variation in the wiring length between the enable signal lines. Become. That is, the difference in wiring length between the plurality of enable signal lines can be eliminated almost or completely in a practical sense.

  Therefore, the delay amount of the enable signal in each enable signal line can be made relatively small, and the variation in the delay amount can be suppressed small in each of the plurality of series. As a result, in the sampling circuit, for each of the sampling timings of the image signals based on the different series of enable signals, the delay amount with respect to the supply timing of the corresponding image signal can be suppressed, and variation in the delay amount can also be suppressed. it can. As a result, the occurrence of image defects such as ghosts can be prevented and high-quality image display can be performed.

  In one aspect of the electro-optical device of the present invention, each of the plurality of enable signal terminals is disposed on an extension line in the extending direction of each of the plurality of enable signal lines as viewed in plan on the substrate. .

  According to this aspect, the wiring length of each enable signal line can be further reduced, and variations in the wiring length among the plurality of enable signal lines can be suppressed to a smaller value.

  In another aspect of the electro-optical device according to the aspect of the invention, various signals that are arranged on the substrate along the direction intersecting the one side in the peripheral region and that drive the shift register are supplied from the external circuit. And a plurality of shift register signal lines electrically connected to the plurality of shift register signal terminals and supplying the various signals to the shift register in the peripheral region. Prepare.

  According to this aspect, like the above-described enable signal terminal, the plurality of shift register signal terminals are arranged along a direction in which the shift register is avoided. Therefore, each shift register signal line can be wired from the shift register signal terminal to the shift register without forming a pattern that bypasses the periphery of the shift register. Therefore, the wiring length of each shift register signal line can be shortened. Thereby, signal delay of various signals in each of the plurality of shift register signal lines can be reduced.

  In the aspect including the shift register signal terminal and the shift register signal line described above, at least a part of the plurality of shift register signal terminals is disposed farther from the one side than the plurality of enable signal terminals, and The shift register signal lines electrically connected to some of the shift register signal terminals may be formed so as to intersect with the plurality of enable signal lines.

  With this configuration, it is possible to ensure the degree of freedom in designing the shift register so that, for example, a plurality of data lines are driven unidirectionally or bidirectionally along the arrangement direction. That is, compared to driving a plurality of data lines in one direction as described above, the number of types of signals for driving the shift register is increased in the case of driving in both directions, and the shift is performed accordingly. Many register signal terminals need to be provided.

  In this aspect, even in such a case, in the peripheral region on the substrate, at least a part of the plurality of shift register signal terminals extends along the same direction as this array while avoiding the array of the plurality of enable signal terminals. Can be arranged. Therefore, the number of signal terminals for a plurality of shift registers, the interval between the terminals (that is, the arrangement pitch), and the routing shape of each shift register signal line also change in accordance with the configuration of the shift register. It becomes possible to make it.

  Furthermore, in this aspect, in the shift register signal line that intersects with the enable signal line, the intersecting portion that intersects with the enable signal line is disposed on a different layer on the substrate via at least the enable signal line and the interlayer insulating film. Therefore, the arrangement area for wiring the enable signal line and the shift register signal line can also be reduced.

  In the aspect in which the shift register signal line intersects with the enable signal line, the pixel unit includes various electronic elements electrically connected to the scan line and the data line, and the plurality of enable signal lines are Each of the shift register signal lines is formed of the same film as one conductive film that constitutes one of the data line and the electronic element, and at least an intersecting portion that intersects the enable signal line includes an interlayer insulating film. The conductive film may be arranged in a different layer from the one conductive film, and may be formed of the same film as another conductive film that constitutes either the data line or the electronic element.

  According to this configuration, in the electro-optical device manufacturing process, the shift register signal line and the plurality of enable signal lines in the peripheral region are formed together with the data lines and the electronic elements in each pixel portion, thereby simplifying the number of processes. Can be realized. Here, the “same film” means films formed on the same occasion in the manufacturing process, and means the same kind of film.

  In another aspect of the electro-optical device of the present invention, N (where N is a natural number of 2 or more) image signals are arranged on the substrate along the direction intersecting the one side in the peripheral region. And N image signal terminals to which the image signal serial-parallel converted into the above-mentioned series is supplied from the external circuit, and a portion wired along the one side in the peripheral region, and the portion is the N image signals arranged between the enable circuit and the sampling circuit and electrically connected to the N image signal terminals and supplying the N series of image signals to the sampling circuit, respectively. And the enable circuit includes a sampling circuit for each sampling switch corresponding to a data line group including a group of N data lines among the plurality of data lines. And it outputs a motion signal.

  According to this aspect, when the electro-optical device is driven, the sampling circuit uses the N image signals supplied from the N image signal lines as the transfer signals after the pulse width output from the enable circuit is shaped. Is sampled and supplied to a plurality of data lines for each data line group.

  In this aspect, at least a part of each of the N image signal lines is wired farther than the sampling circuit and closer to the enable circuit with respect to one side of the pixel region. Similarly to the plurality of enable signal terminals described above, the N image signal terminals are arranged along a direction intersecting one side of the pixel region that avoids the arrangement of the enable circuit and the sampling circuit.

  Therefore, similarly to the plurality of enable signal lines, the N image signal lines can be formed from the image signal terminal along one side of the pixel region without forming a pattern that bypasses the periphery of the enable circuit and the shift register. It is possible to wire between the enable circuit and the sampling circuit so as to have a portion. Therefore, the wiring length of each image signal line is further shortened, and the variation in the wiring length between the N image signal lines is suppressed, that is, the wiring length difference between the N image signal lines is almost or practically reduced. Can be completely eliminated.

  As a result, the delay amount of the image signal in each image signal line can be made relatively small, and variation in the delay amount can be suppressed small in each of the N series. Therefore, in the sampling circuit, for each supply timing of image signals of different series, it is possible to reduce the delay amount with respect to the sampling timing and to suppress variations in the delay amount.

  In another aspect of the electro-optical device of the present invention, the electro-optical device includes a plurality of enable signal supply flexible wirings electrically connected to the plurality of enable signal terminals, and is connected to the substrate at a side intersecting the one side. A flexible wiring board.

  According to this aspect, the plurality of enable signal terminals and the plurality of enable signal supplying flexible wirings are electrically connected in a state where the flexible wiring board is mounted on the electro-optical device. In this state, each of the plurality of enable signal supplying flexible wirings is routed from the external circuit built in the flexible wiring board to the enable signal terminal along the wiring direction similar to the wiring portion of the enable signal line. In addition, one end side of each enable signal line is formed so as to extend from the wiring portion onto the extension line to the enable signal terminal. As a result, for each of the plurality of enable signals, the wiring length of the supply path of the enable signal from the external circuit to the enable circuit can be reduced, and the variation in the wiring length difference can be reduced. Therefore, the delay amount can be reduced and the variation in the delay amount can be suppressed to be small in each series.

  In order to solve the above-described problems, an electronic apparatus according to the present invention includes the above-described electro-optical device according to the present invention (including various aspects thereof).

  Since the electronic apparatus of the present invention includes the above-described electro-optical device of the present invention, a projection display device, a television, a mobile phone, an electronic notebook, a word processor, a view capable of performing high-quality image display. Various electronic devices such as a finder type or a monitor direct-view type video tape recorder, a workstation, a videophone, a POS terminal, and a touch panel can be realized. Further, as the electronic apparatus of the present invention, for example, an electrophoretic device such as electronic paper, a display device using an electron emission device (Field Emission Display and Conduction Electron-Emitter Display), or the like can be realized.

  The operation and other advantages of the present invention will become apparent from the best mode for carrying out the invention described below.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, a driving circuit built-in type TFT active matrix driving type liquid crystal device, which is an example of the electro-optical device of the present invention, is taken as an example.

<Overall configuration of liquid crystal device>
The liquid crystal device according to this embodiment will be described with reference to FIGS.

  First, the overall configuration of the liquid crystal device according to the present embodiment will be described with reference to FIGS. 1 and 2. FIG. 1 is a plan view showing the configuration of the liquid crystal device according to this embodiment, and FIG. 2 is a cross-sectional view taken along the line H-H 'in FIG.

  1 and 2, in the liquid crystal device according to the present embodiment, a TFT array substrate 10 and a counter substrate 20 are arranged to face each other. A liquid crystal layer 50 is sealed between the TFT array substrate 10 and the counter substrate 20, and the TFT array substrate 10 and the counter substrate 20 are surrounded by an image display region 10a as an example of the “pixel region” according to the present invention. They are bonded to each other by a sealing material 52 provided in a sealing region located in the area.

  In FIG. 1, a light-shielding frame light-shielding film 53 that defines the frame area of the image display region 10a is provided on the counter substrate 20 side in parallel with the inside of the seal region where the sealing material 52 is disposed.

  A data line driving circuit 101 is provided along one side of the TFT array substrate 10 in a region located outside the seal region in which the sealing material 52 is disposed in the peripheral region. In the region located inside, the sampling circuit 7 is arranged along one side of the image display region 10 a along one side of the TFT array substrate 10 and covered with the frame light shielding film 53.

  In this embodiment, in particular, a plurality of external circuit connection terminals 102 to which various signals for driving peripheral circuits such as the data line driving circuit 101 and the scanning line driving circuit 104 are supplied include the data line driving circuit 101 and the sampling circuit 7. Are provided along the other side adjacent to one side of the TFT array substrate 10 on which the data line driving circuit 101 is arranged in a direction that avoids the arrangement. That is, the plurality of external circuit connection terminals 102 are arranged along a direction along the other side adjacent to one side of the image display region 10a where the data line driving circuit 101 or the sampling circuit 7 is arranged.

  In addition, the scanning line driving circuit 104 is located inside the seal region along two sides adjacent to one side where the data line driving circuit 101 of the TFT array substrate 10 is disposed (that is, the other side and the side opposite thereto). The frame shading film 53 is provided so as to be covered. The two scanning line driving circuits 104 are electrically connected to each other by a plurality of wirings 105 provided along the remaining one side of the TFT array substrate 10.

  On the TFT array substrate 10, vertical conduction terminals 106 for electrically connecting the two substrates with a vertical conduction material are disposed in regions facing the four corner portions of the counter substrate 20.

  In FIG. 2, on the TFT array substrate 10, a laminated structure in which wirings such as pixel switching TFTs (Thin Film Transistors), scanning lines, and data lines are formed. In the image display area 10a, a pixel electrode 9a is provided in an upper layer of wiring such as a pixel switching TFT, a scanning line, and a data line. On the pixel electrode 9a, an alignment film (not shown) is formed. In the present embodiment, the pixel switching element may be constituted by various transistors, TFD, or the like in addition to the TFT.

  On the other hand, a light shielding film 23 is formed on the surface of the counter substrate 20 facing the TFT array substrate 10. A counter electrode 21 made of a transparent material such as ITO (Indium Tin Oxide) is formed on the light shielding film 23 so as to face the plurality of pixel electrodes 9a. Further, an alignment film (not shown) is formed in the drawing.

  The liquid crystal layer 50 is made of, for example, a liquid crystal in which one kind or several kinds of nematic liquid crystals are mixed, and takes a predetermined alignment state between the pair of alignment films described above.

  Although not shown here, in addition to the data line driving circuit 101 and the scanning line driving circuit 104, the TFT array substrate 10 is used for inspecting the quality, defects, etc. of the liquid crystal device during manufacturing or at the time of shipment. An inspection circuit, an inspection pattern, or the like may be formed.

  Next, an electrical configuration of the liquid crystal device will be described with reference to FIGS. FIG. 3 is a block diagram for explaining an external circuit electrically connected to the liquid crystal device, and FIG. 4 is a block diagram showing an electrical configuration for driving each pixel portion of the liquid crystal device. It is.

  As shown in FIG. 3, the liquid crystal device is provided with external circuits including an image signal supply circuit 720, a timing control circuit 730, and a power supply circuit 710 that are electrically connected.

  The timing control circuit 730 is configured to output various timing signals used in each unit. A timing signal output means that is a part of the timing control circuit 730 generates a dot clock that is a minimum unit clock and scans each pixel. Based on the dot clock, a Y clock signal CLY and an inverted Y clock signal are generated. CLYinv, X clock signal CLX, inverted X clock signal CLXinv, Y start pulse DY and X start pulse DX are generated and supplied to the liquid crystal device 100. In addition, for example, four series of enable signals ENB <b> 1 to ENB <b> 4 are generated and output from the timing control circuit 730 and supplied to the liquid crystal device 100.

  One line of input image data VID is input to the image signal supply circuit 720 from the outside. The image signal supply circuit 720 performs serial-parallel conversion on one system of input image data VID to obtain N series or N phases (where N is a natural number of 2 or more). In this embodiment, for example, 6 series or 6 phases (N = 6) image signals VID1 to VID6 are generated. Further, in the image signal supply circuit 720, the voltages of the image signals VID1 to VID6 are inverted to a positive polarity and a negative polarity with respect to a predetermined reference potential, and the image signals VID1 to VID6 thus inverted in polarity are output. You may be made to do. The image signals VID <b> 1 to VID <b> 6 generated in this way are supplied from the image signal supply circuit 720 to the liquid crystal device 100.

  The power supply circuit 710 supplies the liquid crystal device 100 with various power sources such as a common power source having a predetermined common potential LCC, scanning line driving circuit power sources VDDY and VSSY, and data line driving circuit power source VDDX.

  Next, in FIG. 4, the liquid crystal device is provided with a scanning line driving circuit 104, a data line driving circuit 101, and a sampling circuit 7 constituting an internal driving circuit in the peripheral region of the TFT array substrate 10. In FIG. 4, an example of a configuration relating to the arrangement of these various circuits in the internal drive circuit is also schematically shown.

  A Y clock signal CLY, an inverted Y clock signal CLYinv, a Y start pulse DY, and power supplies VDDY and VSSY are supplied to the scanning line driving circuit 104 via the external circuit connection terminal 102. When the Y start pulse DY is input, the scanning line driving circuit 104 sequentially generates and outputs the scanning signals G1,..., Gm at a timing based on the Y clock signal CLY and the inverted Y clock signal CLYinv.

  In the present embodiment, the data line driving circuit 101 includes a shift register 101a and an enable circuit 101b. The shift register 101a has an X clock signal CLX, an inverted X clock signal CLXinv, and an X start via a shift register signal terminal and a shift register signal line (see FIG. 6 described later) provided as an external circuit connection terminal 102. The pulse DX and the power supply VDDX (further, in addition to the high-potential power supply, the low-potential power supply VSSX (the configuration related to the supply of the power supply is not shown)) are supplied.

  For example, four series of enable signals ENB1 to ENB4 are supplied to the enable circuit 101b via an enable signal terminal and an enable signal line (see FIG. 6) provided as an external circuit connection terminal 102 described later. Note that the enable signals are not limited to four sequences, and may be generated as two or more sequences.

  Furthermore, the sampling circuit 7 includes a plurality of sampling switches 7a each composed of a P-channel or N-channel single-channel TFT or a complementary TFT. In the sampling circuit 7, image signals VID1 to VID6 serially and parallelly developed in 6 phases (or 6 series) are provided as image signal terminals provided as external circuit connection terminals 102 and 6 (N = 6) images. It is supplied via the signal line 170. In the sampling circuit 7, each sampling switch 7 a connects the six data lines 6 a to a group according to the sampling circuit drive signals S 1,..., S 2 n output from the enable circuit 101 b of the data line drive circuit 101. The image signals VID1 to VID6 are supplied for each data line group. Therefore, in the present embodiment, since the plurality of data lines 6a are driven for each data line group, the driving frequency can be suppressed.

  The liquid crystal device includes data lines 6 a and scanning lines 11 a that are wired vertically and horizontally in an image display region 10 a that occupies the center of the TFT array substrate 10. Each pixel portion 700 corresponding to the intersection is provided with a pixel electrode 9a of a liquid crystal element 118 arranged in a matrix and a TFT 30 for switching control of the pixel electrode 9a. In the present embodiment, the total number of scanning lines 11a is m (where m is a natural number of 2 or more), and the total number of data lines 6a is 2n × 6 (where n is a natural number of 2 or more). explain.

  In FIG. 4, when attention is paid to the configuration of one pixel portion 700, the data line 6a to which the image signal VIDk (where k = 1, 2, 3,..., 6) is supplied to the source electrode of the TFT 30. Is electrically connected to the gate electrode of the TFT 30, and a scanning line 11a to which a scanning signal Gj (j = 1, 2, 3,..., M) is supplied is electrically connected. In addition, the pixel electrode 9 a of the liquid crystal element 118 is connected to the drain electrode of the TFT 30. Here, in each pixel portion 700, the liquid crystal element 118 has a liquid crystal sandwiched between the pixel electrode 9 a and the counter electrode 21. Accordingly, each pixel unit 700 is arranged in a matrix corresponding to each intersection of the scanning line 11a and the data line 6a.

  Each scanning line 11a is selected line-sequentially by scanning signals G1,..., Gm output from the scanning line driving circuit 104. In the pixel portion 700 corresponding to the selected scanning line 11a, when the scanning signal Gj is supplied to the TFT 30, the TFT 30 is turned on and the pixel portion 700 is in a selected state. An image signal VIDk is supplied to the pixel electrode 9a of the liquid crystal element 118 at a predetermined timing from the data line 6a by closing the switch of the TFT 30 for a certain period. As a result, an applied voltage defined by the potentials of the pixel electrode 9 a and the counter electrode 21 is applied to the liquid crystal element 118. The liquid crystal modulates light and enables gradation display by changing the orientation and order of the molecular assembly depending on the applied voltage level. In the normally white mode, the transmittance for incident light is reduced according to the voltage applied in units of each pixel, and in the normally black mode, the light is incident according to the voltage applied in units of each pixel. The light transmittance is increased, and light having a contrast corresponding to the image signals VID1 to VID6 is emitted from the liquid crystal panel 100 as a whole.

  Here, in order to prevent the held image signal from leaking, a storage capacitor 70 is added in parallel with the liquid crystal element 118. One electrode of the storage capacitor 70 is connected to the drain of the TFT 30 in parallel with the pixel electrode 9a, and the other electrode is connected to the capacitor wiring 400 with a fixed potential so as to have a constant potential.

  Note that a common power supply of a common potential LCC is supplied to the vertical conduction terminal 106, and the reference potential of the counter electrode 21 described above is defined based on the common power supply.

<Specific configuration of pixel portion>
Next, a specific configuration of the pixel portion that realizes the above-described operation will be described with reference to FIG. FIG. 5 is a cross-sectional view illustrating a configuration of a cross-sectional portion of the pixel portion. In FIG. 5, the scale of each layer / member is different for each layer / member to have a size that can be recognized on the drawing. About this point, it is the same also about each figure of FIGS. 7-12 mentioned later, and it may mutually differ about each scale about this scale.

  In FIG. 5, each circuit element of the pixel portion described above is patterned and constructed on the TFT array substrate 10 as a laminated conductive film, and the side on which such a laminated structure is formed is opposed to the counter substrate 20. The TFT array substrate 10 is disposed so as to face each other. Hereinafter, the laminated structure on the TFT array substrate 10 side will be described in detail.

  First, the first layer in the stacked structure includes the scanning line 11a, and the base insulating film 12 is formed on the upper layer side of the scanning line 11a.

  Then, a second layer including the TFT 30 and the like is formed on the upper layer side of the base insulating film 12. The TFT 30 has an LDD (Lightly Doped Drain) structure, for example, and includes a gate electrode 3a, a semiconductor layer 1a, and an insulating film 2 including a gate insulating film that insulates the gate electrode 3a from the semiconductor layer 1a. The semiconductor layer 1a includes a channel region 1a ′, a low concentration source region 1b and a low concentration drain region 1c, and a high concentration source region 1d and a high concentration drain region 1e. The gate electrode 3a of the TFT 30 is electrically connected to the scanning line 11a through a contact hole 12cv formed in the base insulating film 12 in a part 3b thereof.

  An interlayer insulating film 41 is formed on the upper layer side from the TFT 30 and the like, and a third layer including the data line 6a and the like is formed on the upper layer side from the interlayer insulating film 41. The third layer includes the data line 6a and the relay layer 600. The data line 6 a is formed of, for example, a material containing aluminum and is electrically connected to the high concentration source region 1 d of the TFT 30 through a contact hole 81 that penetrates the interlayer insulating film 41. The relay layer 600 is formed of the same film as the data line 6a, for example, and is electrically connected to the high-concentration drain region 1e of the TFT 30 through a contact hole 83 that penetrates the interlayer insulating film 41.

  Further, an interlayer insulating film 42 is formed above the data line 6a and the like, and a fourth layer including a storage capacitor 70 and the like is formed above the interlayer insulating film 42. The storage capacitor 70 has a configuration in which a capacitor electrode 300 and a lower electrode 71 formed of, for example, a material containing aluminum are arranged to face each other with a dielectric film 75 interposed therebetween. The capacitor electrode 300 is formed as a part of the capacitor wiring 400 (see FIG. 4), and is electrically connected to the capacitor wiring 400. The extending portion of the lower electrode 71 is electrically connected to the relay layer 600 through a contact hole 84 that penetrates the interlayer insulating film 42.

  Further, an interlayer insulating film 43 is formed on the upper layer side from the storage capacitor 70 and the like, and a pixel electrode 9a made of a transparent conductive film such as ITO is formed on the fifth layer above the interlayer insulating film 43. The The pixel electrode 9 a is electrically connected to the extending portion of the lower electrode 71 through a contact hole 85 that penetrates the interlayer insulating film 43. That is, the potential of the lower electrode 71 is a pixel potential. Further, as described above, the extended portion of the lower electrode 71 and the relay layer 600 and the relay layer 600 and the high-concentration drain region 1e of the TFT 30 are electrically connected through the contact holes 84 and 83, respectively. ing. That is, the pixel electrode 9a and the high-concentration drain region 1e of the TFT 30 are relay-connected through the relay layer 600 and the extended portion of the lower electrode 71.

  An alignment film 16 that has been subjected to a predetermined alignment process such as a rubbing process is provided above the pixel electrode 9a.

  The above is the configuration of the pixel portion on the TFT array substrate 10 side.

  On the other hand, the counter substrate 20 is provided with a counter electrode 21 on the entire surface of the counter substrate 20, and an alignment film 22 is further provided thereon (under the counter electrode 21 in FIG. 5). As with the pixel electrode 9a, the counter electrode 21 is made of a transparent conductive film such as an ITO film. A light-shielding film 23 is provided between the counter substrate 20 and the counter electrode 21 so as to cover at least a region facing the TFT 30 in order to prevent generation of light leakage current in the TFT 30.

  A liquid crystal layer 50 is provided between the TFT array substrate 10 thus configured and the counter substrate 20. The liquid crystal layer 50 is formed by sealing liquid crystal in a space formed by sealing the peripheral portions of the substrates 10 and 20 with a sealing material. The liquid crystal layer 50 takes a predetermined alignment state by the alignment film 16 and the alignment film 22 that have been subjected to an alignment process such as a rubbing process in a state where an electric field is not applied between the pixel electrode 9 a and the counter electrode 21. It is like that.

<Configuration related to driving of data line>
In the following, the configuration related to the driving of the characteristic data line in the present embodiment will be described in more detail with reference to FIGS.

  FIG. 6 schematically shows the arrangement relationship between the data line driving circuit and the sampling circuit, other various signal lines and signal terminals, and their electrical connection relationship. FIG. 6 shows in detail the configuration related to the final stage (second nth stage) in the data line driving circuit 101, but the following stages (that is, the first stage to the (2n-1) th stage). For each of the above, the configuration and operation thereof are the same as those in the final stage.

  In FIG. 1, FIG. 4 or FIG. 6, in the peripheral region on the TFT array substrate 10, the data line driving circuit 101 and the sampling circuit 7 are arranged in this order in the arrangement direction of the data lines 6a in the image display region 10a. In the data line drive circuit 101, the shift register 101a and the enable circuit 101b are arranged in this order so as to approach one side of the image display area 10a. Is done. Further, as described with reference to FIG. 1 or FIG. 4, the shift register 101a, the enable circuit 101b, and the sampling circuit 7 are arranged along one side of the image display area 10a, that is, in the arrangement direction of the plurality of data lines 6a ( (X direction).

  As described with reference to FIG. 1, in the peripheral region on the TFT array substrate 10, the direction along the other side adjacent to the one side where the data line driving circuit 101 or the sampling circuit 7 of the image display region 10a is arranged (see FIG. 6, a plurality of, in this embodiment, four enable signal terminals 102 e 1 to 102 e 4 and a plurality of shift register signal terminals 102 sr as external circuit connection terminals respectively along the Y direction or the extending direction of the data line 6 a). , And 6 (N = 6) image signal terminals 102v1 to 102v6 are arranged.

  The shift register 101a and the plurality of shift register signal terminals 102sr are electrically connected by a plurality of shift register signal lines 128. Each of the plurality of shift register signal lines 128 is electrically connected to the shift register signal terminal 102sr at one end side and electrically connected to the shift register 101a at the other end side.

  The shift register 101a is supplied with various signals such as an X clock signal CLX, an inverted X clock signal CLXinv, and an X start pulse DX from a plurality of shift register signal terminals 102sr via shift register signal lines 128, respectively. When the X start pulse DX is input, the shift register 101a sequentially generates and outputs the transfer signals SR1,..., SRn at a timing based on the X clock signal CLX and the inverted X clock signal XCLXinv.

  Each stage of the enable circuit 101b is configured by, for example, an AND circuit 121. Each of the four enable signal terminals 102e1 to 102e4 is electrically connected to one end side of each of the four enable signal lines 122-1 to 122-4, so that the four enable signal lines 122- The other end side of each of 1-122-4 is electrically connected to each AND circuit 121 in the enable circuit 101b.

  In the enable circuit 101b, each AND circuit 121 is supplied with transfer signals SR1,..., SRn sequentially output from the shift register 101a, and four enable signal lines from the enable signal terminals 102e1 to 102e4. Any one of four series of enable signals ENB1 to ENB4 is supplied via 122-1 to 122-4. Here, as shown in FIG. 6, in the present embodiment, the enable circuit 101b is configured to output two types of sampling circuit drive signals S2i from one output of the transfer signal SRi (i = 1, 2, 3,..., N). And S2i-1. For this reason, two AND circuits 121 are driven for one output of the transfer signal SRi.

  Then, each AND circuit 121 calculates the logical product of the transfer signal SRi and any one of the enable signals ENB1 to ENB4, so that each pulse width of the transfer signal SRi is based on each pulse width of the enable signals ENB1 to ENB4. To shape. Each AND circuit 121 outputs the transfer signal SRi thus shaped as the sampling circuit drive signal S2i or S2i-1.

  In this embodiment, the data line driving circuit 101 may be provided with a level shifter circuit and the like in addition to the shift register 101a and the enable circuit 101b.

  Sampling circuit drive signals S1,..., S2n are sequentially supplied from the enable circuit 101b of the data line drive circuit 101 to the sampling circuit 7 for each sampling switch 7a corresponding to the data line group. ..., each sampling switch 7a is turned on in response to S2n. Therefore, the image signals VID1 to VID6 from the six image signal lines 170-1 to 170-6 are simultaneously applied to the data line 6a belonging to the data line group via the sampling switch 7a which is turned on, and the data line group. Sequentially supplied every time. Each of the six image signal lines 170-1 to 170-6 is electrically connected to each of the image signal terminals 102v1 to 102v6, and the other end is electrically connected to the sampling switch 7a of the sampling circuit 7. Is done.

  Next, the configuration of the image signal line and the enable signal line will be described in more detail with reference to FIG. FIG. 7 is a plan view schematically showing the configuration of each of the image signal line and the enable signal line.

  FIG. 7 shows six image signal lines 170-1 to 170-6 and six image signal terminals 102v1 to 102v6, respectively, and four enable signal lines 122-1 to 122-4 and four enable signals. Focusing only on each of the signal terminals 102e1 to 102e4, an example of the wiring shape viewed in plan on the TFT array substrate 10 and the arrangement relationship with respect to the shift register 101a, the enable circuit 101b, and the sampling circuit 7 are illustrated. . In FIG. 7, illustrations of detailed configurations of the signal lines or wirings and terminals other than the signal terminals, and the shift register 101 a, the enable circuit 101 b, and the sampling circuit 7 are omitted.

  In the present embodiment, each of the four enable signal lines 122-1 to 122-4 is wired along the arrangement direction of the plurality of data lines 6a (that is, a portion wired along the X direction). have. The portions of the enable signal lines 122-1 to 122-4 that are wired along the X direction are between the shift register 101 a and the sampling circuit 7, and include six image signal lines 170-1 to 170-. It is arranged at a position farther from one side of the image display area 10 a than 6.

  In other words, each of the enable signal lines 122-1 to 122-4 wired in the X direction is between the shift register 101 a and the sampling circuit 7 and has six image signal lines 170-1. It is arranged at a position closer to one side of the substrate 10 on the side where the shift register 101a is arranged than ˜170-6.

  In addition, the enable signal terminals 102e1 to 102e4 are directions to avoid disposing the plurality of data lines 6a of the shift register 101a, the enable circuit 101b, and the sampling circuit 7 along the arrangement direction (X direction), that is, the data line 6a. Are arranged along the extending direction (Y direction in FIG. 7).

  Accordingly, the four enable signal lines 122-1 to 122-4 do not have to be formed as a pattern that bypasses the periphery of the shift register 101 a, and enable signal terminals from the portion wired along the X direction. The wiring can be extended to each of 102e1 to 102e4.

  Accordingly, the wiring length of each of the enable signal lines 122-1 to 122-4 can be reduced as compared with the case where the enable signal lines 122-1 to 122-4 are routed around the shift register 101a. In order to bypass the periphery of the shift register 101a, one of the enable signal lines 122-1 to 122-4, which is wired closer to the shift register 101a, and this one signal line There is a large difference in wiring length between other signal lines that are further away from the shift register 101a. That is, the wiring length varies between the enable signal lines 122-1 to 122-4.

  On the other hand, in the present embodiment, the positional relationship of each of the enable signal lines 122-1 to 122-4 with respect to the shift register 101a and the sampling circuit 7 does not have a great influence on the wiring length. It becomes possible to suppress the variation in the wiring length among each of −1 to 122-4. That is, the difference in wiring length between the enable signal lines 122-1 to 122-4 can be eliminated almost or preferably completely.

  Returning to FIG. 6, since the plurality of shift register signal terminals 102sr are also arranged in the same manner as the enable signal terminals 102e1 to 102e4, each shift register signal line 128 shifts toward one end thereof. Wiring from the shift register signal terminal 102 sr to the shift register 101 a is possible without forming the pattern around the register 101 a so as to be detoured to the side farther from one side of the image display area 10 a than the shift register 101 a. Is possible. Therefore, the wiring length of each shift register signal line 128 can be shortened.

  Therefore, in this embodiment, in each of the enable signal lines 122-1 to 122-4, the delay amount of each of the four series of enable signals ENB 1 to ENB 4 is made relatively small and the delay amount varies among the four series. Can be kept small. As a result, in the sampling circuit 7, for each of the sampling timings of the image signals VID1 to VID6 based on the different series of enable signals ENB1 to ENB4, the delay amount with respect to the supply timing of the corresponding image signal VIDk is suppressed, and this delay Variations in the amount can be kept small.

  Further, a part of the plurality of shift register signal terminals 102sr is located on one side of the image display region 10a in the arrangement direction as compared with the four enable signal terminals 102e1 to 102e4 when viewed in plan on the TFT array substrate 10. It is disposed near, that is, far from the side on which the shift register 101a of the substrate 10 is disposed. The shift register signal lines 128 whose one end is electrically connected to a part of the shift register signal terminals 102 sr arranged in this way are each enabled signal lines from one end to the other end. It is formed so as to cross each of 122-1 to 122-4.

  Here, FIG. 8 is an enlarged plan view showing a configuration relating to the intersection of the enable signal line and the shift register signal line, and FIG. 9 is a cross-sectional view taken along line A-A ′ of FIG. 8.

  8 or 9, preferably, in the peripheral region on the TFT array substrate 10 among the conductive films constituting each of the lower electrode 71 and the capacitor electrode 300 of the storage capacitor 70 described with reference to FIG. The signal lines 122-1 to 122-4 are each formed of the same film as the lower electrode 71, and the intersection 128 b of the shift register signal line 128 that intersects with the enable signal lines 122-1 to 122-4 is a capacitive electrode. The other portion 128 a other than the intersecting portion 128 b is formed of the same film as the lower electrode 71. As a result, the crossing portion 128b of the shift register signal line 128 is disposed in the same layer as the capacitor electrode 300, and the other portion 128a of the shift register signal line 128 and the enable signal lines 122-1 to 122-4 are located below. The electrode 71 is disposed in the same layer.

  In the shift register signal line 128, the intersecting portion 128b and the other portion 128a other than the intersecting portion 128b are electrically connected to each other through contact holes 128aa and 128ab opened through the dielectric film 75. Connected.

  Therefore, in the present embodiment, the configuration of the shift register 101a is appropriately changed, and for example, each data line 6a as described with reference to FIG. 4 or 6 is driven in one direction along the arrangement direction. Even in the case where the configuration is such that the drive is performed bidirectionally, at least part of the plurality of shift register signal terminals 102sr is connected to the enable signal terminal 102e1 in accordance with the increase / decrease in the types of various signals for driving the shift register 101a. It can be arranged along the same direction as this arrangement, avoiding the arrangement of ~ 1022e4. Therefore, the number of shift register signal terminals 102sr, the interval between the terminals, and the routing shape of each shift register signal line 128 can be changed in accordance with the configuration of the shift register 101a. Become. Further, even if the routing shape or the like of each shift register signal line 128 is appropriately changed in this way, at least a part of the signal line is intersected with the enable signal lines 122-1 to 122-4 so that these signal lines are The arrangement area required for the arrangement can be reduced.

  In FIG. 6 or FIG. 7, at least a part of each of the six image signal lines 170-1 to 170-6 is the same as the wiring part of each of the enable signal lines 122-1 to 122-4. From the end side to the one end side, the plurality of data lines 6a are wired along the arrangement direction (X direction in FIG. 7), and from the sampling circuit 7 to one side of the image display area 10a along the X direction. It is wired far away and closer to the enable circuit 101b. For example, each of the six image signal lines 170-1 to 170-6 is preferably formed of the same film as the data line 6a described with reference to FIG.

  In addition, the six image signal terminals 102v1 to 102v6 are arranged in directions to avoid the arrangement of the shift register 101a, the enable circuit 101b, and the sampling circuit 7 (data lines), similarly to the four enable signal terminals 102e1 to 102e4 described above. 6a extending direction or Y direction).

  Therefore, like the enable signal lines 122-1 to 122-4, the six image signal lines 170-1 to 170-6 are formed as patterns that bypass the periphery of the enable circuit 101 b and the shift register 101 a, respectively. Even if not, it is possible to wire between the enable circuit 101b and the sampling circuit 7 from each of the image signal terminals 102v1 to 102v6 from one end side to the other end side. Accordingly, the wiring length of each of the image signal lines 170-1 to 170-6 is further shortened, and variations in the wiring length between these signal lines are also suppressed, that is, the image signal lines 170-1 to 170-6. The difference in the wiring length between them can be eliminated almost or preferably completely.

  Therefore, in each of the image signal lines 170-1 to 170-6, the delay amount of each of the image signals VID1 to VID6 can be made relatively small, and variation in the delay amount among the six sequences can be suppressed to be small. Therefore, in the sampling circuit 7, for each supply timing of the image signals VID1 to VID6 of different series, it is possible to reduce the delay amount with respect to the sampling timing and to suppress variations in the delay amount.

  As described above, in the present embodiment, the difference in the wiring length between the enable signal lines 122-1 to 122-4 can be almost eliminated, the occurrence of image defects such as ghosts can be prevented, and a high-quality image can be obtained. Display can be made. Furthermore, in this embodiment, the difference in wiring length between the image signal lines 170-1 to 170-6 can be almost eliminated, and a higher quality image display can be performed.

  In the present embodiment, as described above, the shift register signal line 128, the enable signal lines 122-1 to 122-4, or the image signal lines 170-1 to 170-6 are connected to the storage capacitor 70 or the data line 6a. In the manufacturing process of the liquid crystal device, the number of steps for forming these various signal lines can be simplified.

<Modification>
Next, a modified example will be described with reference to FIGS. FIG. 10 is an enlarged plan view showing a configuration relating to the intersection of the enable signal line and the shift register signal line, and FIG. 11 is a cross-sectional view taken along line BB ′ of FIG. is there.

  In the present modification, in FIG. 10 or FIG. 11, in the peripheral region on the TFT array substrate 10, the enable signal lines 122-1 to 122-4 are each formed of the same film as the lower electrode 71, for example. In addition to the intersecting portions of the signal line 128 that intersect the enable signal lines 122-1 to 122-4, other portions other than the intersecting portions may be formed of the same film as the capacitor electrode 300, for example.

  With this configuration, in FIG. 11, the shift register signal line 128 is not required to be electrically connected to the other end portions of the crossing portion with other portions other than the crossing portion through the contact holes. Therefore, it is possible to reduce the contact resistance in the shift register signal line 128 and further simplify the manufacturing process related to the formation.

  FIG. 12 is a partial plan view schematically showing a configuration related to the mounting of the flexible wiring board on the enable signal terminal in another configuration in the present modification.

  For example, the external circuit as described with reference to FIG. 3 is connected to the liquid crystal device by mounting the flexible wiring board 200 on the plurality of external circuit connection terminals 102 shown in FIG. In this case, each of the four enable signal supply flexible wirings 210-1 to 210-4 that supplies four series of enable signals ENB <b> 1 to ENB <b> 4 in the flexible wiring board 200 in a state of being mounted on the liquid crystal device is enabled. Each of the signal terminals 102e1 to 102e4 is electrically and mechanically connected via an anisotropic conductive film on the side of the substrate 10 in the Y direction. In this state, for example, the enable signal supplying flexible wirings 210-1 to 210-4 are arranged along the X direction in FIG. 12, that is, along the same direction as the arrangement direction of the plurality of data lines 6a. It is formed.

  In contrast, in the peripheral region on the TFT array substrate 10, one end side of each of the enable signal lines 122-1 to 122-4 is extended from a wiring portion (see FIG. 7) wired along the X direction. It is preferable that the wiring is formed so as to extend to the lines of the enable signal terminals 102e1 to 102e4.

With this configuration, the wiring length of each of the enable signal lines 122-1 to 122-4 is made smaller in the peripheral region on the TFT array substrate 10, and the variation in wiring length between these signal lines is further increased. It can be kept small. Further, for each of the enable signals ENB1 to ENB4, it is possible to reduce the wiring length of the signal supply path from the external circuit to the enable circuit 101b, and to reduce the variation in the wiring length between these supply paths. It becomes. Therefore, the delay amount can be reduced and the variation in the delay amount can be suppressed to be small in each series.
<Electronic equipment>
Next, the case where the liquid crystal device which is the above-described electro-optical device is applied to various electronic devices will be described.

  First, a projector using this liquid crystal device as a light valve will be described. FIG. 13 is a plan view showing a configuration example of the projector. As shown in this figure, a lamp unit 1102 including a white light source such as a halogen lamp is provided inside the projector 1100. The projection light emitted from the lamp unit 1102 is separated into three primary colors of RGB by four mirrors 1106 and two dichroic mirrors 1108 arranged in the light guide 1104, and serves as a light valve corresponding to each primary color. The light enters the liquid crystal panels 1110R, 1110B, and 1110G.

  The configurations of the liquid crystal panels 1110R, 1110B, and 1110G are the same as those of the liquid crystal device described above, and are driven by R, G, and B primary color signals supplied from the image signal processing circuit. The light modulated by these liquid crystal panels enters the dichroic prism 1112 from three directions. In this dichroic prism 1112, R and B light is refracted at 90 degrees, while G light travels straight. Accordingly, as a result of the synthesis of the images of the respective colors, a color image is projected onto the screen or the like via the projection lens 1114.

  Here, paying attention to the display images by the liquid crystal panels 1110R, 1110B, and 1110G, the display image by the liquid crystal panel 1110G needs to be horizontally reversed with respect to the display images by the liquid crystal panels 1110R, 1110B.

  Since light corresponding to the primary colors R, G, and B is incident on the liquid crystal panels 1110R, 1110B, and 1110G by the dichroic mirror 1108, it is not necessary to provide a color filter.

  In addition to the electronic device described with reference to FIG. 13, a mobile personal computer, a mobile phone, a liquid crystal television, a viewfinder type, a monitor direct view type video tape recorder, a car navigation device, a pager, and an electronic notebook Calculators, word processors, workstations, videophones, POS terminals, devices with touch panels, and the like. Needless to say, the present invention can be applied to these various electronic devices.

  In addition to the liquid crystal device described in the above embodiment, the present invention also includes a reflective liquid crystal device (LCOS) in which elements are formed on a silicon substrate, a plasma display (PDP), a field emission display (FED, SED), The present invention can also be applied to an organic EL display, a digital micromirror device (DMD), an electrophoresis apparatus, and the like.

  The present invention is not limited to the above-described embodiments, and can be appropriately changed without departing from the spirit or concept of the invention that can be read from the claims and the entire specification. An electronic apparatus including the electro-optical device is also included in the technical scope of the present invention.

It is a top view which shows the structure of a liquid crystal device. It is sectional drawing in the HH 'line of FIG. It is a block diagram for demonstrating an external circuit. It is a block diagram which shows the electrical structure for driving each pixel part of a liquid crystal device. It is sectional drawing which shows the structure of the cross-sectional part of a pixel part. It is a figure which shows roughly the arrangement | positioning relationship of various signal lines and signal terminals, and these electrical connection relationships, a data line drive circuit and a sampling circuit. It is a top view which shows roughly about each structure of an image signal line and an enable signal line. FIG. 6 is an enlarged plan view showing a configuration related to an intersection of an enable signal line and a shift register signal line. It is A-A 'sectional drawing of FIG. FIG. 10 is an enlarged plan view showing a configuration related to the intersection of an enable signal line and a shift register signal line in one configuration in the present modification. It is B-B 'sectional drawing of FIG. It is a fragmentary top view which shows schematically the structure regarding mounting of the flexible wiring board with respect to an enable signal terminal about the other structure in this modification. It is a top view which shows the structure of the projector which is an example of the electronic device to which the electro-optical apparatus is applied.

Explanation of symbols

  6a ... data line, 7 ... sampling circuit, 10 ... TFT array substrate, 10a ... pixel area, 11a ... scanning line, 101a ... shift register, 101b ... enable circuit, 102e1-102e4 ... enable signal terminal, 122-1-122- 4 ... enable signal line, 700 ... pixel portion

Claims (8)

On the board
A plurality of pixel portions;
A plurality of scanning lines and a plurality of data lines wired so as to cross each other in a pixel region in which the plurality of pixel portions are arranged;
A shift register that is arranged along one side of the substrate along the arrangement direction of the plurality of data lines in a peripheral region located around the pixel region, and sequentially outputs a transfer signal;
An enable circuit that is arranged in the peripheral region and that outputs the transfer signal as a sampling circuit drive signal by limiting the transfer signal with the pulse width of each of a plurality of series of enable signals;
A sampling circuit including a plurality of sampling switches for supplying an image signal to each of the plurality of data lines in response to the sampling circuit driving signal;
In the peripheral region, a plurality of enable signal terminals arranged along a direction intersecting the one side, and the plurality of series of enable signals are supplied from an external circuit;
Each of the peripheral regions has a portion wired so as to extend in the direction of the one side, and is electrically connected to each of the plurality of enable signal terminals, and the plurality of series of enable signals are supplied to the enable circuit. An electro-optical device comprising: a plurality of enable signal lines to be supplied.   The plurality of enable signal terminals are arranged on extension lines in the extending direction of each of the plurality of enable signal lines as viewed in plan on the substrate. Electro-optic device. On the substrate,
In the peripheral region, a plurality of shift register signal terminals arranged along a direction intersecting the one side and supplied with various signals for driving the shift register from the external circuit;
2. The shift register according to claim 1, further comprising: a plurality of shift register signal lines electrically connected to the plurality of shift register signal terminals in the peripheral region and supplying the various signals to the shift register. Or the electro-optical device according to 2; At least some of the plurality of shift register signal terminals are arranged farther from the one side than the plurality of enable signal terminals,
4. The shift register signal line electrically connected to the part of the shift register signal terminals is formed so as to intersect with the plurality of enable signal lines. 5. Electro-optic device. The pixel unit includes various electronic elements electrically connected to the scan line and the data line,
Each of the plurality of enable signal lines is formed of the same film as one conductive film constituting either the data line or the electronic element,
Of the shift register signal lines, at least an intersecting portion intersecting with the enable signal line is disposed in a layer different from the one conductive film via an interlayer insulating film, and constitutes either the data line or the electronic element The electro-optical device according to claim 4, wherein the electro-optical device is formed of the same film as the other conductive film. On the substrate,
In the peripheral region, an image signal arranged in a direction intersecting the one side and serial-parallel converted into N (where N is a natural number of 2 or more) series is supplied from the external circuit as the image signal. N image signal terminals,
Each of the peripheral areas has a portion wired along the one side, and the portions are disposed between the enable circuit and the sampling circuit and are electrically connected to the N image signal terminals. N image signal lines for supplying the N series of image signals to the sampling circuit, respectively.
The enable circuit outputs the sampling circuit drive signal for each of the sampling switches corresponding to a data line group including a group of N data lines among the plurality of data lines. The electro-optical device according to claim 5.   A plurality of enable signal supplying flexible wirings electrically connected to the plurality of enable signal terminals, respectively, and a flexible wiring board connected to the substrate at a side crossing the one side. The electro-optical device according to claim 1.   An electronic apparatus comprising the electro-optical device according to claim 1.

Images