JP3635972B2 - Electro-optical device drive circuit, electro-optical device, and electronic apparatus - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an electro-optical device capable of high-quality display while suppressing the occurrence of so-called ghost and crosstalk, a drive circuit thereof, and an electronic apparatus using the electro-optical device as a display unit.
[0002]
[Prior art]
A driving circuit of a conventional electro-optical device, for example, a liquid crystal device, a data line driving circuit for supplying an image signal, a scanning signal, and the like to a data line, a scanning line, etc. wired in an image display area at a predetermined timing, It is composed of a scanning line driving circuit, a sampling circuit, and the like.
[0003]
Of these, the data line driving circuit generally includes a plurality of latch circuits (shift register circuits), and sequentially shifts the transfer signal supplied at the beginning of the horizontal scanning period in accordance with the clock signal, which is used as the sampling signal. Similarly, the scanning line driving circuit includes a plurality of latch circuits, and sequentially shifts the transfer signal supplied at the beginning of the vertical scanning period according to the clock signal and uses this as the scanning signal. Output. The sampling circuit includes a sampling switch provided for each data line, samples an image signal supplied from the outside according to a sampling signal from the data line driving circuit, and supplies it to each data line. is there.
[0004]
[Problems to be solved by the invention]
However, if sampling signals that should be mutually exclusive are output in an overlapping manner for some reason, an image signal that should be sampled on a certain data line is also sampled on a data line adjacent thereto. As a result, so-called ghost or crosstalk occurs, resulting in a problem that display quality is deteriorated.
[0005]
In particular, recently, in order to cope with the higher frequency of the dot clock, one system image signal is serial-parallel converted (phase expansion) into a plurality of m systems, and these m system image signals are simultaneously converted according to the sampling signal. A technique for sampling and supplying to m data lines has been developed. In such a technique, when sampling signals are output in an overlapping manner, ghost or crosstalk occurs in units of m. Therefore, the deterioration of display quality becomes a more serious problem.
[0006]
The present invention has been made in view of the above-described circumstances, and an object of the present invention is to prevent the overlap of sampling signals output from the data line driving circuit, and to display quality caused by ghosts and crosstalk. It is an object to provide a drive circuit for an electro-optical device that suppresses the decrease in the electro-optical device, an electro-optical device, and an electronic apparatus using the electro-optical device for a display unit.
[0007]
[Means for Solving the Problems]
In order to achieve the above object, in the drive circuit of the electro-optical device according to the present invention, the substrate includes a plurality of scanning lines, a plurality of data lines, and the switching elements connected to the scanning lines and the data lines. A drive circuit of an electro-optical device having a pixel electrode connected to the switching element, a plurality of unit circuits that sequentially shift and output an input signal according to a clock signal, and a plurality of unit circuits Each is provided corresponding to each, and the active period of the signal output from the corresponding unit circuit is limited according to the limit signal and output as a sampling signal, while the pulse width is limited corresponding to the own stage In the first case where the active period of the signal and the active period of the signal whose pulse width is limited corresponding to the subsequent stage overlap, regardless of the limited signal, A pulse width limiter circuit that deactivates the output signal of the unit circuit corresponding to its own stage and outputs it as a sampling signal, and is provided corresponding to each of the data lines, each according to the sampling signal by the pulse width limiter circuit A switch for sampling an image signal and supplying the sampled signal to a corresponding data line.
[0008]
According to the present invention, in principle, the active period of the signal output from each unit circuit is limited according to the limit signal, and this is output as the sampling signal. However, as an exception, in the first case where the active period of the signal whose pulse width is limited corresponding to its own stage and the active period of the signal whose pulse width is limited corresponding to its subsequent stage overlap, Regardless of the limiting signal that limits the pulse width, the output signal of the unit circuit corresponding to the own stage is made inactive and is output as a sampling signal. For this reason, in principle and exceptionally, the overlap of the active periods in each sampling signal is prevented beforehand. Therefore, if the image signal is sampled according to such a sampling signal, a situation in which the same image signal is sampled on different data lines can be avoided, so that occurrence of so-called ghost or crosstalk can be suppressed.
[0009]
Here, in the present invention, the limit signal is supplied in a plurality of series, and one of the limit signals corresponds to one of the plurality of unit circuits, and is supplied corresponding to the own stage. A detection circuit that detects an overlap between a limit signal and a limit signal supplied corresponding to a subsequent stage, wherein the pulse width limit circuit detects a case where an overlap is detected by the detection circuit; It is desirable to do so. According to this configuration, when an overlap between the limit signal supplied corresponding to the own stage and the limit signal supplied corresponding to the subsequent stage is detected, the output signal of the unit circuit corresponding to the own stage is Since the signal is rendered inactive and is output as a sampling signal corresponding to its own stage, it is possible to prevent the active periods from overlapping in each sampling signal.
[0010]
In order to achieve such a specific configuration, in the present invention, the detection circuit performs a logical product or negation of a limit signal supplied corresponding to its own stage and a limit signal supplied corresponding to its subsequent stage. A first gate circuit for outputting, and the pulse width limiting circuit includes a signal output from the unit circuit of the own stage, a limiting signal supplied corresponding to the own stage, and an output from the first gate circuit It is desirable to include a second gate circuit that outputs a logical product with the signal or its negation. By doing so, the configuration becomes relatively simple, and it becomes easy to form the constituent elements of the first and second gate circuits in a common process with the switch for sampling the image signal and the element for driving the pixel.
[0011]
Further, in the present invention, the limit signal is supplied in a plurality of series, and one of the limit signals corresponds to one of the plurality of unit circuits, and includes a sampling signal corresponding to the own stage, and a subsequent stage. And a detection circuit that detects an overlap with a limit signal supplied corresponding to the first signal, and the pulse width limit circuit may determine that the overlap is detected by the detection circuit as the first case. desirable. According to this configuration, when an overlap between the sampling signal corresponding to the own stage and the limit signal supplied corresponding to the subsequent stage is detected, the output signal of the unit circuit corresponding to the own stage becomes inactive. Thus, since this is output as a sampling signal corresponding to its own stage, overlapping of the active periods in each sampling signal is prevented.
[0012]
In order to achieve such a specific configuration, in the present invention, the detection circuit outputs a logical product of a sampling signal corresponding to its own stage and a limit signal supplied corresponding to its subsequent stage, or a negative result thereof. The pulse width limiting circuit includes a logic of a signal output from the unit circuit of its own stage, a limiting signal supplied corresponding to its own stage, and an output signal of the first gate circuit It would be desirable to include a second gate circuit that outputs a product or its negation. By doing so, the configuration becomes relatively simple, and it becomes easy to form the constituent elements of the first and second gate circuits in a common process with the switch for sampling the image signal and the element for driving the pixel.
[0013]
On the other hand, in the present invention, the pulse width limiting circuit includes a detection circuit that detects an overlap between an active period of a signal whose pulse width is limited corresponding to its own stage and an active period of a sampling signal corresponding to a subsequent stage. The pulse width limiting circuit preferably uses the first case when an overlap is detected by the detection circuit. According to this configuration, when an overlap between the active period of the signal whose pulse width is limited corresponding to the own stage and the active period of the sampling signal corresponding to the subsequent stage is detected, the unit circuit corresponding to the own stage Since the output signal is made inactive and is output as a sampling signal corresponding to its own stage, the overlap of the active periods in each sampling signal is prevented without monitoring the limit signal.
[0014]
In order to achieve such a specific configuration, in the present invention, the detection circuit performs a logical sum or negation of an active period of a signal whose pulse width is limited corresponding to its own stage and a sampling signal corresponding to the subsequent stage. It is desirable to include an output gate circuit. By doing so, the configuration becomes relatively simple, and it becomes easy to form the constituent elements of the first and second gate circuits in a common process with the switch for sampling the pixel signal and the element for driving the pixel.
[0015]
By the way, in the present invention, the pulse width limiting circuit further exceeds the active period of the signal whose pulse width is limited corresponding to the own stage and the active period of the signal whose pulse width is limited corresponding to the preceding stage. Even in the second case of wrapping, it is desirable to deactivate the output signal of the unit circuit corresponding to its own stage regardless of the limit signal. This is because, even with such a configuration, as in the first case, it is possible to prevent overlap of active periods in the respective sampling signals.
[0016]
In the present invention, it is also desirable that the plurality of unit circuits can shift the input signal in both directions. Accordingly, it is possible to display a normal rotation image and a reverse image by changing the shift direction according to the use of the electro-optical device.
[0017]
Further, in the present invention, the image signal is expanded on the time axis and converted into m (m is an integer of 2 or more) lines, and the data lines are blocked every m lines. It is preferable that the switches corresponding to the m data lines that are blocked are simultaneously driven by one sampling signal. According to this, it is possible to cope with the increase in the frequency of the dot clock without increasing the performance of a switch or the like for sampling the image signal, and it is possible to increase the display contrast.
[0018]
In addition, in the present invention, it is preferable that the switch is of a complementary type, and the pulse width limiting circuit supplies normal and inverted sampling signals to the complementary switch, respectively. According to this, since the input impedance of the sampling switch is increased, even if m sampling switches are driven simultaneously by one sampling signal, the pulse width limiting circuit is provided with a high driving capability. You don't have to.
[0019]
In order to achieve the above object, the electro-optical device according to the present invention is driven by a drive circuit of the electro-optical device. According to this, high-quality display without ghost and crosstalk becomes possible.
[0020]
Here, in the present invention, one of the pair of substrates is interposed between the pixel electrode arranged in a matrix and the pixel electrode and the data line, and is supplied to the scanning line. It is desirable to further include a transistor that opens and closes in accordance with the scanning signal. According to this, since the on-pixel and the off-pixel can be electrically separated by the transistor, the contrast and response are good, and high-definition display is possible.
[0021]
Furthermore, in order to achieve the above object, the electric apparatus according to the present invention is characterized by including the above electro-optical device, so that high-quality display without ghosting and crosstalk becomes possible.
[0022]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0023]
<First Embodiment>
First, the electro-optical device according to the first embodiment of the present invention will be described taking a liquid crystal device using liquid crystal as an electro-optical material as an example.
[0024]
<Overall configuration of liquid crystal device>
FIG. 1 is a block diagram showing an electrical configuration of the liquid crystal device. As shown in this figure, the liquid crystal device includes a liquid crystal panel 100, a timing generator 200, and an image signal processing circuit 300. Among these, the timing generator 200 outputs a timing signal, a control signal, etc. (described later if necessary) used in each unit. The S / P conversion circuit 302 in the image signal processing circuit 300 receives a single image signal Video and converts it into six image signals, which are serial-parallel converted and output. Here, the reason for serial-parallel conversion of the image signal into six systems is that in the sampling circuit 150, the image signal to the source region of a thin film transistor (hereinafter referred to as TFT) constituting the sampling switch 151 is supplied. This is because the application time is lengthened to sufficiently secure the sampling time and charge / discharge time.
[0025]
On the other hand, the amplifying / inverting circuit 304 inverts an image signal that needs to be inverted among the serial-parallel converted image signals, and then amplifies the image signals appropriately and parallels them to the liquid crystal panel 100 as image signals VID1 to VID6. To supply. As for whether or not to invert, in general, whether the data signal application method is (1) polarity inversion in units of scanning lines 112, (2) polarity inversion in units of data lines 114, or (3) It is determined depending on whether the polarity is inverted in units of pixels, and the inversion period is set to one horizontal scanning period or a dot clock period. However, in the present embodiment, for convenience of explanation, (1) the case of polarity inversion in units of 112 scanning lines will be described as an example, but the present invention is not limited to this. Here, the polarity inversion in the present embodiment means that the voltage level is alternately inverted between the positive polarity and the negative polarity with reference to the amplitude center potential of the image signal. Further, the timing of supplying the six image signals VID1 to VID6 to the liquid crystal panel 100 is the same in the liquid crystal device shown in FIG. 1, but may be shifted sequentially in synchronization with the dot clock. The sampling circuit that sequentially samples six image signals.
[0026]
<Configuration of LCD panel>
Next, the electrical configuration of the liquid crystal panel 100 will be described. As will be described later, the liquid crystal panel 100 has a structure in which an element substrate and a counter substrate are pasted with their electrode formation surfaces facing each other. Among them, in the element substrate, a plurality of scanning lines 112 are formed in parallel along the X direction in the drawing, and a plurality of data lines are parallel along the Y direction orthogonal thereto. 114 is formed. At each intersection of the scanning line 112 and the data line 114, the gate electrode of the TFT 116 serving as a switch for controlling each pixel is connected to the scanning line 112, while the source electrode of the TFT 116 is connected to the data line 114. In addition to being connected, the drain electrode of the TFT 116 is connected to the pixel electrode 118. Each pixel includes a pixel electrode 118, a common electrode (described later) formed on the counter substrate, and a liquid crystal sandwiched between these electrodes. As a result, each of the scanning line 112 and the data line 114 Corresponding to the intersections, they are arranged in a matrix. In addition to this, a storage capacitor (not shown) may be formed in parallel with respect to the liquid crystal sandwiched between the pixel electrode 118 and the common electrode for each pixel, as viewed electrically.
[0027]
The drive circuit 120 is composed of at least a scanning line drive circuit 130, a data line drive circuit 140, and a sampling circuit 150. As will be described later, the drive circuit 120 is on the opposing surface of an element substrate made of glass having transparency and insulation. , Formed around the periphery of the display area. Here, since the constituent elements of the driving circuit 120 are configured by combining the TFT 116 for driving the pixel and the P-channel TFT and the N-channel TFT formed by a common manufacturing process, the manufacturing efficiency is improved and the manufacturing cost is increased. Reduction, uniform device characteristics, and the like.
[0028]
<Configuration of data line driving circuit>
Next, the data line driving circuit 140 according to the present embodiment will be described. The data line driving circuit 140 sequentially shifts the transfer start pulse DX-R or DX-L supplied at the beginning of the horizontal scanning period in accordance with the clock signal CLX and its inverted clock signal CLXINV, thereby sampling signals S1 to Sn. Are output in a predetermined order.
[0029]
FIG. 2 is a block diagram showing a configuration of the data line driving circuit 140. In this figure, a clock signal CLX, its inverted clock signal CLXINV, a transfer start pulse DX-R (DX-L), and enable signals (pulse width limit signals) ENB1 and ENB2 are all imaged by the timing generator 200 in FIG. It is supplied in synchronization with the signals VID1 to VID6. Actually, signals obtained by converting a low logic amplitude signal supplied from the timing generator 200 into a high logic amplitude signal by a level shifter (not shown) are used as these signals. The reason for converting the logic amplitude in this way is that the timing generator 200 that supplies various signals to the liquid crystal panel 100 is generally composed of a CMOS circuit, and its output voltage is about 3 to 5 V, whereas the data line This is because the constituent elements of the driving circuit 140 are TFTs formed by the same process as the TFTs 116 for driving the pixels, and therefore a relatively high operating voltage of about 12 V is required.
[0030]
The data line driving circuit 140 includes latch circuits 1430 connected to (n + 1) stages, and one latch circuit 1430 has a level transition (falling, rising) of the clock signal CLX and its inverted clock signal. In some cases, the input level immediately before that is latched and output, and also supplied as an input signal to the latch circuit 1430 located in the subsequent stage.
[0031]
Here, each latch circuit 1430 can transfer in both directions in the R direction and the L direction in the figure. In the case of R direction transfer, a transfer start pulse DX-R is input from the left side of the latch circuit 1430. In the case of transfer in the L direction, the transfer start pulse DX-L is input from the right side of the latch circuit 1430. For this reason, the latter stage means the right side in the case of R direction transfer and the left side in the case of L direction transfer. In order to drive the data line driving circuit 140 bidirectionally, if n is configured with an odd number, there is no need to switch the enable signals ENB1 and ENB2 depending on the transfer direction, and the load on the external circuit can be reduced.
[0032]
As a specific configuration of the latch circuit 1430, for example, the configuration shown in FIG. In this figure, the transfer control signal R is active in the case of R-direction transfer and permits the operation of the clocked inverter 1444, and the transfer control signal L is active in the case of L-direction transfer. This signal permits the operation of the clocked inverter 1454. The odd-numbered clocked inverter 1432 captures and inverts the input signal at the rising edge of the clock signal CLX (falling edge of the inverted clock signal CLXINV) and holds it until the next rising edge. On the contrary, the inverter 1436 takes in and inverts the input signal at the rising edge of the inverted clock signal CLXINV (falling edge of the clock signal CLX) and holds it until the next rising edge. Note that in the even stages, the relationship between the input clock signal CLX and the inverted clock signal CLXINV is replaced with that in the odd stages, so that the timings of capturing and holding the clocked inverters 1432 and 1436 in the even stages are changed. Also, each is replaced with an odd-numbered one.
[0033]
In such a configuration, in the case of R direction transfer, the operation of the clocked inverter 1444 is permitted by the transfer control signal R, but the operation of the clocked inverter 1454 is prohibited. The inverted signal is inverted by the inverter 1444 to be an output signal of the latch circuit 1430, and the inverted signal is fed back to the input of the clocked inverter 1436. At this time, the odd-numbered clocked inverter 1432 captures the input signal at the rising edge of the clock signal CLX, while the subsequent even-numbered clocked inverter 1432 captures the input signal at the rising edge of the inverted clock signal CLXINV. The signal S (i + 1) ′ output from the even-stage clocked inverter 1444 is delayed by a half cycle of the clock signal CLX (inverted clock signal CLXINV) from the signal Si ′ output from the preceding clocked inverter 1444. Will be. Therefore, the signals S1 ′ to Sn ′ output from the first to n-th latch circuits 1430 respectively shift the transfer start pulse DX-R input first for half a cycle of the clock signal CLX. Will be.
[0034]
On the other hand, in the case of L-direction transfer, the operation of the clocked inverter 1454 is permitted by the transfer control signal L, but the operation of the clocked inverter 1444 is prohibited, so that the output of the clocked inverter 1436 is output by the clocked inverter 1454. The inverted signal is output to the latch circuit 1430, and the inverted signal is fed back to the input of the clocked inverter 1432. Therefore, the equivalent circuit of the latch circuit 1430 in the L-direction transfer is obtained by horizontally inverting the one in the R-direction transfer, so that the signals output from the (n + 1) -th to second-stage latch circuits 1430 in the end. Sn ′ to S1 ′ are obtained by sequentially shifting the transfer start pulse DX-L input first for each half cycle of the clock signal CLX.
[0035]
Note that i is a generalized description of the latch circuit 1430 of the first to (n + 1) th stages. Further, if there is no need to perform bi-directional transfer, for example, if only L-direction transfer is performed, the latch circuit 1430 is fixed by the inverter 1434 as shown in FIG. 3B. It is good also as a structure. Further, the latch circuit 1430 is an example of a unit circuit. Besides this, a flip-flop, a capacitor circuit, or the like may be used, or these may be used in appropriate combination.
[0036]
Returning to FIG. 2 again, the signal Si ′ (the signal output from the i-th stage latch circuit 1430 in the case of R-direction transfer, or the (i + 1) -th stage latch circuit in the case of L-direction transfer. 1430) is supplied to the first input terminal of the 3-input NAND circuit 1464. Further, the enable signal ENB1 is supplied to the second input terminal of the NAND circuit 1464 if i is an odd number, while the enable signal ENB2 is supplied if i is an even number. Further, the third input terminal of the NAND circuit 1464 is supplied with the output signal of the NAND circuit 1462, specifically, the NAND signal of the enable signals ENB1 and ENB2. Here, the enable signals ENB1 and ENB2 are signals used for avoiding the H level simultaneously in the adjacent ones of the signals S1 ′ to Sn ′, and each is a half cycle of the clock signal CLX (inverted clock signal CLXINV). The signals have shorter pulse widths and are essentially non-overlapping signals.
[0037]
An output signal of the NAND circuit 1464 corresponding to each stage is inverted by an inverter 1466, and is output as sampling signals S1 to Sn of the data line driving circuit 140. Note that the inverter 1466 may be provided in a plurality of stages such as one stage, three stages, and five stages.
[0038]
<Sampling circuit>
Returning to FIG. 1 again, the sampling circuit 150 will be described next. The sampling circuit 150 groups six data lines 114 into one group (block), and supplies the image signals VID1 to VID6 to the data lines 114 belonging to these groups in accordance with the sampling signals S1 to Sn, respectively. Is. Specifically, the sampling circuit 150 includes a switch 151 provided for each data line 114. Each switch 151 includes one end of the data line 114 and a signal line to which one of the image signals VID1 to VID6 is supplied. It is configured such that a sampling signal is supplied to its gate while being interposed therebetween.
[0039]
Here, the specific configuration of the switch 151 may be constituted by, for example, an N-channel TFT as shown in FIG. 4A, or a P-channel as shown in FIG. It may be constituted by a type TFT, or may be constituted by a complementary type TFT as shown in FIG. In the configuration shown in FIG. 2, it is assumed that the N-channel TFT shown in FIG. 4A is used. Therefore, when the P-channel TFT is used, the sampling signal Si is used. It is necessary to generate a level-inverted signal SiINV. Further, when a complementary TFT is used, a signal line for supplying a sampling signal Si and its inverted signal SiINV is also required. Further, regardless of the type of TFT used as the switch 151 constituting the sampling circuit 150, the pixel electrode 118 is controlled from the viewpoints of integration, manufacturing cost, element uniformity, and the like as described above. It is desirable to form the TFT 116 by a common manufacturing process.
[0040]
<Scanning line drive circuit>
Next, the scanning line driving circuit 130 will be described. The configuration of the scanning line driving circuit 130 is basically the same as the configuration of the data line driving circuit 140 except that the output signal extraction direction is different from the input signal. It is. That is, the scanning line driving circuit 130 is configured by rotating the data line driving circuit 150 counterclockwise by 90 degrees, and as shown in FIG. 1, the pulse DX-R (DX-L) and the transfer control signal R ( L), a pulse DY-D (DY-U) and a transfer control signal D (U) are input, and instead of the clock signal CLX and its inverted clock signal CLXINV, the clock signal CLY is output every horizontal scanning period. The inverted clock signal CLYINV is input.
[0041]
Here, when the vertical scanning direction is downward, the pulse DY-D is supplied at the beginning of the vertical scanning period, and the transfer control signal D becomes active, while the vertical scanning direction is upward. The pulse DY-U is supplied at the beginning of the vertical scanning period, and the transfer control signal U becomes active. The clock signal CLY, its inverted signal CLYINV, and the pulse DY-U (or DY-D) are supplied in synchronization with the image signals VID1 to VID6 by the timing generator 200 in FIG. Further, both of these signals and the transfer control signal R (L) are converted into high logic amplitude signals by a level shifter (not shown).
[0042]
Further, by setting the frequency of these clock signals low, it is sufficiently possible that the scanning signals supplied to adjacent scanning lines do not substantially overlap with each other. There is no problem even if the configuration is simple with a NAND circuit for narrowing the circuit and an inverter following the NAND circuit.
[0043]
<Operation of First Embodiment>
Next, the operation of the liquid crystal device according to the configuration described above will be described. In the following, for convenience of explanation, the vertical scanning direction is the downward direction, and the horizontal scanning direction is the right (R) direction.
[0044]
In this case, the scanning line driving circuit 130 is supplied with the pulse DY-D at the beginning of the vertical scanning period, sequentially shifted by the clock signal CLY and its inverted clock signal CLYINV, and output to each scanning line 112. As a result, the plurality of scanning lines 112 are selected one line at a time in the downward direction.
[0045]
Further, as shown in FIG. 5, the image signal Video of one system is distributed to the image signals VID1 to VID6 by the image signal processing circuit 300 and is expanded six times with respect to the time axis. Further, at the beginning of a period during which a certain scanning line is selected, that is, at the beginning of the horizontal scanning period, the data line driving circuit 140 is supplied with a transfer start pulse DX-R as shown in FIG.
[0046]
In the normal operation, the enable signals ENB1 and ENB2 are supplied from the timing generator 200 so that the H level (active) periods do not overlap each other as shown in FIG. The output signal 1462 continues to be at H level and does not transition to L level. Therefore, the output of the NAND circuit 1464 depends only on the signal Si and the enable signal ENB1 if i is an odd number, and depends only on the signal Si and the enable signal ENB2 if i is an even number. .
[0047]
For this reason, the signals S1 ′ to Sn ′, that is, the transfer start pulse DX-R supplied first by the first to n-th latch circuit 1430 is changed to a half of the clock signal CLX and its inverted clock signal CLXINV. The signals S1 ′ to Sn ′ that are sequentially shifted every period are limited to the H level period SMPa of the enable signals ENB1 and ENB2, and are sequentially output as sampling signals S1 to Sn as shown in FIG. It becomes.
[0048]
Here, when the sampling signal S1 becomes H level, the image signals VID1 to VID6 are sampled on the six data lines 114 belonging to this group, respectively, and these image signals VID1 to VID6 are selected at the present time. Each of the six pixels intersecting with 112 is written by the TFT 116. Thereafter, when the sampling signal S2 becomes H level, the image signals VID1 to VID6 are sampled on the next six data lines 114, respectively, and these image signals VID1 to VID6 are selected at that time. Each of the six pixels intersecting with 112 is written by the TFT 116.
[0049]
Similarly, when the sampling signals S3, S4,..., Sn sequentially become H level, the image signals VID1 to VID6 are sampled on the six data lines 114 belonging to each sampling signal, respectively, and these image signals VID1 to VID1. VID6 is written in each of the six pixels intersecting the scanning line 112 selected at that time. Thereafter, the next scanning line 112 is selected, the sampling signals S1 to Sn are sequentially output again, and similar writing is repeatedly executed.
[0050]
In such a driving method, the sampling time of the image signal by each switch 151 is six times that of a method in which the data lines 114 are driven one by one, so that a sufficient charge / discharge time is ensured in each pixel. . For this reason, high contrast is achieved. Further, the number of stages of the latch circuit 1430 in the data line driving circuit 140 and the frequency of the clock signal CLX and its inverted clock signal CLXINV are each reduced to 1/6, so that the power consumption is reduced along with the reduction of the number of stages. Will also be planned.
[0051]
By the way, the enable signals ENB1 and ENB2 are generated by the timing generator 200 so that the H level periods do not overlap each other. For some reason, for example, the signal waveform is slowed down due to the capacitance and resistance of the signal line. As shown in FIG. 6, there are cases where they overlap each other in the period OVL due to a delay or a decrease in level shifter capability. In such a case, when the pulse widths of the signals S1 ′ to Sn ′ are simply limited by the enable signals ENB1 and ENB2, the H level periods of the sampling signals S1 to Sn are overlapped to form a group. The image signals VID1 to VID6 to be sampled on the data line 114 belonging to the group are also sampled on the data line 114 belonging to a group adjacent to the group, and as a result, so-called ghost or crosstalk occurs, leading to deterioration in display quality. become. This becomes more remarkable as the number of data lines 114 constituting one group increases.
[0052]
On the other hand, in the present embodiment, when the H levels of the enable signals ENB1 and ENB2 overlap each other in the period OVL, the output signal of the NAND circuit 1462 in FIG. 2 transitions to the L level. The output of the input NAND circuit 1464 is unconditionally at the H level. Therefore, the sampling signal Si obtained by inverting the output of the NAND circuit 1464 by the inverter 1466 is forcibly set to the L level that is inactive even if the signal Si ′ is at the H level. That is, the sampling signals S1 to Sn, for example, the adjacent sampling signals S1 and S2 are not simultaneously at the H level as shown in FIG. For this reason, according to the present embodiment, even if the enable signals ENB1 and ENB2 overlap each other, the sampling signals do not overlap. As a result, the ghost, the crosstalk, etc. can be suppressed, so that the display quality can be prevented from deteriorating. It will be.
[0053]
Furthermore, the H level period in the sampling signal can be expanded without being aware of the overlap between the enable signals ENB1 and ENB2 at the time of design. That is, in the configuration in which the pulse widths of the signals S1 ′ to Sn ′ are simply limited by the enable signals ENB1 and ENB2, if the H level period of the enable signals ENB1 and ENB2 is expanded, the possibility that the sampling signals overlap accordingly is high. However, according to the present embodiment, it is possible to extend the H level period in the enable signals ENB1 and ENB2 while preventing the sampling signals from overlapping. For this reason, the period during which the sampling signal is at the H level can be extended. In fact, in FIG. 6, the period SMPb in which the sampling signal is at the H level is longer than the period SMPa in FIG. Therefore, according to the present embodiment, as the H level period of the sampling signal increases, the sampling time by each switch 151 also increases, so that the charge / discharge time in each pixel is further ensured. For this reason, higher contrast is also achieved.
[0054]
In the first embodiment, the horizontal scanning direction has been described as the right (R) direction. Conversely, when the left scanning direction is set to the left (L) direction, each latch circuit 1430 has a configuration for transferring in the R direction. It will be the one flipped left and right. For this reason, the only difference is that the sampling signals are output in the order of Sn, S (n−1),..., S2, S1, and therefore the description of the operation is omitted. The same applies when the vertical scanning period is set to the upward direction.
[0055]
Second Embodiment
In the first embodiment described above, the pulse width of the signal output from the latch circuit is normally limited to the H level period of the enable signal ENB1 or ENB2, but the H level of the enable signals ENB1 and ENB2 is output. When the periods overlap, the output signal of the latch circuit is forcibly set to the L level to prevent the sampling signals from overlapping and suppress the occurrence of ghosts, etc. The invention can suppress the occurrence of ghosts even in other configurations. Therefore, a second embodiment different from the first embodiment will be described.
[0056]
FIG. 7 is a block diagram showing the configuration of the data line driving circuit according to the second embodiment. The data line driving circuit 140 shown in this figure is different from the first embodiment shown in FIG. 2 in that the signal supplied to the third input terminal of the NAND circuit 1464 is the output signal of the 2-input NAND circuit 1468. In that point. Here, one input terminal of the NAND circuit 1468 is supplied with an enable signal ENB2 if i is an odd number, and is supplied with an enable signal ENB1 if i is an even number. A sampling signal Si is fed back and supplied to the other input terminal of the NAND circuit 1468.
[0057]
For the sampling signal Si in which i is an odd number, the enable signal ENB2 is a signal that defines the H level period of the sampling signal S (i + 1) in the case of R direction transfer, and the sampling signal S ( It is a signal that defines the H level period of i-1). That is, in any transfer direction, the enable signal ENB2 is a signal that defines an H level period in the sampling signals corresponding to the preceding stage and the succeeding stage of the sampling signal Si. Similarly, for the sampling signal Si in which i is an even number, the enable signal ENB1 is a signal that defines an H level period in the sampling signals corresponding to the preceding stage and the subsequent stage of the sampling signal Si.
[0058]
Therefore, for the conventional configuration in which the pulse widths of the signals S1 ′ to Sn ′ are simply limited by the enable signals ENB1 and ENB2, there are an H level period of the sampling signal Si in which i is an odd number and an H level period of the enable signal ENB2. The overlap and the H level period of the sampling signal Si where i is an even number and the H level period of the enable signal ENB1 overlap the sampling signal Si and the sampling signal corresponding to the preceding stage or the subsequent stage. This means that the H level periods of each other overlap.
[0059]
On the other hand, in this embodiment, when the H level period of the sampling signal Si in which i is an odd number and the H level period of the enable signal ENB2 overlap, the output signal of the NAND circuit 1468 corresponding to an odd number is the L level. Therefore, the output of the NAND circuit 1464 that inputs this to the third input terminal is unconditionally at the H level. Similarly, when the H level period of the sampling signal Si in which i is an even number and the H level period of the enable signal ENB1 overlap, the output signal of the NAND circuit 1468 in which i is an even number transitions to the L level. The output of the circuit 1464 is unconditionally at the H level.
[0060]
Accordingly, even in the second embodiment, as in the first embodiment, the sampling signals S1 to Sn obtained by inverting the output of the NAND circuit 1464 by the inverter 1466 do not become the H level at the same time. It is possible to prevent the display quality from being deteriorated due to.
[0061]
<Third Embodiment>
In the first and second embodiments described above, when the enable signal overlaps, or when a certain sampling signal and the enable signal supplied corresponding to the subsequent stage overlap, the sampling signal However, it is possible to prevent the sampling signals from overlapping without monitoring the enable signal. Therefore, a third embodiment for preventing the sampling signals from overlapping without monitoring the enable signal will be described.
[0062]
FIG. 8 is a block diagram showing the configuration of the data line driving circuit according to the third embodiment. As shown in this figure, the data line driving circuit 140 according to the present embodiment limits the pulse width of the signal Si ′ where i is an odd number according to the enable signal ENB1, while the signal Si ′ where i is an even number. In addition to a NAND circuit 1472 that restricts the pulse width of 1 in accordance with the enable signal ENB 2, a three-input NOR circuit 1474 and inverters 1476, 1478 are provided corresponding to each NAND circuit 1472.
[0063]
Here, the first input terminal of the NOR circuit 1474 is supplied with the sampling signal S (i−1) which is the preceding stage in the R direction transfer (the latter stage in the L direction transfer), and the second input terminal Is supplied with the output signal of the NAND circuit 1472, and further supplied with the sampling signal S (i + 1) which is the latter stage in the case of the R direction transfer (the former stage in the case of the L direction transfer). Has been. However, in the figure, since there is no corresponding signal at the first input terminal of the NOR circuit 1474 located at the leftmost end and the third input terminal of the NOR circuit 1474 located at the rightmost end, the L level signal Is supplied.
[0064]
Then, the negative OR signal by each NOR circuit 1474 is forwardly rotated by sequentially passing through inverters 1476 and 1478, and this is output as sampling signals S1 to Sn.
[0065]
In such a configuration, the pulse widths of the output signals Si ′ to Sn ′ of each latch circuit 1430 are normally limited to the H level period of the enable signals ENB1 and ENB2, respectively. The level period does not become H level at the same time.
[0066]
However, when the H level periods of the enable signals ENB1 and ENB2 overlap for some reason, the output signals of the NAND circuits 1472, particularly the output signals of the adjacent NAND circuits 1472, also overlap. According to the third embodiment, when the output signal from the NAND circuit 1472 of the own stage overlaps with the sampling signal of the subsequent stage or the preceding stage, the output of the NOR circuit 1474 is forcibly set to the L level.
[0067]
Therefore, even in the third embodiment, the inverted signals by the inverters 1478, that is, the sampling signals S1 to Sn obtained by normalizing the outputs of the NOR circuits 1474 are simultaneously H as in the first and second embodiments. Since the level is not reached, it is possible to prevent the display quality from being deteriorated due to ghost or crosstalk.
[0068]
In the third embodiment, when the overlap is detected, the enable signals ENB1 and ENB2 are not monitored as in the first and second embodiments, so that an input signal to each NOR circuit 1474 is generated. Various configurations can also be applied. For example, as shown in FIG. 9A, the negative logical product of an input signal and an output signal to each latch circuit 1430 (that is, an output signal from a certain latch circuit and an output signal from a subsequent latch circuit) is 2 It may be obtained by the input type NAND circuit 1482 and used as an input signal to each NOR circuit 1474. Further, as shown in FIG. 5B, a NAND operation of the input signal of each latch circuit 1430, the output signal, and one series of enable signals ENB3 is obtained by a three-input NAND circuit 1484, and this is obtained. An input signal to each NOR circuit 1474 may be used. Further, as shown in FIG. 6C, an analog switch 1486 that opens and closes using the output signal of each latch circuit 1430 as a gate is provided, and an enable signal ENB3 via the analog switch 1486 is input to each NOR circuit 1474. It is good also as a structure supplied to an edge.
[0069]
Here, as shown in FIG. 10, the enable signal ENB3 corresponds to a signal in which the functions of the two systems of the enable signals ENB1 and ENB2 are given to one system, and usually has a notch-shaped L level period. It is. However, for some reason, when the L level period disappears, the H level period is substantially continued, so that the original function of narrowing the H level period of the signal output from the latch circuit 1430 is lost. The NOR circuit 1474 in FIG. 8 prevents the sampling signals S1 to Sn from overlapping. Further, since only one enable signal is required, not only the load on the peripheral circuit can be reduced, but also the external circuit connection terminals and enable signal lines can be reduced, which is advantageous for miniaturization of the liquid crystal device.
[0070]
<Configuration example of liquid crystal panel>
Next, the overall configuration of the liquid crystal panel 100 having the data line driving circuit 140 according to each embodiment described above will be described with reference to FIGS. Here, FIG. 11 is a perspective view showing the configuration of the liquid crystal panel 100, and FIG. 12 is a cross-sectional view taken along the line AA 'in FIG.
[0071]
As shown in these drawings, the liquid crystal panel 100 includes a transparent counter substrate such as glass on which pixel electrodes 118 are formed, an element substrate 101 such as a semiconductor or quartz, and glass on which a common electrode 108 is formed. 102 is bonded with a sealant 104 mixed with a spacer 103 so that the electrode forming surfaces face each other while maintaining a certain gap, and a liquid crystal 105 as an electro-optic material is sealed in this gap It has become. Note that the sealant 104 is formed along the periphery of the counter substrate 102, but a part thereof is opened to enclose the liquid crystal 105. For this reason, after the liquid crystal 105 is sealed, the opening is sealed with the sealing material 106.
[0072]
Here, the data line driving circuit 140 and the sampling circuit 150 described above are formed on the opposite surface of the element substrate 101 and on the outer side of the sealing material 104 to drive the data line 114 extending in the Y direction. It has a configuration. Further, a plurality of external circuit connection terminals 107 are formed on this side, and various signals from the timing generator 200 and the image signal processing circuit 300 are input. Further, two scanning line driving circuits 130 are formed on two sides adjacent to the one side, and the scanning lines 112 extending in the X direction are driven from both sides. Note that if the delay of the scanning signal supplied to the scanning line 112 does not become a problem, the scanning line driving circuit 130 may be formed on only one side. In addition, a precharge circuit for precharging each data line 114 to a predetermined potential at a timing preceding the image signal is formed in the element substrate 101 in order to reduce the load of writing the image signal to the data line 114. Also good.
[0073]
On the other hand, the common electrode 108 of the counter substrate 102 is electrically connected to the element substrate 101 by a conductive material provided in at least one of the four corners of the bonding portion with the element substrate 101. In addition, the counter substrate 102 is provided with color filters arranged in a stripe shape, a mosaic shape, a triangle shape, or the like according to the use of the liquid crystal panel 100, and secondly, for example, chromium. A light shielding film such as resin black in which a metal material such as nickel or nickel, carbon, titanium, or the like is dispersed in a photoresist is provided. In the case of color light modulation, a light shielding film is provided on the counter substrate 102 without forming a color filter.
[0074]
In addition, the opposing surfaces of the element substrate 101 and the counter substrate 102 are each provided with an alignment film (not shown) that is rubbed in a predetermined direction, and a polarizing plate corresponding to the alignment direction is provided on each back side thereof. (Not shown) are provided. However, if a polymer dispersion type liquid crystal dispersed as fine particles in a polymer is used as the liquid crystal 105, the above-described alignment film, polarizing plate, etc. are not required. As a result, the light utilization efficiency is increased. This is advantageous in terms of reducing power consumption.
[0075]
Instead of forming part or all of the peripheral circuits such as the drive circuit 120 on the element substrate 101, for example, a driving IC chip mounted on a film using a TAB (Tape Automated Bonding) technique is used. It is good also as a structure electrically and mechanically connected through the anisotropic conductive film provided in the predetermined position of 101, and drive IC chip itself is used for the element substrate 101 using COG (Chip On Grass) technology. It is good also as a structure electrically and mechanically connected to this predetermined position via an anisotropic conductive film.
[0076]
<Relationship between the number of conversions and the number of data lines constituting one group>
By the way, in the above description, the sampling circuit 150 simultaneously samples and supplies the image signals VID1 to VID6 converted into six systems to the six data lines 114 as a group, and the image signals VID1 to VID1. Although the application of VID 6 is performed sequentially for each data line group, the number of conversions and the number of data lines applied simultaneously (that is, the number of data lines constituting one group) are not limited to “6”. For example, if the response speed of the switch 151 in the sampling circuit 150 is sufficiently high, the image signal is serially transmitted to one signal line without being converted into parallel and sequentially sampled for each data line 114. It may be configured. Further, assuming that the number of conversions and the number of data lines to be applied simultaneously are “3”, “12”, “24”, etc., three-line conversion, twelve, twenty-four data lines, etc. A configuration may be adopted in which image signals supplied in parallel by system conversion, 24-system conversion, and the like are supplied simultaneously. Note that the number of conversions and the number of data lines to be applied simultaneously are multiples of 3 in order to simplify the control, the circuit, etc., because the color image signal is composed of signals related to the three primary colors. preferable.
[0077]
<Configuration of element substrate>
Further, in each embodiment, the element substrate 101 of the liquid crystal panel 100 is configured by a transparent insulating substrate such as glass, and a silicon thin film is formed on the substrate, and a source, a drain, and a channel are formed on the thin film. Although it has been described that the formed TFT constitutes the switching element (TFT 116) of the pixel and the element of the driving circuit 120, the present invention is not limited to this.
[0078]
For example, the element substrate 101 is constituted by a semiconductor substrate, and the switching element of the pixel or the element of the driving circuit 120 is constituted by an insulated gate field effect transistor in which a source, a drain, and a channel are formed on the surface of the semiconductor substrate. Also good. When the element substrate 101 is formed of a semiconductor substrate in this manner, it cannot be used as a transmission type electro-optical device. Therefore, the pixel electrode 118 is formed of aluminum or the like and used as a reflection type. Alternatively, the element substrate 101 may be a transparent substrate and the pixel electrode 118 may be a reflection type.
[0079]
Furthermore, in the above-described embodiment, the switching element of the pixel has been described as a three-terminal element typified by a TFT, but may be configured by a two-terminal element such as a diode. However, when a two-terminal element is used as a pixel switching element, the scanning line 112 is formed on one substrate, the data line 114 is formed on the other substrate, and the two-terminal element is connected to the scanning line 112 or the data line. It is necessary to form it between any one of 114 and the pixel electrode 118. In this case, the pixel includes a pixel electrode 118 to which a two-terminal element is connected, a signal line (one of the data line 114 or the scanning line 112) formed on the counter substrate, and a liquid crystal sandwiched therebetween. Will be.
[0080]
Furthermore, as an electro-optical material, in addition to liquid crystal, an electroluminescence element or the like can be used for a display device that performs display by the electro-optical effect. That is, the present invention can be applied to all electro-optical devices having a configuration similar to that of the liquid crystal device described above.
[0081]
<Electronic equipment>
Next, the case where the above-described liquid crystal device is applied to various electronic devices will be described. In this case, as shown in FIG. 13, the electronic apparatus mainly includes a display information output source 1000, a display information processing circuit 1002, a power supply circuit 1004, a liquid crystal panel 100, a drive circuit 120, and a timing generator 200. The Needless to say, the drive circuit 120 may be built in the liquid crystal panel 100. Among them, the display information output source 1000 includes a memory such as a ROM (Read Only Memory) and a RAM (Random Access Memory), a storage unit such as various disks, a tuning circuit that tunes and outputs an image signal, and the like. Display information such as an image signal of a predetermined format is supplied to the display information processing circuit 1002 on the basis of various clock signals generated by. Next, the display information processing circuit 1002 includes various well-known circuits such as a rotation circuit, a gamma correction circuit, and a clamp circuit in addition to the S / P conversion circuit 302 and the amplification / inversion circuit 304 described above. The image signal is supplied to the drive circuit 120 together with the clock signal CLK. The power supply circuit 1004 supplies predetermined power to each component. In FIG. 13, the clock signal CLK is supplied via the display information processing circuit 1002, but as shown in FIG. 1, the clock signal CLK is directly supplied from the timing generator 200 to the drive circuit 120, and the image processing circuit 300. It goes without saying that the display information processing circuit 1002, which is a higher-order configuration, may operate in synchronization with the clock signal from the timing generator 200.
[0082]
Next, some examples in which the above-described liquid crystal device is used in a specific electronic device will be described.
[0083]
<Part 1: Projector>
First, a projector using this liquid crystal panel as a light valve will be described. FIG. 14 is a plan view showing the configuration of the projector. As shown in this figure, a lamp unit 1102 including a white light source such as a halogen lamp is provided inside the projector 1100. The projection light emitted from the lamp unit 1102 is separated into three primary colors of RGB by three mirrors 1106 and two dichroic mirrors 1108 disposed therein, and a liquid crystal panel as a light valve corresponding to each primary color 100R, 100B and 100G, respectively. Here, the light of B color has a long optical path as compared with other R colors and G colors. Therefore, in order to prevent the loss, the light of B color passes through a relay lens system 1121 including an incident lens 1122, a relay lens 1123, and an exit lens 1124. Be guided.
[0084]
The configurations of the liquid crystal panels 100R, 100B, and 100G are the same as those of the liquid crystal panel 100 described above, and are driven by R, G, and B primary color signals supplied from an image signal processing circuit (not shown). is there. The light modulated by these liquid crystal panels enters the dichroic prism 1112 from three directions. In the dichroic prism 1112, the R and B light beams are refracted at 90 degrees, while the G light beam goes straight. Therefore, as a result of the synthesis of the images of the respective colors, a color image is projected onto the screen 1120 via the projection lens 1114.
[0085]
Here, paying attention to the display images by the liquid crystal panels 100R, 100B, and 100G, the display image by the liquid crystal panel 100G needs to be horizontally reversed with respect to the display images by the liquid crystal panels 100R and 100B. Therefore, the horizontal scanning direction is in the opposite direction between the liquid crystal panel 100G and the liquid crystal panels 100R and 100B. Since light corresponding to the primary colors R, G, and B is incident on the liquid crystal panels 100R, 100B, and 100G by the dichroic mirror 1108, it is not necessary to provide a color filter.
[0086]
<Part 2: Mobile computer>
Next, an example in which the liquid crystal panel is applied to a mobile personal computer will be described. FIG. 15 is a perspective view showing the configuration of this personal computer. In the figure, a computer 1200 includes a main body 1204 having a keyboard 1202 and a liquid crystal display unit 1206. The liquid crystal display unit 1206 is configured by adding a backlight to the back surface of the liquid crystal panel 100 described above.
[0087]
<Part 3: Mobile phone>
Further, an example in which this liquid crystal panel is applied to a mobile phone will be described. FIG. 16 is a perspective view showing the configuration of this mobile phone. In the figure, a mobile phone 1300 includes a liquid crystal panel 100 along with a plurality of operation buttons 1302, an earpiece 1304, and a mouthpiece 1306. The liquid crystal panel 100 is also provided with a backlight on the back as necessary.
[0088]
In addition to the electronic devices described with reference to FIGS. 14 to 16, the electronic devices include a liquid crystal television, a viewfinder type, a monitor direct view type video tape recorder, a car navigation device, a pager, an electronic notebook, a calculator, a word processor. , Workstations, videophones, POS terminals, devices with touch panels, and the like. Needless to say, the liquid crystal device and the electro-optical device of each embodiment can be applied to these various electronic devices.
[0089]
【The invention's effect】
As described above, according to the present invention, since sampling signals output from the data line driving circuit are prevented from overlapping, it is possible to suppress deterioration in display quality due to ghost or crosstalk. Become.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an overall configuration of a liquid crystal device to which a drive circuit according to a first embodiment of the present invention is applied.
FIG. 2 is a block diagram showing a configuration of a data line driving circuit in the liquid crystal device.
FIGS. 3A and 3B are circuit diagrams showing configuration examples of latch circuits of the data line driving circuit, respectively.
FIGS. 4A to 4C are circuit diagrams each showing a switch configuration of a sampling circuit in the liquid crystal device.
FIG. 5 is a timing chart for explaining the operation of the data line driving circuit;
FIG. 6 is a timing chart for explaining the operation of the data line driving circuit;
FIG. 7 is a block diagram showing a configuration of a data line driving circuit according to a second embodiment of the present invention.
FIG. 8 is a block diagram showing a configuration of a data line driving circuit according to a third embodiment of the present invention.
FIG. 9 is a block diagram showing a configuration around a latch circuit applicable to the present invention.
FIG. 10 is a timing chart for explaining an operation when a signal ENB3 is used.
FIG. 11 is a perspective view showing a structure of the liquid crystal panel.
FIG. 12 is a partial cross-sectional view for explaining the structure of the liquid crystal panel.
FIG. 13 is a block diagram showing a schematic configuration of an electronic apparatus to which the liquid crystal device is applied.
FIG. 14 is a cross-sectional view illustrating a configuration of a projector as an example of an electronic apparatus to which the liquid crystal device is applied.
FIG. 15 is a perspective view illustrating a configuration of a personal computer as an example of an electronic apparatus to which the liquid crystal device is applied.
FIG. 16 is a perspective view illustrating a configuration of a mobile phone as an example of an electronic apparatus to which the liquid crystal device is applied.
[Explanation of symbols]
100 …… LCD panel
101 …… Element substrate
102 ... Counter substrate
116 …… TFT
120 …… Drive circuit
130... Scanning line driving circuit
140... Data line driving circuit
150 …… Sampling circuit
151 …… Switch
1430 ... Latch circuit
1462, 1468, 1472, 1482, 1484 ... NAND circuit
1474 NOR circuit
1486 …… Analog switch

Claims (14)

A drive circuit for an electro-optical device having a plurality of scanning lines, a plurality of data lines, a switching element connected to each scanning line and each data line, and a pixel electrode connected to the switching element on a substrate Because
A plurality of unit circuits that sequentially shift and output an input signal in accordance with a clock signal, and a plurality of unit circuits are provided corresponding to each of the plurality of unit circuits. While limiting according to the limit signal and outputting as a sampling signal,
In the first case where the active period of the signal whose pulse width is limited corresponding to the own stage and the active period of the signal whose pulse width is limited corresponding to the subsequent stage overlap, regardless of the limiting signal, , A pulse width limiting circuit that deactivates the output signal of the unit circuit corresponding to its own stage and outputs it as a sampling signal;
An electro-optical device comprising: a switch provided corresponding to each of the data lines, each of which includes a switch that samples an image signal according to a sampling signal from the pulse width limiting circuit and supplies the sampled image signal to the corresponding data line. Device drive circuit. The limit signal is supplied in a plurality of series, of which one series of limit signals corresponds to one of a plurality of unit circuits,
It has a detection circuit that detects an overlap between a limit signal supplied corresponding to its own stage and a limit signal supplied corresponding to its subsequent stage,
2. The drive circuit for an electro-optical device according to claim 1, wherein the pulse width limiting circuit sets the first case when an overlap is detected by the detection circuit. The detection circuit includes a first gate circuit that outputs a logical product of a limit signal supplied corresponding to the own stage and a limit signal supplied corresponding to the subsequent stage or the negation thereof.
The pulse width limiting circuit outputs a logical product or negation of a signal output from the unit circuit of its own stage, a limiting signal supplied corresponding to its own stage, and an output signal of the first gate circuit. 3. The drive circuit for an electro-optical device according to claim 2, further comprising: a second gate circuit that performs the operation. The limit signal is supplied in a plurality of series, and one of the limit signals corresponds to one of the plurality of unit circuits,
It has a detection circuit that detects the overlap between the sampling signal corresponding to its own stage and the limit signal supplied corresponding to the subsequent stage,
2. The drive circuit for an electro-optical device according to claim 1, wherein the pulse width limiting circuit sets the first case when an overlap is detected by the detection circuit. The detection circuit includes a first gate circuit that outputs a logical product of a sampling signal corresponding to its own stage and a limit signal supplied corresponding to a subsequent stage or its negation,
The pulse width limiting circuit outputs a logical product or negation of a signal output from the unit circuit of its own stage, a limiting signal supplied corresponding to its own stage, and an output signal of the first gate circuit. 5. The drive circuit for an electro-optical device according to claim 4, further comprising a second gate circuit that performs the operation. The pulse width limiting circuit is
It has a detection circuit that detects the overlap between the active period of the signal whose pulse width is limited corresponding to its own stage and the active period of the sampling signal corresponding to the subsequent stage,
2. The drive circuit for an electro-optical device according to claim 1, wherein the pulse width limiting circuit sets the first case when an overlap is detected by the detection circuit. The detection circuit includes:
7. The electro-optical device according to claim 6, further comprising a gate circuit that outputs a logical sum or negation of an active period of a signal whose pulse width is limited corresponding to the own stage and a sampling signal corresponding to the subsequent stage. Drive circuit. The pulse width limiting circuit further includes:
Even in the second case where the active period of the signal whose pulse width is limited corresponding to its own stage and the active period of the signal whose pulse width is limited corresponding to the previous stage overlap, regardless of the limiting signal, 2. The drive circuit for an electro-optical device according to claim 1, wherein an output signal of the unit circuit corresponding to the own stage is made inactive. 2. The drive circuit for an electro-optical device according to claim 1, wherein the plurality of unit circuits are capable of shifting the input signal in both directions. The image signal is expanded on the time axis and converted to m (m is an integer of 2 or more) lines,
The data lines are blocked every m lines,
2. The drive circuit for an electro-optical device according to claim 1, wherein the switches corresponding to the m data lines blocked are simultaneously driven by one sampling signal. 11. The electro-optical device according to claim 1, wherein the switch is a complementary type, and the pulse width limiting circuit supplies normal and inverted sampling signals to the complementary type switch, respectively. Driving circuit. An electro-optical device driven by the drive circuit for the electro-optical device according to claim 1. One of the pair of substrates is
Pixel electrodes arranged in a matrix;
13. The electro-optical device according to claim 12, further comprising a transistor that is interposed between the pixel electrode and the data line and that opens and closes according to a scanning signal supplied to the scanning line. An electronic apparatus comprising the electro-optical device according to claim 12.

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