JP2004029755A - Electroluminescence display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an EL display device capable of realizing uniform display even when there is dispersion in the characteristics of pixel transistors and capable of removing a blur in a moving picture. <P>SOLUTION: In order to sufficiently charge/discharge the parasitic capacity of a source signal line and to program a prescribed current value on each pixel transistor, it is necessary to output a comparatively large current from a source driver circuit for outputting the current. When the large current is allowed to flow into the source signal line, the large current value is programmed in pixels and a current larger than a required current flows into each EL element 15. When a current of N=10 times is programmed, for instance, the current of 10 times is allowed to flow into the EL element 15 and the EL element 15 emits light at a luminance of ten times. In order to obtain prescribed light emitting luminance, the current flow time into the EL element 15 is shortened to 1/10 of one frame (1F). By this type of driving, the parasitic capacity of the source signal line can be sufficiently charged/discharged and the prescribed light emitting luminance can be obtained. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a self-luminous display panel such as an EL display panel using an organic or inorganic electroluminescence (EL) element. The present invention also relates to a driving circuit (IC) for these display panels. The present invention relates to a driving method and a driving circuit for an EL display panel and an information display device using the same.
[0002]
[Prior art]
In general, in an active matrix display device, an image is displayed by arranging a large number of pixels in a matrix and controlling the light intensity for each pixel according to a given video signal (for example, see Patent Document 1). For example, when liquid crystal is used as the electro-optical material, the transmittance of a pixel changes according to the voltage written to each pixel. In an active matrix type image display device using an organic electroluminescence (EL) material as an electro-optical conversion material, light emission luminance changes according to a current written to a pixel.
[0003]
In a liquid crystal display panel, each pixel operates as a shutter, and displays an image by turning on / off light from a backlight with a shutter which is a pixel. The organic EL display panel is a self-luminous type having a light emitting element in each pixel. Therefore, the organic EL display panel has advantages such as higher image visibility, no backlight, and faster response speed than the liquid crystal display panel.
[0004]
In the organic EL display panel, the luminance of each light emitting element (pixel) is controlled by the amount of current. That is, the liquid crystal display panel is greatly different from the liquid crystal display panel in that the light emitting element is a current drive type or a current control type.
[0005]
The organic EL display panel can be configured in a simple matrix system or an active matrix system. The former has a simple structure, but it is difficult to realize a large and high-definition display panel. But it is cheap. The latter can realize a large, high-definition display panel. However, there is a problem that the control method is technically difficult and relatively expensive. At present, active matrix systems are being actively developed. In the active matrix method, a current flowing through a light emitting element provided in each pixel is controlled by a thin film transistor (transistor) provided inside the pixel.
[0006]
This active matrix type organic EL display panel is disclosed in JP-A-8-234683. FIG. 46 shows an equivalent circuit for one pixel of the display panel. The pixel 16 includes an EL element 15 which is a light emitting element, a first transistor 11a, a second transistor 11b, and a storage capacitor 19. Reference numeral 15 denotes an organic electroluminescence (EL) element. In the present invention, the transistor 11a that supplies (controls) a current to the EL element 15 is referred to as a driving transistor 11. A transistor that operates as a switch, such as the transistor 11b in FIG. 46, is referred to as a switching transistor 11.
Since the EL element 15 has a rectifying property in many cases, it is sometimes called an OLED (organic light emitting diode). In FIG. 46 and the like, a diode symbol is used as the EL element 15.
[0007]
However, the light emitting element in the present invention is not limited to the OLED, and any light emitting element whose luminance is controlled by the amount of current flowing through the element 15 may be used. For example, an inorganic EL element is exemplified. In addition, a white light emitting diode composed of a semiconductor is exemplified. Further, a general light emitting diode is exemplified. In addition, a light emitting transistor may be used. Further, the light emitting element does not necessarily require rectification. It may be a bidirectional diode. The EL element 15 of the present invention may be any of these.
[0008]
In the example of FIG. 46, the source terminal (S) of the P-channel transistor 11a is set to Vdd (power supply potential), and the cathode (cathode) of the EL element 15 is connected to the ground potential (Vss). On the other hand, the anode (anode) is connected to the drain terminal (D) of the transistor 11b. On the other hand, the gate terminal of the P-channel transistor 11a is connected to the gate signal line 17a, the source terminal is connected to the source signal line 18, and the drain terminal is connected to the storage capacitor 19 and the gate terminal (G) of the transistor 11a. I have.
[0009]
In order to operate the pixel 16, first, the gate signal line 17 a is set to a selected state, and a video signal representing luminance information is applied to the source signal line 18. Then, the transistor 11a conducts, the storage capacitor 19 is charged or discharged, and the gate potential of the transistor 11b matches the potential of the video signal. When the gate signal line 17a is in a non-selected state, the transistor 11a is turned off, and the transistor 11b is electrically disconnected from the source signal line 18. However, the gate potential of the transistor 11a is stably held by the storage capacitor (capacitor) 19. The current flowing through the EL element 15 via the transistor 11a has a value corresponding to the voltage Vgs between the gate and the source terminal of the transistor 11a, and the EL element 15 emits light at a luminance corresponding to the amount of current supplied through the transistor 11a. to continue.
[0010]
[Patent Document 1]
JP 2001-147659 A
[0011]
[Problems to be solved by the invention]
Since the liquid crystal display panel is not a self-luminous device, there is a problem that an image cannot be displayed unless a backlight is used. Since a predetermined thickness is required to constitute the backlight, there is a problem that the thickness of the display panel is increased. In order to perform color display on the liquid crystal display panel, it is necessary to use a color filter. Therefore, there is a problem that the light use efficiency is low. There is also a problem that the color reproduction range is narrow.
[0012]
The organic EL display panel is configured using a low-temperature polysilicon transistor array. However, since the EL element emits light by current, there is a problem that display unevenness occurs if the characteristics of the transistor vary.
[0013]
The display unevenness can be reduced by adopting a configuration of the current programming method for the pixels. In order to execute a current program, a driver circuit of a current drive system is required. However, even in the driver circuit of the current driving method, variations occur in the transistor elements constituting the current output stage. For this reason, there is a problem in that the gradation output current from each output terminal varies, and good image display cannot be performed.
[0014]
[Means for Solving the Problems]
According to a first aspect of the present invention, there is provided a gate signal line, a source signal line, a source driver circuit for outputting a program current, a gate driver circuit, and EL elements arranged in a matrix. A driving transistor for supplying a current flowing to the EL element, a first transistor disposed on a current path of the EL element, and a second transistor forming a path for transmitting the program current to the driving transistor. Wherein the source driver circuit outputs the program current to the source signal line, the gate driver circuit is connected to the gate signal line, and a gate terminal of the second transistor is connected to the gate signal line. , The source terminal of the second transistor is connected to the source signal line, the second transistor An EL display device, wherein a drain terminal is connected to a drain terminal of the driving transistor, and the gate driver circuit selects a plurality of the gate signal lines and supplies the program current to the driving transistors of a plurality of pixels. It is.
[0015]
In order to achieve this object, a driver circuit of an EL display panel (EL display device) according to the present invention includes a plurality of transistors that output a unit current, and outputs an output current by changing the number of transistors. It is. Further, the present invention is characterized in that it is constituted by a multi-stage current mirror circuit. A transistor group in which signal transfer is voltage transfer is formed densely, and a signal transfer with a current mirror circuit group employs a current transfer configuration. The reference current is supplied by a plurality of transistors.
[0016]
BEST MODE FOR CARRYING OUT THE INVENTION
In this specification, some drawings are omitted or / and enlarged / reduced in order to facilitate understanding and / or drawing. For example, in the cross-sectional view of the display panel illustrated in FIG. 11, the thin film sealing film 111 and the like are illustrated to be sufficiently thick. On the other hand, in FIG. 10, the sealing lid 85 is shown thinly. Some parts have been omitted.
For example, the display panel of the present invention requires a phase film such as a circularly polarizing plate to prevent reflection. However, it is omitted in each drawing of this specification. The same applies to the following drawings. In addition, portions with the same numbers or symbols have the same or similar forms or materials or functions or operations.
[0017]
It should be noted that the contents described in each drawing and the like can be combined with other embodiments and the like without particular notice. For example, by adding a touch panel or the like to the display panel in FIG. 8, the information display device illustrated in FIGS. 157 and 159 to FIG. 161 can be obtained. Further, a viewfinder (see FIG. 58) used for a video camera (see FIG. 159 and the like) can be configured by attaching the magnifying lens 1582. In addition, the driving method of the present invention described with reference to FIGS. 4, 15, 18, 18, 21, 23, 29, 30, 35, 36, 40, 41, 44, 100, etc. The present invention can be applied to any display device or display panel of the present invention.
[0018]
Note that in this specification, the driving transistor 11 and the switching transistor 11 are described as thin film transistors, but are not limited thereto. A thin film diode (TFD), a ring diode, or the like can also be used. Further, the present invention is not limited to the thin film element, but may be a transistor formed on a silicon wafer. The substrate 71 may be formed of a silicon wafer. Of course, FETs, MOS-FETs, MOS transistors, and bipolar transistors may be used.
These are also basically thin film transistors. In addition, it goes without saying that a varistor, a thyristor, a ring diode, a photodiode, a phototransistor, a PLZT element or the like may be used. That is, the transistor element 11, the gate driver circuit 12, the source driver circuit 14, and the like of the present invention can use any of these.
[0019]
Hereinafter, the EL panel of the present invention will be described with reference to the drawings. As shown in FIG. 10, the organic EL display panel has at least one of an electron transport layer, a light emitting layer, a hole transport layer, and the like on a glass plate 71 (array substrate) on which a transparent electrode 105 as a pixel electrode is formed. The organic functional layer (EL layer) 15 and the metal electrode (reflection film) (cathode) 106 are stacked. A positive voltage is applied to the anode (anode) which is the transparent electrode (pixel electrode) 105 and a negative voltage is applied to the cathode (cathode) of the metal electrode (reflection electrode) 106, that is, a direct current is applied between the transparent electrode 105 and the metal electrode 106. Thereby, the organic functional layer (EL layer) 15 emits light.
[0020]
As the metal electrode 106, an electrode having a small work function, such as lithium, silver, aluminum, magnesium, indium, copper, or an alloy of each of them is preferably used. In particular, it is preferable to use, for example, an Al-Li alloy. For the transparent electrode 105, a conductive material having a large work function, such as ITO, or gold or the like can be used. When gold is used as the electrode material, the electrode is in a translucent state. Note that ITO may be another material such as IZO. This applies to other pixel electrodes 105 as well.
[0021]
Note that a desiccant 107 is disposed in a space between the sealing lid 85 and the array substrate 71.
This is because the EL film 15 is sensitive to humidity. The desiccant 107 absorbs the moisture permeating the sealant to prevent the EL film 15 from deteriorating.
[0022]
FIG. 10 shows a configuration in which sealing is performed using a glass lid 85, but sealing using a film (or a thin film, that is, a thin film sealing film) 111 as shown in FIG. For example, as the sealing film (thin film sealing film) 111, a film obtained by depositing DLC (diamond-like carbon) on a film of an electrolytic capacitor is used. This film has extremely poor moisture permeability (high moisture-proof performance). This film is used as the sealing film 111. Needless to say, a structure in which a DLC (diamond-like carbon) film or the like is directly deposited on the surface of the electrode 106 may be used. Alternatively, a thin film sealing film may be formed by laminating a resin thin film and a metal thin film in multiple layers.
[0023]
The film thickness of the thin film is calculated by n · d (n is the refractive index of the thin film, and when a plurality of thin films are laminated, the refractive index is integrated (calculate n · d of each thin film). , And when a plurality of thin films are laminated, the refractive index is calculated as a whole.) Is preferably equal to or less than the main emission wavelength λ of the EL element 15. By satisfying this condition, the light extraction efficiency from the EL element 15 becomes twice or more as compared with the case where the EL element 15 is sealed with a glass substrate. Further, an alloy, a mixture or a laminate of aluminum and silver may be formed.
[0024]
The structure in which the lid 85 is not used and the sealing is performed by the sealing film 111 as described above is referred to as thin film sealing. In the case of “down extraction (see FIG. 10, the light extraction direction is the direction of the arrow in FIG. 10)” in which light is extracted from the substrate 71 side, thin film sealing is performed after the EL film is formed and the cathode is formed on the EL film. An aluminum electrode is formed. Next, a resin layer as a buffer layer is formed on the aluminum film. Examples of the buffer layer include organic materials such as acrylic and epoxy. Further, a film thickness of 1 μm or more and 10 μm or less is suitable. More preferably, the film thickness is 2 μm or more and 6 μm or less. A sealing film 74 is formed on the buffer film. Without the buffer film, the structure of the EL film collapses due to stress, and a streak-like defect occurs. As described above, the sealing film 111 is exemplified by DLC (diamond-like carbon) or a layer structure of an electric field capacitor (a structure in which a dielectric thin film and an aluminum thin film are alternately multilayer-deposited).
[0025]
In the thin film encapsulation in the case of extracting light from the EL layer 15 side (see FIG. 11 for upward extraction, the light extraction direction is the direction of the arrow in FIG. 11), after forming the EL film 15, the cathode ( An Ag—Mg film serving as an anode is formed with a thickness of 20 Å to 300 Å. A transparent electrode such as ITO is formed thereon to reduce the resistance. Next, a resin layer as a buffer layer is formed on the electrode film. A sealing film 111 is formed on the buffer film.
[0026]
Half of the light generated from the EL layer 15 is reflected by the reflection film 106 and transmitted through the array substrate 71 and emitted. However, external light is reflected on the reflective film 106 to cause reflection, thereby lowering display contrast. To cope with this, a λ / 4 plate 108 and a polarizing plate (polarizing film) 109 are arranged on the array substrate 71. These are generally called circularly polarizing plates (circularly polarizing sheets).
[0027]
When the pixel is a reflective electrode, light generated from the EL layer 15 is emitted upward. Therefore, it goes without saying that the phase plate 108 and the polarizing plate 109 are arranged on the light emission side. Note that a reflective pixel is obtained by forming the pixel electrode 105 with aluminum, chromium, silver, or the like. Further, by providing a convex portion (or a concave and convex portion) on the surface of the pixel electrode 105, the interface with the EL layer 15 is widened, the light emitting area is increased, and the light emitting efficiency is improved. Note that a circularly polarizing plate is not required when a reflective film serving as the cathode 106 (anode 105) is formed on a transparent electrode, or when the reflectance can be reduced to 30% or less. This is because reflection is greatly reduced. It is also desirable to reduce light interference.
[0028]
Since light emitted from the EL element 15 of the EL display panel has no directivity, the light is emitted to an external space via the substrate 71 on which the EL element 15 is formed. Therefore, when light is emitted from a substrate having a high refractive index (refractive index is about 1.5) to a space (refractive index is 1.0), 2/3 of the light has a critical angle based on Snell's law or more, The light is not emitted to the space (that is, ／ of the light generated by the EL element 15 cannot be emitted from the substrate 71). The light confined in the substrate 71 is irregularly reflected in the substrate 71 and becomes halation (see FIG. 420; light 4093 is irregularly reflected in the substrate 71), thereby lowering the display contrast of the EL display panel. Further, this is not preferable because it causes heat generation.
[0029]
In order to solve this problem, in the present invention, as shown in FIG. 410, a light absorbing material is used as the material of the bank (rib) 101. Hereinafter, the bank formed of the light absorbing material is referred to as a light absorbing bank 4101. By using the light absorbing bank 4101, the occurrence of halation occurring on the substrate 71 or the like can be prevented, and the display contrast can be significantly improved.
[0030]
That is, as shown in FIG. 420, light 4093 diffusely reflected in the substrate 71 is absorbed by the light absorbing film 4101 (4102). As shown in FIG. 421, the light absorbing film 4102 (4101) has an invalid area other than the effective area A (a screen 50 through which light effective for image display passes (an area from which effective light for image display is emitted)). It is preferable that the light absorbing film 4102 (4101) is formed or arranged also on the sealing lid 85, as shown in FIG. It is also effective to form 85 from a black material or the like.
[0031]
As a material constituting the light absorbing film, a material containing carbon in an organic material such as an acrylic resin, a material in which a black pigment or pigment is dispersed in an organic resin, and a material such as gelatin or casein in which a black color is applied to a black color like a color filter. Those dyed with an acid dye are exemplified. In addition, a single fluoran dye that is black may be used by coloring, or a black color mixture of a green dye and a red dye may be used. Further, a PrMnO3 film formed by sputtering, a phthalocyanine film formed by plasma polymerization, and the like are exemplified.
[0032]
The above materials are all black materials, but the light absorbing film may be a material having a color complementary to the light color generated by the display element. For example, a light absorbing material for a color filter may be modified so as to obtain desired light absorbing characteristics and used.
Basically, a dye obtained by dyeing a natural resin with a dye may be used as in the case of the above-described black absorbing material. Alternatively, a material in which a dye is dispersed in a synthetic resin can be used. The range of selection of the dye is wider than the black dye, and may be an appropriate one of azo dyes, anthraquinone dyes, phthalocyanine dyes, triphenylmethane dyes, and the like, or a combination of two or more thereof.
[0033]
Further, a metal material may be used as the light absorbing film. For example, hexavalent chromium is exemplified. Hexavalent chromium is black and functions as a light absorbing film. In addition, light scattering materials such as opal glass and titanium oxide may be used. This is because scattering of light is equivalent to absorbing light as a result.
[0034]
Further, as illustrated in FIG. 411, it is preferable to form or dispose the light absorption film 4102 also in a region of the transistor 11 included in the pixel 16 (transistor formation region 4111). This is because when light enters the transistor 11, a photoconductor phenomenon occurs and the off-state characteristics of the transistor deteriorate.
[0035]
Note that the light absorbing film 4102 is also formed on the back surface of the gate driver circuit 12 so that light confined in the substrate 71 does not enter the driver circuit 12. Similarly, it is preferable to form it on the back surface of the source driver circuit (IC) 14. This is for the same reason as forming the base anode line 2631 in FIG.
[0036]
In the EL display panel, the sealing lid 85 and the substrate 71 are attached to each other in order to prevent external moisture from entering the EL element 15. At this time, in order to realize a narrow frame, the bonding portion is located on the gate driver circuit 12. However, when pressure is applied to the bonding portion, the gate driver circuit 12 may be broken due to the pressure. In particular, beads 4121 are mixed with the adhesive forming the adhesive layer 4123 in order to make the adhesive layer 4123 at the bonding portion uniform (see FIG. 412). The beads 4121 may be pressurized and sunk into the gate driver circuit 12 to destroy the gate driver circuit 12. The configuration of the gate driver circuit 12 and the like will be described later.
[0037]
In order to solve this problem, in the present invention, the interlayer insulating film 102 is formed on the gate driver circuit 12. The thickness of the interlayer insulating film 102 is preferably 0.5 μm or more and 2.0 μm or less. In particular, the thickness is preferably 0.8 μm or more and 1.6 μm or less. Further, a light absorbing bank 4101 (bank material 4124) formed simultaneously with the formation of the bank 101 on the interlayer insulating film 102 is formed. Note that, for convenience, the light absorbing bank 4101 is described. However, the bank formed on the gate driver circuit 12 does not function as a bank, and prevents the gate driver circuit 12 from being broken due to the indentation of the beads 4121. It is the main purpose.
[0038]
The light absorbing bank 4101 also has an effect of blocking light incident on the gate driver circuit 12. The thickness of the light absorbing bank 4101 is the same as the height of the bank 101 of the pixel 16. The thickness of the light absorbing bank 4101 is preferably 0.5 μm or more and 2.0 μm or less. In particular, the thickness is preferably 0.8 μm or more and 1.6 μm or less. Note that the main material of the light absorbing bank 4101 is preferably an acrylic resin material.
[0039]
Further, an aluminum thin film 106 serving as a cathode electrode is formed on the light absorbing bank 4101. The aluminum thin film 106 is formed simultaneously with the cathode electrode of the pixel 16. By forming the aluminum thin film 106, the moisture proof performance is significantly improved. It is preferable that the thickness of the aluminum thin film 106 be 0.1 μm or more and 1.5 μm or less. In particular, the thickness is preferably 0.2 μm or more and 1.0 μm or less. This thin film is not limited to aluminum, but may be formed of a material constituting the cathode electrode.
[0040]
As described above, by forming the interlayer insulating film 102, the light absorbing bank 4101, and the aluminum thin film 106 on the gate driver circuit 12, the gate driver circuit 12 is not destroyed by the attachment of the sealing lid 85. In addition, sufficient moisture-proof properties can be obtained.
[0041]
In particular, in FIG. 412, as shown by the arrows, the aluminum thin film 106 covers the light absorbing banks 4101 and the side surfaces of the interlayer insulating film 102. This coating can completely prevent intrusion of moisture. More preferably, a thin film made of an inorganic material is preferably formed on the aluminum thin film 106. Examples of the thin film made of an inorganic material include SiO2 and SiNx. In addition, it goes without saying that Al2O3, Ta2O3 and the like may be used. It is preferable that the thin film made of an inorganic material is formed to have a thickness of 0.1 μm or more. It is also formed on the side surface shown in FIG. The thin film may be a film obtained by evaporating DLC (diamond-like carbon).
[0042]
The diameter of the beads 4121 is preferably 5 μm or more and 30 μm or less, and more preferably 8 μm or more and 15 μm or less. Further, it is preferable that the width of the adhesive layer 4123 be 0.8 mm or more and 2 mm or less. It is preferable to use resin beads as the material of the beads.
[0043]
In the embodiment of FIG. 412, the adhesive layer 4123 of the sealing lid 85 is arranged on the gate driver circuit 12. However, the present invention is not limited to this. As shown in FIG. 413, the adhesive layer 4123 may be arranged so as not to be on the gate driver circuit 12. With the configuration shown in FIG. 413, the gate driver circuit 12 is not destroyed by the beads 4121 and the like.
[0044]
In FIG. 413, the adhesive layer 4123 is formed over the power supply wiring 4131 of the gate driver circuit 12. This is because the power supply wiring 4131 is not broken even when pressure is applied. A range indicated by B in FIG. 414 is a range in which the adhesive layer 4123 to be bonded to the sealing lid 85 is applied (a range of bonding). A voltage is supplied to the gate driver circuit 12 from a power supply wiring 4131 via a voltage supply line 4141.
[0045]
In order to make the film thickness of the adhesive layer 4123 uniform without using the beads 4121, a protrusion 4151 may be formed on the sealing lid 85 as shown in FIG. 415 (shown by a dotted line in FIG. 415). . The protrusion 4151 can be easily formed by pressing. The protrusion 4151 is not limited to being formed on the sealing lid 85, but may be formed on the substrate 71 side.
[0046]
As shown in FIG. 415, it is preferable that the gate driver circuit 12 is not arranged below the protrusion 4151. In the case where the source driver circuit 14 is also formed directly on the substrate 71 as shown in FIG. However, when the convex portion 4151 is formed in a linear shape (4151a, 4151b) as shown in FIG. 416, there is no escape for the applied adhesive (which becomes the adhesive layer 4123). Therefore, as shown in FIG. 417, it is preferable that the protrusions 4151 are formed or arranged in a dot shape. The dot shape means a state other than a linear shape that is not completely interrupted as shown in FIG. This is because, even if the linear convex portion 4151 is partially interrupted, that portion serves as an escape for the adhesive. Therefore, the dot shape may be a linear shape. Other configurations are the same as or similar to those in FIG. 412, and a description thereof will not be repeated.
[0047]
FIG. 412 shows a configuration in which sealing is performed by a sealing lid 85. However, the present invention is not limited to this, and may be sealed with a thin film 111 as shown in FIG. 418 (thin film sealing film 111). Other configurations are the same as those in FIG. As described above, it is exemplified that the thin film sealing film 111 is formed by depositing DLC (diamond-like carbon) on a film of an electrolytic capacitor. Very good moisture resistance. This film is used as the sealing film 111. Needless to say, a structure in which a DLC film or the like is directly deposited on the surface of the electrode 106 may be used.
[0048]
In the case where the source driver IC is COG-mounted (chip-on-glass mounting method) as the source driver circuit 14, attention must be paid to the mounting. This is because the EL material constituting the EL element 15 has a low glass transition temperature and may be deteriorated by heating during COG mounting. In general, when an organic EL material is applied at a temperature of 100 degrees Celsius (Celsius) or more for one minute, its characteristics are degraded.
[0049]
In order to address this problem, the distance between the driver IC to be mounted on the COG and the portion (the display screen 50) where the EL film is formed may be at least a certain distance. According to an experiment, when the maximum heating temperature applied at the time of COG mounting is C and the distance from the terminal position end of the IC to be COG mounted to the nearest EL element forming portion is K, K (mm)> C / It is preferable to satisfy the relation of 120 (mm). More preferably, it is preferable to satisfy the relationship of K (mm)> C / 100 (mm).
[0050]
If this condition cannot be satisfied, a heat radiating plate 4191 (heat radiating means) is arranged between the IC chip and the display screen 50 during COG mounting, as shown in FIG. 419. The heat radiating plate 4191 can prevent heat during COG mounting from being transmitted to the display screen 50. The heat radiating plate 4191 may be of any configuration or material, such as metal, as long as it has better thermal conductivity than the material of the substrate 71.
[0051]
When a thin film sealing configuration is adopted as shown in FIG. 418, it is also effective to dispose or attach a metal plate 4231 or the like to the sealing thin film 111 and radiate heat (FIG. 423). An adhesive made of a silicon material is applied on the sealing thin film 111, and a metal plate 4231 having a heat radiation effect is arranged. Of course, the material is not limited to the metal plate (metal sheet) 4231, and any material may be used as long as it has a heat radiation effect. For example, an organic material such as a diamond thin film and carbon is exemplified. Note that the adhesive layer 4123 is not necessarily required, and a configuration in which the metal plate 4231 is closely attached to the sealing thin film 111 may be employed.
[0052]
In order to further improve the heat radiation effect, as shown in FIG. 426, irregularities may be formed on the surface of the metal plate 4231.
[0053]
As shown in FIG. 423, when the adhesive layer 4123 is applied to the entire surface of the sealing thin film 111, the sealing thin film 111 may be broken due to shrinkage when the adhesive layer is cured. In order to cope with this problem, as shown in FIG. 424, the adhesive 4123 may be applied in a dot shape (dotted shape). Of course, the adhesive 4123 may be applied linearly.
[0054]
In order to suppress the reflection on the cathode 106, the configuration shown in FIG. 425 may be adopted. In FIG. 425, the cathode electrode 106 (4251 in FIG. 425) is formed very thin. Therefore, in FIG. 425, the cathode electrode 4251 is used. The thickness of the cathode electrode 4251 is greater than or equal to 100 Å and less than or equal to 1000 Å. More preferably, the thickness is not less than 200 angstroms and not more than 500 angstroms. By forming the cathode electrode 4251 to be thin, the cathode electrode is in a semi-transmissive state, so that reflection is reduced. However, when the cathode electrode 4251 is thin, the resistance value increases.
[0055]
As a countermeasure, as shown in FIG. 425, a conductor film 4253 made of a transparent material is formed so as to be laminated on the cathode electrode 4251. As the conductor film 4253, ITO or IZO is exemplified. Note that the transparent conductive film 4253 may be a light-absorbing conductive film such as carbon. This is because reflection is suppressed by carbon or the like.
[0056]
The sealing thin film 111 is further formed on the transparent conductor film 4253, or fine beads 4252 are scattered directly on the transparent conductor film 4253. The diameter of the beads is preferably 1 μm or more and 10 μm or less. A fixing material 4254 for fixing the beads 4252 is formed thereon by coating or vapor deposition. The fixing material 4254, an inorganic material such as SiO2 or SiOx, or an organic material such as polyvinyl alcohol or polyimide can be used. Other than the acrylic resin, an epoxy adhesive, a polyester adhesive, or the like can be used. Note that the thickness of the fixing member 4254 is set to 100 μm or less.
[0057]
When depositing a thin film on the pixel electrode 105 or the like, the EL film 15 is preferably formed in an argon atmosphere. Further, by forming a carbon film with a thickness of 20 to 50 nm on ITO serving as the pixel electrode 105, the stability of the interface is improved, and the light emission luminance and light emission efficiency are improved. Further, it is needless to say that the EL film 15 is not limited to being formed by vapor deposition, but may be formed by inkjet. In particular, this inkjet method is effective for a polymer organic EL material. In this case, it is preferable to form a hydrophilic film at a position where the polymer organic EL material is applied.
[0058]
Since the polymer EL material is formed by the ink-jet method, it is necessary to apply the polymer EL material to the substrate 71 well. Basically, as shown in FIG. 429 (a), the periphery is surrounded by a bank 101, and a polymer EL material 4291 is applied inside the bank 101. However, as shown in FIG. 429 (a), when the periphery is surrounded by the bank 101, a portion where the high molecular EL material 4291 is not applied occurs as shown by C in the peripheral portion.
[0059]
In order to solve this problem, the present invention removes the portion D of the bank 101 (the bank 101 is interrupted) as shown in FIG. In this manner, by removing the four corners of the bank 101 in particular, the polymer EL material 4291 can be satisfactorily applied to the periphery of the pixel.
FIG. 428 illustrates the shape and arrangement of the bank 101 of the present invention. The embankment 101 is composed of embankments 101a scattered in dots in the vertical direction and embankments 101b scattered in dots in the horizontal direction.
[0060]
Note that, as shown in FIG. 430, even when the region to which the polymer EL material 4291 is applied is circular (other than a square), as shown in the figure, the bank 101 at the location C is removed. It is good to adopt.
[0061]
Hereinafter, in order to facilitate understanding of the structure of the EL display panel of the present invention, a method of manufacturing the organic EL display panel of the present invention will be described first.
[0062]
The substrate may be formed of sapphire glass in order to improve the heat dissipation of the sealing lid 85 and the substrate 71. Further, a thin film or a thick film having good heat conductivity may be formed. For example, use of a substrate on which a diamond thin film (DLC or the like) is formed is exemplified. Of course, a quartz glass substrate or a soda glass substrate may be used.
In addition, a ceramic substrate such as alumina, a metal plate made of copper or the like, or a metal film or a carbon film formed on an insulating film by vapor deposition or coating may be used. When the pixel electrode 105 is of a reflective type, light is emitted from the substrate surface direction as a substrate material. Therefore, in addition to a transparent or translucent material such as glass, quartz, and resin, a non-transmissive material such as stainless steel can be used.
[0063]
Further, a microlens may be formed or arranged outside or inside the sealing lid 85 and the substrate 71 corresponding to the pixel shape. By configuring the microlens, the directivity of light emitted from the EL film is narrowed, and high luminance can be realized.
[0064]
In the embodiment of the present invention, the cathode electrode 106 and the like are formed of a metal film. However, the present invention is not limited to this, and the cathode electrode 106 and the like may be formed of a transparent film such as ITO and IZO.
By making both the anode and cathode electrodes of the EL element 15 transparent, a transparent EL display panel can be constructed (of course, one may be formed of a light-transmitting metal film. An extremely thin metal film may be used as a cathode electrode, and a transparent conductive material such as ITO may be laminated on the cathode electrode.) By increasing the transmittance to about 80% without using a metal film, it is possible to configure so that the other side of the display panel can be seen almost transparently while displaying characters and pictures.
[0065]
Needless to say, a plastic substrate may be used for the sealing lids 85 and 71. The plastic substrate is hardly damaged and is lightweight, so that it is most suitable as a substrate for a display panel of a mobile phone. The plastic substrate is preferably used as a laminated substrate by bonding an auxiliary substrate to one surface of a base substrate serving as a core material with an adhesive. Of course, these substrates and the like are not limited to plates, and may be films having a thickness of 0.05 mm or more and 0.3 mm or less.
[0066]
It is preferable to use an alicyclic polyolefin resin as the substrate of the base substrate. As such alicyclic polyolefin resin, a single plate of ARTON manufactured by Japan Synthetic Rubber Co., Ltd. having a thickness of 200 μm is exemplified. Polyester resin, polyethylene resin or polyethersulfone resin with a hard coat layer with heat resistance, solvent resistance or moisture resistance function, and a gas barrier layer with air resistance function formed on one side of the base substrate An auxiliary substrate (or film or film) is disposed.
[0067]
When the substrate 71 and the like are formed of plastic as described above, the substrate 71 and the like are formed of a base substrate and an auxiliary substrate. On the other surface of the base substrate, an auxiliary substrate (or film or film) made of a polyether sulfone resin or the like on which a hard coat layer and a gas barrier layer are formed as described above is disposed. It is preferable that the angle between the optical slow axis of the auxiliary substrate and the optical slow axis of the auxiliary substrate be 90 degrees. Note that the base substrate and the auxiliary substrate are attached to each other with an adhesive or a pressure-sensitive adhesive to form a laminated substrate.
[0068]
It is preferable to use a UV (ultraviolet) curable acrylic resin as the adhesive. Further, it is preferable to use an acrylic resin having a fluorine group. In addition, an epoxy-based adhesive or a pressure-sensitive adhesive may be used. It is preferable to use an adhesive or pressure-sensitive adhesive having a refractive index of 1.47 or more and 1.54 or less. Further, it is preferable that the difference in the refractive index from the refractive index of the substrate is 0.03 or less. In particular, it is preferable that the adhesive be added with a light diffusing material such as titanium oxide as described above to function as a light scattering layer.
[0069]
When the auxiliary substrate and the auxiliary substrate are bonded to the base substrate, it is preferable that the angle between the optical slow axis of the auxiliary substrate and the optical slow axis of the auxiliary substrate be 45 degrees or more and 120 degrees or less. It is more preferable that the angle be 80 degrees or more and 100 degrees or less.
By setting the thickness within this range, the retardation generated in the auxiliary substrate and the auxiliary substrate such as polyether sulfone resin can be completely canceled in the laminated substrate. Therefore, the plastic substrate for a display panel can be handled as an isotropic substrate having no phase difference. Therefore, in the configuration using the circularly polarizing plate, the unevenness of the display panel due to the difference in the phase state does not occur. Needless to say, matters relating to the circularly polarizing plate are not limited to a plastic substrate, but are also effective for a glass substrate. This is because a decrease in contrast due to external light reflected on the substrate surface can be effectively suppressed.
[0070]
With this configuration, the versatility is significantly expanded as compared with a film substrate or a film laminated substrate having a phase difference. That is, by combining a retardation film, linearly polarized light can be converted into elliptically polarized light as designed. If there is a phase difference in a substrate or the like, an error from a design value occurs due to the phase difference.
[0071]
Here, as the hard coat layer, a polyester resin, an epoxy resin, a urethane resin, an acrylic resin, or the like can be used, and a stripe electrode (simple matrix EL display panel) or a pixel electrode (active matrix display panel) can be used. ) Also serves as the first undercoat layer of the transparent conductive film.
[0072]
As the gas barrier layer, an inorganic material such as SiO2 or SiOx, or an organic material such as polyvinyl alcohol or polyimide can be used. As the pressure-sensitive adhesive or the adhesive, an epoxy-based adhesive, a polyester-based adhesive, or the like can be used in addition to the acrylic-based adhesive described above. Note that the thickness of the adhesive layer is 100 μm or less. However, the thickness is preferably 10 μm or more in order to smooth the unevenness of the surface such as a substrate.
[0073]
The transistor 11 preferably employs an LDD (lightly doped drain) structure. In this specification, an EL element (described in various abbreviations such as OEL, PEL, PLED, and OLED) 15 will be described as an example of an EL element, but the present invention is not limited to this. It goes without saying that also applies.
[0074]
First, the active matrix method used for the organic EL display panel is as follows.
To be able to select specific pixels and provide necessary display information.
Two conditions must be satisfied that a current can flow through the EL element throughout one frame period.
[0075]
In order to satisfy these two conditions, in the conventional organic EL pixel configuration shown in FIG. 46, the first transistor 11b is a switching transistor for selecting a pixel, and the second transistor 11a is an EL element (EL film). A) a driving transistor for supplying a current to 15;
[0076]
When a gray scale is displayed using this configuration, it is necessary to apply a voltage corresponding to the gray scale as the gate voltage of the driving transistor 11a. Therefore, the variation in the ON current of the driving transistor 11a appears on the display as it is.
[0077]
The on-state current of a transistor is extremely uniform if it is a transistor formed of a single crystal, but it can be formed on an inexpensive glass substrate. , There are variations in the threshold value in the range of ± 0.2 V to 0.5 V. Therefore, the on-current flowing through the driving transistor 11a varies correspondingly, and the display becomes uneven. These irregularities occur not only due to variations in threshold voltage, but also due to the mobility of the transistor, the thickness of the gate insulating film, and the like. The characteristics also change due to the deterioration of the transistor 11.
[0078]
This phenomenon is not limited to the low-temperature polysilicon technology. Even in the high-temperature polysilicon technology having a process temperature of 450 degrees Celsius or more, a transistor or the like is formed using a semiconductor film grown by solid phase (CGS). It also occurs in things. Others also occur in organic transistors. It also occurs in amorphous silicon transistors.
[0079]
The present invention described below has a configuration or system that can cope with these technologies and take measures. In this specification, a transistor formed by a low-temperature polysilicon technology will be mainly described.
[0080]
Therefore, in the method of displaying a gray scale by writing a voltage as shown in FIG. 46, it is necessary to strictly control device characteristics in order to obtain a uniform display. However, current low-temperature polycrystalline polysilicon transistors and the like cannot satisfy the specification of suppressing this variation within a predetermined range.
[0081]
Specifically, the pixel structure of the EL display device of the present invention is formed by a plurality of transistors 11 each having at least four unit pixels and an EL element as shown in FIG.
The pixel electrode is configured to overlap with the source signal line. That is, an insulating film or a flattening film made of an acrylic material is formed on the source signal line 18 for insulation, and the pixel electrode 105 is formed on the insulating film. Such a configuration in which the pixel electrode is overlapped with at least a part of the source signal line 18 is called a high aperture (HA) structure. Unnecessary interference light and the like are reduced, and a favorable light emitting state can be expected.
[0082]
When the gate signal line (first scanning line) 17a is activated (an ON voltage is applied), a current value to be passed through the EL element 15 is supplied to the source through the transistor 11a for driving the EL element 15 and the switching transistor 11c. It flows from the driver circuit 14. Further, the transistor 11b is activated by applying the ON voltage to open the gate signal line 17a so as to short-circuit the gate and drain of the transistor 11a, and a capacitor connected between the gate and the source of the transistor 11a (capacitor, The gate voltage (or drain voltage) of the transistor 11a is stored in the storage capacitor (additional capacitor) 19 (see FIG. 3A).
[0083]
Note that the size of the capacitor (storage capacitance) 19 is preferably 0.2 pF or more and 2 pF or less, and particularly, the size of the capacitor (storage capacitance) 19 is preferably 0.4 pF or more and 1.2 pF or less. . The capacity of the capacitor 19 is determined in consideration of the pixel size. If the capacitance required for one pixel is Cs (pF) and the area occupied by one pixel (not the aperture ratio) is Sp (square μm), then 500 / S ≦ Cs ≦ 20,000 / S, and more preferably 1000 / S / Sp ≦ Cs ≦ 10000 / Sp. Since the gate capacitance of the transistor is small, Q here is the capacitance of the storage capacitance (capacitor) 19 alone.
[0084]
When the gate signal line 17a is inactive (OFF voltage is applied) and the gate signal line 17b is active, a current flow path includes the first transistor 11a, the transistor 11d connected to the EL element 15, and the EL element 15. The path is switched to an operation to flow the stored current to the EL element 15 (see FIG. 3B).
[0085]
This circuit has four transistors 11 in one pixel, and the gate of the transistor 11a is connected to the source of the transistor 11b. The gates of the transistors 11b and 11c are connected to a gate signal line 17a. The drain of the transistor 11b is connected to the source of the transistor 11c and the source of the transistor 11d, and the drain of the transistor 11c is connected to the source signal line 18. The gate of the transistor 11d is connected to the gate signal line 17b, and the drain of the transistor 11d is connected to the anode electrode of the EL element 15.
[0086]
In FIG. 1, all the transistors are configured by P-channel. The P-channel is somewhat lower in mobility than an N-channel transistor, but is preferable because it has a higher breakdown voltage and hardly causes deterioration. However, the present invention is not limited only to the configuration in which the EL element is configured by the P channel. You may comprise only N channels. Further, the configuration may be made using both the N channel and the P channel.
[0087]
Optimally, it is preferable that all the transistors 11 constituting the pixel are formed by P channels, and the built-in gate driver circuit 12 is also formed by P channels. By forming the array with only P-channel transistors in this way, the number of masks becomes five, and cost reduction and high yield can be realized.
[0088]
Hereinafter, in order to further facilitate understanding of the present invention, the configuration of the EL device of the present invention will be described with reference to FIG. The EL element configuration of the present invention is controlled by two timings. The first timing is a timing at which a necessary current value is stored. When the transistor 11b and the transistor 11c are turned on at this timing, the equivalent circuit is as shown in FIG. Here, a predetermined current Iw is written from the signal line. As a result, the transistor 11a has its gate and drain connected, and the current Iw flows through the transistor 11a and the transistor 11c. Therefore, the gate-source voltage of the transistor 11a is such that I1 flows.
[0089]
The second timing is when the transistors 11a and 11c are closed and the transistor 11d is opened, and the equivalent circuit at that time is as shown in FIG. The voltage between the source and the gate of the transistor 11a remains held. In this case, since the transistor 11a always operates in the saturation region, the current of Iw is constant.
[0090]
When operated in this way, the result is as shown in FIG. That is, reference numeral 51a in FIG. 5A indicates a pixel (row) (write pixel row) on the display screen 50 where current is programmed at a certain time. The pixels (rows) 51a are not lit (non-display pixels (rows)) as shown in FIG. The other pixels (rows) are display pixels (rows) 53 (current flows through the EL elements 15 of the pixels 16 in the display area 53, and the EL elements 15 emit light).
[0091]
In the case of the pixel configuration of FIG. 1, as shown in FIG. 3A, at the time of current programming, a program current Iw flows through the source signal line 18. The voltage is set (programmed) on the capacitor 19 so that the current Iw flows through the transistor 11a and the current flowing Iw is held. At this time, the transistor 11d is in an open state (off state).
[0092]
Next, during a period in which a current flows through the EL element 15, the transistors 11c and 11b are turned off and the transistor 11d operates as shown in FIG. That is, an off voltage (Vgh) is applied to the gate signal line 17a, and the transistors 11b and 11c are turned off. On the other hand, an on-voltage (Vgl) is applied to the gate signal line 17b, turning on the transistor 11d.
[0093]
This timing chart is shown in FIG. In FIG. 4 and the like, the suffix in parentheses (for example, (1)) indicates the number of the pixel row. That is, the gate signal line 17a (1) indicates the gate signal line 17a of the pixel row (1).
In addition, * H (arbitrary symbols and numerical values are applied to “*” and indicate horizontal scanning line numbers) in the upper part of FIG. 4 indicates a horizontal scanning period. That is, 1H is the first horizontal scanning period. Note that the above items are for ease of explanation and are not limited (1H number, 1H cycle, order of pixel row number, and the like).
[0094]
As can be seen from FIG. 4, in each selected pixel row (selection period is 1H), when an ON voltage is applied to the gate signal line 17a, an OFF voltage is applied to the gate signal line 17b. I have. During this period, no current flows through the EL element 15 (non-lighting state). In an unselected pixel row, an off voltage is applied to the gate signal line 17a, and an on voltage is applied to the gate signal line 17b. Further, during this period, a current flows through the EL element 15 (lighting state).
[0095]
Note that the gate of the transistor 11a and the gate of the transistor 11c are connected to the same gate signal line 17a. However, the gate of the transistor 11a and the gate of the transistor 11c may be connected to different gate signal lines 17 (see FIG. 32). The number of gate signal lines for one pixel is three (the configuration in FIG. 1 is two). By individually controlling the ON / OFF timing of the gate of the transistor 11b and the ON / OFF timing of the gate of the transistor 11c, variation in the current value of the EL element 15 due to variation in the transistor 11a can be further reduced.
[0096]
When the gate signal line 17a and the gate signal line 17b are shared and the transistors 11c and 11d are of different conductivity types (N-channel and P-channel), the driving circuit can be simplified and the aperture ratio of the pixel can be improved. .
[0097]
With such a configuration, the write path from the signal line is turned off as the operation timing of the present invention. That is, when the predetermined current is stored, if there is a branch in the current flow path, an accurate current value is not stored in the capacitance (capacitor) between the source (S) and the gate (G) of the transistor 11a. By setting the transistor 11c and the transistor 11d to have different conductivity types, the transistor 11d can be turned on after the transistor 11c is turned off at the switching timing of the scanning line by controlling the thresholds of the transistors 11c and 11d.
[0098]
However, in this case, it is necessary to pay attention to the process because it is necessary to accurately control each other's threshold. The above-described circuit can be realized with at least four transistors. However, for more accurate timing control or as described later, the transistor 11e is cascaded as shown in FIG. The operation principle is the same even when the total number of transistors becomes four or more. With such a configuration including the transistor 11e, a current programmed through the transistor 11c can flow to the EL element 15 with higher accuracy.
[0099]
Note that the pixel configuration of the present invention is not limited to the configurations shown in FIGS. For example, the configuration may be as shown in FIG. FIG. 113 does not include the switching transistor 11d as compared with the configuration of FIG. Instead, a changeover switch 1131 is formed or arranged. The switch 11d in FIG. 1 has a function of controlling on / off (flow or not flow) of a current flowing from the driving transistor 11a to the EL element 15. As will be described in the following embodiments, in the present invention, the on / off control function of the transistor 11d is an important component. The configuration in FIG. 113 realizes the on / off function without forming the transistor 11d.
[0100]
In FIG. 113, the terminal a of the changeover switch 1131 is connected to the anode voltage Vdd. The voltage applied to the terminal a is not limited to the anode voltage Vdd, but may be any voltage that can turn off the current flowing through the EL element 15.
[0101]
The b terminal of the changeover switch 1131 is connected to a cathode voltage (shown as ground in FIG. 113). The voltage applied to the terminal b is not limited to the cathode voltage, but may be any voltage that can turn on the current flowing through the EL element 15.
[0102]
The cathode terminal of the EL element 15 is connected to the c terminal of the changeover switch 1131. Note that the changeover switch 1131 may be any switch having a function of turning on and off a current flowing through the EL element 15. Therefore, the position is not limited to the formation position in FIG. 113, and any path may be used as long as the current of the EL element 15 flows. The function of the switch is not limited, and any function may be used as long as the current flowing through the EL element 15 can be turned on and off. That is, in the present invention, any pixel configuration may be used as long as a switching unit capable of turning on and off a current flowing through the EL element 15 is provided in a current path of the EL element 15.
[0103]
Further, OFF does not mean a state in which no current flows completely. What is necessary is just to be able to reduce the current flowing through the EL element 15 more than usual. The same applies to other configurations of the present invention.
[0104]
The changeover switch 1131 can be easily realized by combining P-channel and N-channel transistors, and thus need not be described. For example, two analog switches may be formed. Of course, since the switch 1131 only turns on and off the current flowing through the EL element 15, it goes without saying that the switch 1131 can be formed by a P-channel transistor or an N-channel transistor.
[0105]
When the switch 1131 is connected to the terminal a, the voltage Vdd is applied to the cathode terminal of the EL element 15. Therefore, no current flows through the EL element 15 regardless of the voltage holding state of the gate terminal G of the driving transistor 11a. Therefore, the EL element 15 is turned off.
[0106]
When the switch 1131 is connected to the terminal b, the GND voltage is applied to the cathode terminal of the EL element 15. Therefore, a current flows through the EL element 15 according to the voltage state held at the gate terminal G of the driving transistor 11a. Therefore, the EL element 15 is turned on.
[0107]
As described above, in the pixel configuration of FIG. 113, the switching transistor 11d is not formed between the driving transistor 11a and the EL element 15. However, the lighting control of the EL element 15 can be performed by controlling the switch 1131.
[0108]
In the pixel configurations shown in FIGS. 1 and 2, there is one driving transistor 11a per pixel. The present invention is not limited to this, and a plurality of driving transistors 11a may be formed or arranged in one pixel. FIG. 116 shows the embodiment. In FIG. 116, two driving transistors 11a1 and 11a2 are formed in one pixel, and the gate terminals of the two driving transistors 11a1 and 11a2 are connected to a common capacitor 19. By forming a plurality of driving transistors 11a, there is an effect that the variation in programmed current is reduced. Other configurations are the same as those in FIG.
[0109]
1 and 2 show that the current output from the driving transistor 11a flows through the EL element 15, and the current is turned on / off by a switching transistor 11d disposed between the driving transistor 11a and the EL element 15. However, the present invention is not limited to this. For example, the configuration in FIG. 117 is exemplified.
[0110]
In the embodiment of FIG. 117, the current flowing through the EL element 15 is controlled by the driving transistor 11a. Turning on and off the current flowing through the EL element 15 is controlled by the switching transistor 11d arranged between the Vdd terminal and the EL element 15. Therefore, in the present invention, the arrangement of the switching transistor 11d may be anywhere, and any arrangement can be used as long as the current flowing through the EL element 15 can be controlled.
[0111]
The variation in the characteristics of the transistor 11a has a correlation with the transistor size. In order to reduce variation in characteristics, it is preferable that the channel length of the first transistor 11a be greater than or equal to 5 μm and less than or equal to 100 μm. More preferably, the channel length of the first transistor 11a is preferably greater than or equal to 10 μm and less than or equal to 50 μm. This is considered to be because, when the channel length L is increased, the number of grain boundaries included in the channel increases, so that the electric field is relaxed and the kink effect is suppressed.
[0112]
As described above, according to the present invention, the current flowing through the EL element 15 is controlled on the path through which the current flows into the EL element 15 or the path through which the current flows from the EL element 15 (that is, the current path of the EL element 15). The circuit means is configured or formed or arranged.
[0113]
Even in the case of the current mirror method which is one of the current programming methods, as shown in FIG. 114, by forming or disposing a transistor 11g as a switching element between the driving transistor 11b and the EL element 15, 15 can be turned on and off (can be controlled). Of course, the transistor 11g may be replaced with the switch 1131 in FIG.
[0114]
Although the switching transistors 11d and 11c in FIG. 114 are connected to one gate signal line 17a, as shown in FIG. 115, the transistor 11c is controlled by the gate signal line 17a1, and the transistor 11d is connected to the gate signal line 17a. You may comprise so that it may control by the line 17a2. The versatility of the control of the pixel 16 is higher in the configuration of FIG.
[0115]
As shown in FIG. 42A, the transistors 11b and 11c may be formed by N-channel transistors. As shown in FIG. 42B, the transistors 11c and 11d may be formed by P-channel transistors.
[0116]
An object of the invention of this patent is to propose a circuit configuration in which variation in transistor characteristics does not affect display, and for that purpose, four or more transistors are required.
When determining circuit constants based on these transistor characteristics, it is difficult to determine appropriate circuit constants unless the characteristics of the four transistors are uniform. When the channel direction is horizontal and vertical with respect to the major axis direction of the laser irradiation, the threshold and the mobility of the transistor characteristics are formed differently. The degree of variation is the same in both cases. The mobility and the average value of the threshold are different between the horizontal direction and the vertical direction. Therefore, it is desirable that the channel directions of all the transistors forming the pixel be the same.
[0117]
When the capacitance value of the storage capacitor 19 is Cs and the off-state current value of the second transistor 11b is Ioff, it is preferable that the following expression is satisfied.
[0118]
3 <Cs / Ioff <24
More preferably, it is preferable to satisfy the following expression.
[0119]
6 <Cs / Ioff <18
By setting the off-state current of the transistor 11b to 5 pA or less, the change in the value of the current flowing through the EL can be suppressed to 2% or less. This is because, when the leak current increases, the charge stored between the gate and the source (both ends of the capacitor) cannot be held for one field in the voltage non-writing state. Therefore, if the storage capacity of the capacitor 19 is large, the allowable amount of the off-current becomes large. By satisfying the above expression, the variation of the current value between adjacent pixels can be suppressed to 2% or less.
[0120]
Further, it is preferable that the transistor forming the active matrix is formed as a p-channel polysilicon thin film transistor, and the transistor 11b has a multi-gate structure in which the transistor is a dual gate or more. Since the transistor 11b functions as a switch between the source and the drain of the transistor 11a, a characteristic having an ON / OFF ratio as high as possible is required. When the gate structure of the transistor 11b is a multi-gate structure equal to or greater than the dual-gate structure, characteristics with a high ON / OFF ratio can be realized.
[0121]
The semiconductor film forming the transistor 11 of the pixel 16 is generally formed by laser annealing in a low-temperature polysilicon technique. This variation in the conditions of the laser annealing results in variations in the characteristics of the transistor 11. However, if the characteristics of the transistors 11 in one pixel 16 match, in the method of performing the current programming shown in FIG. 1 or the like, it is possible to drive the EL element 15 so that a predetermined current flows through the EL element 15. This is an advantage over voltage programming. It is preferable to use an excimer laser as the laser.
[0122]
In the present invention, the formation of the semiconductor film is not limited to the laser annealing method, but may be a thermal annealing method or a method using solid phase (CGS) growth. In addition, it is needless to say that the present invention is not limited to the low-temperature polysilicon technology, but may use the high-temperature polysilicon technology. Further, a semiconductor film formed using an amorphous silicon technique may be used.
[0123]
To solve this problem, in the present invention, as shown in FIG. 7, a laser irradiation spot (laser irradiation range) 72 during annealing is irradiated in parallel to the source signal line 18. Further, the laser irradiation spot 72 is moved so as to coincide with one pixel column. Of course, the present invention is not limited to one pixel row. For example, a laser beam may be applied to RGB in FIG. 55 in units of one pixel 16 (in this case, three pixel rows). Further, a plurality of pixels may be irradiated simultaneously. Needless to say, the movements of the laser irradiation ranges may overlap (normally, the moving laser beam irradiation ranges usually overlap).
[0124]
The pixels are formed so as to have a square shape with three pixels of RGB. Therefore, each of the R, G, and B pixels has a vertically long pixel shape. Therefore, by making the laser irradiation spot 72 vertically long and performing annealing, it is possible to prevent the characteristic variation of the transistor 11 from occurring in one pixel. Further, the characteristics (mobility, Vt, S value, and the like) of the transistor 11 connected to one source signal line 18 can be made uniform (that is, the characteristics are different from those of the transistor 11 of the adjacent source signal line 18). However, the characteristics of the transistor 11 connected to one source signal line can be made substantially equal).
[0125]
In the configuration of FIG. 7, three panels are formed so as to be vertically arranged within the range of the length of the laser irradiation spot 72. The annealing device that irradiates the laser irradiation spot 72 recognizes the positioning markers 73a and 73b of the glass substrate 74 (automatic positioning by pattern recognition) and moves the laser irradiation spot 72. Recognition of the positioning marker 73 is performed by a pattern recognition device. The annealing device (not shown) recognizes the positioning marker 73 and determines the position of the pixel row (so that the laser irradiation range 72 is parallel to the source signal line 18). The laser irradiation spot 72 is irradiated so as to overlap the pixel column position, and annealing is sequentially performed.
[0126]
The laser annealing method (a method of irradiating a linear laser spot parallel to the source signal line 18) described with reference to FIG. 7 is preferably employed particularly in a current programming method of an organic EL display panel. This is because the characteristics of the transistor 11 match in the direction parallel to the source signal line (the characteristics of pixel transistors adjacent in the vertical direction are similar). Therefore, a change in the voltage level of the source signal line during current driving is small, and insufficient current writing is unlikely to occur.
[0127]
For example, in the case of white raster display, since the currents flowing through the transistors 11a of the adjacent pixels are almost the same, the change in the amplitude of the current output from the source driver IC 14 is small. If the characteristics of the transistor 11a in FIG. 1 are the same and the current values for current programming in each pixel are equal in the pixel column, the potential of the source signal line 18 during current programming is constant. Therefore, no fluctuation in the potential of the source signal line 18 occurs. If the characteristics of the transistors 11a connected to one source signal line 18 are substantially the same, the potential fluctuation of the source signal line 18 is small. This is the same for other current programming type pixel configurations such as FIG. 38 (that is, it is preferable to apply the manufacturing method of FIG. 7).
[0128]
Furthermore, uniform image display (because display unevenness mainly due to variations in transistor characteristics hardly occurs) can be realized by a method of simultaneously writing a plurality of pixel rows described in FIGS. In FIG. 27 and the like, a plurality of pixel rows are simultaneously selected. Therefore, if the transistors in adjacent pixel rows are uniform, the transistor characteristic unevenness in the vertical direction can be absorbed by the source driver circuit 14.
[0129]
In FIG. 7, the source driver circuit 14 is illustrated as being mounted with an IC chip. However, the present invention is not limited to this. The source driver circuit 14 may be formed in the same process as the pixel 16. Needless to say.
[0130]
In the present invention, in particular, the threshold voltage Vth2 of the driving transistor 11b is set so as not to be lower than the threshold voltage Vth1 of the corresponding driving transistor 11a in the pixel. For example, the gate length L2 of the transistor 11b is made longer than the gate length L1 of the transistor 11a so that Vth2 does not become lower than Vth1 even if the process parameters of these thin film transistors change. This makes it possible to suppress minute current leakage.
[0131]
The above items can also be applied to the pixel configuration of the current mirror shown in FIG. In FIG. 38, the pixel circuit and the data line data are controlled by controlling the gate signal line 17a1 in addition to the driving transistor 11a that controls the driving current flowing through the light emitting element including the EL element 15 and the driving transistor 11a through which the signal current flows. The take-in transistor 11c to be connected or cut off, the switching transistor 11d for short-circuiting the gate and drain of the transistor 11a during the writing period by controlling the gate signal line 17a2, and the gate-source voltage of the transistor 11a are retained even after the writing is completed. And a EL element 15 as a light emitting element.
[0132]
In FIG. 38, the transistors 11c and 11d are configured by N-channel transistors, and the other transistors are configured by P-channel transistors. However, this is an example, and is not necessarily required to be as described above. The capacitor Cs has one terminal connected to the gate of the transistor 11a and the other terminal connected to Vdd (power supply potential). However, the capacitance Cs is not limited to Vdd and may have any constant potential. The cathode (cathode) of the EL element 15 is connected to the ground potential.
[0133]
Next, the EL display panel or the EL display device of the present invention will be described. FIG. 6 is an explanatory diagram focusing on the circuit of the EL display device. The pixels 16 are arranged or formed in a matrix. Each pixel 16 is connected to a source driver circuit 14 that outputs a current for performing a current program for each pixel. At the output stage of the source driver circuit 14, a current mirror circuit corresponding to the number of bits of the video signal is formed (described later). For example, in the case of 64 gradations, 63 current mirror circuits are formed on each source signal line, and a desired current can be applied to the source signal line 18 by selecting the number of these current mirror circuits. (See FIG. 48).
[0134]
The minimum output current of one current mirror circuit is set to 10 nA or more and 50 nA. In particular, the minimum output current of the current mirror circuit is preferably 15 nA or more and 35 nA. This is to ensure the accuracy of the transistors constituting the current mirror circuit in the source driver IC 14.
[0135]
Further, a precharge or discharge circuit for forcibly releasing or charging the electric charge of the source signal line 18 is incorporated. It is preferable that the voltage (current) output value of the precharge or discharge circuit for forcibly releasing or charging the electric charge of the source signal line 18 can be set independently for R, G, and B. This is because the threshold value of the EL element 15 differs between RGB (for the precharge circuit, refer to FIGS. 65 and 67 and the description thereof).
[0136]
It is known that EL elements have large temperature-dependent characteristics (temperature characteristics). A non-linear element such as a thermistor or a posistor that changes the output current is added to the current mirror circuit in order to adjust the change in light emission luminance due to the temperature characteristic. Adjust (change) the current.
[0137]
In the present invention, the source driver 14 is formed of a semiconductor silicon chip, and is connected to the terminal of the source signal line 18 of the substrate 71 by glass-on-chip (COG) technology. The mounting of the source driver 14 is not limited to the COG technology, and the source driver IC 14 or the like described above may be mounted on a chip-on-film (COF) technology and connected to a signal line of a display panel. Further, the drive IC may have a three-chip configuration by separately manufacturing the power supply IC 82.
[0138]
On the other hand, the gate driver circuit 12 is formed by low-temperature polysilicon technology. That is, they are formed in the same process as the transistor of the pixel. This is because the internal structure is easier and the operating frequency is lower than that of the source driver circuit 14. Therefore, even if it is formed by low-temperature polysilicon technology, it can be easily formed, and a narrow frame can be realized. Of course, it goes without saying that the gate driver circuit 12 may be formed of a silicon chip and mounted on the substrate 71 using COG technology or the like. Further, switching elements such as pixel transistors, gate drivers, and the like may be formed by high-temperature polysilicon technology, or may be formed of an organic material (organic transistor).
[0139]
The gate driver circuit 12 includes a shift register circuit 61a for the gate signal line 17a and a shift register circuit 61b for the gate signal line 17b. Each shift register circuit 61 is controlled by positive-phase and negative-phase clock signals (CLKxP, CLKxN) and a start pulse (STx) (see FIG. 6). In addition, it is preferable to add an enable (ENABL) signal for controlling the output and non-output of the gate signal line, and an up-down (UPDWM) signal for reversing the shift direction. In addition, it is preferable to provide an output terminal or the like for confirming that the start pulse is shifted to the shift register and output. The shift timing of the shift register is controlled by a control signal from the control IC 81. Further, a level shift circuit for performing level shift of external data is incorporated.
[0140]
Since the buffer capacity of the shift register circuit 61 is small, the gate signal line 17 cannot be directly driven. Therefore, at least two or more inverter circuits 62 are formed between the output of the shift register circuit 61 and the output gate 63 for driving the gate signal line 17.
[0141]
The same applies to the case where the source driver 14 is formed directly on the substrate 71 by a polysilicon technique such as a low-temperature polysilicon, and between the gate of an analog switch such as a transfer gate for driving the source signal line 18 and the shift register of the source driver circuit 14. A plurality of inverter circuits are formed. The following items (the output of the shift register and the output stage for driving the signal lines (the items relating to the inverter circuit disposed between the output stages such as the output gate and the transfer gate)) are common to the source drive and gate drive circuits. is there.
[0142]
For example, FIG. 6 shows that the output of the source driver 14 is directly connected to the source signal line 18. However, in practice, the output of the shift register of the source driver is connected to a multi-stage inverter circuit, and The output is connected to the gate of an analog switch such as a transfer gate.
The inverter circuit 62 includes a P-channel MOS transistor and an N-channel MOS transistor. As described above, the inverter circuit 62 is connected in multiple stages to the output terminal of the shift register circuit 61 of the gate driver circuit 12, and the final output is connected to the output gate circuit 63. Note that the inverter circuit 62 may be configured with only the P channel. However, in this case, a simple gate circuit may be used instead of the inverter.
[0143]
FIG. 8 is a configuration diagram of the supply of signals and voltages of the display device of the present invention or a configuration diagram of the display device. Signals (power wiring, data wiring, etc.) supplied from the control IC 81 to the source driver circuit 14 a are supplied via the flexible substrate 84.
[0144]
In FIG. 8, the control signal of the gate driver circuit 12 is generated by the control IC, and is applied to the gate driver circuit 12 after the level shift is performed by the source driver 14. Since the drive voltage of the source driver 14 is 4 to 8 (V), the control signal having the 3.3 (V) amplitude output from the control IC 81 is converted into a 5 (V) amplitude that can be received by the gate driver circuit 12. Can be.
[0145]
Although 14 is described as a source driver in FIG. 8 and the like, not only a simple driver but also a power supply circuit, a buffer circuit (including a circuit such as a shift register), a data conversion circuit, a latch circuit, a command decoder, a shift circuit, an address A conversion circuit, an image memory, and the like may be incorporated. It goes without saying that the three-side free configuration or configuration, drive method, or the like described in FIG. 9 or the like can be applied to the configuration described in FIG. 8 or the like.
[0146]
When the display panel is used for an information display device such as a mobile phone, as shown in FIG. 9, the source driver IC (circuit) 14 and the gate driver IC (circuit) 12 are mounted (formed) on one side of the display panel. (Note that this form of mounting (forming) a driver IC (circuit) on one side is referred to as a three-side free configuration (structure). Conventionally, a gate driver IC 12 is mounted on the X side of the display area, and The source driver IC 14 was mounted on the side). This is because the center line of the screen 50 is easily designed to be at the center of the display device, and the mounting of the driver IC is also easy. Note that the gate driver circuit may be manufactured with a three-sided free structure using high-temperature polysilicon or low-temperature polysilicon technology (that is, at least one of the source driver circuit 14 and the gate driver circuit 12 in FIG. It is formed directly on the substrate 71 by a technique).
[0147]
The three-side free configuration means not only a configuration in which an IC is directly mounted or formed on the substrate 71 but also a film (TCP, TAB technology, etc.) on which a source driver IC (circuit) 14, a gate driver IC (circuit) 12, and the like are attached. ) Is attached to one side (or almost one side) of the substrate 71. In other words, it means a configuration, arrangement, or all similar structures in which an IC is not mounted or mounted on two sides.
[0148]
When the gate driver circuit 12 is arranged beside the source driver circuit 14 as shown in FIG. 9, the gate signal line 17 needs to be formed along the side C.
[0149]
In FIG. 9 and the like, the portions shown by thick solid lines indicate the portions where the gate signal lines 17 are formed in parallel. Therefore, the gate signal lines 17 corresponding to the number of the scanning signal lines are formed in parallel in the part b (the lower part of the screen), and one gate signal line 17 is formed in the part a (the upper part of the screen).
[0150]
The pitch of the gate signal lines 17 formed on the side C is 5 μm or more and 12 μm or less.
If it is less than 5 μm, noise will be added to the adjacent gate signal line due to the influence of parasitic capacitance. According to the experiment, the influence of the parasitic capacitance is remarkably generated at 7 μm or less. Further, when the diameter is less than 5 μm, image noise such as a beat is generated on the display screen. In particular, the occurrence of noise differs between the left and right sides of the screen, and it is difficult to reduce this beat-like image noise. On the other hand, when the reduction exceeds 12 μm, the frame width D of the display panel becomes too large and is not practical.
[0151]
In order to reduce the above-described image noise, a grant pattern (a conductive pattern fixed at a fixed voltage or set to a stable potential as a whole) is arranged below or above the portion where the gate signal line 17 is formed. This can be reduced. In addition, a shield plate (shield foil (a conductive pattern fixed at a fixed voltage or set to a stable potential as a whole)) provided separately may be disposed on the gate signal line 17.
[0152]
The gate signal line 17 on the side C in FIG. 9 may be formed by an ITO electrode, but is preferably formed by laminating ITO and a metal thin film in order to reduce resistance. In addition, it is preferable to form a metal film. When laminating with ITO, a titanium film is formed on the ITO, and aluminum or an alloy thin film of aluminum and molybdenum is formed thereon. Alternatively, a chromium film is formed on ITO. In the case of a metal film, it is formed of an aluminum thin film or a chromium thin film. The above is the same in other embodiments of the present invention.
[0153]
In FIG. 9 and the like, the gate signal lines 17 and the like are arranged on one side of the display area. However, the present invention is not limited to this, and they may be arranged on both sides. For example, the gate signal line 17a may be arranged (formed) on the right side of the display screen 50 and the gate signal line 17b may be arranged (formed) on the left side of the display screen 50. The above is the same in other embodiments.
[0154]
Further, the source driver IC 14 and the gate driver IC 12 may be integrated into one chip. If one chip is used, only one IC chip needs to be mounted on the display panel. Therefore, the mounting cost can be reduced. Also, various voltages used in the one-chip driver IC can be generated simultaneously.
[0155]
The source driver IC 14 and the gate driver IC 12 are fabricated on a semiconductor wafer such as silicon and mounted on a display panel. However, the present invention is not limited to this. Needless to say, this may be done.
[0156]
The pixels have three primary colors of R, G, and B, but are not limited thereto, and may have three colors of cyan, yellow, and magenta. Further, two colors of B and yellow may be used. Of course, it may be a single color. Further, six colors of R, G, B, cyan, yellow, and magenta may be used. R, G, B, cyan, and magenta may be used. These are natural colors, the color reproduction range is expanded, and good display can be realized. As described above, the EL display device of the present invention is not limited to the one that performs color display using the three primary colors of RGB.
[0157]
There are mainly three methods for colorizing an organic EL display panel, and the color conversion method is one of them. It is sufficient to form a single layer of only blue as the light emitting layer, and the remaining green and red necessary for full colorization are created by color conversion from blue light. Therefore, there is an advantage that there is no need to separately apply each layer of RGB, and it is not necessary to prepare organic EL materials of each color of RGB. The color conversion method does not lower the yield unlike the color separation method. The EL display panel and the like of the present invention can be applied to any of these methods.
[0158]
Further, pixels emitting white light may be formed in addition to the three primary colors. A pixel emitting white light can be realized by manufacturing (forming or forming) by stacking structures of R, G, and B light emission. One set of pixels includes three primary colors of RGB and a pixel 16W that emits white light. By forming a pixel that emits white light, it becomes easier to express white peak luminance. Therefore, it is possible to realize a bright image display.
[0159]
Even when a set of pixels includes three primary colors such as RGB, it is preferable that the areas of the pixel electrodes of each color be different. Of course, if the luminous efficiency of each color is well-balanced and the color purity is well-balanced, the same area may be used. However, if the balance of one or more colors is poor, it is preferable to adjust the pixel electrode (light emitting area).
The electrode area of each color may be determined based on the current density. In other words, when the white balance is adjusted within the range of the color temperature of 7000 K (Kelvin) or more and 12000 K or less, the difference of the current density of each color is set within ± 30%. More preferably, it is within ± 15%. For example, if the current density is 100 A / square meter, the three primary colors are set to be 70 A / square meter or more and 130 A / square meter or less. More preferably, all three primary colors are set to be 85 A / square meter or more and 115 A / square meter or less.
[0160]
The EL element 15 is a self light emitting element. When light due to this light emission enters a transistor as a switching element, a photoconductor phenomenon (photocon) occurs.
The photocon is a phenomenon in which leakage (off-leakage) when a switching element such as a transistor is off due to photoexcitation increases.
[0161]
In order to address this problem, in the present invention, a light-shielding film below the gate driver circuit 12 (or the source driver 14 in some cases) and the pixel transistor 11 is formed. The light-shielding film is formed of a thin metal film such as chromium and has a thickness of 50 nm or more and 150 nm or less. If the film thickness is small, the light-shielding effect is poor, and if the film thickness is large, unevenness occurs, making it difficult to pattern the upper transistor 11A1.
[0162]
The gate driver circuit 12 and the like should suppress the entry of light not only from the back surface but also from the front surface. This is because a malfunction occurs due to the influence of the photocon. Therefore, in the present invention, when the cathode electrode is a metal film, the cathode electrode is also formed on the surface of the driver 12 and the like, and this electrode is used as a light shielding film.
[0163]
However, if a cathode electrode is formed on the driver 12, the driver may malfunction due to an electric field from the cathode electrode, or electrical contact between the cathode electrode and the driver circuit may occur. In order to address this problem, in the present invention, at least one layer, preferably a plurality of layers of EL films are formed on the gate driver circuit 12 and the like at the same time when the EL films on the pixel electrodes are formed.
[0164]
When the terminals of one or more transistors 11 of the pixel or the transistor 11 and the signal line are short-circuited, the EL element 15 may always be a bright spot to be lit. Since the bright spot is visually prominent, it needs to be turned into a black spot (non-lighting). For the bright spot, the corresponding pixel 16 is detected, and the capacitor 19 is irradiated with laser light to short-circuit the terminals of the capacitor. Therefore, the charge cannot be held in the capacitor 19, so that the transistor 11a can prevent the current from flowing. It is desirable to remove the cathode film at the position where the laser beam is irradiated. This is to prevent a short circuit between the terminal electrode of the capacitor 19 and the cathode film due to laser irradiation.
[0165]
The defect of the transistor 11 of the pixel 16 affects the source driver IC 14 and the like. For example, in FIG. 45, when a source-drain (SD) short 452 occurs in the driving transistor 11a, the Vdd voltage of the panel is applied to the source driver IC 14. Therefore, it is preferable that the power supply voltage of the source driver IC 14 is equal to or higher than the power supply voltage Vdd of the panel. It is preferable that the reference current used in the source driver IC be adjusted by the electronic regulator 451.
[0166]
When the SD short 452 occurs in the transistor 11a, an excessive current flows through the EL element 15. That is, the EL element 15 is always in a lighting state (bright point). Bright spots are prominent as defects. For example, in FIG. 45, when the source-drain (SD) short-circuit of the transistor 11a occurs, a current always flows from the Vdd voltage to the EL element 15 regardless of the magnitude of the gate (G) terminal potential of the transistor 11a ( When the transistor 11d is on). Therefore, it becomes a bright spot.
[0167]
On the other hand, if an SD short occurs in the transistor 11a, the Vdd voltage is applied to the source signal line 18 and the Vdd voltage is applied to the source driver 14 when the transistor 11c is in the on state. If the power supply voltage of the source driver 14 is equal to or lower than Vdd, the withstand voltage may be exceeded and the source driver 14 may be broken. Therefore, the power supply voltage of the source driver 14 is preferably equal to or higher than the Vdd voltage (the higher voltage of the panel).
[0168]
An SD short circuit of the transistor 11a may cause not only a point defect but also a destruction of a source driver circuit of the panel, and a bright spot is conspicuous, resulting in a panel failure. Therefore, it is necessary to cut the wiring connecting the transistor 11a and the EL element 15 to make the bright spot a black spot defect. This cutting is preferably performed using an optical means such as a laser beam.
[0169]
Hereinafter, the driving method of the present invention will be described. As shown in FIG. 1, the gate signal line 17a is turned on during the row selection period (here, the transistor 11 in FIG. 1 is a p-channel transistor and turned on at a low level), and the gate signal line 17b is turned off during the non-selection period. Sometimes, it becomes conductive.
[0170]
The source signal line 18 has a parasitic capacitance (not shown). The parasitic capacitance is generated due to the capacitance at the cross section between the source signal line 18 and the gate signal line 17, the channel capacitance of the transistors 11b and 11c, and the like.
[0171]
Assuming that the time t required for changing the current value of the source signal line 18 is C, the voltage of the source signal line is V, and the current flowing through the source signal line is I, t = C · V / I. Being able to increase the value ten times can reduce the time required for changing the current value to nearly one-tenth. Alternatively, even if the parasitic capacitance of the source signal line 18 increases tenfold, it can be changed to a predetermined current value. Therefore, it is effective to increase the current value in order to write a predetermined current value within a short horizontal scanning period.
[0172]
When the input current is increased by a factor of ten, the output current also increases by a factor of ten, and the luminance of the EL increases by a factor of ten. To obtain a predetermined luminance, the conduction period of the transistor 17d in FIG. Is set to 1/10, so that a predetermined luminance is displayed. Note that the explanation is given by exemplifying 10 times for easy understanding. Needless to say, it is not limited to 10 times.
[0173]
That is, in order to sufficiently charge and discharge the parasitic capacitance of the source signal line 18 and to program the transistor 11a of the pixel 16 with a predetermined current value, it is necessary to output a relatively large current from the source driver 14. However, when such a large current flows through the source signal line 18, the current value is programmed into the pixel, and a large current flows to the EL element 15 with respect to a predetermined current. For example, if programming is performed with a 10-fold current, a 10-fold current naturally flows through the EL element 15, and the EL element 15 emits light with a 10-fold luminance. In order to achieve a predetermined light emission luminance, the time that flows through the EL element 15 may be reduced to 1/10. By driving in this manner, the parasitic capacitance of the source signal line 18 can be sufficiently charged and discharged, and a predetermined light emission luminance can be obtained.
[0174]
Note that a 10-fold current value is written to the transistor 11a of the pixel (accurately, the terminal voltage of the capacitor 19 is set), and the ON time of the EL element 15 is reduced to 1/10, but this is an example. In some cases, a 10-fold current value may be written to the transistor 11a of the pixel to reduce the ON time of the EL element 15 to 1/5. Conversely, a 10-fold current value may be written to the transistor 11a of the pixel, and the ON time of the EL element 15 may be reduced by half.
[0175]
The present invention is characterized in that the pixel is driven in such a manner that the write current to the pixel is set to a value other than a predetermined value and the current flowing through the EL element 15 is intermittent. In this specification, for the sake of simplicity, a description will be given assuming that an N-fold current value is written to the transistor 11 of the pixel and the ON time of the EL element 15 is reduced to 1 / N times. However, the present invention is not limited to this. It goes without saying that an N1 times current value is written to the transistor 11 of the pixel, and the ON time of the EL element 15 may be 1 / (N2) times (different from N1 and N2). .
[0176]
In the white raster display, it is assumed that the average luminance in one field (frame) period of the display screen 50 is B0. At this time, the current (voltage) programming is performed such that the luminance B1 of each pixel 16 is higher than the average luminance B0. In addition, the driving method is such that the non-display area 53 is generated in at least one field (frame) period. Therefore, in the driving method of the present invention, the average luminance during one field (frame) period is lower than B1.
[0177]
The intermittent intervals (non-display area 52 / display area 53) are not limited to equal intervals. For example, it may be random (as long as the display period or the non-display period is a predetermined value (constant ratio) as a whole). In addition, RGB may be different. That is, the driving method of the present invention may be adjusted (set) so that the R, G, B display period or the non-display period has a predetermined value (constant ratio) so that the white (white) balance is optimal. 1 / N will be described as 1 / N with reference to 1F (one field or one frame). However, it is needless to say that there is a time during which one pixel row is selected and a current value is programmed (usually, one horizontal scanning period (1H)), and an error occurs depending on a scanning state.
[0178]
For example, the current may be programmed in the pixel 16 with N = 10 times the current, and the EL element 15 may be turned on for 1/5 period. The EL element 15 is turned on with 10/5 = 2 times the luminance. The current may be programmed into the pixel 16 with N = 2 times the current, and the EL element 15 may be turned on for a period of ４. The EL element 15 is lit at a luminance of 2/4 = 0.5 times. In other words, in the present invention, programming is performed with a current that is not N = 1 times, and a display other than the state of always lighting (1/1, that is, not intermittent display) is performed. Further, the driving method is such that the current supplied to the EL element 15 is turned off at least once in one frame (or one field) period. In addition, the driving method is such that the pixel 16 is programmed with a current larger than a predetermined value, and at least intermittent display is performed.
[0179]
The organic (inorganic) EL display device also has a problem that a display method is fundamentally different from a display such as a CRT which displays an image as a set of line displays by an electron gun. That is, in the EL display device, the current (voltage) written to the pixel is held during the period of 1F (one field or one frame). Therefore, there is a problem that when displaying a moving image, the outline of a displayed image is blurred.
[0180]
In the present invention, a current flows through the EL element 15 only during the 1F / N period, and does not flow during the other period (1F (N-1) / N). Consider a case in which this driving method is implemented and one point on the screen is observed. In this display state, image data display and black display (non-lighting) are repeatedly displayed every 1F. That is, the image data display state is temporally intermittent display state. When the moving image data display is viewed in the intermittent display state, a good display state can be realized without blurring of the outline of the image. That is, it is possible to realize moving image display close to a CRT.
[0181]
According to the driving method of the present invention, intermittent display is realized. However, the intermittent display only needs to perform on / off control of the transistor 11d in a 1H cycle. Therefore, since the main clock of the circuit is not different from the conventional one, the power consumption of the circuit does not increase. The liquid crystal display panel requires an image memory to realize intermittent display. In the present invention, image data is held in each pixel 16. Therefore, an image memory for performing intermittent display is unnecessary.
[0182]
According to the present invention, the current flowing to the EL element 15 is controlled only by turning on / off the switching transistor 11d or the transistor 11e. That is, even if the current Iw flowing through the EL element 15 is turned off, the image data is held in the capacitor 19 as it is. Therefore, when the switching transistor 11d and the like are turned on at the next timing and a current flows through the EL element 15, the flowing current is the same as the previously flowing current value. In the present invention, it is not necessary to increase the main clock of the circuit even when black insertion (intermittent display such as black display) is realized. In addition, there is no need for an image memory because it is not necessary to extend the time axis. In addition, the EL element 15 has a short time from application of a current to emission of light, and responds at high speed. Therefore, it is possible to solve the problem of displaying a moving image, which is a problem of a conventional data holding type display panel (a liquid crystal display panel, an EL display panel, and the like) which is suitable for displaying a moving image and performing intermittent display.
[0183]
Further, when the wiring length of the source signal line 18 is increased and the parasitic capacitance of the source signal line 18 is increased in a large display device, it is possible to cope with the problem by increasing the N value. When the value of the program current applied to the source signal line 18 is N times, the conduction period of the gate signal line 17b (transistor 11d) may be set to 1F / N. Accordingly, the present invention can be applied to a large display device such as a television and a monitor.
[0184]
Hereinafter, the driving method of the present invention will be described in more detail with reference to the drawings. The parasitic capacitance of the source signal line 18 is generated by a coupling capacitance between adjacent source signal lines 18, a buffer output capacitance of the source drive IC (circuit) 14, a cross capacitance between the gate signal line 17 and the source signal line 18, and the like. This parasitic capacitance is usually 10 pF or more. In the case of voltage driving, since a voltage is applied to the source signal line 18 with low impedance from the source driver IC 14, even if the parasitic capacitance is somewhat large, there is no problem in driving.
[0185]
However, in the case of current driving, particularly for displaying an image at a black level, it is necessary to program the capacitor 19 of the pixel with a very small current of 20 nA or less. Therefore, when the parasitic capacitance is generated with a magnitude equal to or larger than a predetermined value, the time required for programming one pixel row (usually within 1H, but is not limited to 1H since two pixel rows may be written simultaneously). ), The parasitic capacitance cannot be charged and discharged. If charge and discharge cannot be performed in the 1H period, writing to the pixel will be insufficient, and the resolution will not be high.
[0186]
In the case of the pixel configuration of FIG. 1, as shown in FIG. 3A, at the time of current programming, a program current Iw flows through the source signal line 18. The voltage is set (programmed) on the capacitor 19 so that the current Iw flows through the transistor 11a and the current flowing Iw is held. At this time, the transistor 11d is in an open state (off state).
[0187]
Next, during a period in which a current flows through the EL element 15, the transistors 11c and 11b are turned off and the transistor 11d operates as shown in FIG. That is, an off voltage (Vgh) is applied to the gate signal line 17a, and the transistors 11b and 11c are turned off. On the other hand, an on-voltage (Vgl) is applied to the gate signal line 17b, turning on the transistor 11d.
[0188]
Now, assuming that the current I1 is N times the current (predetermined value) originally flowing, the current flowing through the EL element 15 in FIG. 3B also becomes Iw. Therefore, the EL element 15 emits light at a luminance 10 times the predetermined value. That is, as shown in FIG. 12, as the magnification N increases, the display luminance B of the pixel 16 also increases. Therefore, the magnification and the luminance of the pixel 16 have a proportional relationship.
[0189]
Therefore, if the transistor 11d is turned on only for 1 / N of the time that the transistor 11d is originally turned on (approximately 1F) and is turned off for the other period (N-1) / N, the average brightness of the entire 1F is a predetermined brightness. Become. This display state is similar to a CRT scanning the screen with an electron gun. The difference is that the display range of the image is 1 / N of the entire screen (the entire screen is 1). (On a CRT, the lit range is one pixel row (strictly, Is one pixel).
[0190]
In the present invention, the 1F / N image display area 53 moves from the top to the bottom of the screen 50 as shown in FIG. In the present invention, a current flows through the EL element 15 only during the 1F / N period, and no current flows during the other period (1F · (N−1) / N). Therefore, each pixel 16 is displayed intermittently. However, since the image is held by human eyes due to the afterimage, the entire screen appears to be displayed uniformly.
[0191]
Note that, as shown in FIG. 13, the writing pixel row 51a is a non-lighting display 52a. However, this is the case with the pixel configuration shown in FIGS. In the pixel configuration of the current mirror illustrated in FIG. 38 and the like, the writing pixel row 51a may be turned on. However, in this specification, in order to facilitate the description, description will be made mainly by exemplifying the pixel configuration in FIG. A driving method in which programming is performed with a current larger than the predetermined driving current Iw and intermittent driving as in FIGS. 13 and 16 is called N-fold pulse driving.
[0192]
In this display state, image data display and black display (non-lighting) are repeatedly displayed every 1F. In other words, the image data display state is a temporally intermittent display (intermittent display) state. In a liquid crystal display panel (an EL display panel other than the present invention), data is held in pixels for the period of 1F. Therefore, in the case of moving image display, even if image data changes, the change cannot be followed. The video was blurred (outline blur of the image).
However, according to the present invention, since the image is displayed intermittently, the outline of the image is not blurred and a favorable display state can be realized. That is, it is possible to realize moving image display close to a CRT.
[0193]
As shown in FIG. 13, in order to drive, the current programming period of the pixel 16 (the period in which the ON voltage Vgl of the gate signal line 17a is applied in the pixel configuration of FIG. 1) and the EL element It is necessary to be able to independently control the period during which the gate 15 is turned off or on (in the pixel configuration in FIG. 1, the period during which the on voltage Vgl or the off voltage Vgh of the gate signal line 17b is applied). Therefore, the gate signal lines 17a and 17b need to be separated.
[0194]
For example, when there is one gate signal line 17 wired from the gate driver circuit 12 to the pixel 16, the logic (Vgh or Vgl) applied to the gate signal line 17 is applied to the transistor 11 b and the gate signal line 17 is connected to the gate signal line 17. In a configuration in which the applied logic is converted (Vgl or Vgh) by an inverter and applied to the transistor 11d, the driving method of the present invention cannot be implemented. Therefore, in the present invention, a gate driver circuit 12a for operating the gate signal line 17a and a gate driver circuit 12b for operating the gate signal line 17b are required.
[0195]
In addition, the driving method of the present invention is a driving method for non-lighting display even in the pixel configuration of FIG. 1 and in a period other than the current programming period (1H).
[0196]
FIG. 14 shows a timing chart of the driving method in FIG. Note that, in the present invention and the like, the pixel configuration unless otherwise specified is shown in FIG. As can be seen from FIG. 14, when the ON voltage (Vgl) is applied to the gate signal line 17a in each selected pixel row (selection period is 1H) (see FIG. 14A). In FIG. 14, an off voltage (Vgh) is applied to the gate signal line 17b (see FIG. 14B). During this period, no current flows through the EL element 15 (non-lighting state). In an unselected pixel row, an off voltage (Vgh) is applied to the gate signal line 17a, and an on voltage (Vgl) is applied to the gate signal line 17b. Further, during this period, a current flows through the EL element 15 (lighting state).
Further, in the lighting state, the EL element 15 is lit at a predetermined N-fold luminance (NB), and the lighting period is 1 F / N. Therefore, the display luminance of the display panel obtained by averaging 1F is (N · B) × (1 / N) = B (predetermined luminance).
[0197]
FIG. 15 shows an embodiment in which the operation of FIG. 14 is applied to each pixel row. 3 shows a voltage waveform applied to the gate signal line 17. In the voltage waveform, the off voltage is Vgh (H level), and the on voltage is Vgl (L level). Subscripts such as (1) and (2) indicate the selected pixel row number.
[0198]
In FIG. 15, a gate signal line 17a (1) is selected (Vgl voltage), and a program current flows through the source signal line 18 from the transistor 11a of the selected pixel row toward the source driver 14. This program current is N times a predetermined value (N will be described as N = 10 for ease of explanation. Of course, the predetermined value is a data current for displaying an image, and is not a fixed value unless white raster display or the like is used. )). Therefore, the capacitor 19 is programmed so that a current flows ten times to the transistor 11a. When the pixel row (1) is selected, an off voltage (Vgh) is applied to the gate signal line 17b (1) in the pixel configuration of FIG. 1, and no current flows through the EL element 15.
[0199]
After 1H, the gate signal line 17a (2) is selected (Vgl voltage), and a program current flows through the source signal line 18 from the transistor 11a of the selected pixel row toward the source driver 14. This program current is N times the predetermined value (for the sake of simplicity, it is assumed that N = 10). Therefore, the capacitor 19 is programmed so that a current flows ten times to the transistor 11a. When the pixel row (2) is selected, an off voltage (Vgh) is applied to the gate signal line 17b (2) in the pixel configuration of FIG. 1, and no current flows through the EL element 15. However, the off-state voltage (Vgh) is applied to the gate signal line 17a (1) of the previous pixel row (1), and the on-state voltage (Vgl) is applied to the gate signal line 17b (1). It has become.
[0200]
After the next 1H, the gate signal line 17a (3) is selected, the off voltage (Vgh) is applied to the gate signal line 17b (3), and no current flows through the EL element 15 of the pixel row (3). However, the off voltage (Vgh) is applied to the gate signal lines 17a (1) (2) of the previous pixel row (1) (2), and the on voltage (Vgl) is applied to the gate signal lines 17b (1) (2). ) Is applied, so that it is turned on.
[0201]
The above operation is synchronized with the 1H synchronization signal to display an image. However, in the driving method shown in FIG. 15, a 10-fold current flows through the EL element 15. Therefore, the display screen 50 is displayed with about ten times the brightness. Of course, in order to perform a predetermined luminance display in this state, it goes without saying that the program current may be reduced to 1/10. However, if the current is 1/10, insufficient writing occurs due to parasitic capacitance or the like. Therefore, it is the basic gist of the present invention to program with a high current and obtain a predetermined luminance by inserting the black screen 52.
[0202]
Note that, in the driving method of the present invention, the concept is that a current higher than a predetermined current flows through the EL element 15 and the parasitic capacitance of the source signal line 18 is sufficiently charged and discharged. That is, it is not necessary to supply N times the current to the EL element 15. For example, a current path is formed in parallel with the EL element 15 (a dummy EL element is formed, and this EL element is formed with a light shielding film so as not to emit light). You may shed. For example, when the signal current is 0.2 μA, the program current is set to 2.2 μA, and 2.2 μA is supplied to the transistor 11 a. Among these currents, a method in which a signal current of 0.2 μA flows to the EL element 15 and a current of 2 μA flows to the dummy EL element is exemplified. That is, the dummy pixel row 271 in FIG. 27 is always in the selected state. The dummy pixel row is configured not to emit light or to form a light-shielding film or the like so that even if it emits light, it is not visible.
[0203]
With the above-described configuration, by increasing the current flowing through the source signal line 18 by N times, it is possible to program the driving transistor 11a so that the current flows N times. In this case, a current sufficiently smaller than N times can flow. In the above method, as shown in FIG. 5, the entire display screen 50 can be used as the image display area 53 without providing the non-display area 52.
[0204]
FIG. 13A illustrates a state of writing on the display screen 50. In FIG. 13A, reference numeral 51a denotes a writing pixel row. A program current is supplied from the source driver IC 14 to each source signal line 18. In FIG. 13 and the like, one pixel row is written in the 1H period. However, it is not limited to 1H at all, and may be a 0.5H period or a 2H period. In addition, although a program current is written to the source signal line 18, the present invention is not limited to the current program method, and a voltage program method (FIG. 46 or the like) in which data is written to the source signal line 18 may be used. .
[0205]
In FIG. 13A, when the gate signal line 17a is selected, the current flowing through the source signal line 18 is programmed in the transistor 11a. At this time, an off voltage is applied to the gate signal line 17b, and no current flows through the EL element 15. This is because when the transistor 11d is in the ON state on the EL element 15 side, the capacitance component of the EL element 15 can be seen from the source signal line 18 and the capacitance cannot be used to perform sufficiently accurate current programming in the capacitor 19. It is. Therefore, in the configuration of FIG. 1 as an example, a pixel row to which a current is written becomes the non-display area 52 as shown in FIG.
[0206]
Assuming that the current is programmed with N times (here, N = 10 as described above) times, the brightness of the screen becomes 10 times. Therefore, the 90% range of the display screen 50 may be set as the non-display area 52. Therefore, if the number of horizontal scanning lines in the image display area is 220 lines of QCIF (S = 220), 22 lines and the display region 53 may be used, and 220−22 = 198 lines may be used as the non-display region 52. Generally speaking, if the horizontal scanning line (the number of pixel rows) is S, the S / N area is the display area 53, and the display area 53 emits light at N times the luminance. Then, the display area 53 is scanned in the vertical direction of the screen. Therefore, the area of S (N-1) / N is set as the non-display area 52.
This non-display area is for black display (non-light emission). The non-light emitting section 52 is realized by turning off the transistor 11d. It is to be noted that the light is turned on at N times the brightness, but it goes without saying that the brightness is adjusted to N times by gamma adjustment.
[0207]
Further, in the above embodiment, if the programming is performed with a current 10 times, the luminance of the screen is increased by a factor of 10, and the 90% range of the display screen 50 may be set as the non-display area 52. However, this is not limited to the case where the RGB pixels are commonly used as the non-display area 52. For example, for the R pixel, 1/8 is the non-display area 52, the G pixel is 1/6 the non-display area 52, and the B pixel is 1/10 the non-display area 52. May be changed. In addition, the non-display area 52 (or the display area 53) may be individually adjusted with RGB colors. In order to realize these, separate gate signal lines 17b are required for R, G, and B. However, by enabling the above-described individual adjustment of RGB, it is possible to adjust the white balance, and it becomes easy to adjust the color balance in each gradation (see FIG. 41).
[0208]
As shown in FIG. 13B, a pixel row including the writing pixel row 51a is a non-display area 52, and a range of S / N (1F / N in time) on a screen above the writing pixel row 51a. Is the display area 53 (if the writing scan is from the top to the bottom of the screen, if the screen is scanned from the bottom to the top, the reverse is true). In the image display state, the display area 53 has a band shape and moves from the top to the bottom of the screen.
[0209]
In the display of FIG. 13, one display area 53 moves downward from the top of the screen. When the frame rate is low, the movement of the display area 53 is visually recognized. In particular, it becomes easier to recognize when the eyelids are closed or when the face is moved up and down.
[0210]
To solve this problem, the display area 53 may be divided into a plurality of parts as shown in FIG. If the divided sum has an area of S (N-1) / N, the brightness becomes equal to the brightness in FIG. The divided display areas 53 need not be equal (equally divided). Also, the divided non-display areas 52 need not be equal.
[0211]
As described above, the screen flicker is reduced by dividing the display area 53 into a plurality. Therefore, flicker does not occur, and good image display can be realized. The division may be made finer. However, the more the image is divided, the lower the moving image display performance.
[0212]
FIG. 17 illustrates the voltage waveform of the gate signal line 17 and the emission luminance of EL. As is clear from FIG. 17, the period (1F / N) in which the gate signal line 17b is set to Vgl is divided into a plurality (division number K). In other words, the period of 1 V / (K · N) is performed K times during the period of setting Vgl. With such control, the occurrence of flicker can be suppressed, and an image display at a low frame rate can be realized. In addition, it is preferable that the number of divisions of the image is configured to be variable. For example, the user may press the brightness adjustment switch or turn the brightness adjustment volume to detect this change and change the value of K. Further, the configuration may be such that the user adjusts the luminance. You may comprise so that it may change manually or automatically according to the content and data of the image to be displayed.
[0213]
In FIG. 17 and the like, the period (1F / N) for setting the gate signal line 17b to Vgl is divided into a plurality (division number K), and the period for setting Vgl to 1F / (K · N) is implemented K times. However, this is not a limitation. The period of 1F / (K · N) may be performed L (L ≠ K) times. That is, in the present invention, the screen 50 is displayed by controlling the period (time) of flowing to the EL element 15. Therefore, performing the period of 1F / (K · N) L (L ≠ K) times is included in the technical idea of the present invention. Also, by changing the value of L, the luminance of the screen 50 can be digitally changed. For example, when L = 2 and L = 3, the luminance (contrast) changes by 50%. When the image display area 53 is divided, the period during which the gate signal line 17b is set to Vgl is not limited to the same period.
[0214]
In the above embodiment, the display screen 50 is turned on / off (lighting / non-lighting) by interrupting the current flowing through the EL element 15 and connecting the current flowing through the EL element. That is, substantially the same current flows through the transistor 11a a plurality of times by the charges held in the capacitor 19. The present invention is not limited to this. For example, a method may be used in which the display screen 50 is turned on / off (lighting / non-lighting) by charging / discharging the electric charge held in the capacitor 19.
[0215]
FIG. 18 shows a voltage waveform applied to the gate signal line 17 for realizing the image display state of FIG. The difference between FIG. 18 and FIG. 15 is the operation of the gate signal line 17b. The gate signal lines 17b are turned on and off (Vgl and Vgh) by the number corresponding to the number of screen divisions. The other points are the same as those in FIG.
[0216]
In the EL display device, the black display is completely turned off, so that the contrast does not decrease as in the case where the liquid crystal display panel is intermittently displayed. In addition, in the configurations of FIGS. 1, 2, 32, 43, and 117, intermittent display can be realized only by turning on / off the transistor 11d. 38, 51, and 115, intermittent display can be realized only by turning on / off the transistor element 11e. In FIG. 113, intermittent display can be realized by controlling the switching circuit 1131. In FIG. 114, intermittent display can be realized by controlling on / off of the transistor 11g. This is because image data is stored in the capacitor 19 (the number of gradations is infinite because it is an analog value). That is, the image data is held in each pixel 16 during the period of 1F. Whether the current corresponding to the held image data flows to the EL element 15 is realized by controlling the transistors 11d and 11e.
[0219]
Therefore, the above driving method is not limited to the current driving method, but can be applied to the voltage driving method. In other words, in a configuration in which the current flowing through the EL element 15 is stored in each pixel, intermittent driving is realized by turning on and off the current path between the driving transistor 11 and the EL element 15.
[0218]
Maintaining the terminal voltage of the capacitor 19 is important for reducing flicker and reducing power consumption. This is because if the terminal voltage of the capacitor 19 changes (charges and discharges) during one field (frame) period, the screen brightness changes, and flicker (flicker etc.) occurs when the frame rate decreases. It is necessary that the current that the transistor 11a passes through the EL element 15 during one frame (one field) period does not decrease to at least 65% or less. This 65% means that the current flowing to the EL element 15 immediately before writing to the pixel 16 in the next frame (field) is 65% or more when the initial current of writing to the pixel 16 and flowing to the EL element 15 is 100%. It is to be.
[0219]
In the pixel configuration of FIG. 1, the number of transistors 11 forming one pixel does not change when intermittent display is realized or not. That is, the effect of the parasitic capacitance of the source signal line 18 is eliminated while the pixel configuration is kept as it is, and a good current program is realized. In addition, a moving image display similar to that of a CRT is realized.
[0220]
Further, since the operation clock of the gate driver circuit 12 is sufficiently slower than the operation clock of the source driver circuit 14, the main clock of the circuit does not increase. Further, it is easy to change the value of N.
[0221]
The image display direction (image writing direction) may be downward from the top of the screen in the first field (first frame), and may be upward from the bottom of the screen in the second field (frame). That is, the direction from top to bottom and the direction from bottom to top are alternately repeated.
[0222]
Further, in the first field (first frame), the screen is set downward from the top, and once the entire screen is displayed in black (non-display), in the second field (frame), the screen is set downward from the bottom. Is also good. Further, the entire screen may be displayed black (non-display) once.
[0223]
In the above description of the driving method, the screen writing method is described from the top to the bottom or from the bottom to the top of the screen. However, the invention is not limited to this. The writing direction of the screen is constantly fixed from top to bottom or bottom to top. The operation direction of the non-display area 52 is from top to bottom in the first field, and the bottom of the screen in the second field. May be upward. Also, one frame may be divided into three fields, and one frame may be formed by three fields, with R being the first field, G being the second field, and B being the third field. Further, R, G, and B may be switched and displayed every one horizontal scanning period (1H) (see FIGS. 125 to 132 and the description thereof). The above is the same in other embodiments of the present invention.
[0224]
The non-display area 52 does not need to be completely turned off. There is no practical problem even if there is weak light emission or low-luminance image display. That is, it should be interpreted as a region where the display luminance is lower than that of the image display region 53. The non-display area 52 includes a case where only one or two colors of the R, G, and B image displays are in the non-display state.
Further, a case where only one or two colors of the R, G, and B image displays are in a low-luminance image display state is also included.
[0225]
Basically, when the brightness (brightness) of the display area 53 is maintained at a predetermined value, the brightness of the screen 50 increases as the area of the display area 53 increases. For example, when the luminance of the display area 53 is 100 (nt), if the ratio of the display area 53 to the display screen 50 is changed from 10% to 20%, the luminance of the screen is doubled. Therefore, by changing the area of the display area 53 occupying the display screen 50, the display luminance of the screen can be changed. The display brightness of the screen 50 is proportional to the ratio of the display area 53 to the screen 50.
[0226]
The area of the display area 53 can be arbitrarily set by controlling the data pulse (ST2) to the shift register 61. The display state of FIG. 16 and the display state of FIG. 13 can be switched by changing the input timing and cycle of the data pulse. If the number of data pulses in the 1F cycle is increased, the screen 50 becomes brighter, and if it is reduced, the screen 50 becomes darker. When the data pulse is continuously applied, the display state shown in FIG. 13 is obtained. When the data pulse is intermittently input, the display state shown in FIG. 16 is obtained.
[0227]
FIG. 19A shows a brightness adjustment method when the display area 53 is continuous as shown in FIG. The display luminance of the screen 50 in (a1) of FIG. 19 is the brightest. The display brightness of the screen 50 in (a2) of FIG. 19 is the next brightest, and the display brightness of the screen 50 of (a3) in FIG. 19 is the darkest. FIG. 19A is most suitable for displaying a moving image.
[0228]
The change from (a1) in FIG. 19 to (a3) in FIG. 19 (or vice versa) can be easily realized by controlling the shift register circuit 61 of the gate driver circuit 12 as described above. At this time, it is not necessary to change the Vdd voltage in FIG. That is, the luminance of the display screen 50 can be changed without changing the power supply voltage. Further, at the time of the change from (a1) in FIG. 19 to (a3) in FIG. 19, the gamma characteristic of the screen does not change at all. Therefore, the contrast and gradation characteristics of the displayed image are maintained regardless of the luminance of the screen 50. This is an advantageous feature of the present invention.
[0229]
In the conventional brightness adjustment of the screen, when the brightness of the screen 50 is low, the gradation performance is reduced. In other words, in most cases, 64 gray scale display can be realized at the time of high luminance display, but only less than half the number of gray scales can be displayed at the time of low luminance display. In comparison, the driving method of the present invention can realize the highest 64 gradation display without depending on the display luminance of the screen.
[0230]
FIG. 19B shows a brightness adjustment method when the display areas 53 are dispersed as shown in FIG. The display brightness of the screen 50 in (b1) of FIG. 19 is the brightest. The display luminance of the screen 50 in (b2) of FIG. 19 is the next brightest, and the display luminance of the screen 50 of (b3) in FIG. 19 is the darkest. The change from (b1) in FIG. 19 to (b3) in FIG. 19 (or vice versa) can be easily realized by controlling the shift register circuit 61 of the gate driver circuit 12 as described above. If the display areas 53 are dispersed as shown in FIG. 19B, flicker does not occur even at a low frame rate.
[0231]
In order to prevent flicker even at a low frame rate, the display area 53 may be finely dispersed as shown in FIG. However, the display performance of moving images is reduced. Therefore, the driving method of FIG. 19A is suitable for displaying a moving image. When a still image is displayed and low power consumption is desired, the driving method shown in FIG. 19C is suitable. The switching of the driving method from FIG. 19A to FIG. 19C can be easily realized by controlling the shift register 61.
[0232]
The above embodiment is mainly an embodiment in which N = 2 times, 4 times, and the like. However, it goes without saying that the present invention is not limited to integer multiples. Further, it is not limited to N = 2 or more. For example, an area less than half of the display screen 50 at a certain time may be set as the non-display area 52. If a current is programmed with a current Iw that is 5/4 times the predetermined value and the LED is turned on for 4/5 of 1F, a predetermined luminance can be realized.
[0233]
The present invention is not limited to this. As an example, there is a method in which current programming is performed with a current Iw that is 10/4 times larger and lighting is performed during a 4/5 period of 1F.
In this case, the light is lit at twice the predetermined luminance. There is also a method in which current programming is performed with a current Iw that is 5/4 times as much as the current Iw and lighting is performed for 2/5 of 1F. In this case, the light is turned on at half the predetermined luminance. There is also a method in which current programming is performed with a current Iw that is 5/4 times larger and lighting is performed during a 1/1 period of 1F. In this case, the light is lit at 5/4 times the predetermined luminance.
[0234]
That is, the present invention is a method of controlling the luminance of the display screen by controlling the magnitude of the program current and the lighting period of 1F. In addition, by turning on the light for a period shorter than the 1F period, the black screen 52 can be inserted, and the moving image display performance can be improved. A bright screen can be displayed by turning on the light constantly during the period of 1F.
[0235]
When the pixel size is A square mm and the predetermined white raster display brightness is B (nt), the program current I (μA) is as follows:
(A × B) / 20 <= I <= (A × B)
It is preferable to set it in the range. Luminous efficiency is improved, and insufficient current writing is eliminated.
[0236]
Further, preferably, the program current I (μA) is
(A × B) / 10 <= I <= (A × B)
It is preferable to set it in the range.
[0237]
FIG. 20 is an explanatory diagram of another embodiment for increasing the current flowing through the source signal line 18. Basically, a plurality of pixel rows are selected at the same time, and the parasitic capacitance and the like of the source signal line 18 are charged / discharged with the combined current of the plurality of pixel rows, thereby greatly improving the insufficient current writing. However, since a plurality of pixel rows are selected at the same time, the driving current per pixel can be reduced. Therefore, the current flowing through the EL element 15 can be reduced. Here, for ease of explanation, an example will be described where N = 10 (the current flowing through the source signal line 18 is increased by a factor of 10).
[0238]
In the present invention described with reference to FIG. 20, the pixel row selects M pixel rows at the same time. The source driver IC 14 applies a current N times the predetermined current to the source signal line 18. A current N / M times the current flowing through the EL element 15 is programmed in each pixel. As an example, in order for the EL element 15 to have a predetermined light emission luminance, the time flowing through the EL element 15 is set to M / N time of one frame (one field) (however, the invention is not limited to M / N. / N is for easy understanding. Needless to say, as described above, it can be freely set depending on the luminance of the screen 50 to be displayed.) By driving in this manner, the parasitic capacitance of the source signal line 18 can be sufficiently charged and discharged, and a satisfactory resolution and a predetermined emission luminance can be obtained.
[0239]
The current is supplied to the EL element 15 only during the M / N period of one frame (one field), and the current is not displayed during the other period (1F (N-1) M / N). In this display state, image data display and black display (non-lighting) are repeatedly displayed every 1F. In other words, the image data display state is a temporally intermittent display (intermittent display) state. Therefore, it is possible to realize good moving image display without blurring of the outline of the image. Further, since the source signal line 18 is driven with N times the current, it is possible to cope with a high definition display panel without being affected by the parasitic capacitance.
[0240]
FIG. 21 is an explanatory diagram of driving waveforms for realizing the driving method of FIG. The signal waveform has an off voltage of Vgh (H level) and an on voltage of Vgl (L level). The suffix of each signal line indicates the pixel row number ((1), (2), (3), etc.). The number of rows is 220 for the QCIF display panel and 480 for the VGA panel.
[0241]
In FIG. 21, a gate signal line 17a (1) is selected (Vgl voltage), and a program current flows through the source signal line 18 from the transistor 11a of the selected pixel row toward the source driver 14. Here, for the sake of simplicity, it is assumed that the write pixel row 51a is the first pixel row.
[0242]
Further, the program current flowing through the source signal line 18 is N times a predetermined value (for the sake of simplicity, the description will be made on the assumption that N = 10. Of course, the predetermined value is a data current for displaying an image, so that white raster display is used. It is not a fixed value unless it is the same.) Further, description will be made assuming that five pixel rows are simultaneously selected (M = 5). Therefore, ideally, the capacitor 19 of one pixel is programmed so that the current flows twice (N / M = 10/5 = 2) to the transistor 11a.
[0243]
When the writing pixel row is the (1) -th pixel row, (1), (2), (3), (4), and (5) are selected as the gate signal lines 17a as shown in FIG. That is, the switching transistors 11b and 11c of the pixel rows (1), (2), (3), (4), and (5) are on. The gate signal line 17b has an opposite phase to the gate signal line 17a. Therefore, the switching transistors 11d of the pixel rows (1), (2), (3), (4), and (5) are off, and no current flows through the EL element 15 of the corresponding pixel row. That is, it is the non-lighting state 52.
[0244]
Ideally, the transistors 11a of the five pixels each pass a current of Iw × 2 to the source signal line 18 (that is, Iw × 2 × N = Iw × 2 × 5 = Iw × 10 for the source signal line 18). Therefore, if the predetermined current Iw is the case where the N-fold pulse drive of the present invention is not performed, a current 10 times the Iw flows through the source signal line 18).
[0245]
By the above operation (driving method), a double current is programmed in the capacitor 19 of each pixel 16. Here, in order to facilitate understanding, the description will be made assuming that the characteristics (Vt, S value) of the transistors 11a match.
[0246]
Since five pixel rows are selected simultaneously (M = 5), five driving transistors 11a operate. That is, a current of 10/5 = 2 times flows through the transistor 11a per pixel. In the source signal line 18, a current obtained by adding the program current of the five transistors 11a flows. For example, the write current Iw is originally written in the write pixel row 51 a, and a current of Iw × 10 flows through the source signal line 18.
This is a pixel row used as an auxiliary to increase the amount of current flowing to the source signal line 18 in the write pixel row 51b in which image data is written after the write pixel row (1). However, there is no problem in the writing pixel row 51b because normal image data is written later.
[0247]
Therefore, in the four pixel rows 51b, the display is the same as that of 51a during the 1H period. Therefore, at least the non-display state 52 is set for the writing pixel row 51a and the pixel row 51b selected for increasing the current. However, in the pixel configuration of the current mirror as shown in FIG. 38 and other pixel configurations of the voltage programming method, the display state may be set.
[0248]
After 1H, the gate signal line 17a (1) is deselected, and the ON voltage (Vgl) is applied to the gate signal line 17b. At the same time, the gate signal line 17a (6) is selected (voltage Vgl), and a program current flows through the source signal line 18 from the transistor 11a of the selected pixel row (6) toward the source driver 14.
By operating in this manner, regular image data is held in the pixel row (1).
[0249]
After the next 1H, the gate signal line 17a (2) is not selected, and the ON voltage (Vgl) is applied to the gate signal line 17b. At the same time, the gate signal line 17a (7) is selected (voltage Vgl), and a program current flows through the source signal line 18 from the transistor 11a of the selected pixel row (7) toward the source driver 14. By operating in this manner, regular image data is held in the pixel row (2). By performing the above operation and scanning while shifting one pixel row at a time, one screen is rewritten.
[0250]
In the driving method shown in FIG. 20, since each pixel is programmed with twice the current (voltage), the emission luminance of the EL element 15 of each pixel is ideally doubled. Therefore, the brightness of the display screen is twice as large as the predetermined value. In order to set this to a predetermined luminance, as shown in FIG. 16, the non-display area 52 may include a writing pixel row 51 and a half range of the display screen 50.
[0251]
As in FIG. 13, when one display area 53 moves downward from the top of the screen as shown in FIG. 20, it is visually recognized that the display area 53 moves when the frame rate is low. In particular, it becomes easier to recognize when the eyelids are closed or when the face is moved up and down.
[0252]
To solve this problem, the display area 53 may be divided into a plurality of parts as shown in FIG. If the area obtained by adding the divided non-display area 52 has an area of S (N-1) / N, it is the same as the case where no division is performed.
[0253]
FIG. 23 shows a voltage waveform applied to the gate signal line 17. The difference between FIG. 21 and FIG. 23 is basically the operation of the gate signal line 17b. The gate signal lines 17b are turned on and off (Vgl and Vgh) by the number corresponding to the number of screen divisions. Other points are almost the same as or similar to those in FIG.
[0254]
As described above, the screen flicker is reduced by dividing the display area 53 into a plurality. Therefore, flicker does not occur, and good image display can be realized. The division may be made finer. However, the more the image is divided, the more the flicker is reduced. In particular, since the response of the EL element 15 is fast, the display luminance does not decrease even if the EL element 15 is turned on / off in a time shorter than 5 μsec.
[0255]
In the driving method of the present invention, on / off of the EL element 15 can be controlled by on / off of a signal applied to the gate signal line 17b. Therefore, in the driving method of the present invention, control can be performed at a low frequency on the order of KHz. Further, an image memory or the like is not required to realize black screen insertion (insertion of the non-display area 52). Therefore, the driving circuit or method of the present invention can be realized at low cost.
[0256]
FIG. 24 shows a case where two pixel rows are selected at the same time. According to the examination result, in the display panel formed by the low-temperature polysilicon technology, the method of simultaneously selecting two pixel rows has a practical display uniformity. This is presumed to be because the characteristics of the driving transistors 11a of the adjacent pixels are very similar. In laser annealing, a favorable result was obtained by irradiating the stripe-shaped laser in parallel with the source signal line 18.
[0257]
This is because the characteristics of the semiconductor film in the range of annealing at the same time are uniform. That is, the semiconductor film is uniformly formed within the stripe-shaped laser irradiation range, and the Vt and the mobility of the transistor using the semiconductor film are substantially equal. Therefore, by irradiating a stripe-shaped laser shot in parallel with the direction in which the source signal line 18 is formed, and by moving this irradiation position, pixels (pixel columns, pixels in the vertical direction of the screen) along the source signal line 18 are formed. The characteristics are made almost equally. Therefore, when current programming is performed by simultaneously turning on a plurality of pixel rows, the program current is selected at the same time, and the current obtained by dividing the program current by the number of selected pixels is substantially the same for the plurality of pixels. Is done. Therefore, a current program close to the target value can be executed, and uniform display can be realized. Therefore, there is a synergistic effect between the laser shot direction and the driving method described with reference to FIG.
[0258]
As described above, by making the direction of the laser shot substantially coincide with the direction in which the source signal line 18 is formed (see FIG. 7), the characteristics of the transistor 11a in the vertical direction of the pixel become substantially the same, and a good current The program can be executed (even if the characteristics of the transistors 11a in the horizontal direction of the pixel do not match). The above operation is performed by shifting the position of the selected pixel row by one pixel row or a plurality of pixel rows in synchronization with 1H (one horizontal scanning period).
[0259]
Although the direction of the laser shot is set to be parallel to the source signal line 18 as described with reference to FIG. 8, the direction is not necessarily parallel. This is because the characteristics of the transistor 11a in the vertical direction of the pixel along one source signal line 18 are formed to be substantially the same even when a laser shot is applied to the source signal line 18 in an oblique direction. Therefore, irradiating a laser shot in parallel with the source signal line means that a pixel adjacent above or below any pixel along the source signal line 18 is formed so as to be within one laser irradiation range. . Further, the source signal line 18 is generally a wiring for transmitting a program current or voltage serving as a video signal.
[0260]
In the embodiment of the present invention, the writing pixel row position is shifted every 1H. However, the present invention is not limited to this, and the writing pixel row position may be shifted every 2H (every 2 pixel rows). Pixel rows. Also, the shift may be performed in arbitrary time units. Further, the shift may be performed by skipping one pixel row.
[0261]
The shift time may be changed according to the screen position. For example, the shift time at the center of the screen may be shortened, and the shift time at the top and bottom of the screen may be increased. For example, the central part of the screen 50 shifts one pixel row every 200 μsec, and the upper and lower parts of the screen 50 shift one pixel row every 100 μsec. By such a shift, the light emission luminance at the center of the screen 50 is increased, and the periphery (the upper and lower parts of the screen 50) can be lowered. It goes without saying that the shift time between the center of the screen 50 and the upper part of the screen and the shift time between the center of the screen 50 and the lower part of the screen smoothly change over time, and control is performed so that the luminance contour does not occur.
[0262]
Note that the reference current of the source driver circuit 14 may be changed (see FIG. 146 and the like) in accordance with the scanning position of the screen 50. For example, the reference current at the center of the screen 50 is 10 μA, and the reference current at the top and bottom of the screen 50 is 5 μA. By changing the reference current in accordance with the position of the screen 50 in this manner, the light emission luminance at the center of the screen 50 increases and the periphery (the upper and lower parts of the screen 50) can be lowered. The value of the reference current between the center of the screen 50 and the upper part of the screen, the value of the reference current between the center of the screen 50 and the lower part of the screen smoothly change with time, and the reference current is changed so that the luminance contour is not formed. Needless to say, to control.
[0263]
Further, it goes without saying that the image display may be performed by combining a driving method for controlling the time for shifting the pixel row according to the screen position and a driving method for changing the reference current corresponding to the position of the screen 50.
[0264]
The shift time may be changed for each frame. Further, the present invention is not limited to selecting a plurality of continuous pixel rows. For example, a pixel row that is set to one pixel row may be selected.
[0265]
That is, the first and third pixel rows are selected during the first horizontal scanning period, and the second and fourth pixel rows are selected during the second horizontal scanning period. Then, a third pixel row and a fifth pixel row are selected during the third horizontal scanning period, and a fourth pixel row and a sixth pixel row are selected during the fourth horizontal scanning period This is a driving method. Of course, a driving method of selecting the first pixel row, the third pixel row, and the fifth pixel row in the first horizontal scanning period is also within the technical scope. Of course, it is better to select a pixel row position that extends to a plurality of pixel rows.
[0266]
Note that the combination of the above-described laser shot direction and simultaneous selection of a plurality of pixel rows is not limited to the pixel configurations of FIGS. 1, 2, and 32 but the pixel configuration of the current mirror. Needless to say, the present invention can be applied to pixel configurations of other current drive systems such as 38, 42, and 50. Also, the present invention can be applied to the voltage-driven pixel configurations shown in FIGS. That is, if the characteristics of the transistors above and below the pixel match, voltage programming can be performed satisfactorily with the voltage applied to the same source signal line 18.
[0267]
In FIG. 24, when the writing pixel row is the (1) -th pixel row, (1) and (2) are selected as the gate signal lines 17a (see FIG. 25). That is, the switching transistors 11b and the transistors 11c in the pixel rows (1) and (2) are on. Therefore, at least the switching transistors 11d of the pixel rows (1) and (2) are off, and no current flows through the EL elements 15 of the corresponding pixel rows. That is, it is the non-lighting state 52. In FIG. 24, the display area 53 is divided into five parts in order to reduce the occurrence of flicker.
[0268]
Ideally, the transistors 11a of two pixels (rows) each have Iw × 5 (N = 10; that is, K = 2), so that the current flowing through the source signal line 18 is Iw × K × 5 = Iw × 10) is supplied to the source signal line 18. Then, the capacitor 19 of each pixel 16 is programmed with five times the current.
[0269]
Since two pixel rows are selected at the same time (K = 2), two driving transistors 11a operate. That is, a current of 10/2 = 5 times flows through the transistor 11a per pixel. In the source signal line 18, a current obtained by adding the program current of the two transistors 11a flows.
[0270]
For example, a current Id is originally written in the write pixel row 51 a, and a current of Iw × 10 flows through the source signal line 18. There is no problem in the writing pixel row 51b because normal image data is written later. The pixel row 51b has the same display as the pixel row 51a during the 1H period. Therefore, at least the non-display state 52 is set for the writing pixel row 51a and the pixel row 51b selected for increasing the current.
[0271]
After the next 1H, the gate signal line 17a (1) becomes unselected, and the ON voltage (Vgl) is applied to the gate signal line 17b. At the same time, the gate signal line 17a (3) is selected (Vgl voltage), and a program current flows through the source signal line 18 from the transistor 11a of the selected pixel row (3) toward the source driver 14. By operating in this manner, regular image data is held in the pixel row (1).
[0272]
After the next 1H, the gate signal line 17a (2) is not selected, and the ON voltage (Vgl) is applied to the gate signal line 17b. At the same time, the gate signal line 17 a (4) is selected (Vgl voltage), and a program current flows from the transistor 11 a of the selected pixel row (4) to the source driver 14 toward the source driver 14. By operating in this manner, regular image data is held in the pixel row (2). The above operation and the shift by one pixel row (of course, the shift may be performed by a plurality of pixel rows. For example, in the case of the pseudo-interlace driving, the shift may be performed by two rows. One screen is rewritten by scanning while scanning the same image in the pixel row).
[0273]
In the driving method of FIG. 24, since the programming is performed with five times the current (voltage) in each pixel, the emission luminance of the EL element 15 of each pixel is ideally five times. . Therefore, the brightness of the display area 53 is five times the predetermined value. In order to set this to a predetermined luminance, as shown in FIG. 16 and the like, the non-display area 52 may include a writing pixel row 51 and １ ／ of the display screen 1.
[0274]
As shown in FIG. 27, two write pixel rows 51 (51a, 51b) are selected, and are sequentially selected from the upper side to the lower side of the screen 50 (see also FIG. 26).
In FIG. 26, the pixel rows 16a and 16b are selected). However, as shown in FIG. 27B, when reaching the lower side of the screen, the write pixel row 51a exists, but the write pixel row 51b disappears. That is, there is only one pixel row to be selected. Therefore, all the current applied to the source signal line 18 is written to the pixel row 51a. Therefore, twice as much current is programmed into the pixel as compared to the pixel row 51a.
[0275]
To address this problem, the present invention forms (arranges) a dummy pixel row 271 on the lower side of the screen 50 as shown in FIG. Therefore, when the selected pixel row is selected up to the lower side of the screen 50, the last pixel row and the dummy pixel row 271 of the screen 50 are selected. Therefore, a prescribed current is written in the write pixel row of FIG. 27B.
[0276]
Although the dummy pixel row 271 is illustrated as being formed adjacent to the upper end or lower end of the display screen 50, the present invention is not limited to this. It may be formed at a position distant from the display screen 50. In the dummy pixel row 271, it is not necessary to form the switching transistor 11 d and the EL element 15 shown in FIG. By not forming, the size of the dummy pixel row 271 is reduced.
[0277]
FIG. 28 shows the state of FIG. As is clear from FIG. 28, when the selected pixel row has been selected up to the pixel 16c row on the lower side of the screen 50, the last pixel row (dummy pixel row) 271 of the screen 50 is selected. The dummy pixel row 271 is arranged outside the display screen 50. That is, the dummy pixel row (dummy pixel) 271 is configured not to be lit, not to be lit, or not to be displayed even if lit.
For example, the contact hole between the pixel electrode 105 and the transistor 11 is eliminated, or the EL film 15 is not formed in the dummy pixel row 271. Further, a configuration in which an insulating film is formed over the pixel electrode 105 in the dummy pixel row is exemplified.
[0278]
In FIG. 27, the dummy pixels (rows) 271 are provided (formed, arranged) on the lower side of the screen 50, but the present invention is not limited to this. For example, as shown in FIG. 29A, when scanning from the lower side to the upper side of the screen (upside-down reverse scanning), dummy pixels are also provided on the upper side of the screen 50 as shown in FIG. 29B. Row 271 should be formed. That is, the dummy pixel rows 271 are formed (arranged) on the upper side of the screen 50 and on the lower side. With the above configuration, it is possible to cope with upside down scanning of the screen. In the above embodiment, two pixel rows are simultaneously selected.
[0279]
The present invention is not limited to this. For example, a method of simultaneously selecting five pixel rows (see FIG. 23) may be used. That is, in the case of simultaneous driving of five pixel rows, four dummy pixel rows 271 may be formed. Therefore, the number of the dummy pixel rows 271 may be equal to the number of pixels of the pixel row -1 to be selected at the same time. However, this is the case where the pixel rows to be selected are shifted one pixel row at a time. In the case of shifting by a plurality of pixel rows, when the number of selected pixels is M and the number of shifted pixel rows is L, (M−1) × L pixel rows may be formed.
[0280]
The dummy pixel row configuration or the dummy pixel row driving of the present invention is a method using at least one or more dummy pixel rows. Of course, it is preferable to use a combination of the dummy pixel row driving method and the N-fold pulse driving.
[0281]
In a driving method in which a plurality of pixel rows are selected at the same time, it becomes more difficult to absorb variations in characteristics of the transistors 11a as the number of pixel rows selected at the same time increases.
However, when the number M of simultaneously selected pixel rows decreases, the current programmed into one pixel increases, causing a large current to flow through the EL element 15. If the current flowing through the EL element 15 is large, the EL element 15 tends to deteriorate.
[0282]
FIG. 30 solves this problem. The basic concept of FIG. 30 is a method of simultaneously selecting a plurality of pixel rows in 1 / 2H (1/2 of the horizontal scanning period), as described with reference to FIGS. The subsequent (1/2) H (1/2 of the horizontal scanning period) is obtained by combining the method of selecting one pixel row as described with reference to FIGS. With such a combination, variations in characteristics of the transistor 11a can be absorbed, and high-speed and in-plane uniformity can be improved. In addition, in order to make understanding easy, it demonstrates as operating by (1/2) H, However, It does not restrict to this. The first period may be (1/4) H and the second period may be (3/4) H.
[0283]
In FIG. 30, for ease of description, the description is given on the assumption that five pixel rows are simultaneously selected in the first period and one pixel row is selected in the second period. First, in the first period (1 / 2H of the first half), five pixel rows are simultaneously selected as shown in (a1) of FIG. This operation has been described with reference to FIG. As an example, the current flowing through the source signal line 18 is set to 25 times a predetermined value. Therefore, the transistor 11a of each pixel 16 (in the case of the pixel configuration of FIG. 1) is programmed with five times the current (25/5 pixel row = 5). Since the current is 25 times, the parasitic capacitance generated in the source signal line 18 and the like is charged and discharged in a very short time. Therefore, the potential of the source signal line 18 becomes the target potential in a short time, and the terminal voltage of the capacitor 19 of each pixel 16 is programmed so that the current flows five times. The application time of the 25-times current is set to 1 / 2H of the first half (1/2 of one horizontal scanning period).
[0284]
Naturally, the same image data is written in the five pixel rows of the writing pixel row, so that the transistors 11d in the five pixel rows are turned off so as not to display.
Therefore, the display state is (a2) in FIG.
[0285]
In the second half of the second half period, one pixel row is selected and current (voltage) programming is performed. This state is illustrated in (b1) of FIG. The write pixel row 51a is current (voltage) programmed to flow a current five times as before. The reason why the same current is applied to each pixel between (a1) in FIG. 30 and (b1) in FIG. 30 is that the change in the terminal voltage of the programmed capacitor 19 is reduced so that the target current can flow more quickly. That is to ensure.
[0286]
That is, in (a1) of FIG. 30, a current is caused to flow through a plurality of pixels to approach a value at which an approximate current flows at high speed. In the first stage, since the programming is performed by the plurality of transistors 11a, an error occurs due to variations in the transistors with respect to the target value. In the second stage, only the pixel rows in which data is written and held are selected, and a complete program is performed from a rough target value to a predetermined target value.
[0287]
Note that scanning the non-display area 52 from the top of the screen to the bottom and the writing pixel row 51a from the top of the screen to the bottom are the same as in the embodiment of FIG. .
[0288]
FIG. 31 shows driving waveforms for realizing the driving method of FIG. As can be seen from FIG. 31, 1H (one horizontal scanning period) is composed of two phases. These two phases are switched by the ISEL signal. The ISEL signal is illustrated in FIG.
[0289]
First, the ISEL signal will be described. The source driver circuit 14 implementing FIG. 30 includes a current output circuit A and a current output circuit B. Each current output circuit is composed of a DA circuit for DA-converting 8-bit grayscale data, an operational amplifier, and the like. In the embodiment of FIG. 30, the current output circuit A is configured to output a 25-fold current. On the other hand, the current output circuit B is configured to output five times the current. The outputs of the current output circuits A and B are applied to the source signal line 18 by controlling a switch circuit formed (arranged) in the current output section by the ISEL signal. This current output circuit is arranged for each source signal line.
[0290]
When the ISEL signal is at the L level, the current output circuit A that outputs a 25-fold current is selected, and the current from the source signal line 18 is absorbed by the source driver IC 14 (more appropriately, formed in the source driver circuit 14). The current output circuit A thus absorbed). It is easy to adjust the magnitude of the current output circuit current, such as 25 times or 5 times. This is because it can be easily configured with a plurality of resistors and analog switches.
[0291]
As shown in FIG. 30, when the writing pixel row is the (1) pixel row (see the 1H column in FIG. 30), the gate signal lines 17a are (1), (2), (3), (4), and (5). Is selected (in the case of the pixel configuration of FIG. 1). That is, the switching transistors 11b and 11c of the pixel rows (1), (2), (3), (4), and (5) are on. Further, since ISEL is at the L level, the current output circuit A that outputs a 25-fold current is selected and connected to the source signal line 18. Further, an off voltage (Vgh) is applied to the gate signal line 17b. Therefore, the switching transistors 11d of the pixel rows (1), (2), (3), (4), and (5) are off, and no current flows through the EL elements 15 of the corresponding pixel row. That is, it is the non-lighting state 52.
[0292]
Ideally, the transistors 11a of the five pixels each pass a current of Iw × 2 to the source signal line 18. Then, the capacitor 19 of each pixel 16 is programmed with five times the current. Here, in order to facilitate understanding, the description will be made assuming that the characteristics (Vt, S value) of the transistors 11a match.
[0293]
Since five pixel rows are selected at the same time (K = 5), five driving transistors 11a operate. That is, a current of 25/5 = 5 times flows through the transistor 11a per pixel. In the source signal line 18, a current obtained by adding the program current of the five transistors 11a flows. For example, when the current Iw to be written into the pixel by the conventional driving method is set to the writing pixel row 51a, a current of Iw × 25 flows through the source signal line 18. This is a pixel row used as an auxiliary to increase the amount of current flowing to the source signal line 18 in the write pixel row 51b in which image data is written after the write pixel row (1). However, there is no problem in the writing pixel row 51b because normal image data is written later.
[0294]
Therefore, the pixel row 51b has the same display as the pixel row 51a during the 1H period. Therefore, at least the non-display state 52 is set for the writing pixel row 51a and the pixel row 51b selected for increasing the current.
[0295]
In the next 1 / 2H (1/2 of the horizontal scanning period), only the write pixel row 51a is selected. That is, (1) only the pixel row is selected. As is clear from FIG. 31, only the gate signal line 17a (1) is applied with the ON voltage (Vgl), and the gate signal lines 17a (2) (3) (4) (5) are applied with the OFF voltage (Vgh). Have been. Accordingly, the transistor 11a in the pixel row (1) is in an operating state (a state in which current is supplied to the source signal line 18), but the switching transistor 11b in the pixel row (2), (3), (4), and (5). , The transistor 11c is off. That is, it is in a non-selected state.
[0296]
Further, since ISEL is at the H level, the current output circuit B that outputs a five-fold current is selected, and the current output circuit B and the source signal line 18 are connected. Further, the state of the gate signal line 17b does not change from the state of the previous 1 / 2H, and the off voltage (Vgh) is applied. Therefore, the switching transistors 11d of the pixel rows (1), (2), (3), (4), and (5) are off, and no current flows through the EL element 15 of the corresponding pixel row. That is, it is the non-lighting state 52.
[0297]
From the above, the transistors 11a in the pixel row (1) each pass a current of Iw × 5 to the source signal line 18. Then, a five-fold current is programmed in the capacitor 19 of each pixel row (1).
[0298]
In the next horizontal scanning period, one pixel row and a writing pixel row shift. That is, this time, the writing pixel row is (2). In the first 1 / 2H period, when the write pixel row is the (2) pixel row as shown in FIG. 31, the gate signal lines 17a are (2) (3) (4) (5) (6) Selected. That is, the switching transistors 11b and the transistors 11c in the pixel rows (2), (3), (4), (5), and (6) are on. Further, since ISEL is at the L level, the current output circuit A that outputs a 25-fold current is selected and connected to the source signal line 18. Further, an off voltage (Vgh) is applied to the gate signal line 17b.
[0299]
Therefore, the switching transistors 11d of the pixel rows (2), (3), (4), (5), and (6) are off, and no current flows through the EL element 15 of the corresponding pixel row. That is, it is the non-lighting state 52. On the other hand, since the voltage Vgl is applied to the gate signal line 17b (1) of the pixel row (1), the transistor 11d is in the ON state, and the EL element 15 of the pixel row (1) is turned on.
[0300]
Since five pixel rows are selected at the same time (K = 5), five driving transistors 11a operate. That is, a current of 25/5 = 5 times flows through the transistor 11a per pixel. In the source signal line 18, a current obtained by adding the program current of the five transistors 11a flows.
[0301]
In the next 1 / 2H (1/2 of the horizontal scanning period), only the write pixel row 51a is selected. That is, (2) only the pixel row is selected. As is apparent from FIG. 31, only the gate signal line 17a (2) is applied with the on-voltage (Vgl), and the gate signal lines 17a (3) (4) (5) (6) are applied with the off-voltage (Vgh). Have been.
[0302]
Therefore, the transistors 11a of the pixel rows (1) and (2) are in an operating state (the pixel row (1) supplies a current to the EL element 15 and the pixel row (2) supplies a current to the source signal line 18). However, the switching transistors 11b and 11c in the pixel rows (3), (4), (5), and (6) are off. That is, it is in a non-selected state.
[0303]
Further, since ISEL is at the H level, the current output circuit B that outputs a five-fold current is selected, and the current output circuit 1222b and the source signal line 18 are connected. Further, the state of the gate signal line 17b does not change from the state of the previous 1 / 2H, and the off voltage (Vgh) is applied. Therefore, the switching transistors 11d of the pixel rows (2), (3), (4), (5), and (6) are off, and no current flows through the EL element 15 of the corresponding pixel row. That is, it is the non-lighting state 52.
[0304]
From the above, the transistors 11a in the pixel row (2) flow a current of Iw × 5 to the source signal line 18, respectively. Then, a five-fold current is programmed in the capacitor 19 of each pixel row (2). One screen can be displayed by sequentially performing the above operations.
[0305]
In the driving method described with reference to FIG. 30, a G pixel row (G is 2 or more) is selected in the first period, and programming is performed so that an N-fold current flows in each pixel row. In a second period after the first period, a B pixel row (B is smaller than G, 1 or more) is selected, and programming is performed so that N times the current flows to the pixel.
[0306]
However, there are other strategies. In the first period, G pixel rows (G is 2 or more) are selected, and programming is performed so that the total current of each pixel row becomes N times the current. In a second period after the first period, a B pixel row (B is smaller than G, 1 or more) is selected, and a current of the sum of the selected pixel rows (however, when the selected pixel row is 1, This is a method of programming so that the current of one pixel row) becomes N times. For example, in (a1) of FIG. 30, five pixel rows are selected at the same time, and twice the current flows through the transistor 11a of each pixel.
Therefore, a current of 5 × 2 = 10 times flows through the source signal line 18. In the next second period, one pixel row is selected in (b1) of FIG. A 10-fold current flows through the transistor 11a of one pixel.
[0307]
In FIG. 31, the period during which a plurality of pixel rows are selected at the same time is ＨH, and the period during which one pixel row is selected is ＨH, but the present invention is not limited to this. The period for simultaneously selecting a plurality of pixel rows may be １ ／ H, and the period for selecting one pixel row may be ／ H. In addition, the period in which the period for selecting a plurality of pixel rows at the same time and the period for selecting one pixel row are added is 1H, but is not limited to this. For example, the period may be 2H or 1.5H.
[0308]
In FIG. 30, the period in which five pixel rows are simultaneously selected may be set to 1 / 2H, and two pixel rows may be simultaneously selected in the next second period. Even in this case, a practically acceptable image display can be realized.
[0309]
Further, in FIG. 30, the first period for simultaneously selecting five pixel rows is set to 1 / 2H, and the second period for selecting one pixel row is set to 1 / 2H. However, the present invention is not limited to this. Absent. For example, the first stage may select five pixel rows at the same time, and the second period may select three pixel rows among the five pixel rows and finally select three pixel rows. . That is, image data may be written to a pixel row in a plurality of stages.
[0310]
The above embodiment is a method of sequentially selecting one pixel row and performing current programming on the pixels, or a method of sequentially selecting a plurality of pixel rows and performing current programming on the pixels. However, the present invention is not limited to this. A method of sequentially selecting one pixel row according to image data and performing current programming on the pixel may be combined with a method of sequentially selecting a plurality of pixel rows and performing current programming on the pixel.
[0311]
Hereinafter, the interlace driving of the present invention will be described. FIG. 133 shows a configuration of a display panel of the present invention that performs interlace driving. In FIG. 133, the gate signal lines 17a of the odd pixel rows are connected to the gate driver circuit 12a1. The gate signal line 17a of the even-numbered pixel row is connected to the gate driver circuit 12a2. On the other hand, the gate signal line 17b of the odd pixel row is connected to the gate driver circuit 12b1. The gate signal line 17b of the even-numbered pixel row is connected to the gate driver circuit 12b2.
[0312]
Therefore, the image data of the odd-numbered pixel rows is sequentially rewritten by the operation (control) of the gate driver circuit 12a1. In the odd-numbered pixel rows, the lighting (non-lighting) of the EL elements is controlled by the operation (control) of the gate driver circuit 12b1. Further, the image data of the even-numbered pixel rows is sequentially rewritten by the operation (control) of the gate driver circuit 12a2. Further, in the even-numbered pixel rows, the lighting (non-lighting) of the EL elements is controlled by the operation (control) of the gate driver circuit 12b2.
[0313]
FIG. 134A shows the operation state of the display panel in the first field. FIG. 134 (b) shows the operation state of the display panel in the second field. It is assumed that one frame is composed of two fields for ease of explanation. In FIG. 134, the hatched gate driver circuit 12 indicates that the data scanning operation is not performed. That is, in the first field of FIG. 134A, the gate driver circuit 12a1 operates as the writing control of the program current, and the gate driver circuit 12b2 operates as the lighting control of the EL element 15. In the second field of FIG. 134B, the gate driver circuit 12a2 operates as the write control of the program current, and the gate driver circuit 12b1 operates as the lighting control of the EL element 15. The above operation is repeated in the frame.
[0314]
FIG. 135 shows an image display state in the first field. FIG. 135 (a) shows the position of the write pixel row (the odd pixel row where the current (voltage) program is performed. FIG. 135 (a1) → (a2) → (a3)) In the first field, odd-numbered pixel rows are sequentially rewritten (image data of even-numbered pixel rows are retained), and FIG. 135 (b) illustrates a display state of odd-numbered pixel rows. 135 (b) shows only odd-numbered pixel rows, and even-numbered pixel rows are shown in (c) of Fig. 135. As is clear from (b) of Fig. 135, odd-numbered pixel rows are shown. 135. On the other hand, the even-numbered pixel row scans the display area 53 and the non-display area 52 as shown in FIG. 135 (c) (N-fold pulse). Drive).
[0315]
FIG. 136 shows an image display state in the second field. FIG. 136 (a) shows the write pixel row (the position of the odd pixel row where the current (voltage) programming is performed. The write pixel row position shown in FIG. 136 is (a1) → (a2) → (a3). In the second field, the even-numbered pixel rows are sequentially rewritten (the image data of the odd-numbered pixel rows are retained), and FIG. 136 (b) illustrates the display state of the odd-numbered pixel rows. 136 (b) shows only odd-numbered pixel rows, and even-numbered pixel rows are shown in (c) of Fig. 136. As is clear from (b) of Fig. 136, even-numbered pixel rows are shown. 136. The EL element 15 of the pixel corresponding to the pixel row is in the non-lighting state, while the odd-numbered pixel row scans the display area 53 and the non-display area 52 as shown in FIG. Drive).
[0316]
By driving as described above, interlaced driving can be easily realized on the EL display panel. In addition, by performing the N-fold pulse driving, insufficient writing does not occur and moving image blur does not occur. Further, control of a current (voltage) program and lighting control of the EL element 15 are easy, and a circuit can be easily realized.
[0317]
The driving method of the present invention is not limited to the driving methods shown in FIGS. 135 and 136. For example, the driving method shown in FIG. 137 is also exemplified. 135 and 136, the odd-numbered pixel rows or even-numbered pixel rows on which the current (voltage) programming is performed are set as the non-display area 52 (non-lighting, black display). In the embodiment of FIG. 137, both of the gate driver circuits 12b1 and 12b2 for controlling the lighting of the EL element 15 are operated in synchronization. However, it goes without saying that the pixel row 51 on which the current (voltage) program is being performed is controlled so as to be a non-display area (this is not necessary in the current mirror pixel configuration of FIG. 38). In FIG. 137, since the lighting control of the odd-numbered pixel rows and the even-numbered pixel rows is the same, it is not necessary to provide the two gate driver circuits 12b1 and 12b2. The lighting control can be performed by one gate driver circuit 12b.
[0318]
FIG. 137 shows a driving method for making the lighting control of the odd-numbered pixel rows and the even-numbered pixel rows the same. However, the present invention is not limited to this. FIG. 138 is an embodiment in which the lighting control of the odd-numbered pixel rows and the even-numbered pixel rows is made different. In particular, FIG. 138 shows an example in which the reverse pattern of the lighting state of the odd-numbered pixel row (the display area 53 and the non-display area 52) is changed to the lighting state of the even-numbered pixel row. Therefore, the area of the display area 53 and the area of the non-display area 52 are set to be the same. Of course, the area of the display area 53 and the area of the non-display area 52 are not limited to being the same.
[0319]
In addition, in FIGS. 136 and 135, it is not limited to setting all the pixel rows in the odd-numbered pixel rows or the even-numbered pixel rows to the non-lighting state.
[0320]
The above embodiment is a driving method for executing a current (voltage) program for each pixel row. However, the driving method of the present invention is not limited to this. Needless to say, current (voltage) programming may be performed simultaneously on two pixel rows (a plurality of pixel rows) as shown in FIG. 139 (FIG. 27). And its description). FIG. 139 (a) shows an embodiment of an odd field, and FIG. 139 (b) shows an embodiment of an even field. In odd fields, (1, 2) pixel rows, (3, 4) pixel rows, (5, 6) pixel rows, (7, 8) pixel rows, (9, 10) pixel rows, (11, 12) pixels ...,...,... (N, n + 1) pixel rows (n is an integer of 1 or more) are sequentially selected as two pixel rows, and current programming is performed. In even fields, (2,3) pixel rows, (4,5) pixel rows, (6,7) pixel rows, (8,9) pixel rows, (10,11) pixel rows, (12,13) pixel rows ... (N + 1, n + 2) pixel rows (n is an integer of 1 or more) are sequentially selected as two pixel rows, and current programming is performed.
[0321]
As described above, by selecting a plurality of pixel rows in each field and performing current programming, the current flowing through the source signal line 18 can be increased, and black writing can be improved. In addition, the resolution of an image can be improved by shifting at least one pixel of a set of a plurality of pixel rows selected in an odd field and an even field.
[0322]
In the embodiment of FIG. 139, two pixel rows are selected in each field. However, the present invention is not limited to this, and three pixel rows may be used. In this case, two sets of a method of shifting one pixel and a method of shifting two pixels can be selected as a set of three pixel rows selected in the odd field and the even field. The number of pixel rows selected in each field may be four or more. Further, as shown in FIGS. 125 to 132, one frame may be composed of three or more fields.
[0323]
In the embodiment of FIG. 139, two pixel rows are selected at the same time. However, the present invention is not limited to this. 1H is set to the first half and the second half, and in odd fields, the first half of the first H period is set. The current programming is performed by selecting the first pixel row in the 1 / 2H period of the second half, and selecting the second pixel row in the second half of the H period.
In the first half H period of the next second H period, the third pixel row is selected and current programming is performed, and in the second half H period, the fourth pixel row is selected and current programming is performed. In addition, the current programming is performed by selecting the fifth pixel row during the first half of the first H period of the next third H period, and selecting the sixth pixel row during the second half of the first H period. Do. ... May be driven.
[0324]
In the even field, the current programming is performed by selecting the second pixel row in the first half H period of the first H period and performing the current programming by selecting the third pixel row in the latter half H period. In the first half of the next second H period, the fourth pixel row is selected and current programming is performed, and in the latter half of the second H period, the fifth pixel row is selected and current programming is performed. Further, the current programming is performed by selecting the sixth pixel row in the first half of the first H period of the next third H period, and selecting the seventh pixel row in the second half of the first H period. Do. ... May be driven.
[0325]
In the above embodiment, the number of pixel rows selected in each field is two pixel rows. However, the present invention is not limited to this, and three pixel rows may be used. In this case, two sets of a method of shifting one pixel and a method of shifting two pixels can be selected as a set of three pixel rows selected in the odd field and the even field. The number of pixel rows selected in each field may be four or more.
[0326]
According to the N-fold pulse driving method of the present invention, the waveform of the gate signal line 17b is made the same in each pixel row, and the pixel signals are shifted and applied at intervals of 1H. By performing the scanning in this manner, the pixel rows to be lit can be sequentially shifted while the time during which the EL element 15 is lit is set to 1 F / N. As described above, it is easy to realize that the waveform of the gate signal line 17b is made the same and shifted in each pixel row. This is because ST1 and ST2, which are data applied to the shift register circuits 61a and 61b in FIG. 6, may be controlled. For example, when Vgl is output to the gate signal line 17b when the input ST2 is at the L level, and Vgh is output to the gate signal line 17b when the input ST2 is at the H level, the ST2 applied to the shift register 61b is The signal is input at the L level only during the 1F / N period, and is set at the H level during the other periods. Only the input ST2 is shifted by the clock CLK2 synchronized with 1H.
[0327]
The cycle of turning on and off the EL element 15 needs to be 0.5 msec or more. If this cycle is short, a perfect black display state will not be obtained due to the afterimage characteristics of the human eye, and the image will be blurred, as if the resolution were reduced. Further, the display state of the data holding type display panel is set. However, when the on / off cycle is 100 msec or more, the light beam appears to be blinking. Therefore, the ON / OFF cycle of the EL element should be 0.5 μsec or more and 100 msec or less. More preferably, the on / off cycle should be no less than 2 msec and no more than 30 msec. More preferably, the on / off cycle should be 3 msec or more and 20 msec or less.
[0328]
As described above, when the number of divisions of the black screen 52 is set to one, a favorable moving image display can be realized, but flickering of the screen becomes easy to see. Therefore, it is preferable to divide the black insertion portion into a plurality. However, if the number of divisions is too large, moving image blur occurs. The number of divisions should be 1 or more and 8 or less. More preferably, it is preferably 1 or more and 5 or less.
[0329]
It is preferable that the number of divisions of the black screen is configured to be changed between a still image and a moving image. When the number of divisions is N = 4, 75% is a black screen and 25% is an image display. At this time, the number of divisions is one in which the 75% black display section is scanned in the vertical direction of the screen in a 75% black band state. The number of divisions is three, which is scanned by three blocks of a 25% black screen and a 25/3% display screen. For still images, increase the number of divisions. For videos, reduce the number of divisions. The switching may be performed automatically (moving image detection or the like) according to the input image, or may be manually performed by the user. In addition, it may be configured to switch to a video or the like of the display device in accordance with the input outlet.
[0330]
For example, in a mobile phone or the like, the number of divisions is set to 10 or more on the wallpaper display and input screen (in extreme cases, it may be turned on and off every 1H). When displaying an NTSC moving image, the number of divisions is set to 1 or more and 5 or less. The number of divisions is preferably configured to be switchable in three or more stages. For example, there is no division number, 2, 4, 8, or the like.
[0331]
The ratio of the black screen to the entire display screen is preferably 0.2 or more and 0.9 or less (1.2 or more and 9 or less when displayed by N), when the area of the entire screen is 1.
In particular, it is preferable to be 0.25 or more and 0.6 or less (1.25 or more and 6 or less when indicated by N). If it is less than 0.20, the effect of improving moving image display is low. When the ratio is 0.9 or more, the brightness of the display portion increases, and it is easy to visually recognize that the display portion moves up and down.
[0332]
The number of frames per second is preferably 10 or more and 100 or less (10 Hz or more and 100 Hz or less). Further, the frequency is preferably 12 or more and 65 or less (12 Hz or more and 65 Hz or less). When the number of frames is small, flickering of the screen becomes conspicuous. When the number of frames is too large, writing from the source driver circuit 14 or the like becomes difficult, and the resolution is deteriorated.
[0333]
Needless to say, the above items can be applied to the pixel configuration of the current program shown in FIG. 38 and the pixel configuration of the voltage program shown in FIGS. 43, 51, and 54. 38, the transistor 11d in FIG. 43, the transistor 11d in FIG. 43, and the transistor 11e in FIG. As described above, by turning on / off the wiring that allows the current to flow through the EL element 15, the N-fold pulse driving of the present invention can be easily realized.
[0334]
In addition, the time when the gate signal line 17b is set to Vgl only during the period of 1F / N may be any time in the period of 1F (it is not limited to 1F. It may be a unit period). This is because a predetermined average luminance is obtained by turning on the EL element 15 for a predetermined period in a unit time. However, it is preferable that the gate signal line 17b be set to Vgl immediately after the current programming period (1H) to cause the EL element 15 to emit light. This is because the effect of the retention characteristic of the capacitor 19 of FIG. 1 is reduced.
[0335]
In addition, it is preferable that the number of divisions of the image is configured to be variable. For example, when the user presses the brightness adjustment switch or turns the brightness adjustment volume, the change is detected and the value of K is changed. You may comprise so that it may change manually or automatically according to the content and data of the image to be displayed.
[0336]
Changing the value of K (the number of divisions of the image display unit 53) in this manner can be easily realized. This is because, in FIG. 6, the timing of the data applied to ST (when the L level is set at 1F) may be adjusted or changed.
[0337]
In FIG. 16 and the like, the period (1F / N) for setting the gate signal line 17b to Vgl is divided into a plurality (division number M), and the period for setting Vgl to 1F / (K · N) is implemented K times. However, this is not a limitation. The period of 1F / (K · N) may be performed L (L ≠ K) times. That is, in the present invention, the screen 50 is displayed by controlling the period (time) of flowing to the EL element 15. Therefore, performing the period of 1F / (K · N) L (L ≠ K) times is included in the technical idea of the present invention. Also, by changing the value of L, the luminance of the screen 50 can be digitally changed. For example, when L = 2 and L = 3, the luminance (contrast) changes by 50%. It goes without saying that these controls can also be applied to other embodiments of the present invention (of course, the present invention described below). These are also N-time pulse driving of the present invention.
[0338]
In the above embodiment, the transistor 11d as a switching element is disposed (formed) between the EL element 15 and the driving transistor 11a, and the screen 50 is turned on and off by controlling the transistor 11d. . With this driving method, the current programming method eliminates insufficient current writing in the black display state, and achieves good resolution or black display. That is, in the current programming method, it is important to realize good black display. The driving method described below resets the driving transistor 11a and realizes a good black display. The embodiment will be described below with reference to FIG.
[0339]
FIG. 32 is basically the pixel configuration of FIG. In the pixel configuration of FIG. 32, the programmed Iw current flows through the EL element 15, and the EL element 15 emits light. That is, the driving transistor 11a retains the ability to flow current by being programmed. A method of resetting (turning off) the transistor 11a by utilizing the ability to flow this current is the driving method in FIG. Hereinafter, this driving method is referred to as reset driving.
[0340]
In order to realize reset driving with the pixel configuration of FIG. 1, it is necessary to configure the transistor 11b and the transistor 11c so that on / off control can be performed independently. That is, as shown in FIG. 32, the gate signal line 17a (gate signal line WR) for turning on / off the transistor 11b and the gate signal line 17c (gate signal line EL) for turning on / off the transistor 11c can be controlled independently. I do. The control of the gate signal lines 17a and 17c may be performed by two independent shift registers 61 as shown in FIG.
[0341]
The driving voltage of the gate signal line 17a for driving the transistor 11b and the driving voltage of the gate signal line 17b for driving the transistor 11d may be changed (in the case of the pixel configuration in FIG. 1). The amplitude value (the difference between the ON voltage and the OFF voltage) of the gate signal line 17a is smaller than the amplitude value of the gate signal line 17b.
[0342]
If the amplitude value of the gate signal line 17 is large, the penetration voltage between the gate signal line 17 and the pixel 16 becomes large, and black floating occurs. The amplitude of the gate signal line 17a may be controlled by controlling whether the potential of the source signal line 18 is not applied to the pixel 16 (applied (when selected)). Since the potential fluctuation of the source signal line 18 is small, the amplitude value of the gate signal line 17a can be reduced.
[0343]
On the other hand, the gate signal line 17b needs to perform EL on / off control. Therefore, the amplitude value increases. To deal with this, the output voltages of the shift registers 61a and 61b are changed. When the pixel is formed of a P-channel transistor, Vgh (off voltage) of the shift registers 61a and 61b is made substantially the same, and Vgl (on voltage) of the shift register 61a is made higher than Vgl (on voltage) of the shift register 61b. make low.
[0344]
Hereinafter, the reset driving method will be described with reference to FIG. FIG. 33 is a diagram for explaining the principle of reset driving. First, as illustrated in FIG. 33A, the transistors 11c and 11d are turned off, and the transistor 11b is turned on. Then, the drain (D) terminal and the gate (G) terminal of the driving transistor 11a are short-circuited, and an Ib current flows. Generally, transistor 11a is current programmed in the previous field (frame). In this state, when the transistor 11d is turned off and the transistor 11b is turned on, the drive current Ib flows to the gate (G) terminal of the transistor 11a.
Therefore, the gate (G) terminal and the drain (D) terminal of the transistor 11a have the same potential, and the transistor 11a is reset (state in which no current flows).
[0345]
Note that before the operation in FIG. 33A, it is preferable to perform an operation in which the transistor 11b and the transistor 11c are turned off, the transistor 11d is turned on, and current flows to the driving transistor 11a. This operation is preferably completed in as short a time as possible. This is because a current may flow through the EL element 15 to turn on the EL element 15 and lower the display contrast. It is preferable that the operation time is 0.1% or more and 10% or less of 1H (one horizontal scanning period). It is more preferable that the content be 0.2% or more and 2% or less. Alternatively, it is preferable that the time be 0.2 μsec or more and 5 μsec or less. Further, the above-described operation (the operation performed before (a) in FIG. 33) may be collectively performed on the pixels 16 on the entire screen. By performing the above operation, the drain (D) terminal voltage of the driving transistor 11a decreases, and a smooth Ib current can flow in the state of FIG. Note that the above items also apply to other reset driving methods of the present invention.
[0346]
33A, the Ib current flows, and the terminal voltage of the capacitor 19 tends to decrease as the implementation time of FIG. Therefore, the implementation time in FIG. 33A needs to be a fixed value. According to experiments and studies, it is preferable that the implementation time in FIG. 33A be 1H or more and 5H or less.
[0347]
It is preferable that this period be different for the R, G, and B pixels. This is because the EL material differs for each color pixel, and there is a difference in the rising voltage of the EL material. In each pixel of RGB, the most optimal period is set according to the EL material. In this embodiment, the period is set to 1H or more and 5H or less. However, it is needless to say that the period may be 5H or more in a driving method mainly for black insertion (black screen writing). The longer the period, the better the black display state of the pixel.
[0348]
After the operation of FIG. 33 (a) is performed, the state of FIG. 33 (b) is set in a period of 1H or more and 5H or less. FIG. 33B shows a state in which the transistor 11c and the transistor 11b are turned on and the transistor 11d is turned off. The state of FIG. 33B is a state in which current programming is being performed, as described above. That is, the program current Iw is output (or absorbed) from the source driver circuit 14, and the program current Iw is supplied to the driving transistor 11a. The potential of the gate (G) terminal of the driving transistor 11a is set so that the program current Iw flows (the set potential is held by the capacitor 19).
[0349]
If the program current Iw is 0 (A), the transistor 11a maintains the state in which the current shown in FIG. 33 (a) does not flow, so that good black display can be realized. Even if the white display current programming is performed in FIG. 33B or the characteristic variation of the driving transistor of each pixel occurs, the current programming is performed from the offset voltage in the completely black display state. Do. Therefore, the time programmed to the target current value becomes equal according to the gradation. Therefore, there is no gradation error due to variations in the characteristics of the transistor 11a, and a favorable image display can be realized.
[0350]
After the current programming of FIG. 33B, as shown in FIG. 33C, the transistors 11b and 11c are turned off, the transistor 11d is turned on, and the program current Iw (=) from the driving transistor 11a is turned on. Ie) flows through the EL element 15 to cause the EL element 15 to emit light. 33 (c) has already been described with reference to FIG.
[0351]
That is, the driving method (reset driving) described with reference to FIG. 33 disconnects the driving transistor 11a and the EL element 15 (a state in which no current flows), and connects the drain (D) terminal and the gate (G ) Terminal (or two terminals including a source (S) terminal and a gate (G) terminal, more generally, two terminals including a gate (G) terminal of a driving transistor); Thereafter, a second operation of performing a current (voltage) program on the driving transistor is performed. Further, at least the second operation is performed after the first operation. Note that in order to perform the reset driving, the transistor 11b and the transistor 11c must be configured to be independently controllable as in the configuration in FIG.
[0352]
In the image display state (if an instantaneous change can be observed), first, the pixel row on which current programming is performed is in a reset state (black display state), and after 1H, current programming is performed (at this time, Is also in a black display state because the transistor 11d is off.) Next, a current is supplied to the EL element 15, and the pixel row emits light at a predetermined luminance (programmed current). That is, the pixel row for black display moves downward from the top of the screen, and the image should appear to be rewritten at the position where the pixel row has passed.
[0353]
Although the current programming is performed 1 H after the reset, this period may be set within about 5 H. This is because it takes a relatively long time for the reset of FIG. 33A to be completely performed. If this period is set to 5H, 5 pixel rows should display black (6 pixel rows including the current programming pixel row).
[0354]
Further, the reset state is not limited to being performed one pixel row at a time, but may be performed simultaneously for a plurality of pixel rows. Alternatively, the scanning may be performed while simultaneously resetting a plurality of pixel rows and overlapping each other. For example, if four pixel rows are to be reset simultaneously, the pixel rows (1), (2), (3), and (4) are reset in the first horizontal scanning period (one unit), and the next second horizontal row is reset. During the scanning period, the pixel rows (3), (4), (5), and (6) are reset, and during the next third horizontal scanning period, the pixel rows (5), (6), (7), and (8) are reset. State. Further, a driving state in which the pixel rows (7), (8), (9), and (10) are reset in the next fourth horizontal scanning period is exemplified. It should be noted that the driving states shown in FIGS. 33B and 33C are naturally performed in synchronization with the driving state shown in FIG.
[0355]
It goes without saying that the driving shown in FIGS. 33 (b) and (c) may be performed after all the pixels on one screen are reset at the same time or in the scanning state. Needless to say, the reset state (interlacing of one or more pixel rows) may be set in the interlaced driving state (interlacing scanning of one or more pixel rows). Further, a random reset state may be performed. Further, the description of the reset driving of the present invention is a method of operating a pixel row (that is, controlling the vertical direction of the screen). However, the concept of the reset drive is not limited to the control direction of the pixel row. For example, it goes without saying that the reset driving may be performed in the pixel column direction.
[0356]
Note that the reset driving in FIG. 33 can achieve better image display by being combined with the N-fold pulse driving or the like of the present invention or by interlaced driving. In particular, the configuration of FIG. 22 is a driving method of intermittent N / K times pulse driving (a plurality of lighting regions are provided in one screen. This driving method is easy by controlling the gate signal line 17b and turning on / off the transistor 11d). This has been described previously.), So that good image display can be realized without occurrence of flicker.
[0357]
Needless to say, further excellent image display can be realized by combining with another driving method, for example, a precharge driving method described below. As described above, it goes without saying that the reset driving can be performed in combination with the other embodiments of the present specification, similarly to the present invention.
[0358]
FIG. 34 is a configuration diagram of a display device that realizes reset driving. The gate driver circuit 12a controls the gate signal lines 17a and 17b in FIG. By applying an on / off voltage to the gate signal line 17a, the on / off control of the transistor 11b is performed. The transistor 11d is turned on / off by applying an on / off voltage to the gate signal line 17b. The gate driver circuit 12b controls the gate signal line 17c in FIG. The transistor 11c is turned on and off by applying an on / off voltage to the gate signal line 17c.
[0359]
Therefore, the gate signal line 17a is operated by the gate driver circuit 12a, and the gate signal line 17c is operated by the gate driver circuit 12b. Therefore, the timing at which the transistor 11b is turned on to reset the driving transistor 11a and the timing at which the transistor 111c is turned on and current programming is performed on the driving transistor 11a can be freely set. Other configurations and the like are the same as or similar to those described previously, and thus description thereof is omitted.
[0360]
FIG. 35 is a timing chart of the reset driving. When an ON voltage is applied to the gate signal line 17a to turn on the transistor 11b and reset the driving transistor 11a, an OFF voltage is applied to the gate signal line 17b to turn off the transistor 11d. Therefore, the state shown in FIG. During this period, the Ib current flows.
[0361]
In the timing chart of FIG. 35, the reset time is 2H (an on-voltage is applied to the gate signal line 17a and the transistor 11b is turned on), but the reset time is not limited to this. It may be 2H or more. If the reset can be performed very quickly, the reset time may be less than 1H.
[0362]
The H period for the reset period can be easily changed by the DATA (ST) pulse period input to the gate driver circuit 12. For example, if DATA input to the ST terminal is at the H level during the 2H period, the reset period output from each gate signal line 17a is the 2H period. Similarly, if DATA input to the ST terminal is kept at the H level during the 5H period, the reset period output from each gate signal line 17a becomes the 5H period.
[0363]
After the reset for the 1H period, an on-voltage is applied to the gate signal line 17c (1) of the pixel row (1). When the transistor 11c is turned on, the program current Iw applied to the source signal line 18 is written to the driving transistor 11a via the transistor 11c.
[0364]
After the current programming, an off-voltage is applied to the gate signal line 17c of the pixel (1), the transistor 11c is turned off, and the pixel is disconnected from the source signal line. At the same time, the off-state voltage is also applied to the gate signal line 17a, and the reset state of the driving transistor 11a is eliminated. (Note that in this period, it is more appropriate to express the current program state than the reset state. is there). Further, an on-voltage is applied to the gate signal line 17b, the transistor 11d is turned on, and a current programmed in the driving transistor 11a flows through the EL element 15. It is to be noted that the same applies to the pixel row (2) and subsequent pixel rows, and the description thereof is omitted because the operation is clear from FIG.
[0365]
In FIG. 35, the reset period was a 1H period. FIG. 36 shows an embodiment in which the reset period is set to 5H. The H period for the reset period can be easily changed by the DATA (ST) pulse period input to the gate driver circuit 12. FIG. 36 shows an embodiment in which DATA input to the ST1 terminal of the gate driver circuit 12a is at H level for a 5H period, and a reset period output from each gate signal line 17a is a 5H period. The longer the reset period is, the more completely the reset is performed, and an excellent black display can be realized. However, the display luminance is reduced by the proportion of the reset period.
[0366]
FIG. 36 shows an embodiment in which the reset period is set to 5H. This reset state was a continuous state. However, the reset state is not limited to being performed continuously. For example, the signal output from each gate signal line 17a may be turned on and off every 1H. Such an on / off operation can be easily realized by operating an enable circuit (not shown) formed at the output stage of the shift register. Further, it can be easily realized by controlling the DATA (ST) pulse input to the gate driver circuit 12.
[0367]
In the circuit configuration of FIG. 34, the gate driver circuit 12a requires at least two shift register circuits (one for controlling the gate signal line 17a and the other for controlling the gate signal line 17b). Therefore, there is a problem that the circuit scale of the gate driver circuit 12a becomes large. FIG. 37 shows an embodiment in which the gate driver circuit 12a has one shift register. A timing chart of an output signal obtained by operating the circuit of FIG. 37 is as shown in FIG. Note that the signs of the gate signal lines 17 output from the gate driver circuits 12a and 12b are different between FIG. 35 and FIG. 37.
[0368]
As is apparent from the addition of the OR circuit 371 in FIG. 37, the output of each gate signal line 17a is output by ORing with the output of the previous stage of the shift register circuit 61a. That is, an ON voltage is output from the gate signal line 17a during the 2H period. On the other hand, the output of the shift register circuit 61a is output as it is to the gate signal line 17c. Therefore, the ON voltage is applied during the 1H period.
[0369]
For example, when the H-level signal is being output to the second of the shift register circuit 61a, an ON voltage is output to the gate signal line 17c of the pixel 16 (1), and the pixel 16 (1) is in a current (voltage) program state. It is. At the same time, an on-voltage is also output to the gate signal line 17a of the pixel 16 (2), the transistor 11b of the pixel 16 (2) is turned on, and the driving transistor 11a of the pixel 16 (2) is reset.
[0370]
Similarly, when an H-level signal is output to the third position of the shift register circuit 61a, an on-voltage is output to the gate signal line 17c of the pixel 16 (2), and the pixel 16 (2) performs the current (voltage) program. State. At the same time, an on-voltage is also output to the gate signal line 17a of the pixel 16 (3), the transistor 11b of the pixel 16 (3) is turned on, and the transistor 11a for driving the pixel 16 (3) is reset. An ON voltage is output from the gate signal line 17a, and an ON voltage is output to the gate signal line 17c for 1H.
[0371]
In the programmed state, if the transistor 11b and the transistor 11c are simultaneously turned on (FIG. 33 (b)), when transitioning to the non-programmed state (FIG. 33 (c)), the transistor 11c is higher than the transistor 11b. If it is turned off first, it will be in the reset state shown in FIG. To prevent this, the transistor 11c needs to be turned off later than the transistor 11b. For this purpose, it is necessary to control so that the ON voltage is applied to the gate signal line 17a before the gate signal line 17c.
[0372]
The above embodiment is an embodiment relating to the pixel configuration of FIG. 32 (basically, FIG. 1). However, the present invention is not limited to this. For example, the present invention can be implemented even with a current mirror pixel configuration as shown in FIG. In FIG. 38, the N-fold pulse driving shown in FIGS. 13 and 15 can be realized by controlling the transistor 11e to be turned on and off. FIG. 39 is an explanatory diagram of an embodiment using the pixel configuration of the current mirror of FIG. Hereinafter, the reset driving method in the pixel configuration of the current mirror will be described with reference to FIG.
[0373]
As shown in FIG. 39A, the transistors 11c and 11e are turned off, and the transistor 11d is turned on. Then, the drain (D) terminal and the gate (G) terminal of the current programming transistor 11b are short-circuited, and an Ib current flows as shown in the figure. In general, the transistor 11b is current-programmed in the immediately preceding field (frame), and has a capability of flowing current (the gate potential is held in the capacitor 19 for 1F, and an image is displayed. When the display is completely black, no current flows).
In this state, when the transistor 11e is turned off and the transistor 11d is turned on, the drive current Ib flows in the direction of the gate (G) terminal of the transistor 11a (the gate (G) terminal and the drain (D) terminal are short-circuited). ). Therefore, the gate (G) terminal and the drain (D) terminal of the transistor 11a have the same potential, and the transistor 11a is reset (state in which no current flows). Further, since the gate (G) terminal of the driving transistor 11b is common to the gate (G) terminal of the current programming transistor 11a, the driving transistor 11b is also reset.
[0374]
The reset state (state in which no current flows) of the transistors 11a and 11b is equivalent to the state in which the offset voltage of the voltage offset canceller method described in FIG. 51 and the like is held. In other words, in the state of FIG. 39A, an offset voltage (a starting voltage at which a current starts flowing) between terminals of the capacitor 19. By applying a voltage that is equal to or greater than the absolute value of this voltage, a current flows through the transistor 11. ) Is held. This offset voltage has a different voltage value depending on the characteristics of the transistors 11a and 11b. Therefore, by performing the operation of FIG. 39A, the state in which the transistor 11a and the transistor 11b do not flow the current to the capacitor 19 of each pixel (that is, the black display current (almost equal to 0)) is maintained. (Reset to the starting voltage at which current starts to flow).
[0375]
In FIG. 39 (a), similarly to FIG. 33 (a), the longer the reset execution time is, the more the Ib current flows and the terminal voltage of the capacitor 19 tends to decrease. Therefore, the implementation time in FIG. 39A needs to be a fixed value.
According to experiments and studies, the implementation time in FIG. 39A is preferably 1H or more and 10H (10 horizontal scanning periods) or less. More preferably, it is 1H or more and 5H or less. Alternatively, it is preferable that the time be 20 μsec or more and 2 msec or less. This is the same in the driving method shown in FIG.
[0376]
33 (a) is the same, but when the reset state of FIG. 39 (a) and the current program state of FIG. 39 (b) are performed in synchronization with each other, FIG. There is no problem since the period from the reset state to the current program state in FIG. 39B is a fixed value (constant value) (it is fixed). That is, the period from the reset state of FIG. 33 (a) or FIG. 39 (a) to the current programming state of FIG. 33 (b) or FIG. 39 (b) is 1H or more and 10H (10 horizontal scanning periods). ) It is preferred that: Furthermore, it is preferable to set it to 1H or more and 5H or less. Alternatively, it is preferable to set the period between 20 μsec and 2 msec. If this period is short, the driving transistor 11 is not completely reset.
If it is too long, the driving transistor 11 is completely turned off, and it takes a long time to program the current. Further, the brightness of the screen 50 also decreases.
[0377]
After performing (a) of FIG. 39, the state of (b) of FIG. 39 is set. FIG. 39B shows a state in which the transistor 11c and the transistor 11d are turned on and the transistor 11e is turned off. The state shown in FIG. 39B is a state in which current programming is performed. That is, the program current Iw is output (or absorbed) from the source driver circuit 14, and the program current Iw is supplied to the current programming transistor 11a. The potential of the gate (G) terminal of the driving transistor 11b is set to the capacitor 19 so that the program current Iw flows.
[0378]
If the program current Iw is 0 (A) (black display), the transistor 11b maintains the state in which the current shown in FIG. 33 (a) does not flow, thereby achieving good black display. it can. In the case of performing the white display current programming in FIG. 39B, even if the characteristic variation of the driving transistor of each pixel occurs, the offset voltage in the completely black display state (the characteristic of each driving transistor) is obtained. The current program is performed from the start voltage at which the current set according to the current flows. Therefore, the time programmed to the target current value becomes equal according to the gradation. Therefore, there is no gradation error due to variations in the characteristics of the transistor 11a or 11b, and a favorable image display can be realized.
[0379]
After the current programming of FIG. 39B, as shown in FIG. 39C, the transistors 11c and 11d are turned off, the transistor 11e is turned on, and the program current Iw (= Ie) flows through the EL element 15 to cause the EL element 15 to emit light. 39 (c) of FIG. 39 has already been described, and thus the details are omitted.
[0380]
In the drive method (reset drive) described with reference to FIGS. 33 and 39, the drive transistor 11a or 11b is disconnected from the EL element 15 (a state in which no current flows, which is performed by the transistor 11e or 11d) and the drive is performed. Between the drain (D) terminal and the gate (G) terminal of the driving transistor (or the source (S) terminal and the gate (G) terminal, or more generally, two terminals including the gate (G) terminal of the driving transistor) And a second operation of performing a current (voltage) program on the driving transistor after the above operation.
[0381]
At least the second operation is performed after the first operation. Note that the operation of disconnecting the driving transistor 11a or the transistor 11b from the EL element 15 in the first operation is not always an essential condition. If the driving transistor 11a or the transistor 11b and the EL element 15 in the first operation are not disconnected, the first operation of short-circuiting the drain (D) terminal and the gate (G) terminal of the driving transistor is performed. This is because there may be a case where a slight variation in the reset state occurs. This is determined by examining the transistor characteristics of the manufactured array.
[0382]
The pixel configuration of the current mirror in FIG. 39 is a driving method in which the current transistor 11a is reset, and as a result, the driving transistor 11b is reset.
[0383]
In the pixel configuration of the current mirror shown in FIG. 39, it is not always necessary to disconnect the driving transistor 11b and the EL element 15 in the reset state. Therefore, the drain (D) terminal and the gate (G) terminal (or the source (S) terminal and the gate (G) terminal of the current programming transistor a, or more generally, the gate (G) terminal of the current programming transistor a) (Or two terminals including the gate (G) terminal of the driving transistor), and a second operation of performing a current (voltage) program on the current programming transistor after the operation. Operation. At least the second operation is performed after the first operation.
[0384]
In the image display state (if an instantaneous change can be observed), first, the pixel row on which current programming is performed is in a reset state (black display state), and after a predetermined H, current programming is performed. The pixel row for black display moves from the top to the bottom of the screen, and the image should appear to be rewritten at the position where the pixel row has passed.
[0385]
In the above embodiments, the description has been made mainly on the pixel configuration of the current program. However, the reset driving of the present invention can be applied to the pixel configuration of the voltage program. FIG. 43 is an explanatory diagram of a pixel configuration (panel configuration) of the present invention for performing reset driving in a pixel configuration of voltage programming.
[0386]
In the pixel configuration of FIG. 43, a transistor 11e for resetting the driving transistor 11a is formed. When the on-voltage is applied to the gate signal line 17e, the transistor 11e is turned on, and the gate (G) terminal and the drain (D) terminal of the driving transistor 11a are short-circuited. Further, a transistor 11d for cutting a current path between the EL element 15 and the driving transistor 11a is formed. Hereinafter, the reset driving method of the present invention in the pixel configuration of the voltage program will be described with reference to FIG.
[0387]
As shown in FIG. 44A, the transistors 11b and 11d are turned off and the transistor 11e is turned on. The drain (D) terminal and the gate (G) terminal of the driving transistor 11a are short-circuited, and an Ib current flows as shown in the figure. Therefore, the gate (G) terminal and the drain (D) terminal of the transistor 11a have the same potential, and the driving transistor 11a is reset (state in which no current flows). Before resetting the transistor 11a, as described in FIG. 33 or FIG. 39, the transistor 11d is first turned on, the transistor 11e is turned off, and a current is supplied to the transistor 11a in synchronization with the HD synchronization signal. Keep it. Thereafter, the operation of FIG. 44A is performed.
[0388]
In the pixel configuration of the voltage program, similarly to the pixel configuration of the current program, the longer the reset execution time in FIG. 44A is, the more the Ib current flows and the terminal voltage of the capacitor 19 tends to decrease. is there. Therefore, the implementation time in FIG. 44A needs to be a fixed value. It is preferable that the operation time is not less than 0.2H and not more than 5H (5 horizontal scanning periods). More preferably, it is set to 0.5H or more and 4H or less. Alternatively, it is preferable that the period be 2 μsec or more and 400 μsec or less.
[0389]
Further, it is preferable that the gate signal line 17e is shared with the gate signal line 17a of the preceding pixel row. That is, the gate signal line 17e and the gate signal line 17a of the preceding pixel row are formed in a short state. This configuration is called a pre-stage gate control system.
Note that the pre-stage gate control method uses a gate signal line waveform of a pixel row selected at least 1H or more before the pixel row of interest. Therefore, it is not limited to one pixel row before. For example, the driving transistor 11a of the target pixel may be reset using the signal waveform of the gate signal line two rows before the pixel row.
[0390]
The following describes the pre-stage gate control system more specifically. The pixel row of interest is the (N) pixel row, and its gate signal lines are the gate signal line 17e (N) and the gate signal line 17a (N). In the preceding pixel row selected before 1H, the pixel row is (N-1) pixel row, and its gate signal lines are gate signal line 17e (N-1) and gate signal line 17a (N-1). . A pixel row selected 1H after the target pixel row is an (N + 1) pixel row, and its gate signal lines are a gate signal line 17e (N + 1) and a gate signal line 17a (N + 1).
[0391]
In the (N-1) H period, when an ON voltage is applied to the gate signal line 17a (N-1) of the (N-1) th pixel row, the gate signal line 17e (N) of the (N) th pixel row is applied. ) Is also applied to the ON voltage. This is because the gate signal line 17e (N) and the gate signal line 17a (N-1) of the preceding pixel row are formed in a short state. Therefore, the transistor 11b (N-1) of the pixel in the (N-1) th pixel row is turned on, and the voltage of the source signal line 18 is written to the gate (G) terminal of the driving transistor 11a (N-1). At the same time, the transistor 11e (N) of the pixel in the (N) th pixel row is turned on, the gate (G) terminal and the drain (D) terminal of the driving transistor 11a (N) are short-circuited, and the driving transistor 11a (N ) Is reset.
[0392]
In the (N) period following the (N-1) H period, when an ON voltage is applied to the gate signal line 17a (N) of the (N) pixel row, the gate signal of the (N + 1) pixel row The ON voltage is also applied to the line 17e (N + 1). Therefore, the transistor 11b (N) of the pixel in the (N) th pixel row is turned on, and the voltage applied to the source signal line 18 is written to the gate (G) terminal of the driving transistor 11a (N). At the same time, the transistor 11e (N + 1) of the pixel in the (N + 1) th pixel row is turned on, the gate (G) terminal and the drain (D) terminal of the driving transistor 11a (N + 1) are short-circuited, and the driving transistor 11a (N + 1) ) Is reset.
[0393]
Similarly, in the (N + 1) -th period following the (N) H-period, when an on-voltage is applied to the gate signal line 17a (N + 1) of the (N + 1) -th pixel row, the (N + 2) -th pixel row An on-voltage is also applied to the gate signal line 17e (N + 2). Therefore, the transistor 11b (N + 1) of the pixel in the (N + 1) th pixel row is turned on, and the voltage applied to the source signal line 18 is written to the gate (G) terminal of the driving transistor 11a (N + 1). At the same time, the transistor 11e (N + 2) of the pixel in the (N + 2) th pixel row is turned on, the gate (G) terminal and the drain (D) terminal of the driving transistor 11a (N + 2) are short-circuited, and the driving transistor 11a (N + 2). ) Is reset.
[0394]
In the above-described pre-stage gate control method of the present invention, the driving transistor 11a is reset for the 1H period, and thereafter, a voltage (current) program is executed.
[0395]
33 (a) is the same, but when the reset state of FIG. 44 (a) and the voltage program state of FIG. 44 (b) are performed in synchronization with each other, There is no problem since the period from the reset state to the current program state shown in FIG. 44B is a fixed value (constant value) (it is fixed). If this period is short, the driving transistor 11 is not completely reset. If it is too long, the driving transistor 11a is completely turned off, and it takes a long time to program the current. Further, the luminance of the screen 12 also decreases.
[0396]
After carrying out (a) of FIG. 44, the state of (b) of FIG. 44 is set. FIG. 44B shows a state where the transistor 11b is turned on and the transistors 11e and 11d are turned off. The state shown in FIG. 44B is a state in which voltage programming is being performed. That is, a program voltage is output from the source driver circuit 14, and the program voltage is written to the gate (G) terminal of the driving transistor 11a (the potential of the gate (G) terminal of the driving transistor 11a is set to the capacitor 19). In the case of the voltage programming method, it is not always necessary to turn off the transistor 11d during voltage programming. In addition, the driving method is a combination with the N-times pulse driving shown in FIGS. 13 and 15 or the intermittent N / K-times pulse driving (a driving method in which a plurality of lighting regions are provided on one screen. (Which can be easily realized by turning on / off the transistor 11e), the transistor 11e is not required. Since this has been described previously, the description is omitted.
[0397]
In the case of performing the white display voltage programming by the configuration of FIG. 43 or the driving method of FIG. 44, even if the characteristic variation of the driving transistor of each pixel occurs, the offset voltage of the completely black display state (each driving transistor) The voltage program is performed from the start voltage at which the current set according to the characteristic of (1) flows. Therefore, the time programmed to the target current value becomes equal according to the gradation. Therefore, there is no gradation error due to variations in the characteristics of the transistor 11a, and a favorable image display can be realized.
[0398]
After the current programming of FIG. 44 (b), as shown in FIG. 44 (c), the transistor 11b is turned off, the transistor 11d is turned on, and the program current from the driving transistor 11a flows to the EL element 15. The EL element 15 emits light.
[0399]
As described above, in the reset driving of the present invention in the voltage program of FIG. 43, first, in synchronization with the HD synchronizing signal, the transistor 11d is first turned on, the transistor 11e is turned off, and the current flows to the transistor 11a. 1, the connection between the transistor 11a and the EL element 15 is cut off, and the drain (D) terminal and the gate (G) terminal (or the source (S) terminal and the gate (G) terminal of the driving transistor 11a; In other words, a second operation of short-circuiting between two terminals including the gate (G) terminal of the driving transistor) and a third operation of performing a voltage program on the driving transistor 11a after the above operation are performed. Things.
[0400]
In the above embodiment, the current flowing from the driving transistor 11a (in the case of the pixel configuration in FIG. 1) to the EL element 15 is controlled by turning the transistor 11d on and off. In order to turn on / off the transistor 11d, it is necessary to scan the gate signal line 17b, and a scan requires the shift register 61 (gate driver circuit 12). However, the size of the shift register 61 is large, and the frame cannot be narrowed by using the shift register 61 for controlling the gate signal line 17b. The method described with reference to FIG. 40 solves this problem.
[0401]
The present invention will be described mainly by exemplifying the pixel configuration of the current program shown in FIG. 1 and the like. However, the present invention is not limited to this. Needless to say, the present invention can be applied to the pixel configuration. Needless to say, the technical concept of turning on / off in a block can be applied to a pixel configuration of a voltage program as shown in FIG.
[0402]
FIG. 40 shows an embodiment of the block drive system. First, for ease of explanation, the description will be made assuming that the gate driver circuit 12 is formed directly on the substrate 71 or the silicon chip gate driver IC 12 is mounted on the substrate 71. Further, the source driver 14 and the source signal line 18 are omitted because the drawing becomes complicated.
[0403]
In FIG. 40, the gate signal line 17a is connected to the gate driver circuit 12. On the other hand, the gate signal line 17b of each pixel is connected to the lighting control line 401. In FIG. 40, four gate signal lines 17b are connected to one lighting control line 401.
[0404]
It should be noted that blocking with the four gate signal lines 17b is not limited to this, and it goes without saying that more than four blocks may be used. Generally, it is preferable that the display screen 50 be divided into at least five or more. More preferably, it is preferably divided into 10 or more. Furthermore, it is preferable to divide into 20 or more. When the number of divisions is small, flicker is easily seen. If the number of divisions is too large, the number of lighting control lines 401 increases, and the layout of the control lines 401 becomes difficult.
[0405]
Therefore, in the case of a QCIF display panel, since the number of vertical scanning lines is 220, it is necessary to block at least 220/5 = 44 or more, and preferably block at 220/10 = 11 or more. There is a need to. However, when two blocks are formed in the odd-numbered rows and the even-numbered rows, flickering is relatively small even at a low frame rate, so that two blocks may be sufficient.
[0406]
In the embodiment of FIG. 40, the ON voltage (Vgl) or the OFF voltage (Vgh) is sequentially applied to the lighting control lines 401a, 401b, 401c, 401d,. Turns the flowing current on and off.
[0407]
In the embodiment of FIG. 40, the gate signal line 17b does not cross the lighting control line 401. Therefore, a short-circuit defect between the gate signal line 17b and the lighting control line 401 does not occur. Further, since the gate signal line 17b and the lighting control line 401 are not capacitively coupled, the addition of capacitance when the gate signal line 17b side is viewed from the lighting control line 401 is extremely small. Therefore, the lighting control line 401 is easily driven.
[0408]
A gate signal line 17a is connected to the gate driver circuit 12. By applying an on-voltage to the gate signal line 17a, a pixel row is selected, the transistors 11b and 11c of each selected pixel are turned on, and the current (voltage) applied to the source signal line 18 is applied to each pixel. Program the capacitor 19. On the other hand, the gate signal line 17b is connected to the gate (G) terminal of the transistor 11d of each pixel. Therefore, when the ON voltage (Vgl) is applied to the lighting control line 401, a current path between the driving transistor 11a and the EL element 15 is formed. Conversely, when the OFF voltage (Vgh) is applied, the EL element is Open 15 anode terminals.
[0409]
The control timing of the on / off voltage applied to the lighting control line 401 and the timing of the pixel row selection voltage (Vgl) output to the gate signal line 17a by the gate driver circuit 12 are synchronized with one horizontal scanning clock (1H). Is preferred. However, it is not limited to this.
[0410]
The signal applied to the lighting control line 401 merely turns on and off the current to the EL element 15. Further, it is not necessary to synchronize with the image data output from the source driver 14. This is because the signal applied to the lighting control line 401 controls the current programmed in the capacitor 19 of each pixel 16. Therefore, it is not always necessary to synchronize with the selection signal of the pixel row. Also, even in the case of synchronization, the clock is not limited to the 1H signal, and may be 1 / 2H or 1 / 4H.
[0411]
Even in the case of the current mirror pixel configuration shown in FIG. 38, the transistor 11e can be turned on and off by connecting the gate signal line 17b to the lighting control line 401. Therefore, block driving can be realized.
[0412]
In FIG. 32, if the gate signal line 17a is connected to the lighting control line 401 and reset is performed, block driving can be realized. That is, the block driving of the present invention is a driving method in which a plurality of pixel rows are simultaneously turned off (or black displayed) by one control line.
[0413]
In the above embodiments, one selected pixel row is arranged (formed) for each pixel row. The present invention is not limited to this, and one selection gate signal line may be arranged (formed) in a plurality of pixel rows.
[0414]
FIG. 41 shows the embodiment. Note that, for ease of description, the pixel configuration will be described mainly by exemplifying the case of FIG. In FIG. 41, the selection gate signal line 17a in the pixel row selects three pixels (16R, 16G, 16B) at the same time. The symbol of R means red pixel association, the symbol of G means green pixel association, and the symbol of B means blue pixel association.
[0415]
Therefore, by selecting the gate signal line 17a, the pixel 16R, the pixel 16G, and the pixel 16B are selected at the same time, and a data writing state is set. The pixel 16R writes data from the source signal line 18R to the capacitor 19R, and the pixel 16G writes data from the source signal line 18G to the capacitor 19G. The pixel 16B writes data from the source signal line 18B to the capacitor 19B.
[0416]
The transistor 11d of the pixel 16R is connected to the gate signal line 17bR. The transistor 11d of the pixel 16G is connected to the gate signal line 17bG, and the transistor 11d of the pixel 16B is connected to the gate signal line 17bB. Therefore, the EL element 15R of the pixel 16R, the EL element 15G of the pixel 16G, and the EL element 15B of the pixel 16B can be separately controlled on / off. That is, the EL element 15R, the EL element 15G, and the EL element 15B can individually control the lighting time and the lighting cycle by controlling the respective gate signal lines 17bR, 17bG, and 17bB.
[0417]
To realize this operation, in the configuration of FIG. 6, a shift register circuit 61 that scans the gate signal line 17a, a shift register circuit 61 that scans the gate signal line 17bR, and a shift register circuit that scans the gate signal line 17bG It is appropriate to form (arrange) four circuits 61 and a shift register circuit 61 that scans the gate signal line 17bB.
[0418]
Although a current N times the predetermined current flows through the source signal line 18 and a current N times the predetermined current flows through the EL element 15 for a period of 1 / N, this cannot be realized in practice.
This is because a signal pulse applied to the gate signal line 17 actually penetrates through the capacitor 19, and a desired voltage value (current value) cannot be set in the capacitor 19. Generally, a voltage value (current value) lower than a desired voltage value (current value) is set to the capacitor 19. For example, even if driving is performed so as to set a current value ten times, only about five times the current is set in the capacitor 19. For example, even when N = 10, the current that actually flows through the EL element 15 is the same as when N = 5. Therefore, the present invention is a method of setting an N-fold current value and driving the EL element 15 so that a current proportional to or corresponding to N-times flows to the EL element 15. Alternatively, a driving method in which a current larger than a desired value is applied to the EL element 15 in a pulse shape.
[0419]
In addition, a current (voltage) program is applied to the driving transistor 11a (in the case of FIG. 1) by applying a current (a current that becomes higher than a desired luminance when a current is continuously applied to the EL element 15) to a desired value. The intermittent current flowing through the EL element 15 is used to obtain a desired emission luminance of the EL element.
[0420]
It is preferable that the switching transistors 11b and 11c shown in FIG. This is because the penetration voltage to the capacitor 19 is reduced. Further, since the off-leakage of the capacitor 19 is reduced, it can be applied to a low frame rate of 10 Hz or less.
[0421]
Further, depending on the pixel configuration, when the penetration voltage acts in a direction to increase the current flowing through the EL element 15, the white peak current increases, and the sense of contrast in image display increases. Therefore, good image display can be realized.
[0422]
Conversely, it is also effective to make the switching transistors 11b and 11c of FIG. 1 P-channel so that a punch-through occurs to make black display better. When the P-channel transistor 11b turns off, the voltage becomes Vgh. Therefore, the terminal voltage of the capacitor 19 slightly shifts to the Vdd side. Therefore, the gate (G) terminal voltage of the transistor 11a increases, and the display becomes more black. In addition, since the current value used for the first gradation display can be increased (a constant base current can be supplied until gradation 1), the shortage of the write current can be reduced by the current programming method.
[0423]
The transistor 11b in FIG. 1 operates to hold the current flowing from the driving transistor 11a in the capacitor 19. That is, it has a function of short-circuiting between the gate terminal (G) and the drain terminal (D) or the source terminal (S) of the driving transistor 11a during programming. A switching transistor having such a function as the transistor 11b will be referred to as a short-circuit transistor. The short-circuit transistor has a source terminal or a drain terminal connected to the holding capacitor 19. The short-circuit transistor is turned on and off by a voltage applied to the gate signal line 17a. The problem is that the voltage of the gate signal line 17a penetrates through the capacitor 19 when the off-voltage is applied. Due to this penetration voltage, the potential of the capacitor 19 (= the potential of the gate terminal (G) of the driving transistor 11a) fluctuates, so that good current programming cannot be performed and laser shot unevenness occurs. Therefore, it is necessary to reduce the penetration voltage.
[0424]
In order to reduce the penetration voltage, the size of the short-circuit transistor 11b may be reduced. Now, it is assumed that the size Scc of the short-circuit transistor is a channel width W (μm), a channel length L (μm), and Scc = W · L (square μm). When a plurality of short-circuit transistors are connected in series, Scc is the total size of the connected transistors. For example, if W = 5 (μm), L = 6 (μm) and the number (n = 4) of one short-circuit transistor are connected and Scc = 5 × 6 × 4 = 120 (square μm) ).
[0425]
There is a correlation between the size of the short-circuit transistor and the penetration voltage. FIG. 194 shows this relationship. It is assumed that the short-circuit transistor is a P-channel transistor. However, an N-channel transistor can be applied.
[0426]
In FIG. 194, the horizontal axis is Scc / n. Scc is the sum of the sizes of the short-circuit transistors as described above. n is the number of connected short-circuit transistors. In FIG. 194, the horizontal axis is obtained by dividing Scc by n pieces. That is, the size of each short-circuit transistor is one.
[0427]
In the first embodiment, the size Scc of the short-circuit transistor is defined as channel width W (μm) and channel length L (μm). If the number of short-circuit transistors is n = 4, Scc / n = 5 × 6 × 4/4 = 30 (square μm). In FIG. 194, the vertical axis represents the penetration voltage (V).
[0428]
If the punch-through voltage is not less than 0.3 (V), laser shot unevenness occurs and is visually unacceptable. Therefore, the size of each short-circuit transistor needs to be 25 (square μm) or less. On the other hand, if the short-circuit transistor is not set to 5 (square μm) or more, the processing accuracy of the transistor will not be high, and the variation will be large. In addition, there is a problem in driving performance. From the above, it is necessary to set the short-circuit transistor 11b to 5 (square μm) or more and 25 (square μm) or less. More preferably, the short-circuit transistor 11b needs to be 5 (square μm) or more and 20 (square μm) or less.
[0429]
The punch-through voltage of the short-circuit transistor also has a correlation with the amplitude value (Vgh-Vgl) of the voltage (Vgh, Vgl) for driving the short-circuit transistor. The punch-through voltage increases as the amplitude value increases. This relationship is illustrated in FIG. In FIG. 196, the horizontal axis represents the amplitude value (Vgh−Vhl) (V). The vertical axis is the penetration voltage. As described with reference to FIG. 194, the penetration voltage needs to be 0.3 (V) or less.
[0430]
Note that the permissible value of the penetration voltage 0.3 (V) is, in other words, １ ／ or less (20% or less) of the amplitude value of the source signal line 18. The source signal line 18 is 1.5 (V) when the program current is white display, and is 3.0 (V) when the program current is black display. Therefore, (3.0-1.5) /5=0.3 (V).
[0431]
On the other hand, if the amplitude value (Vgh−Vhl) of the gate signal line is not more than 4 (V), the pixel 16 cannot be sufficiently written. From the above, the amplitude value (Vgh−Vgl) of the gate signal line needs to satisfy the condition of 4 (V) or more and 15 (V) or less. More preferably, the amplitude value (Vgh-Vgl) of the gate signal line must satisfy the condition of 5 (V) or more and 12 (V) or less.
[0432]
In the EL element 15, electrons are injected from the cathode (cathode) into the electron transport layer, and holes are also injected from the anode (anode) into the hole transport layer. The injected electrons and holes move to the opposite electrode by the applied electric field. At this time, carriers are trapped in the organic layer or carriers are accumulated as in the case of a difference in energy level at the interface of the light emitting layer.
[0433]
When space charges are accumulated in the organic layer, the molecules are oxidized or reduced, and the generated radical anion molecules or radical cation molecules are unstable. Is known to cause an increase in the driving voltage. To prevent this, as an example, the device structure is changed and a reverse voltage is applied.
[0434]
When a reverse bias voltage is applied, a reverse current is applied, so that the injected electrons and holes are extracted to the cathode and the anode, respectively. As a result, the formation of space charges in the organic layer is eliminated, and the electrochemical deterioration of molecules is suppressed, so that the life can be extended.
[0435]
The reverse bias drive of the present invention described below is performed during a period when no image is displayed. That is, after the display panel of the present invention is turned on, reverse bias driving is performed for a certain period. Alternatively, reverse bias driving is performed for a certain period before the display panel is turned on.
[0436]
FIG. 340 is an explanatory diagram for explaining the reverse bias driving method of the present invention. The power supply circuit (IC) 82 has two terminals, one terminal A is connected to the base anode line 2631 and applies an anode voltage Vdd to the anode line of the pixel 16. On the other hand, the other terminal B is connected to the base cathode line 2671 and supplies the Vss voltage to the cathode of the pixel 16.
[0437]
Note that, for ease of explanation, the description will be made on the assumption that the anode voltage Vdd is higher than the cathode voltage Vss. The pixel configuration will be described by exemplifying the configuration in FIG. 1, but is not limited to this pixel configuration. This is because the reverse bias driving method of the present invention described below changes the voltage applied to at least one of the cathode and the anode to apply the reverse bias voltage to the EL element 15. More preferably, a predetermined voltage is written to the pixel from the source driver circuit 14, and a reverse bias voltage is applied by this voltage and the voltage applied to the EL element 15 changed. Therefore, the present invention is not limited to the pixel configuration.
[0438]
In order to further facilitate understanding, as an example, the drive voltage and signal amplitude of each section are embodied as voltage values. First, the source driver circuit 14 operates with a power supply voltage of GND (0 (V)) and 5.5 (V), and outputs a video signal of a maximum of 5.5 (V) and a minimum of 0.5 (V). (Because the operation of the unit transistor 634 in FIG. 71 requires about 0.5 (V), the output minimum amplitude is GND + 0.5 (V)). Therefore, a video signal having a potential of 5.5 (V) to 0.5 (V) is output to the source signal line 18. The precharge voltage output from the source driver circuit 14 is set to 5.5 (V) to 0 (V).
[0439]
On the other hand, the anode voltage Vdd of the pixel is set to 5.5 (V) of the power supply voltage of the source driver circuit 14. Therefore, when the driving TFT 11a of the pixel 16 flows the maximum current Imax required for displaying an image, the voltage drop of the channel (between S and D) in the diode connection state is set within 5.0 (V). This is important. In other words, when the voltage Vic (5.5 (V) in this case) -0.5 (V) used by the source driver circuit 14 is used, the driving transistor of the pixel 16 is diode-connected (the G-D short-circuit state of the TFT 11a). Then, when a maximum current (white display) required for image display is applied, the pixel voltage is set so that the channel voltage (SD voltage) is smaller than Vic-0.5 (V). Make the design. That is, in the above embodiment, the voltage of the video signal output from the source driver circuit 14 to the source signal line 18 is 5.0 (V). At this time, the SD voltage of the diode-connected TFT 11a is set to be 5.0 (V) or less at the maximum. The diode characteristics can be freely changed by designing the channel width (W) and channel length (L) of the transistor to predetermined values.
[0440]
The cathode voltage Vss is set to -8 (V). The ON voltage Vgl applied to the gate signal line 17 is set to -8 + (-2) =-10 (V), and the OFF voltage Vgh applied to the gate signal line 17 is set to + 5.5 + 1.5 = + 7 (V). . The precharge voltage Vp output from the source driver circuit 14 is 5 (V), and Vm is 0 (V).
[0441]
FIG. 340 shows an image display state. From the power supply circuit (IC) 82, the Vdd voltage is applied to the anode of the pixel 16, and the Vss voltage is applied to the anode. A video signal is applied to the source signal line 18 from the source driver circuit 14 based on a video signal displayed on the display panel. Further, as described in FIGS. 65, 66, 67, 232, 233, etc., the precharge voltage Vp is applied to the source signal line 18 as necessary. The gate driver circuit 12 synchronizes with the horizontal synchronization signal, sequentially selects the gate signal lines 17, and applies an ON voltage to the selected gate signal lines 17.
[0442]
With the above operation, the program current Iw corresponding to the video signal is written to the pixel 16, and a current corresponding to the program current Iw is applied from the driving TFT 11a to the EL element 15, and the EL element 15 emits light. The above is the operation in the image display state.
[0443]
When the user turns off the power switch, the controller 81 (see FIG. 8 and the like) detects that the power switch is turned off, controls the power circuit 82 and the source driver circuit 14, and starts reverse bias driving. FIG. 341 is an explanatory diagram of the reverse bias driving state.
[0444]
At the time of reverse bias driving, first, the gate driver circuit 12b on the EL side is controlled to apply an off voltage Vgh to the gate signal line 17b so that no current flows through the EL element 15. Next, the precharge voltage Vm is output from the source driver circuit 14 to the source signal line 18. In addition, the gate driver circuits 12a on the selection side are sequentially or simultaneously operated to operate the selection TFTs 11b and 11c, and the Vm voltage is written to the gate terminal of the TFT 11a (or written to the pixel electrode 105 rather than to the pixel electrode 105. This is the anode side terminal of the EL element 15). For the relationship between the EL element 15 and the pixel electrode, see FIG. 10 and the description thereof.
[0445]
Next, an off voltage is applied to the gate signal line 17a to turn off the selected TFTs 11b and 11c. Note that when the source driver circuit 14 can fix the potential of the source signal line 18 to the voltage Vm without change, the TFTs 11b and 11c may be kept on.
[0446]
At the same time as the next or previous operation, the power supply circuit 82 is controlled to apply a voltage of V2 = Vdd to the base cathode line 2671 and apply a voltage of V1 = Vm−2 (V) to the base anode line 2631. I do. The voltage V1 is set to Vm-2 (V) in order to completely turn off the TFT 11a and prevent a current from flowing. Therefore, the voltage V1 may be any voltage as long as the TFT 11a can be set to a current value equal to or less than the leak state in relation to the voltage Vm.
[0447]
In the above state, the gate driver circuit 12a on the EL side is operated to turn on the TFT 11d. When the TFT 11d is turned on, the Vm voltage is applied to the anode side of the EL element 15 (applied to the pixel electrode 105), and the V2 voltage is applied to the cathode side (reflection electrode) of the EL element 15. Therefore, a reverse bias voltage is applied to the EL element 15.
[0448]
Note that the TFT 11d is turned on after applying the Vm voltage to the pixel electrode 105, but is not limited to this. The Vm voltage may be applied with the TFT 11d turned on. However, when the voltage V2 is applied to the cathode terminal while the TFTs 11d and 11c are on, the potential of the source signal line 18 decreases and the source driver circuit 14 may be destroyed. It is necessary to consider (examine) the control timing.
[0449]
Further, the voltage V2 is the voltage Vdd, but is not limited thereto. Since the Vdd voltage is a voltage generated by the power supply circuit 82, using it has an effect of reducing the circuit scale of the power supply circuit 82. However, as the voltage applied to the cathode of the EL element 15 is higher, the effect of the reverse bias is higher, and the rise in the terminal voltage of the EL element 15 due to deterioration is often reduced. Therefore, another voltage (it may be higher than the Vdd voltage and lower than the Vdd voltage in some cases) may be used. That is, the effect of applying the reverse bias voltage needs to be determined by experiment. Here, for the sake of simplicity, the description will be made assuming that V2 = Vdd. Further, the Vm voltage can be set to Vm = 0 (V) or less (for example, -5 (V) or the like).
[0450]
Further, the reverse bias voltage Vs (Vs = (V2-Vm) absolute value) applied to the EL element 15 needs to be 3 (V) or more when the EL element 15 is made of a polymer EL material. , Preferably 5 (V) or more. Note that the maximum value Vs needs to be equal to or less than 15 (V). (If the reverse bias voltage is higher than a predetermined value, a short circuit or the like may occur between the anode electrode and the cathode electrode of the EL element 15 due to application of the reverse bias voltage. appear). When the EL element 15 is made of a low-molecular EL material, the Vs voltage needs to be 5 (V) or more, preferably 10 (V) or more. Note that the maximum value Vs needs to be 20 (V) or less. (If the reverse bias voltage is higher than a predetermined value, a short circuit or the like occurs between the anode electrode and the cathode electrode of the EL element 15 due to the application of the reverse bias voltage. appear).
[0451]
FIG. 344 illustrates the effect of the reverse bias driving method of FIG. 341 (the same applies to other embodiments described later). In FIG. 344, the vertical axis indicates the change voltage ratio. The change voltage ratio is a ratio of a voltage change between when a reverse bias voltage is applied and when no reverse bias voltage is applied. For example, the initial terminal voltage when a constant current of 1 (μA) flows through the EL element 15 is set to 10 (V), and the power failure of 1 (μA) occurs when the reverse bias voltage drive of the present invention is not performed. Assuming that the terminal voltage of the EL element 15 at the time of the dragon becomes 13 (V), the change voltage ratio is 13 (V) / 10 (V) = 1.3.
[0452]
When the reverse bias voltage driving is performed, a rise in the terminal voltage of the EL element 15 due to the deterioration is reduced. For example, when the initial terminal voltage when a constant current of 1 (μA) is applied to the EL element 15 is set to 10 (V) and the reverse bias voltage driving of the present invention is performed, the EL at the time of a power failure of 1 (μA) is obtained. The terminal voltage of the element 15 becomes 11 (V) or less, and a remarkable improvement effect is obtained. In this case, the change voltage ratio is 11 (V) / 10 (V) = 1.1.
[0453]
In FIG. 344, the horizontal axis represents the application time of the reverse bias voltage applied after using the display panel. When the EL element 15 is made of a polymer EL material, the reverse bias voltage Vs is required to be 3 (V) or more, preferably 5 (V) or more. Note that the maximum value Vs needs to be 15 (V) or less. When the EL element 15 is made of a low-molecular EL material, the Vs voltage needs to be 5 (V) or more, preferably 10 (V) or more. Note that the maximum value Vs needs to be 20 (V) or less. Note that the solid line in FIG. 344 shows the case where the EL element 15 is a low molecular material, and the dotted line shows the case where the EL element 15 is a high molecular material. FIG. 344 shows a case where the G color is displayed at 200 (nt), continuous lighting is performed for 10 minutes, and then a reverse bias voltage is applied to the EL element 15 so that the total lighting time becomes 2000 hours. 3 shows the voltage change ratio. However, the tendency is the same or similar for R and B.
[0454]
As can be seen from FIG. 344, when no reverse bias voltage is applied, the terminal voltage of the EL element 15 increases by as much as 30%. However, the change voltage ratio is reduced by performing the reverse bias voltage driving of the present invention. When a reverse bias voltage is applied for 2 seconds after continuous lighting of the EL display element, the change voltage ratio changes by about 5% (1.05). Therefore, it is preferable to apply the reverse bias voltage for 2 seconds (sec) or more. In particular, when a reverse bias voltage is applied for 5 seconds after continuous lighting of the EL display element, the change voltage ratio changes by about 2% (1.02). Therefore, more preferably, the reverse bias voltage is preferably applied for a time of 5 seconds (sec) or more. The maximum period for applying the reverse bias voltage is a constraint on the use of the system. When the reverse bias voltage is applied for a long time, it is necessary to operate the controller 81 and the like while the reverse bias voltage is being applied. Therefore, the power consumption of the system (display device) increases. Therefore, the period for applying the reverse bias voltage needs to be within 60 seconds (60 seconds) at the maximum.
[0455]
FIG. 344 is an example in which the reverse bias voltage driving of the present invention is performed after using the display panel. In the case where the display panel is used after performing the reverse bias voltage driving of the present invention before using the display panel. However, the characteristics in FIG. 344 are the same. FIG. 344 shows an example in which the display panel is used for 10 minutes and then the reverse bias voltage driving of the present invention is performed. There is no difference in the effect of the reverse bias voltage driving depending on the use time of the display panel. That is, regardless of whether the display panel is used continuously for 3 minutes or for 60 minutes, applying the reverse bias voltage for 2 seconds or more prevents the terminal voltage of the EL element 15 from rising. Can be suppressed. This is considered to be because the charge charged in the EL element 15 can be discharged by applying a voltage equal to or higher than a certain value regardless of the usage period.
[0456]
FIG. 342 illustrates a connection state between the power supply circuit 82 and the source driver circuit 14 of the present invention. Voltages (Vp, Vm) are applied to the source signal line 18 from a precharge circuit. At the time of normal display, the analog switch 561b2 applies the Vp voltage to the source signal line 18. At the time of reverse bias voltage driving, the Vm voltage is applied to the source signal line 18 in synchronization with the power supply circuit 82 (synchronization is controlled by the controller 81).
When applying the Vm voltage, the analog switch 561 disposed or formed between the output terminal of the current output circuit 654 and the connection terminal 2633 is turned off (open). This is to protect the current output circuit 654 from the Vm voltage or the voltage output from the pixel 16 to the source signal line 18 and prevent the current output circuit 654 from being broken.
[0457]
Although the Vm voltage is applied to the source signal line 18 from the source driver circuit 14, the application of the Vm voltage is not limited to the application from the source driver circuit 14. For example, as described with reference to FIG. 92, the precharge voltage PV may be generated in the array substrate, and the PV voltage may be changed to the Vm voltage and applied to the source signal line 18. Alternatively, as shown in FIG. 103, the probe may be directly contacted with the connection terminal 971, and the Vm voltage may be applied from the probe.
[0458]
FIG. 343 is a block diagram of the power supply circuit (IC) 82 of the present invention. The power supply circuit 82 of the present invention includes two booster circuits 3433. A reference voltage or a DC voltage Vd supplied from a battery is applied to the booster circuit 3433. This DC voltage Vd is converted into a rectangular wave (AC) by a switching circuit (not shown). The converted rectangular wave is boosted to a specified value (desired value) by a transformer 1121 composed of a single-turn coil. The boosted rectangular wave is converted into a DC voltage again by the smoothing circuit formed or arranged in the boosting circuit 3433. This DC voltage can be easily changed by the switching cycle or timing of the switching circuit. Further, the polarity of the generated DC voltage can be freely set according to the winding direction of the coil of the transformer 1121.
[0459]
As described above, two voltages (Va and Vb) are generated by the two booster circuits, and these two voltages are applied to the a terminal and the b terminal of the switching circuit 481 (481c and 481d).
[0460]
The switching circuit 481c controls whether to output the Va voltage or the Vb voltage to the base anode line 2631 under the control of the controller 81. Similarly to the switching circuit 481d, the controller 81 controls whether to output the Va voltage or the Vb voltage to the base cathode line 2671.
[0461]
Reference numeral 3431 denotes an output buffer circuit having a function of holding the Va voltage or the Vb voltage at a constant voltage value regardless of the magnitude of the output current. The switches 561c and 561d are switches for setting the voltage output to the base anode line 2631 or the base cathode line 2671 to a high impedance state as shown in FIG.
[0462]
FIG. 345 is a timing chart of the reverse bias voltage driving of the present invention. When the display control signal is at the H level, the power is on (a state in which an image is displayed on the display panel), and when the display control signal is at the L level, the user is off (a state in which no image is displayed on the display panel). Therefore, the controller 81 detects when the display control signal goes low, and enters the reverse bias voltage drive mode.
[0463]
After the display control signal becomes L level (point b) and after t1 (point c), the voltage (V1 applied voltage) applied to the base anode line 2631 is changed from the VH1 voltage (Vdd voltage) to the VL1 voltage (Vm voltage). −2 (V)) (see FIG. 341). Further, the voltage (V2 applied voltage) applied to the base cathode line 2671 changes from the VL2 voltage (Vss voltage) to the VH2 voltage (Vdd voltage) (see FIG. 341). Thus, the preparation for applying the reverse bias voltage to the EL element 15 is completed. The Vm voltage does not need to be a constant value and may be changed.
[0464]
The time (t1) between the points c and b needs to be 1 msec or more. This is to secure a period for changing the selection state of the gate signal line 17. Further, the time between the point d and the point c (t2: t2 is a period from when the first gate signal line 17a is selected to when the Vm voltage is applied to the pixel electrode 105. Basically, the pixel electrode 105 is driven for reverse bias driving. It is necessary to secure a period of at least 1 msec. More preferably, it is required to be 4 msec or more. This is because the cathode electrode has a capacitance of 0.01 μF or more, so that a relatively long time is required until the voltages (V1, V2) output from the power supply circuit 82 reach the predetermined voltages.
[0465]
On the other hand, the gate signal lines 17a are sequentially scanned, and the Vm voltage applied to the source signal lines 18 is applied to the pixel electrodes 105. At this time, in synchronization with the on / off of the TFT 11d on the EL side, the TFT 11d is not turned on when the Vm voltage is applied (writing) to the pixel electrode 105. Since the period in which the TFTs 11c and 11b are on is the selection period of one gate signal line 17a (basically, one horizontal scanning period), the TFT 11d is turned off, and a reverse bias voltage is applied to the EL element 15. The periods that are not are almost negligible.
[0466]
As described above, the reverse bias voltage can be applied to the EL element 15 by sequentially selecting the gate signal lines 17a, applying the Vm voltage to the anode side of the EL element 15 and applying the + voltage to the cathode side. Therefore, the terminal voltage of the EL element 15 does not increase, and the life of the EL display panel can be extended.
[0467]
In the embodiment of FIG. 345, the period for selecting each gate signal line 17a in order to apply a reverse bias voltage is set to one horizontal scanning period (1H) which is the same as that during normal image display. There is no limitation. For example, as shown in FIG. 346, the period (T1) may be longer than 1H. That is, since an image is not displayed, it is not necessary to limit to 1H. By setting T1> 1H, the stability at the time of applying the reverse bias voltage is improved.
[0468]
Further, in the embodiment of FIG. 345, the gate signal line 17a is selected by scanning, but the present invention is not limited to this. For example, as shown in FIG. 347, the ON voltage may be applied to all the gate signal lines 17a, and the Vm voltage may be applied to the anode of the EL element 15 of each pixel 16.
[0469]
Similarly, as shown in FIG. 348, the period (T2) for applying the ON voltage to all the gate signal lines 17a and the period (T3) for applying the OFF voltage may be alternately repeated. As shown in FIG. 349, the ON voltage is applied to the even-numbered gate signal lines 17a, and at this time, the OFF-state voltage is applied to the odd-numbered gate signal lines 17a, An ON voltage may be applied to the gate signal line 17a, and at that time, a state in which an OFF voltage is applied to the even-numbered gate signal lines 17a may be alternately repeated.
[0470]
FIG. 341 shows that a voltage of V1 = Vm−2 (V) is applied to the base anode line 2631. The reason why the voltage V1 = Vm−2 (V) is applied is to turn off the TFT 11 a and prevent a current from flowing into the pixel electrode 105. To prevent the current from flowing, the source (S) terminal of the driving TFT 11a may be opened as shown in FIG. By opening the source terminal, no current flows between the channels of the TFT 11a. Opening can be easily realized by opening the switch 561 (see FIG. 343). Alternatively, the connection point between the power supply circuit 82 and the base anode line 2631 may be removed.
[0471]
With the configuration in FIG. 350 as well, the voltage Vm applied to the source signal line 18 from the source driver circuit 14 can be applied to the pixel electrode 105 (the Vm voltage can be applied to the anode side of the EL element 15). Further, a Vdd voltage can be applied from the power supply circuit 82 to the cathode side of the EL element 15, and a reverse bias voltage can be applied to the EL element 15.
[0472]
In the above-described embodiment, the Vm voltage is written to the anode side of the EL element 15 by sequentially selecting, always selecting, or selecting at a predetermined cycle the gate signal line 17a. By writing the Vm voltage, the potential on the anode side of the EL element 15 is accurately determined. However, if the purpose is to apply a reverse bias voltage to the EL element 15, the anode potential of the EL element 15 does not need to be accurate (predetermined value). For example, there may be an error of about ± 2 (V) from the voltage Vm.
[0473]
Therefore, as in the embodiment of FIG. 351, the on / off state of the gate signal lines 17a and 17b is not timing-controlled, an off voltage is applied to the gate signal line 17a, and the TFTs 11b and 11c are maintained in the off state, and An ON voltage may be applied to the signal line 17b to keep the TFT 11d in the ON state. In this state, the voltage V1 is applied to the base anode line 2631 and the voltage V2 is applied to the base cathode line 2671 as shown in FIG. In this case, the potential Vc of the pixel electrode 105 is divided by the voltage between the channels of the TFT 11a and the voltage between the terminals of the EL element 15 (basically determined by the impedance of both elements). Therefore, the Vc voltage is not an accurate value, but at least the relationship of Vc> V1 and Vc <V2 is satisfied, so that a reverse bias voltage is applied to the EL element 15.
[0474]
The above embodiment has been described by exemplifying the pixel configuration of FIG. However, the present invention is not limited to this. For example, as shown in FIG. 352, the reverse bias voltage drive of the present invention can be implemented even with a pixel configuration of a current mirror. Also, as shown in FIG. 353, it goes without saying that the reverse bias voltage driving of the present invention can be implemented by a pixel configuration driven by voltage. Even in the pixel configurations of FIGS. 352 and 353, the reverse bias voltage driving method is the same as or similar to the previously described method or configuration, and a description thereof will be omitted.
[0475]
As described above, the deterioration of the EL element 15 can be prevented by the reverse bias voltage driving of the present invention. However, measures using only the driving method are not perfect. This is because burn-in occurs when the luminance of the EL element 15 decreases by 1 to 5%. The burn-in in the case of the liquid crystal display panel disappears by driving for 1 to 2 hours, but the burn-in of the EL display panel is caused by deterioration of the EL element 15 and therefore does not disappear once.
[0476]
To solve this problem, the EL display panel (apparatus) of the present invention has a display area for one character both vertically and horizontally, as shown in FIG. 354, on a display screen 50 of M characters horizontally and N characters vertically. . Assuming that one character is represented by horizontal D1 dots × vertical D2 dots as shown in FIG. 355, the number of display dots larger than the originally required display dot number by horizontal D1 dots and vertical D2 dots is calculated. have.
[0477]
Burn-in occurs because the fixed pattern is displayed at the same position. Therefore, if the fixed pattern (character or wallpaper) is moved at a constant cycle or interval, the occurrence of printing is reduced. The moving cycle (timing, that is, the time interval for moving from one display location state to another display location) is preferably set to 10 seconds or more and 120 seconds or less. If the time is less than 10 seconds, the screen (characters, etc.) moves while the user is gazing at the screen, which is visually unacceptable. On the other hand, if displayed at the same position for an excessively long time, burning will occur.
[0478]
It is preferable that the interval of movement be within 3 dots. More preferably, it is preferable to be within one dot. If the number of dots is four or more, when the screen (characters, etc.) moves while the user is watching the screen, it is recognized as a large fluctuation state, and is visually unacceptable. When the power is turned off and the next power is turned on, the previous image display position may be stored in the flash memory.
[0479]
In FIG. 355, the movement from (a) in FIG. 355 to (b) in 355 shows a state in which one dot has been moved both vertically and horizontally. However, as shown in FIG. 356, it is preferable that the movement be performed in small increments in the vertical or horizontal direction. In FIG. 355, first, the character display position is moved downward (upper left in FIG. 356), then one dot is moved left and right, and this time, the character display position is moved upward. ing. When it is moved to the end (upper right in FIG. 356), it is moved in the reverse order of the arrow. This operation is repeated.
[0480]
As described above, by moving the display position, the burning of the fixed pattern on the EL display panel can be significantly reduced.
[0481]
Hereinafter, another driving method of the present invention will be described with reference to the drawings. FIG. 125 is an explanatory diagram of a display panel for performing the sequence driving of the present invention. The source driver circuit 14 switches and outputs R, G, and B data to the connection terminal 681. Therefore, the number of output terminals of the source driver circuit 14 can be reduced to 1/3 as compared with the case of FIG.
[0482]
A signal output from the source driver circuit 14 to the connection terminal 681 is distributed to the source signal lines 18R, 18G, and 18B by the output switching circuit 1251. The output switching circuit 1251 is formed directly on the substrate 71 using polysilicon technology or amorphous silicon technology. Alternatively, the output switching circuit 1251 may be formed using a silicon chip and mounted on the substrate 71 by using a COG technique, a TAB technique, or a COF technique. Further, the output switching circuit 1251 may include the switch 1251 as a circuit of the source driver circuit 14 in the source driver circuit 14.
[0483]
When the changeover switch 1252 is connected to the R terminal, the output signal from the source driver circuit 14 is applied to the source signal line 18R. When the changeover switch 1252 is connected to the G terminal, an output signal from the source driver circuit 14 is applied to the source signal line 18G. When the changeover switch 1252 is connected to the B terminal, the output signal from the source driver circuit 14 is applied to the source signal line 18B.
[0484]
In the configuration of FIG. 126, when the changeover switch 1252 is connected to the R terminal, the G terminal and the B terminal of the changeover switch are open. Therefore, the current input to source signal lines 18G and 18B is 0A. Therefore, the pixels 16 connected to the source signal lines 18G and 18B perform black display.
[0485]
When the changeover switch 1252 is connected to the G terminal, the R terminal and the B terminal of the changeover switch are open. Therefore, the current input to source signal lines 18R and 18B is 0A. Therefore, the pixels 16 connected to the source signal lines 18R and 18B display black.
[0486]
In the configuration of FIG. 126, when the changeover switch 1252 is connected to the B terminal, the R terminal and the G terminal of the changeover switch are open. Therefore, the current input to source signal lines 18R and 18G is 0A. Therefore, the pixels 16 connected to the source signal lines 18R and 18G perform black display.
[0487]
Basically, when one frame is composed of three fields, R image data is sequentially written to the pixels 16 of the display screen 50 in the first field. In the second field, G image data is sequentially written to the pixels 16 on the display screen 50. In the third field, a B image is sequentially written to the pixels 16 on the display screen 50.
[0488]
As described above, for each field, R data → G data → B data → R data → G data → B data → R data →... The N-fold pulse driving by turning on / off the switching transistor 11d as shown in FIG. 1 has been described with reference to FIG. 5, FIG. 13, FIG. It goes without saying that these driving methods can be combined with the sequence driving. Of course, it goes without saying that other driving methods of the present invention can be combined with sequence driving.
[0489]
In the embodiment described above, when writing image data to the R pixel 16, black data is written to the G pixel and the B pixel. When writing image data to the G pixel 16, black data is written to the R and B pixels. When writing image data to the B pixel 16, black data is written to the R and G pixels. The present invention is not limited to this.
[0490]
For example, when writing image data to the R pixel 16, the image data of the G pixel and the B pixel may hold the image data rewritten in the previous field. By driving in this manner, the brightness of the screen 50 can be increased. When writing the image data to the G pixel 16, the image data of the R pixel and the B pixel hold the image data rewritten in the previous field. When writing image data to the B pixel 16, the image data of the G pixel and the R pixel hold the image data rewritten in the previous field.
[0490]
As described above, in order to hold the image data of the pixels other than the color pixel being rewritten, it is sufficient that the RGB signal can independently control the gate signal line 17a. For example, as shown in FIG. 125, the gate signal line 17aR is a signal line for controlling on / off of the transistors 11b and 11c of the R pixel. The gate signal line 17aG is a signal line for controlling on / off of the transistors 11b and 11c of the G pixel. The gate signal line 17aB is a signal line for controlling on / off of the transistors 11b and 11c of the B pixel. On the other hand, the gate signal line 17b is a signal line that commonly turns on and off the transistors 11d of the R, G, and B pixels.
[0492]
With the above configuration, when the source driver circuit 14 outputs R image data and the switch 1252 is switched to the R contact, an on-voltage is applied to the gate signal line 17aR, and the gate signal line aG and the gate signal line aG are connected. An off-state voltage can be applied to the signal line aB. Therefore, the R image data can be written into the R pixel 16, and the G pixel 16 and the B pixel 16 can retain the image data of the field previously.
[0493]
In the second field, when the source driver circuit 14 outputs G image data and the switch 1252 is switched to the G contact, an on-voltage is applied to the gate signal line 17aG, and the gate signal line aR and the gate signal line aB are connected to each other. Can be applied with an off-voltage. Therefore, the G image data can be written to the G pixel 16, and the R pixel 16 and the B pixel 16 can keep the image data of the previous field.
[0494]
In the third field, when the source driver circuit 14 outputs the image data of B and the switch 1252 is switched to the B contact, an on-voltage is applied to the gate signal line 17aB, and the gate signal line aR and the gate signal line aG are Can be applied with an off-voltage. Therefore, the image data of B can be written to the B pixel 16, and the R pixel 16 and the G pixel 16 can keep the image data of the previous field.
[0495]
In the embodiment of FIG. 125, a gate signal line 17a for turning on / off the transistor 11b of the pixel 16 is formed or arranged for each of RGB. However, the present invention is not limited to this. For example, as shown in FIG. 126, a configuration may be employed in which a common gate signal line 17a is formed or arranged in the RGB pixels 16.
[0496]
In the configuration of FIG. 125 and the like, it has been described that when the changeover switch 1252 selects the R source signal line, the G source signal line and the B source signal line are open. However, the open state is an electrically floating state, which is not preferable.
[0497]
FIG. 126 shows a configuration in which measures have been taken to eliminate this floating state. The terminal a of the switch 1252 of the output switching circuit 1251 is connected to the Vaa voltage (voltage for displaying black). The terminal b is connected to the output terminal of the source driver circuit 14. The switch 1252 is provided for each of RGB.
[0498]
In the state of FIG. 126, the switch 1252R is connected to the Vaa terminal. Therefore, the Vaa voltage (black voltage) is applied to the source signal line 18R.
The switch 1252G is connected to the Vaa terminal. Therefore, the Vaa voltage (black voltage) is applied to the source signal line 18G. The switch 1252B is connected to the output terminal of the source driver circuit 14. Therefore, the B video signal is applied to the source signal line 18B.
[0499]
The above state is a rewriting state of the B pixel, and a black display voltage is applied to the R pixel and the G pixel. By controlling the switch 1252 as described above, the image of the pixel 16 is rewritten. Note that the control of the gate signal line 17b and the like are the same as those of the previously described embodiment, and thus the description is omitted.
[0500]
In the above embodiment, the R pixel 16 is rewritten in the first field, the G pixel 16 is rewritten in the second field, and the B pixel 16 is rewritten in the third field. That is, the color of the pixel rewritten for each field changes. The present invention is not limited to this. The color of the pixel to be rewritten may be changed every one horizontal scanning period (1H). For example, the driving method is such that the R pixel is rewritten at 1H, the G pixel is rewritten at 2H, the B pixel is rewritten at 3H, and the R pixel is rewritten at 4H, and so on. Of course, the color of the pixel to be rewritten may be changed every two or more horizontal scanning periods, or the color of the pixel to be rewritten may be changed every ３ field.
[0501]
FIG. 127 shows an embodiment in which the color of the pixel to be rewritten is changed every 1H. In FIGS. 127 to 129, the pixels 16 indicated by diagonal lines indicate that the image data of the previous field is retained without rewriting the pixels, or that the pixels 16 are displayed in black. Of course, it may be repeatedly performed such as displaying a pixel in black or retaining data of the previous field.
[0502]
It is needless to say that in the driving methods shown in FIGS. 125 to 129, N-fold pulse driving and M-row simultaneous driving as shown in FIG. 13 may be performed. FIGS. 125 to 129 illustrate the writing state of the pixel 16. Although the lighting control of the EL element 15 is not described, it is needless to say that the embodiments described before or after can be combined. Needless to say, a configuration in which the dummy pixel row 271 is formed as described with reference to FIG. 27 and a driving method using the dummy pixel row may be combined.
[0503]
Also, one frame is not limited to being composed of three fields. The number of fields may be two or four or more. In the case where one frame is composed of two fields and three primary colors of RGB, an example in which R and G pixels are rewritten in the first field and B pixels are rewritten in the second field is exemplified. If one frame is composed of four fields and three primary colors of RGB, the R pixel is rewritten in the first field, the G pixel is rewritten in the second field, and the B pixel is rewritten in the third and fourth fields. An example is illustrated. In these sequences, white balance can be more efficiently obtained by considering the luminous efficiency of the RGB EL elements 15.
[0504]
In the above embodiment, the R pixel 16 is rewritten in the first field, the G pixel 16 is rewritten in the second field, and the B pixel 16 is rewritten in the third field. That is, the color of the pixel to be rewritten changes for each field.
[0505]
In the embodiment of FIG. 127, the R pixel is rewritten at 1H in the first field, the G pixel is rewritten at 2H, the B pixel is rewritten at 3H, the R pixel is rewritten at 4H, and so on. This is the driving method. Of course, the color of the pixel to be rewritten may be changed every two or more horizontal scanning periods, or the color of the pixel to be rewritten may be changed every ３ field.
[0506]
In the embodiment of FIG. 127, the R pixel is rewritten at 1H in the first field, the G pixel is rewritten at 2H, the B pixel is rewritten at 3H, and the R pixel is rewritten at 4H. The G pixel is rewritten at 1H in the second field, the B pixel is rewritten at 2H, the R pixel is rewritten at 3H, and the G pixel is rewritten at 4H. The B pixel is rewritten at 1H in the third field, the R pixel is rewritten at 2H, the G pixel is rewritten at 3H, and the B pixel is rewritten at 4H.
[0507]
As described above, the R, G, and B pixels can be rewritten arbitrarily or with a predetermined regularity in each field, thereby preventing R, G, and B color separation. Further, generation of flicker can be suppressed.
[0508]
In FIG. 128, the number of colors of the pixel 16 rewritten every 1H is plural. In FIG. 127, in the first field, the 1H-th rewritten pixel 16 is an R pixel, and the 2H-th rewritten pixel 16 is a G pixel. The 3H-th rewritten pixel 16 is a B pixel, and the 4H-th rewritten pixel 16 is an R pixel.
[0509]
In FIG. 128, the color position of the pixel to be rewritten is changed every 1H. The R, G, and B pixels can be different in each field (needless to say, they may have a predetermined regularity), and by sequentially rewriting, the R, G, and B color separation can be prevented. Further, generation of flicker can be suppressed.
[0510]
In the embodiment of FIG. 128 as well, in each picture element (a set of RGB pixels), the lighting time or the emission intensity of RGB is made to match. It goes without saying that this is carried out in the embodiments shown in FIGS. 126 and 127 as well. This is because the color becomes uneven.
[0511]
As shown in FIG. 128, the case where the number of colors of pixels to be rewritten every 1H (the three colors of R, G, and B are rewritten at the 1Hth in the first field of FIG. 128) is plural in FIG. , The source driver circuit 14 can output a video signal of any color (may have a certain regularity) to each output terminal, and the switch 1252 sets the contacts R, G, and B to arbitrary (a certain rule). May be connected).
[0512]
The display panel of the embodiment shown in FIG. 129 has W (white) pixels 16W in addition to the three primary colors of RGB. By forming or arranging the pixel 16W, the color peak luminance can be satisfactorily realized. Further, high-luminance display can be realized. FIG. 129 (a) shows an embodiment in which R, G, B and W pixels 16 are formed in one pixel row. FIG. 129 (b) shows a configuration in which RGBW pixels 16 are arranged for each pixel row.
[0513]
In the driving method of FIG. 129, it goes without saying that the driving methods of FIGS. 127 and 128 can be implemented. It goes without saying that N-fold pulse driving and M pixel row simultaneous driving can be implemented. These items can be easily embodied by those skilled in the art in the present specification, and thus description thereof is omitted.
[0514]
In addition, in order to facilitate the description of the present invention, the display panel of the present invention is described as having three primary colors of RGB, but the present invention is not limited to this. In addition to RGB, cyan, yellow, and magenta may be added, or a display panel using a single color of R, G, and B, or two colors of R, G, and B may be used.
[0515]
In the above-described sequence driving method, RGB is operated for each field, but it is needless to say that the present invention is not limited to this. The embodiment of FIGS. 125 to 129 describes a method of writing image data to the pixel 16. It does not describe (of course is related to) a method of operating the transistor 11d in FIG. 1 or the like to display an image by supplying a current to the EL element 15. In the pixel configuration of FIG. 1, the current flowing through the EL element 15 is controlled by controlling the transistor 11d.
[0516]
In the driving methods shown in FIGS. 127 and 128, the RGB images can be sequentially displayed by controlling the transistor 11d (in the case of FIG. 1). For example, in FIG. 130A, the R display area 53R, the G display area 53G, and the B display area 53B are scanned from the top to the bottom of the screen (or from the bottom to the top) during one frame (one field). . An area other than the RGB display area is a non-display area 52.
That is, intermittent driving is performed.
[0517]
FIG. 130B shows an embodiment in which a plurality of RGB display areas 53 are generated in one field (one frame) period. This driving method is similar to the driving method of FIG. Therefore, no explanation will be needed. By dividing the display area 53 into a plurality of parts as shown in FIG. 130 (b), the occurrence of flicker disappears even at a lower frame rate.
[0518]
FIG. 131A shows a case where the area of the display area 53 is made different in the RGB display area 53 (the area of the display area 53 is obviously proportional to the lighting period). In FIG. 131 (a), the R display area 53R and the G display area 53G have the same area. The area of the B display area 53B is larger than that of the G display area 53G. In an organic EL display panel, the luminous efficiency of B is often poor. By making the B display area 53B larger than the display areas 53 of other colors as shown in FIG. Will be able to do it.
[0519]
FIG. 131B shows an example in which one field (frame) period has a plurality of B display periods 53B (53B1, 53B2). FIG. 131A shows a method of changing one B display area 53B. The white balance can be adjusted well by changing the white balance. FIG. 131 (b) improves the white balance by displaying a plurality of B display areas 53B having the same area.
[0520]
The driving method of the present invention is not limited to either FIG. 131 (a) or FIG. 131 (b). The purpose of the present invention is to generate a display area 53 for R, G, and B, and to intermittently display the image, thereby taking measures against blurred moving images and improving insufficient writing to the pixel 16. In the driving method of FIG. 16, the display area 53 in which R, G, and B are independent does not occur. RGB are displayed at the same time (it should be expressed that the W display area 53 is displayed). It goes without saying that (a) of FIG. 131 and (b) of FIG. 131 may be combined. For example, a driving method for changing the RGB display area 53 in FIG. 131A and generating a plurality of RGB display areas 53 in FIG.
[0521]
130 to 131 are not limited to the driving methods of the present invention shown in FIGS. 125 to 129. As shown in FIG. 41, if the current flowing through the EL element 15 (EL element 15R, EL element 15G, and EL element 15B) can be controlled for each of RGB, the driving methods shown in FIGS. 130 and 131 can be easily implemented. Not sure. By applying an on / off voltage to the gate signal line 17bR, the R pixel 16R can be on / off controlled. By applying an on / off voltage to the gate signal line 17bG, the G pixel 16G can be on / off controlled. By applying an on / off voltage to the gate signal line 17bB, the B pixel 16B can be turned on / off.
[0522]
In order to realize the above driving, as shown in FIG. 132, the gate driver circuit 12bR for controlling the gate signal line 17bR, the gate driver circuit 12bG for controlling the gate signal line 17bG, and the gate signal line 17bB are controlled. The gate driver circuit 12bB may be formed or arranged. Driving the gate driver circuits 12bR, 12bG, and 12bB of FIG. 132 by the method described with reference to FIG. 6 and the like can realize the driving methods of FIGS. Needless to say, the driving method shown in FIG. 16 can be realized with the configuration of the display panel shown in FIG.
[0523]
In addition, in the configuration shown in FIGS. 125 to 128, if the method is to rewrite black image data to the pixels 16 other than the pixel 16 for rewriting image data, the gate signal line 17bR for controlling the EL element 15R and the EL element 15G are controlled. It is needless to say that even if the gate signal line 17bG and the gate signal line bB for controlling the EL element 15B are not separated, and the gate signal line 17b is common to the RGB pixels, the driving methods shown in FIGS. 130 and 131 can be realized. .
[0524]
In FIG. 15, FIG. 18, FIG. 21, etc., it is assumed that the gate signal line 17b (EL side selection signal line) applies an on voltage (Vgl) and an off voltage (Vgh) in units of one horizontal scanning period (1H). Did. However, the light emission amount of the EL element 15 is proportional to the flowing time when the flowing current is a constant current. Therefore, the flowing time does not need to be limited to 1H unit.
In order to introduce the concept of output enable (OEV), it is defined as follows. By performing the OEV control, it becomes possible to apply the on / off voltage (Vgl voltage, Vgh voltage) to the pixel 16 to the gate signal lines 17a and 17b within one horizontal scanning period (1H).
For ease of explanation, in the display panel of the present invention, the description will be made assuming that the gate signal line 17a (in the case of FIG. 1) selects a pixel row on which current programming is performed. The output of the gate driver circuit 12a that controls the gate signal line 17a is called a WR side selection signal line. The description will be made on the assumption that the gate signal line 17b selects the EL element 15 (in the case of FIG. 1). The output of the gate driver circuit 12b that controls the gate signal line 17b is called an EL-side selection signal line.
[0525]
The gate driver circuit 12 receives a start pulse and sequentially shifts the input start pulse in the shift register as held data. Whether the voltage output to the WR-side selection signal line is the on-voltage (Vgl) or the off-voltage (Vgh) is determined by the data held in the shift register of the gate driver circuit 12a. Further, an OEV1 circuit (not shown) for forcibly turning off the output is formed or arranged in the output stage of the gate driver circuit 12a. When the OEV1 circuit is at the L level, the WR side selection signal output from the gate driver circuit 12a is output to the gate signal line 17a as it is. If the above relationship is logically illustrated, the relationship shown in FIG. 224A is obtained (an OR circuit). Note that the ON voltage is a logic level L (0), and the OFF voltage is a logic voltage H (1).
[0526]
That is, when the gate driver circuit 12a outputs the off voltage, the off voltage is applied to the gate signal line 17a. When the gate driver circuit 12a outputs an on-voltage (L level in logic), the output of the OEV1 circuit is ORed by the OR circuit and output to the gate signal line 17a. That is, when the OEV1 circuit is at the H level, the voltage output to the gate driver signal line 17a is turned off (Vgh) (see the example of the timing chart in FIG. 176).
[0527]
The data held in the shift register of the gate driver circuit 12b determines whether the voltage output to the gate signal line 17b (EL-side selection signal line) is an on voltage (Vgl) or an off voltage (Vgh). Further, an OEV2 circuit (not shown) for forcibly turning off the output is formed or arranged in the output stage of the gate driver circuit 12b. When the OEV2 circuit is at the L level, the output of the gate driver circuit 12b is directly output to the gate signal line 17b. If the above relationship is logically illustrated, the relationship shown in FIG. Note that the ON voltage is a logic level L (0), and the OFF voltage is a logic voltage H (1).
[0528]
That is, when the gate driver circuit 12b outputs the off-voltage (the EL-side selection signal is the off-voltage), the off-voltage is applied to the gate signal line 17b. When the gate driver circuit 12b outputs an on-voltage (L level in logic), the output of the OEV2 circuit is ORed by the OR circuit and output to the gate signal line 17b. That is, when the input signal is at the H level, the OEV2 circuit sets the voltage output to the gate driver signal line 17b to the off voltage (Vgh). Therefore, even if the EL-side selection signal of the OEV2 circuit is in the on-voltage output state, the signal forcibly output to the gate signal line 17b becomes the off-voltage (Vgh). If the input of the OEV2 circuit is L, the EL-side selection signal is output to the gate signal line 17b in a through manner (see the example of the timing chart in FIG. 176).
[0529]
The screen brightness is adjusted by the control of OEV2. There is an allowable range of brightness that can be changed depending on the screen brightness. FIG. 175 illustrates the relationship between the allowable change (%) and the screen luminance (nt). As can be seen from FIG. 175, the permissible change amount is small for a relatively dark image. Therefore, the brightness adjustment of the screen 50 by the control by the OEV 2 or the duty ratio control is controlled in consideration of the brightness of the screen 50. The permissible change by the control shortens when the screen is darker than when it is bright.
[0530]
FIG. 140 shows １ ／ duty ratio drive. During the 1H period during the 4H period, the ON voltage is applied to the gate signal line 17b (EL side selection signal line), and the position where the ON voltage is applied is scanned in synchronization with the horizontal synchronization signal (HD). Therefore, the ON time is 1H unit.
[0531]
However, the present invention is not limited to this, and may be less than 1H (１ ／ H in FIG. 143) as shown in FIG. 143, or may be 1H or less. In other words, the present invention is not limited to the 1H unit, and generation other than the 1H unit is easy.
An OEV2 circuit formed or arranged at the output stage of the gate driver circuit 12b (which controls the gate signal line 17b) may be used. The OEV2 circuit is the same as the OEV1 circuit described above, and thus the description is omitted.
[0532]
In FIG. 141, the ON time of the gate signal line 17b (EL-side selection signal line) is not in units of 1H. The on-voltage is applied to the gate signal line 17b (EL-side selection signal line) of the odd-numbered pixel row for a little less than 1H. The on-voltage is applied to the gate signal line 17b (EL-side selection signal line) of the even-numbered pixel row for a very short period. Also, the on-voltage time T1 applied to the gate signal line 17b (EL-side selection signal line) of the odd-numbered pixel row and the on-voltage time T2 applied to the gate signal line 17b (EL-side selection signal line) of the even-numbered pixel row are determined. The added time is set to be 1H period. FIG. 141 is the state of the first field.
[0533]
In the second field subsequent to the first field, the on-voltage is applied to the gate signal line 17b (EL-side selection signal line) of the even-numbered pixel row for a little less than 1H. The on-voltage is applied to the gate signal line 17b (EL-side selection signal line) of the odd-numbered pixel row for an extremely short period. Further, the on-voltage time T1 applied to the gate signal line 17b (EL-side selection signal line) of the even-numbered pixel row and the on-voltage time T2 applied to the gate signal line 17b (EL-side selection signal line) of the odd-numbered pixel row are determined. The added time is set to be 1H period.
[0534]
As described above, the sum of the ON times applied to the gate signal lines 17b (EL-side selection signal lines) in a plurality of pixel rows is made constant, and the lighting time of the EL elements 15 in each pixel row in a plurality of fields is set. May be constant.
[0535]
In FIG. 142, the ON time of the gate signal line 17b (EL-side selection signal line) is 1.5H. Further, the rise and fall of the gate signal line 17b (EL-side selection signal line) at point A overlap. The gate signal line 17b (EL side select signal line) and the source signal line 18 are coupled. Therefore, when the waveform of the gate signal line 17 b (EL side selection signal line) changes, the change in the waveform penetrates the source signal line 18. If a potential change occurs in the source signal line 18 due to the penetration, the accuracy of the current (voltage) program is reduced, and the characteristic unevenness of the driving transistor 11a is displayed.
[0536]
In FIG. 142, at point A, the gate signal line 17B (EL-side selection signal line) (1) changes from an ON voltage (Vgl) applied state to an OFF voltage (Vgh) applied state. The gate signal line 17B (EL side selection signal line) (2) changes from the off voltage (Vgh) applied state to the on voltage (Vgl) applied state. Therefore, at point A, the signal waveform of gate signal line 17B (EL-side selection signal line) (1) and the signal waveform of gate signal line 17B (EL-side selection signal line) (2) cancel each other. Therefore, even if the source signal line 18 and the gate signal line 17B (EL side selection signal line) are coupled, the waveform change of the gate signal line 17B (EL side selection signal line) does not penetrate into the source signal line 18. Absent. Therefore, good current (voltage) program accuracy can be obtained, and uniform image display can be realized.
[0537]
FIG. 142 shows an example in which the ON time is 1.5H. However, the present invention is not limited to this. Needless to say, as shown in FIG. 144, the application time of the on-voltage may be 1H or less.
[0538]
By adjusting the period during which the ON voltage is applied to the gate signal line 17B (EL-side selection signal line), the luminance of the display screen 50 can be linearly adjusted. This can be easily realized by controlling the OEV2 circuit. For example, in FIG. 145, the display luminance is lower in FIG. 145 (b) than in FIG. 145 (a). The display luminance of FIG. 145 (c) is lower than that of FIG. 145 (b).
[0539]
FIG. 109 illustrates the relationship between OEV2 and the signal waveform of the gate signal line 17b. In FIG. 109, the period in which OEV2 is at the L level is the shortest in FIG. Therefore, the period during which the ON voltage is applied to the gate signal line 17b is short, and the current period flowing through the EL element 15 is short. This state is a state in which the duty ratio is small as a result. In FIG. 109 (b), the period during which the OEV2 goes low next is long. Further, in FIG. 109 (c), the period during which OEV2 is at the L level is longer than in FIG. 109 (b). Therefore, the duty ratio in FIG. 109 (c) is larger than the duty ratio in FIG. 109 (b).
[0540]
In the embodiment of FIGS. 109 (a), (b) and (c), the duty ratio control is performed in a period shorter than 1H. However, the present invention is not limited to this, and the duty ratio control may be performed in 1H units as illustrated in FIG. 109 (d). FIG. 109D shows an example in which the duty ratio is 1/2.
In FIG. 109A, the period when OEV2 is at the L level is shortest. Therefore, the period during which the ON voltage is applied to the gate signal line 17b is short, and the current period flowing through the EL element 15 is short. This state is a state in which the duty ratio is small as a result. In FIG. 109A, the period when OEV2 is at the L level is shortest. Therefore, the period during which the ON voltage is applied to the gate signal line 17b is short, and the current period flowing through the EL element 15 is short. This state is a state in which the duty ratio is small as a result.
Further, as illustrated in FIG. 146, a set of a period in which an ON voltage is applied and a period in which an OFF voltage is applied in a 1H period may be provided a plurality of times. FIG. 146 (a) shows an embodiment provided six times. FIG. 146 (b) is an embodiment provided three times. FIG. 146 (c) is an embodiment provided once. In FIG. 146, the display luminance is lower in FIG. 146 (b) than in FIG. 146 (a). Further, the display luminance of FIG. 146 (c) is lower than that of FIG. 146 (b). Therefore, the display luminance can be easily adjusted (controlled) by controlling the number of ON periods.
[0541]
Hereinafter, the current driver type source driver IC (circuit) 14 of the present invention will be described. The source driver IC of the present invention is used to realize the above-described driving method and driving circuit of the present invention. Further, the driving method, the driving circuit, and the display device of the present invention are used in combination. The description will be made as an IC chip, but the present invention is not limited to this. Needless to say, the IC chip may be formed on the substrate 71 of the display panel using a low-temperature polysilicon technology, an amorphous silicon technology, or the like.
[0542]
First, FIG. 55 shows an example of a conventional driver circuit of a current drive system. However, FIG. 55 is a principle for explaining the current-driven source driver IC (source driver circuit) 14 of the present invention.
[0543]
In FIG. 55, reference numeral 551 denotes a D / A converter. An n-bit data signal is input to the D / A converter 551, and an analog signal is output from the D / A converter based on the input data. This analog signal is input to the operational amplifier 552. The operational amplifier 552 is input to the N-channel transistor 471a, and the current flowing through the transistor 471a flows through the resistor 531. The terminal voltage of the resistor R becomes the negative input of the operational amplifier 552, and the voltage of this negative terminal and the positive terminal of the operational amplifier 552 become the same voltage. Therefore, the output voltage of the D / A converter 551 becomes the terminal voltage of the resistor 531.
[0544]
If the resistance value of the resistor 531 is 1 MΩ and the output of the D / A converter 551 is 1 (V), a current of 1 (V) / 1 MΩ = 1 (μA) flows through the resistor 531. This is a constant current circuit. Therefore, the analog output of the D / A converter 551 changes according to the value of the data signal, and a predetermined current flows through the analog output to the resistor 531 based on the value, and becomes the program current Iw.
[0545]
However, the circuit scale of the DA conversion circuit 551 is large. Further, the circuit scale of the operational amplifier 552 is large. If the DA conversion circuit 551 and the operational amplifier 552 are formed in one output circuit, the size of the source driver IC 14 becomes huge. Therefore, it cannot be practically manufactured.
[0546]
The present invention has been made in view of such a point. The source driver circuit 14 of the present invention has a circuit configuration and a layout configuration for reducing the size of the current output circuit and minimizing the output current variation between the current output terminals as much as possible.
[0547]
FIG. 47 shows a configuration diagram of a current driver type source driver IC (circuit) 14 according to an embodiment of the present invention. FIG. 47 shows a multi-stage current mirror circuit in a case where the current source has a three-stage configuration (471, 472, 473) as an example.
[0548]
In FIG. 47, the current value of the first-stage current source 471 is copied to N (where N is an arbitrary integer) second-stage current sources 472 by the current mirror circuit. Further, the current value of the second-stage current source 472 is copied to M (where M is an arbitrary integer) third-stage current sources 473 by the current mirror circuit. With this configuration, as a result, the current value of the first-stage current source 471 is copied to N × M third-stage current sources 473.
[0549]
For example, when one source driver IC 14 drives the source signal line 18 of the display panel of the QCIF format, the output is 176 (since the source signal line needs 176 outputs for each RGB). In this case, N is set to 16 and M = 11. Therefore, 16 × 11 = 176, which can correspond to 176 outputs. By setting one of N and M to 8 or 16 or a multiple thereof, the layout design of the current source of the driver IC becomes easy.
[0550]
In the current driver type source driver IC (circuit) 14 using the multi-stage current mirror circuit of the present invention, as described above, the current value of the first-stage current source 471 is directly supplied to the N × M third-stage current sources 473. Since the second-stage current source 472 is provided in the middle instead of being copied by the current mirror circuit, it is possible to absorb variations in transistor characteristics there.
[0551]
In particular, the present invention is characterized in that the first stage current mirror circuit (current source 471) and the second stage current mirror circuit (current source 472) are arranged closely. In the case of the first-stage current source 471 to the third-stage current source 473 (that is, a two-stage configuration of the current mirror circuit), the number of the second-stage current sources 473 connected to the first-stage current source is In many cases, the first-stage current source 471 and the third-stage current source 473 cannot be arranged closely.
[0552]
Like the source driver circuit 14 of the present invention, the current of the first-stage current mirror circuit (current source 471) is copied to the second-stage current mirror circuit (current source 472), and the second-stage current mirror circuit (current source 472) is copied. In this configuration, the current of the current source 472 is copied to the current mirror circuit (current source 472) in the third stage. In this configuration, the number of second-stage current mirror circuits (current sources 472) connected to the first-stage current mirror circuits (current sources 471) is small. Therefore, the first-stage current mirror circuit (current source 471) and the second-stage current mirror circuit (current source 472) can be arranged closely.
[0553]
If transistors forming the current mirror circuit can be arranged closely, naturally, the variation of the transistors is reduced, and the variation of the copied current value is also reduced. Also, the number of the third-stage current mirror circuits (current sources 473) connected to the second-stage current mirror circuits (current sources 472) is reduced.
Therefore, the second-stage current mirror circuit (current source 472) and the third-stage current mirror circuit (current source 473) can be arranged closely.
[0554]
That is, as a whole, the transistors in the current receiving units of the first-stage current mirror circuit (current source 471), the second-stage current mirror circuit (current source 472), and the third-stage current mirror circuit (current source 473) are used. Can be placed closely. Therefore, since the transistors constituting the current mirror circuit can be arranged closely, variations in the transistors are reduced, and variations in the current signal from the output terminal are extremely reduced (high accuracy).
[0555]
In the present invention, it is expressed as a current source 471, 472, 473 or as a current mirror circuit. These are used synonymously. In other words, the current source is a basic configuration concept of the present invention, and when the current source is specifically configured, it becomes a current mirror circuit. Therefore, the current source is not limited to the current mirror circuit alone, but may be a constant current circuit including a combination of the operational amplifier 552, the transistor 471, and the resistor R.
[0556]
FIG. 48 is a more specific structure diagram of the source driver IC (circuit) 14. FIG. 48 illustrates a portion of the third current source 473. That is, the output unit is connected to one source signal line 18. The last stage current mirror configuration is composed of a plurality of current mirror circuits of the same size (unit transistor 484 (one unit)), and the number is weighted in correspondence with the bits of the image data.
[0557]
The transistors constituting the source driver IC (circuit) 14 of the present invention are not limited to the MOS type, but may be of the bipolar type. The invention is not limited to a silicon semiconductor, but may be a gallium arsenide semiconductor. Further, a germanium semiconductor may be used. Alternatively, the substrate may be directly formed by a polysilicon technology such as low-temperature polysilicon or an amorphous silicon technology.
[0558]
As is apparent from FIG. 48, a case of a 6-bit digital input is shown as one embodiment of the present invention. That is, since it is 2 to the sixth power, 64 gradation display is performed. By mounting the source driver IC 14 on the array substrate, 64 (64 × 64 × 64) = about 260,000 colors can be displayed because red (R), green (G), and blue (B) have 64 gradations each. Become.
[0559]
In the case of 64 gradations, one D0 bit unit transistor 484, two D1 bit unit transistors 484, four D2 bit unit transistors 484, eight D3 bit unit transistors 484, and eight D4 bit unit transistors 484 are provided. Since there are 16 unit transistors 484 and 32 D5-bit unit transistors 484, there are 63 total unit transistors 484. That is, the present invention configures (forms) one unit transistor 484 with one output, which is the number of expressed gradations (64 gradations in this embodiment). Note that, even when one unit transistor is divided into a plurality of sub-unit transistors, the unit transistor is simply divided into sub-unit transistors. Therefore, there is no difference in the fact that the present invention is configured by the number of unit transistors represented by the number of gradations-1 (synonymous).
[0560]
In FIG. 48, D0 indicates an LSB input, and D5 indicates an MSB input. When the D0 input terminal is at the H level (at the time of positive logic), the switch 481a is an on / off means. Needless to say, it may be constituted by a single transistor, or may be an analog switch combining a P-channel transistor and an N-channel transistor. ) Turns on. Then, a current flows toward a current source (one unit) 484 constituting the current mirror. This current flows through the internal wiring 483 in the source driver IC 14. Since the internal wiring 483 is connected to the source signal line 18 via the terminal electrode of the source driver IC 14, the current flowing through the internal wiring 483 becomes the program current of the pixel 16.
[0561]
For example, when the D1 input terminal is at the H level (at the time of positive logic), the switch 481b is turned on. Then, current flows toward two current sources (one unit) 484 constituting the current mirror. This current flows through the internal wiring 483 in the source driver IC 14. Since the internal wiring 483 is connected to the source signal line 18 via the terminal electrode of the source driver IC 14, the current flowing through the internal wiring 483 becomes the program current of the pixel 16.
[0562]
The same applies to the other switches 481. When the D2 input terminal is at the H level (at the time of positive logic), the switch 481c is turned on. Then, current flows toward four current sources (one unit) 484 constituting the current mirror. When the D5 input terminal is at the H level (at the time of positive logic), the switch 481f is turned on. Then, a current flows toward 32 current sources (one unit) 484 constituting the current mirror.
[0563]
As described above, according to external data (D0 to D5), a current flows toward the corresponding current source (one unit). Therefore, according to the data, the current flows from 0 to 63 current sources (1 unit).
[0564]
Although the present invention employs 63 6-bit current sources for ease of explanation, the present invention is not limited to this. In the case of 8 bits, 255 unit transistors 484 may be formed (arranged). In the case of 4 bits, 15 unit transistors 484 may be formed (arranged). The transistors 484 constituting the unit current source have the same channel width W and channel width L. By using the same transistor as described above, an output stage with less variation can be configured.
[0565]
Further, all the unit transistors 484 are not limited to flowing the same current. For example, each unit transistor 484 may be weighted. For example, a current output circuit may be formed by mixing one unit transistor 484, a double unit transistor 484, a quadruple unit transistor 484, and the like. However, when the unit transistors 484 are configured by weighting, the weighted current sources do not have the weighted ratios, which may cause variations. Therefore, even when weighting is performed, it is preferable that each current source be configured by forming a plurality of transistors serving as one unit of current source.
[0566]
The size of the transistor forming the unit transistor 484 needs to be a certain size or more. The smaller the transistor size, the greater the variation in output current. The size of the transistor 484 is a size obtained by multiplying the channel length L by the channel width W. For example, if W = 3 μm and L = 4 μm, the size of the transistor 484 forming one unit current source is W × L = 12 square μm. It is considered that the variation increases as the transistor size decreases, because the state of the crystal interface of the silicon wafer has an influence. Therefore, when one transistor is formed over a plurality of crystal interfaces, the output current variation of the transistors is reduced.
[0567]
FIG. 119 shows the relationship between the transistor size and the variation in the output current. The horizontal axis of the graph in FIG. 119 is the transistor size (square μm). The vertical axis shows the variation of the output current in%. However, the variation% of the output current can be calculated by forming a unit current source (one unit transistor) 484 in 63 sets (forming 63 units), forming a large number of sets on a wafer, and reducing the variation in output current. It is what I sought. Therefore, the horizontal axis of the graph is shown by the transistor size (the size of the unit transistor 484) constituting one unit current source, but the area is 63 times since there are actually 63 parallel transistors. However, FIG. 119 considers the size of the unit transistor 484 as a unit. Therefore, in FIG. 119, when 63 unit transistors 484 each having 30 μm square are formed, the variation of the output current at that time is 0.5%.
[0568]
In the case of 64 gradations, 100/64 = 1.5%. Therefore, the output current variation needs to be within 1.5%. In order to make it 1.5% or less from FIG. 119, the size of the unit transistor needs to be 2 μm or more (63 unit transistors of 2 μm operate for 64 gradations). On the other hand, there is a limit on the transistor size. This is because the IC chip size becomes large and the width per output is limited. From this point, the upper limit of the size of the unit transistor 484 is 300 μm. Therefore, in the 64-gradation display, the size of the unit transistor 484 needs to be not less than 2 μm and not more than 300 μm.
[0569]
In the case of 128 gradations, 100/128 = 1%. Therefore, the output current variation must be within 1%. In order to make it 1% or less from FIG. 119, the size of the unit transistor needs to be 8 square μm or more. Therefore, in the case of 128 gradation display, the size of the unit transistor 484 needs to be set to be 8 μm or more and 300 μm or less.
[0570]
Generally, when the number of gradations is K and the size of the unit transistor 484 is St (square μm),
The relationship of 40 ≦ K / √ (St) and St ≦ 300 is satisfied.
More preferably, it is preferable to satisfy the relationship of 120 ≦ K / √ (St) and St ≦ 300.
[0571]
The above example is a case where 63 transistors are formed with 64 gradations. When 64 gradations are formed by 127 unit transistors 484, the size of the unit transistor 484 is a size obtained by adding two unit transistors 484. For example, if the size of the unit transistor 484 is 10 μm square and the number of the unit transistors is 127 in 64 gradations, it is necessary to see the column of 10 × 2 = 20 in FIG. 119 for the size of the unit transistor. Similarly, if the unit transistor 484 is 10 square μm in 64 gradations and 255 units are formed, it is necessary to look at the column of 10 × 4 = 40 in FIG. 119 for the unit transistor size.
[0572]
It is necessary to consider not only the size but also the shape of the unit transistor 484. This is to reduce the effect of kink. Kink is a phenomenon in which the current flowing through the unit transistor 484 changes when the source (S) -drain (D) voltage of the unit transistor 484 changes while the gate voltage of the unit transistor 484 is kept constant. To tell. In the case where there is no kink effect (ideal state), the current flowing through the unit transistor 484 does not change even if the voltage applied between the source (S) and the drain (D) is changed.
[0573]
The effect of the kink occurs when the source signal lines 18 are different due to the variation in Vt of the driving transistor 11a shown in FIG. The source driver circuit 14 supplies a program current to the source signal line 18 so that the program current flows to the driving transistor 11a of the pixel. This program current changes the gate terminal voltage of the driving transistor 11a, so that the program current flows through the driving transistor 11a. As can be seen from FIG. 3, when the selected pixel 16 is in the programmed state, the gate terminal voltage of the driving transistor 11a = the potential of the source signal line 18.
[0574]
Therefore, the potential of the source signal line 18 varies depending on the Vt variation of the driving transistor 11a of each pixel 16. The potential of the source signal line 18 becomes the source-drain voltage of the unit transistor 484 of the source driver circuit 14. That is, the source-drain voltage applied to the unit transistor 484 differs due to the Vt variation of the driving transistor 11a of the pixel 16, and the unit transistor 484 generates a variation in output current due to kink due to the source-drain voltage.
[0575]
FIG. 123 is a graph of a deviation (variation) from the unit transistor L / W and a target value. When the L / W ratio of the unit transistor is 2 or less, the deviation from the target value is large (the slope of the straight line is large). However, as L / W increases, the deviation of the target value tends to decrease. When the unit transistor L / W is 2 or more, the change in deviation from the target value is small. The deviation (variation) from the target value is L / W = 2 or more and 0.5% or less. Therefore, the accuracy of the transistor can be adopted in the source driver circuit 14. Note that L is the channel length of the unit transistor 484, and W is the channel width of the unit transistor.
[0576]
However, the channel length L of the unit transistor 484 cannot be increased arbitrarily. This is because the longer L is, the larger the source driver IC 14 becomes. Further, the gate terminal voltage of the unit transistor 484 increases, and the power supply voltage required for the source driver IC 14 increases. When the power supply voltage increases, it is necessary to employ an IC process with a high breakdown voltage. The source driver IC 14 formed by the high withstand voltage IC process has a large output variation of the unit transistor 484 (see FIG. 121 and its description). According to the result of the study, L / W is preferably set to 100 or less. More preferably, L / W is preferably 50 or less.
[0577]
From the above, it is preferable that the unit transistor L / W be two or more. Further, L / W is preferably set to 100 or less. More preferably, L / W is preferably 40 or less.
[0578]
Further, the magnitude of L / W also depends on the number of gradations. When the number of gradations is small, the difference between the gradations is large, so that there is no problem even if the output current of the unit transistor 484 varies due to the effect of kink. However, in a display panel having a large number of gradations, the difference between the gradations is small. Therefore, if the output current of the unit transistor 484 varies even slightly due to the effect of kink, the number of gradations is reduced.
[0579]
In consideration of the above, in the source driver circuit 14 of the present invention, the number of gradations is K, and the L / W of the unit transistor 484 (L is the channel length of the unit transistor 484, and W is the channel width of the unit transistor). Time,
(√ (K / 16)) ≦ L / W ≦ and (√ (K / 16)) × 20
Is formed (formed) so as to satisfy the relationship (1). FIG. 120 illustrates this relationship. The upper side of the straight line in FIG. 120 is the working range of the present invention.
[0580]
The variation of the output current of the unit transistor 484 also depends on the withstand voltage of the source driver IC14. The withstand voltage of the source driver IC generally means the power supply voltage of the IC. For example, with a 5 (V) withstand voltage, a power supply voltage is used at a standard voltage of 5 (V). Note that the IC withstand voltage may be read as the maximum operating voltage. These withstand voltages are standardized and held by semiconductor IC manufacturers as 5 (V) withstand voltage process and 10 (V) withstand voltage process.
[0581]
It is considered that the IC breakdown voltage affects the output variation of the unit transistor 484 due to the film quality and thickness of the gate insulating film of the transistor 484. The transistor 484 manufactured by a process with a high IC breakdown voltage has a thick gate insulating film. This is to prevent dielectric breakdown from occurring even when a high voltage is applied. When the insulating film is thick, it becomes difficult to control the thickness of the gate insulating film, and the quality of the gate insulating film varies greatly. Therefore, variation in transistors is increased. In addition, a transistor manufactured by a high breakdown voltage process has low mobility. When the mobility is low, the characteristics are different only by slightly changing the electrons injected into the gate of the transistor. Therefore, variations in the transistors are increased. Therefore, in order to reduce the variation of the unit transistors 484, it is preferable to employ an IC process having a low IC withstand voltage.
[0582]
FIG. 121 illustrates the relationship between the IC breakdown voltage and the output variation of the unit transistor 484. The variation ratio on the vertical axis indicates that the variation of the unit transistor 484 is 1 manufactured by a 1.8 (V) withstand voltage process. FIG. 121 shows the output variation of the unit transistor 484 manufactured by each withstand voltage process, with the shape L / W of the unit transistor 484 set to 12 (μm) / 6 (μm). In addition, a plurality of unit transistors are formed in each IC withstand voltage process, and variations in output current are determined. However, the breakdown voltage process is 1.8 (V) breakdown voltage, 2.5 (V) breakdown voltage, 3.3 (V) breakdown voltage, 5 (V) breakdown voltage, 8 (V) breakdown voltage, 10 (V) breakdown voltage, 15 (V) breakdown voltage. V) It is a discrete value such as a withstand voltage. However, for ease of explanation, the variation of transistors formed at each breakdown voltage is plotted on a graph and connected by a straight line.
[0583]
As can be seen from FIG. 121, up to an IC withstand voltage of about 9 (V), the increase ratio of the variation ratio (the output current variation of the unit transistor 484) to the IC process is small. However, when the IC breakdown voltage is 10 (V) or more, the gradient of the variation ratio with respect to the IC breakdown voltage increases.
[0584]
The variation ratio within 3 in FIG. 121 is the variation allowable range in the 64-gradation to 256-gradation display. However, this variation ratio differs depending on the area and L / W of the unit transistor 484. However, even if the shape and the like of the unit transistor 484 are changed, there is almost no change in the variation ratio of the variation ratio with respect to the IC breakdown voltage.
When the IC breakdown voltage is 9 to 10 (V) or more, the variation ratio tends to increase.
[0585]
On the other hand, the potential of the output terminal 681 in FIG. 48 changes according to the program current of the driving transistor 11a of the pixel 16. Almost equal to the gate terminal voltage of the driving transistor 11a and the potential of the source signal line 18. Further, the potential of the source signal line 18 becomes the potential of the output terminal 681 of the source driver IC (circuit) 14. The gate terminal potential Vw when the driving transistor 11a of the pixel 16 supplies a current of white raster (maximum white display) is set. The gate terminal potential Vb when the driving transistor 11a of the pixel 16 flows a current of black raster (complete black display). The absolute value of Vw-Vb needs to be 2 (V) or more. When the voltage Vw is applied to the terminal 681, the voltage between channels of the unit transistor 484 needs to be 0.5 (V).
[0586]
Therefore, the output terminal 681 (the terminal 681 is connected to the source signal line 18 and the gate terminal voltage of the driving transistor 11a of the pixel 16 is applied at the time of current programming) from 0.5 (V) to ((Vw −Vb) +0.5) (V). Since Vw-Vb is 2 (V), a maximum of 2 (V) +0.5 (V) = 2.5 (V) is applied to the terminal 681. Therefore, even if the output voltage (current) of the source driver IC 14 is a rail-to-rail circuit configuration (a circuit configuration capable of outputting a voltage up to the IC power supply potential), the IC withstand voltage needs to be 2.5 (V). . The required amplitude range of the terminal 741 needs to be 2.5 (V) or more.
[0587]
From the above, it is preferable to use a process in which the withstand voltage of the source driver IC 14 is 2.5 (V) or more and 10 (V) or less. More preferably, the withstand voltage of the source driver IC 14 preferably uses a process of 3 (V) or more and 9 (V) or less.
[0588]
In the above description, the withstand voltage process of the source driver IC 12 uses a process of 2.5 (V) or more and 10 (V) or less. However, this withstand voltage is also applied to the embodiment in which the source driver circuit 14 is formed directly on the substrate 71 (such as a low-temperature polysilicon process). The withstand voltage of the source driver circuit 14 formed on the substrate 71 may be as high as 15 (V) or more. In this case, the power supply voltage used for the source driver circuit 14 may be replaced with the IC breakdown voltage shown in FIG. Further, even in the case of the source driver IC 14, the power supply voltage to be used may be replaced without using the IC withstand voltage.
[0589]
The area of the unit transistor 484 has a correlation with the variation of the output current. FIG. 122 is a graph when the area of the unit transistor 484 is fixed and the transistor width W of the unit transistor 484 is changed. In FIG. 121, the variation of the channel width W = 2 (μm) of the unit transistor 484 is set to 1. The vertical axis of the graph is a relative ratio when the variation of the channel width W = 2 (μm) is set to 1.
[0590]
As shown in FIG. 122, the variation ratio gradually increases from 2 (μm) to 9 to 10 (μm) from the unit transistor W, and the variation ratio tends to increase more than 10 (μm). In addition, the variation ratio tends to increase when the channel width W is 2 (μm) or less.
[0591]
The variation ratio within 3 in FIG. 122 is an allowable variation range in the 64-gradation to 256-gradation display. However, the variation ratio differs depending on the area of the unit transistor 484. However, even if the area of the unit transistor 484 is changed, there is almost no change in the variation ratio of the variation ratio with respect to the IC breakdown voltage.
[0592]
From the above, it is preferable that the channel width W of the unit transistor 484 be greater than or equal to 2 (μm) and less than or equal to 10 (μm). More preferably, the channel width W of the unit transistor 484 is preferably 2 (μm) or more and 9 (μm) or less. However, when the number of gradations is 64, even if the channel width W is 2 (μm) or more and 15 (μm) or less, there is no practical problem.
[0593]
As shown in FIG. 52, the current flowing through the second-stage transistor 472b is copied to the transistor 473a constituting the third-stage current mirror circuit, and when the current mirror magnification is 1, the current flows into the transistor 473b. Flows to This current is copied to the last unit transistor 484.
[0594]
Since the portion corresponding to D0 is constituted by one unit transistor 484, it is the current value flowing through the unit transistor 473 of the last stage current source. Since the portion corresponding to D1 is composed of two unit transistors 484, the current value is twice the current value of the final stage current source. Since D2 is composed of four unit transistors 484, the current value is four times that of the last stage current source. Since the portion corresponding to D5 is composed of 32 transistors, The current value is 32 times the current value of the stage current source. However, this is a case where the mirror ratio of the last-stage current mirror circuit is 1.
[0595]
The program current Iw is output to the source signal line via the switch controlled by the 6-bit image data D0, D1, D2,..., D5 (the current is drawn). Therefore, according to the ON / OFF of the 6-bit image data D0, D1, D2,..., D5, the output line is connected to the first, second, fourth,. The current of 32 times is added and output. That is, a current value of 0 to 63 times that of the final stage current source 473 is output from the output line by the 6-bit image data D0, D1, D2,..., D5 (the current is drawn from the source signal line 18).
[0596]
Actually, as shown in FIGS. 76, 77, 78, and 118, the reference currents (IaR, IaG, IaB) for each of R, G, and B are stored in the source driver IC 14 by the resistors 491 (491R). , 491G, 491B). By adjusting the reference current Ia, the white balance can be easily adjusted.
In order to realize full color display on the EL display panel, it is necessary to form (create) a reference current for each of RGB. The white balance can be adjusted by the ratio of the RGB reference currents. In the case of the current driving method, the present invention determines the value of the current flowing through the unit transistor 484 from one reference current. Therefore, if the magnitude of the reference current is determined, the current flowing through the unit transistor 484 can be determined. Therefore, if the respective reference currents of R, G, and B are set, white balance can be obtained for all gradations. The above is an effect exerted because the source driver circuit 14 outputs a current step (current drive). Therefore, the point is how the magnitude of the reference current can be set for each of RGB.
The luminous efficiency of an EL element is determined by the thickness of the EL material deposited or applied. Or it is the dominant factor. The film thickness is almost constant for each lot. Therefore, if the formed film thickness of the EL element 15 is managed in lots, the relationship between the current flowing through the EL element 15 and the light emission luminance is determined. That is, the current value for obtaining the white balance is fixed for each lot.
[0597]
FIG. 49 shows an example of a circuit diagram of 176 outputs (N × M = 176) by a three-stage current mirror circuit. In FIG. 49, the current source 471 of the first-stage current mirror circuit is referred to as a parent current source, the current source 472 of the second-stage current mirror circuit is referred to as a child current source, and the current source 473 of the third-stage current mirror circuit is referred to as a grandchild current source. ing. With the configuration of an integral multiple of the current source by the third-stage current mirror circuit, which is the last-stage current mirror circuit, variation in 176 output is suppressed as much as possible, and highly accurate current output is possible.
[0598]
Note that the dense arrangement means that the first current source 471 and the second current source 472 are arranged at a distance of at least 8 mm (current or voltage output side and current or voltage input side). . Furthermore, it is preferable to arrange within 5 mm. This is because, within this range, the characteristics (Vt, mobility (μ)) of the transistor are hardly different due to the arrangement in the silicon chip according to the study. Similarly, the second current source 472 and the third current source 473 (current output side and current input side) are arranged at a distance of at least 8 mm or less. More preferably, it is preferable to arrange at a position within 5 mm. Needless to say, the above items are also applied to other embodiments of the present invention.
[0599]
The current or voltage output side and the current or voltage input side mean the following relationship. In the case of the voltage transfer in FIG. 50, the transistor 471 (output side) of the (I) -th current source and the transistor 472a (input side) of the (I + 1) -th current source are densely arranged. In the case of the current transfer shown in FIG. 51, the (I) -th stage current source transistor 471a (output side) and the (I + 1) -th current source transistor 472b (input side) are closely arranged.
[0600]
Although the number of the transistor 471 is one in FIGS. 49 and 50, the number of the transistor 471 is not limited to this. For example, a plurality of small sub-transistors 471 may be formed, and the source or drain terminals of the plurality of sub-transistors may be connected to the resistor 491 to form the unit transistor 484. By connecting a plurality of small sub-transistors in parallel, variations in the unit transistors 484 can be reduced.
[0601]
Similarly, the number of the transistor 472a is one, but it is not limited to this. For example, a plurality of small transistors 472a may be formed, and a plurality of gate terminals of the transistor 472a may be connected to a gate terminal of the transistor 471. By connecting a plurality of small transistors 472a in parallel, variation in the transistors 472a can be reduced.
[0602]
Therefore, as a configuration of the present invention, a configuration in which one transistor 471 and a plurality of transistors 472a are connected, a configuration in which a plurality of transistors 471 and one transistor 472a are connected, a configuration in which a plurality of transistors 471 and a plurality Of the transistor 472a. The above embodiment will be described later in detail.
[0603]
The above is also applied to the configuration of the transistor 473a and the transistor 473b in FIG. A structure in which one transistor 473a is connected to a plurality of transistors 473ba, a structure in which a plurality of transistors 473a are connected to a single transistor 473b, and a structure in which a plurality of transistors 473a and a plurality of transistors 473b are connected. Is exemplified. This is because by connecting a plurality of small transistors 473 in parallel, variation in the transistors 473 can be reduced.
[0604]
The above is also applicable to the relationship with the transistors 472a and 472b in FIG. It is preferable that the transistor 473b in FIG. 48 also include a plurality of transistors. Similarly, the transistor 473 in FIGS. 56 and 57 is preferably formed of a plurality of transistors.
[0605]
Here, the source driver IC 14 will be described as being formed of a silicon chip, but the present invention is not limited to this. The source driver IC 14 may be another semiconductor chip formed on a gallium substrate, a germanium substrate, or the like. Further, the unit transistor 484 may be any of a bipolar transistor, a CMOS transistor, an FET, a bi-CMOS transistor, and a DMOS transistor. However, from the viewpoint of reducing the output variation of the unit transistor 484, it is preferable that the unit transistor 484 be a CMOS transistor.
[0606]
It is preferable that the unit transistor 484 be configured with an N channel. The output variation of a unit transistor formed of a P-channel transistor is 1.5 times that of a unit transistor formed of an N-channel transistor.
[0607]
Since the unit transistor 484 of the source driver IC 14 is preferably formed of an N-channel transistor, the program current of the source driver IC 14 is a current drawn from the pixel 16 to the source driver IC. Therefore, the driving transistor 11a of the pixel 16 is configured with a P channel. Further, the switching transistor 11d of FIG. 1 is also formed of a P-channel transistor.
[0608]
As described above, the configuration in which the unit transistor 484 in the output stage of the source driver IC (circuit) 14 is configured by an N-channel transistor and the driving transistor 11a of the pixel 16 is configured by a P-channel transistor is a feature of the present invention. Configuration. Note that all of the transistors 11 (the transistors 11a, 11b, 11c, and 11d) included in the pixel 16 may be formed as P-channels. Since the process for forming an N-channel transistor can be eliminated, cost reduction and high yield can be realized.
[0609]
Although the unit transistor 484 is formed in the source driver IC 14, the present invention is not limited to this. The source driver circuit 14 may be formed by low-temperature polysilicon technology. Also in this case, it is preferable that the unit transistor 484 in the source driver circuit 14 is formed of an N-channel transistor.
[0610]
FIG. 51 shows an embodiment of the current transfer configuration. FIG. 50 shows an embodiment of the voltage transfer configuration. 50 and 51 are the same as the circuit diagrams, and differ in the layout configuration, that is, the way of wiring. In FIG. 50, reference numeral 471 denotes a first-stage current source N-channel transistor, 472a denotes a second-stage current source N-channel transistor, and 472b denotes a second-stage current source P-channel transistor.
[0611]
In FIG. 51, reference numeral 471a denotes a first-stage current source N-channel transistor, 472a denotes a second-stage current source N-channel transistor, and 472b denotes a second-stage current source P-channel transistor.
[0612]
In FIG. 50, the gate voltage of the first-stage current source constituted by the variable resistor 491 (used for changing the current) and the N-channel transistor 471 is changed to the gate of the N-channel transistor 472a of the second-stage current source. , The layout configuration is of a voltage passing system.
[0613]
On the other hand, in FIG. 51, the gate voltage of the first-stage current source constituted by the variable resistor 491 and the N-channel transistor 471a is applied to the gate of the N-channel transistor 472a of the adjacent second-stage current source. Since the flowing current value is transferred to the P-channel transistor 472b of the second-stage current source, the layout configuration is of a current transfer type.
[0614]
In the embodiment of the present invention, the relationship between the first current source and the second current source has been mainly described for the sake of easy explanation or understanding, but the present invention is not limited to this. However, it is needless to say that the present invention can be applied (applicable) in the relationship between the second current source and the third current source or in the relationship with other current sources.
[0615]
In the layout configuration of the voltage transfer type current mirror circuit shown in FIG. 50, the N-channel transistor 471 of the first-stage current source and the N-channel transistor 472a of the second-stage current source forming the current mirror circuit are separated from each other. (It should be easy to be separated.) Therefore, a difference easily occurs between the transistor characteristics of the two transistors. Therefore, the current value of the first-stage current source is not accurately transmitted to the second-stage current source, and variation is likely to occur.
[0616]
On the other hand, in the layout configuration of the current transfer type current mirror circuit shown in FIG. 51, the N-channel transistor 471a of the first-stage current source and the N-channel transistor 472a of the second-stage current source which constitute the current mirror circuit are adjacent to each other. (Easily arranged adjacent to each other), it is difficult for the two transistors to have a difference in transistor characteristics, the current value of the first-stage current source is accurately transmitted to the second-stage current source, and variation is less likely to occur.
[0617]
As described above, the circuit configuration of the multi-stage current mirror circuit of the present invention (the current driver type source driver IC (circuit) 14 of the present invention has a layout configuration in which current delivery is performed instead of voltage delivery is realized. The above embodiment can be applied to other embodiments of the present invention.
[0618]
For the sake of explanation, the case where the first-stage current source is switched to the second-stage current source is shown, but the second-stage current source is switched to the third-stage current source, the third-stage current source is switched to the fourth-stage current source,. It goes without saying that the same applies to the case of multiple stages such as. Needless to say, the present invention may employ a single-stage current source configuration (see FIGS. 48, 164, 165, 166, etc.).
FIG. 52 shows an example in which the three-stage current mirror circuit (three-stage current source) of FIG. 49 is of a current transfer type (therefore, FIG. 49 shows a voltage transfer type circuit configuration). ).
[0619]
In FIG. 52, first, a reference current is created by the variable resistor 491 and the N-channel transistor 471. Although the reference current is adjusted by the variable resistor 491, the source voltage of the transistor 471 is set by an electronic volume circuit formed (or arranged) in the source driver IC (circuit) 14 in practice. It is configured to be adjusted. Alternatively, the reference current is adjusted by directly supplying the current output from the current-type electronic regulator composed of a number of current sources (one unit) 484 as shown in FIG. 48 to the source terminal of the transistor 471. (See FIG. 53).
[0620]
The gate voltage of the first-stage current source by the transistor 471 is applied to the gate of the N-channel transistor 472a of the adjacent second-stage current source. As a result, the current flowing through the transistor is changed to the P-channel transistor 472b of the second-stage current source. Handed over to Further, the gate voltage of the transistor 472b of the second current source is applied to the gate of the N-channel transistor 473a of the adjacent third-stage current source, and as a result, the value of the current flowing through the transistor becomes N-channel of the third-stage current source. The signal is passed to the transistor 473b. On the gate of the N-channel transistor 473b of the third-stage current source, a number of unit transistors 484 shown in FIG. 48 are formed (arranged) according to the required number of bits.
[0621]
FIG. 53 is characterized in that the first-stage current source 471 of the multistage current mirror circuit includes a current value adjusting element. With this configuration, it is possible to control the output current by changing the current value of the first-stage current source 471.
[0622]
Vt variations (characteristic variations) of the transistors vary by about 100 (mV) within one wafer. However, the Vt variation of the transistor formed close to 100 μm is at least 10 (mV) or less (actual measurement). That is, by forming transistors close to each other to form a current mirror circuit, it is possible to reduce variations in output current of the current mirror circuit. Therefore, it is possible to reduce the variation in the output current of each terminal of the source driver IC.
[0623]
Note that although the description will be made on the assumption that the variation of the transistor is Vt, the variation of the transistor is not limited to Vt. However, since Vt variation is a main factor of transistor variation, Vt variation = transistor variation will be described for easy understanding.
[0624]
FIG. 118 shows the measurement results of the transistor formation area (square millimeter) and the output current variation of the single transistor 484. The output current variation is a current variation at the Vt voltage. The black dots indicate the transistor output current variations of the evaluation samples (10 to 200) manufactured within a predetermined formation area. The transistor formed in the region A (forming area within 0.5 square millimeter) in FIG. 118 has almost no variation in output current (substantially, there is only variation in output current in an error range. That is, a constant output current has a constant value. Output). Conversely, in the region C (formation area of 2.4 mm 2 or more), the variation of the output current with respect to the formation area tends to increase sharply. In the region B (formation area not less than 0.5 square millimeters and not more than 2.4 square millimeters), the variation of the output current with respect to the formation area is in a substantially proportional relationship.
[0625]
However, the absolute value of the output current differs for each wafer. However, this problem can be solved by adjusting the reference current or setting it to a predetermined value in the source driver IC (circuit) 14 of the present invention. In addition, it is possible to cope (can be solved) with a circuit device such as a current mirror circuit.
[0626]
The present invention changes (controls) the amount of current flowing through the source signal line 18 by switching the number of currents flowing through the unit transistor 484 according to the input digital data (D). If the number of gradations is 64 or more, 1/64 = 0.015, so it is theoretically necessary to keep the output current variation within 1-2%. Note that it is difficult to visually discriminate the output variation within 1%, and it is almost impossible to discriminate the output variation below 0.5% (it looks uniform).
[0627]
In order to make the output current variation (%) within 1%, it is necessary to make the formation area of the transistor group (transistors to suppress the variation) within 2 square millimeters as shown in the result of FIG. . More preferably, the variation in the output current (that is, the variation in the Vt of the transistor) is set to be within 0.5%. As shown in the results of FIG. 118, the formation area of the transistor group 521 may be set within 1.2 square millimeters. Note that the formation area is an area of length × width. For example, as an example, for 1.2 square millimeters, it is 1 mm × 1.2 mm.
[0628]
The same applies to a set of unit transistors 484 (a cluster of 63 transistors 484 for 64 gradations (see FIG. 48 and the like). More preferably, the formation area of the unit transistor set 484 should be within 1.2 square millimeters.
[0629]
Note that the above is particularly the case of 8 bits (256 gradations) or more. In the case of 256 gradations or less, for example, in the case of 6 bits (64 gradations), the variation of the output current may be about 2% (there is no problem in actuality in image display). In this case, the transistor group 521 may be formed within 5 square millimeters. Further, both the transistor group 521 (in FIG. 52, two transistor groups 521a and 521b are illustrated) need not satisfy this condition. If at least one of them is constituted (one or more transistor groups 521 when there are three or more), the effect of the present invention can be exerted if it is configured to satisfy this condition. In particular, it is preferable to satisfy this condition with respect to the lower transistor group 521 (521a is higher and 521b is lower). This is because a problem does not easily occur in image display.
[0630]
In the source driver IC (circuit) 14 of the present invention, as shown in FIG. 52, a plurality of current sources such as a parent, a child, and a grandchild are connected in multiple stages, and the current sources are densely arranged (of course, Parent and child may be connected in two stages). Further, current is passed between each current source (between the transistor groups 521). Specifically, a range (transistor group 521) surrounded by a dotted line in FIG. 52 is densely arranged. The transistor group 521 has a relationship of voltage transfer. Further, the parent current source 471 and the child current source 472a are formed or arranged substantially at the center of the source driver IC 14 chip. This is because the distance between the transistor 472a constituting the child current source and the transistor 472b constituting the child current source arranged on the left and right of the chip can be made relatively short. That is, the uppermost transistor group 521a is arranged at a substantially central portion of the IC chip. Then, the lower transistor group 521b is arranged on the left and right sides of the source driver IC14. Preferably, the lower transistor group 521b is arranged, formed or manufactured such that the number of the lower transistor groups 521b is substantially equal on the left and right sides of the IC chip. Note that the above items are not limited to the source driver IC 14 but also apply to the source driver circuit 14 formed directly on the substrate 71 using the low-temperature polysilicon technology or the high-temperature polysilicon technology. The same applies to other items.
[0631]
In the present invention, one transistor group 521a is formed, arranged, formed, or manufactured substantially in the center of the source driver IC 14, and eight transistor groups 521b are formed on each of the left and right sides of the chip (N = 8 + 8, FIG. 47). The child transistor groups 521b are equal to the left and right sides of the chip, or the number of transistor groups 521b formed or arranged on the left side and the right side of the chip, It is preferable that the difference between the number of the transistor groups 521b and the number of the transistor groups 521b be four or less. Furthermore, it is preferable that the difference between the number of transistor groups 521b formed or arranged on the left side of the chip and the number of transistor groups 521b formed or arranged on the right side of the chip be within one. . The same applies to the transistor group as a grandchild (although omitted in FIG. 52).
[0632]
Voltage transfer (voltage connection) is performed between the parent current source 471 and the transistor 472a. Therefore, the transistor is easily affected by Vt variation. Therefore, the portion of the transistor group 521a is densely arranged. The formation area of the transistor group 521a is formed within an area of 2 square millimeters as shown in FIG. More preferably, it is formed within 1.2 square millimeters. Of course, when the number of gradations is 64 gradations or less, it may be within 5 square millimeters.
[0633]
Since data is transferred between the transistor group 521a and the child transistor 472b by current (current transfer), the distance may flow. As described above, the range of this distance (for example, the distance from the output terminal of the upper transistor group 521a to the input terminal of the lower transistor 521b) is the same as that of the transistor 472a constituting the second current source (child). The transistor 472b constituting the second current source (child) is disposed at a distance of at least 10 mm or less. Preferably, it is arranged or formed within 8 mm. Furthermore, it is preferable to arrange within 5 mm.
[0634]
This is because, within this range, a difference in transistor characteristics (Vt, mobility (μ)) arranged in the silicon chip and having little effect on current transfer is examined. In particular, this relationship is preferably implemented in a lower transistor group. For example, if the transistor group 521a is at the top and the transistor group 521b is at the bottom and the transistor group 521c is at the bottom, the current transfer between the transistor group 521b and the transistor group 521c satisfies this relationship. Therefore, the present invention is not limited to all the transistor groups 521 satisfying this relationship. At least one set of transistors 521 should satisfy this relationship. In particular, this is because the number of transistor groups 521 increases in the lower order.
[0635]
The same applies to the transistor 473a forming the third current source (grandchild) and the transistor 473b forming the third current source. It goes without saying that the present invention can be applied almost to the voltage transfer.
[0636]
The transistor group 521b is formed, manufactured, or arranged in the left-right direction (longitudinal direction, that is, at a position facing the output terminal 681) of the chip. The transistor group 521b is formed, manufactured, or arranged in the left-right direction (longitudinal direction, that is, at a position facing the output terminal 681) of the chip. The number M of the transistor groups 521b is 11 in the present invention (see FIG. 47).
[0637]
Voltage is transferred (voltage connected) between the transistor 472b and the grandchild current source 473a. Therefore, similarly to the transistor group 521a, the transistor group 521b is densely arranged. The formation area of the transistor group 521b is formed within an area of 2 square millimeters as shown in FIG. More preferably, it is formed within 1.2 square millimeters. However, if the Vt of the transistor group 521b varies even a little, it is easily recognized as an image. Therefore, the formation area is preferably set to the region A (within 0.5 square millimeters) in FIG. 118 so that almost no variation occurs.
[0638]
Since the transistor group 521b exchanges data (current exchange) between the grandchild transistor 473a and the transistor 473b by current, the distance may flow somewhat. The range of this distance is the same as described above. The transistor 473a forming the third current source (grandchild) and the transistor 473b forming the second current source (grandchild) are disposed at least within a distance of 8 mm. Furthermore, it is preferable to arrange within 5 mm.
[0639]
FIG. 53 shows a case where the current value control element is formed of an electronic regulator. The electronic regulator is composed of a resistor 531 (which creates a current limit and each reference voltage. The resistor 531 is formed of polysilicon), a decoder 532, a level shifter 533, and the like. The electronic volume outputs a current. The transistor 481 functions as an analog switch circuit.
[0640]
In the source driver IC (circuit) 14, a transistor may be referred to as a current source. This is because a current mirror circuit or the like including transistors functions as a current source.
[0641]
The electronic volume circuits are formed (or arranged) according to the number of colors of the EL display panel. For example, in the case of three primary colors of RGB, it is preferable to form (or arrange) three electronic volume circuits corresponding to each color so that each color can be adjusted independently. However, when one color is used as a reference (fixed), an electronic volume circuit for one color is formed (or arranged).
[0642]
FIG. 68 shows a configuration in which a resistive element 491 for independently controlling the reference current for the three primary colors of RGB is formed (arranged). Of course, it goes without saying that the resistance element 491 may be replaced with an electronic regulator. Further, the resistance element 491 may be built in the source driver IC (circuit) 14. Current sources such as the current source 471 and the current source 472, which are basic (root) current sources such as the parent current source and the child current source, are densely arranged in the current output circuit 654 in the area shown in FIG. By arranging them densely, variations in output from each source signal line 18 are reduced. As shown in FIG. 68, the current output circuit 654 (not limited to the current output circuit) is provided at the center of the IC chip (circuit) 14.
The reference current generation circuit unit and the controller unit may be used. That is, 654 is an area where an output circuit is not formed), so that it becomes easy to uniformly distribute current from the current sources 471 and 472 to the left and right of the IC chip (circuit) 14. . Therefore, left and right output variations hardly occur.
[0643]
However, the arrangement is not limited to the arrangement of the current output circuit 654 at the center. It may be formed at one end or both ends of the IC chip. In addition, it may be formed or arranged in parallel with the output current circuit 654.
[0644]
Forming the controller or the output current circuit 654 in the central portion of the source driver IC 14 is not so preferable because it is easily affected by the Vt distribution of the unit transistor 484 of the source driver IC 14 (the Vt of the wafer is smooth within the wafer). This is because a strong distribution occurs.)
[0645]
In the circuit configuration of FIG. 52, one transistor 473a and one transistor 473b are connected in a one-to-one relationship. In FIG. 51 as well, one transistor 472a and one transistor 472b are connected one-to-one. The same applies to FIG. 49 and the like.
[0646]
However, when one transistor and one transistor are connected in a one-to-one relationship, the characteristics of the corresponding transistor (such as Vt) vary and the output of the transistor connected to this transistor varies. Would.
[0647]
An embodiment of a configuration that solves this problem is the configuration in FIG. In the configuration of FIG. 58, as an example, a transmission transistor group 521b (521b1, 521b2, 521b3) composed of four transistors 473a and a transmission transistor group 521c (521c1, 521c2, 521c3) composed of four transistors 473b are connected. However, the transfer transistor group 521b and the transfer transistor group 521c are each configured by four transistors 473, but are not limited thereto, and needless to say, may be three or less, or five or more. That is, the reference current Ib flowing through the transistor 473a is output by the plurality of transistors 473 forming a current mirror circuit together with the transistor 473a, and the output current is received by the plurality of transistors 473b.
[0648]
It is preferable that the plurality of transistors 473a and the plurality of transistors 473b have substantially the same size and the same number. Also, the number of unit transistors 484 forming one output (63 in the case of 64 gradations as shown in FIG. 48) and the number of transistors 473b forming a current mirror with the unit transistor 484 are substantially the same size and the same. It is preferable to make the number. Specifically, it is preferable that the difference between the size of the unit transistor 484 and the size of the transistor 473b be within ± 25%. With the above configuration, the current magnification can be set with high accuracy, and the variation in the output current can be reduced. Note that the area of the transistor refers to an area obtained by multiplying the channel length L of the transistor by the channel width W of the transistor.
[0649]
Note that the current Ib flowing through the transistor 473b is preferably set to be five times or more the current Ic1 flowing through the transistor 473b. This is because the gate potential of the transistor 473a is stabilized and the occurrence of a transient phenomenon due to the output current can be suppressed.
[0650]
Further, four transistors 473a are arranged adjacent to the transmission transistor group 521b1, a transmission transistor group 521b2 is arranged adjacent to the transmission transistor group 521b1, and four transistors 473a are arranged adjacent to the transmission transistor group 521b2. It is described that they are arranged and arranged, but the invention is not limited to this. For example, the transistors 473a of the transfer transistor group 521b1 and the transistors 473a of the transfer transistor group 521b2 may be arranged or formed such that their positional relationship is crossed with each other. By interchanging the positional relationship (exchanging the arrangement of the transistors 473 between the transmission transistor groups 521), the variation in the output current (program current) at each terminal can be further reduced.
[0651]
By configuring the transistors that transfer current as described above with a plurality of transistors, variations in output current as a whole transistor group can be reduced, and variations in output current (program current) at each terminal can be further reduced.
[0652]
An important item is the sum of the formation areas of the transistors 473 forming the transmission transistor group 521. Basically, as the total area of the transistors 473 increases, the variation in the output current (program current flowing from the source signal line 18) decreases. In other words, the variation becomes smaller as the formation area of the transfer transistor group 521 (the sum of the formation areas of the transistors 473) increases. However, if the formation area of the transistor 473 increases, the chip area increases, and the price of the source driver IC 14 increases.
[0653]
Note that the formation area of the transmission transistor group 521 is the total area of the transistors 473 included in the transmission transistor group 521. The area of the transistor 473 refers to an area obtained by multiplying a channel length L of the transistor 473 by a channel width W of the transistor 473. Therefore, if the transistor 521 is composed of ten transistors 473 and the channel length L of the transistor 473 is 10 μm and the channel width W of the transistor 473 is 5 μm, the formation area Tm (square μm) of the transmission transistor group 521 is 10 μm × 5 μm × 10 = 500 (square μm).
[0654]
The formation area of the transmission transistor group 521 needs to maintain a predetermined relationship with the unit transistor 484. Further, it is necessary to maintain a predetermined relationship between the transmission transistor group 521a and the transmission transistor group 521b.
[0655]
The relationship between the formation area of the transistor group 521 and the unit transistor 484 will be described. As shown in FIG. 50, a plurality of unit transistors 484 are connected to one transistor 473b. In the case of 64 gradations, there are 63 unit transistors 484 corresponding to one transistor 473b (in the case of the configuration in FIG. 48). The formation area Ts (square μm) of this unit transistor group (63 unit transistors 484 in this example) is 10 μm × 10 μm if the channel length L of the unit transistor 473 is 10 μm and the channel width W of the transistor 473 is 10 μm. 10 μm × 63 = 6300 square μm.
[0656]
The transistor 473b in FIG. 48 corresponds to the transmission transistor group 521c in FIG. The formation area Ts of the unit transistor group and the formation area Tm of the transmission transistor group 521c are set to have the following relationship.
[0657]
1/4 ≦ Tm / Ts ≦ 6
More preferably, the formation area Ts of the unit transistor group and the formation area Tm of the transmission transistor group 521c have the following relationship.
[0658]
1/2 ≦ Tm / Ts ≦ 4
By satisfying the above relationship, the variation in the output current (program current) at each terminal can be reduced.
[0659]
Further, the formation area Tmm of the transmission transistor group 521b and the formation area Tms of the transmission transistor group 521c are set to have the following relationship.
[0660]
1/2 ≦ Tmm / Tms ≦ 8
More preferably, the formation area Ts of the unit transistor group and the formation area Tm of the transmission transistor group 521c have the following relationship.
[0661]
1 ≦ Tmm / Tms ≦ 4
By satisfying the above relationship, the variation in the output current (program current) at each terminal can be reduced.
[0662]
When the output current Ic1 from the transistor group 521b1, the output current Ic2 from the transistor group 521b2, and the output current Ic3 from the transistor group 521b2 are required, the output current Ic1, the output current Ic2, and the output current Ic3 need to match. In the present invention, since the transistor group 521 includes a plurality of transistors 473, the output current Ic of the transistor group 521 does not vary even if the individual transistors 473 vary.
[0663]
The above embodiment is not limited to the configuration of the three-stage current mirror connection (multi-stage current mirror connection) as shown in FIG. It goes without saying that the present invention can be applied to a single-stage current mirror connection. In the embodiment of FIG. 52, a transistor group 521b (521b1, 521b2, 521b3...) Including a plurality of transistors 473a and a transistor group 521c (521c1, 521c2, 521c3...) Including a plurality of transistors 473b are provided. ...) were connected. However, the present invention is not limited to this, and one transistor 473a and a transistor group 521c (521c1, 521c2, 521c3,...) Including a plurality of transistors 473b may be connected. Further, a transistor group 521b (521b1, 521b2, 521b3,...) Including a plurality of transistors 473a may be connected to one transistor group 473b.
[0664]
In FIG. 48, a switch 481a corresponds to the 0th bit, a switch 481b corresponds to the 1st bit, a switch 481c corresponds to the 2nd bit,..., A switch 481f corresponds to the 5th bit. The 0th bit is composed of one unit transistor, the first bit is composed of two unit transistors, the second bit is composed of four unit transistors,... The fifth bit is composed of 32 unit transistors. . For the sake of simplicity, the description will be made on the assumption that the source driver circuit 14 is compatible with 64-gradation display and has 6 bits.
[0665]
In the configuration of the source driver IC (circuit) 14 of the present invention, the first bit outputs twice the program current as the 0th bit. The second bit outputs twice the program current as the first bit. The third bit outputs twice as much programming current as the second bit. The fourth bit outputs twice the program current as the third bit. The fifth bit outputs twice as much programming current as the fourth bit. Conversely, each adjacent bit must be configured to output exactly twice the program current.
[0666]
In the configuration of FIG. 58, the output current of the plurality of transistors 473a is received by the plurality of transistors 473b, so that the variation in the output current of each terminal is reduced. FIG. 60 shows a configuration in which variations in output current are reduced by supplying a reference current from both sides of a transistor group. That is, a plurality of supply sources of the current Ib are provided. In the present invention, the current Ib1 and the current Ib2 have the same current value, and a transistor that generates the current Ib1 and a transistor that generates the current Ib2 constitute a current mirror circuit with a pair of transistors.
[0667]
Therefore, the present invention has a configuration in which a plurality of transistors (current generating means) for generating a reference current that defines the output current of the unit transistor 484 are formed or arranged. More preferably, the output current from the plurality of transistors is connected to a current receiving circuit such as a transistor constituting a current mirror circuit, and the output current of the unit transistor 484 is controlled by the gate voltage generated by the plurality of transistors. is there. That is, the present invention has a structure in which the unit transistor 484 and a plurality of transistors 473b forming a current mirror circuit are formed. In FIG. 58, five transistors 473b forming a current mirror circuit are arranged (formed) in a transistor group in which 63 unit transistors 484 are formed.
[0668]
When the IC chip is a silicon chip, the gate terminal voltage of the unit transistor 484 is preferably set in a range from 0.52 to 0.68 (V). Within this range, variations in the output current of the unit transistor 484 are reduced. The above is the same in other embodiments of the present invention such as FIGS. 163, 164, and 165.
[0669]
In FIG. 60, if the reference current Ib1 and the reference current Ib2 are configured to be individually adjustable, the voltage at the point a and the voltage at the point b of the gate terminal 581 can be set freely. By adjusting the reference currents Ib1 and Ib2, the Vt of the unit transistor is different between the left and right sides of the source driver IC14, so that it is possible to correct even when the output current is inclined.
[0670]
It is preferable that the current generated by the transistors constituting the current mirror circuit be transferred by a plurality of transistors. The characteristics of the transistors formed in the source driver IC 14 vary. In order to suppress variations in transistor characteristics, there is a method of increasing the transistor size. However, even if the transistor size is increased, the current mirror magnification of the current mirror circuit may be largely shifted. In order to solve this problem, it is preferable that a plurality of transistors pass current or voltage. If a plurality of transistors are used, even if the characteristics of the transistors vary, the variation in characteristics as a whole can be reduced. Also, the accuracy of the current mirror magnification is improved. Considering the total, the IC chip area is also reduced.
[0671]
FIG. 58 shows a current mirror circuit including the transistor group 521a and the transistor group 521b. The transistor 521a includes a plurality of transistors 472b. On the other hand, the transistor group 521b includes a transistor 473a. Similarly, the transistor group 521c includes a plurality of transistors 473b.
[0672]
The transistors 473a forming the transistor group 521b1, the transistor group 521b2, the transistor group 521b3, the transistor group 521b4,... Are formed in the same number. The total area of the transistors 473a in each transistor group 521b (the WL size of the transistors 473a in the transistor group 521b × the number of transistors 473a) is (substantially) equal. The same applies to the transistor group 521c.
[0673]
The total area of the transistors 473b of the transistors 521c (the WL size of the transistors 473b in the transistor group 521c × the number of transistors 473b) is Sc. Further, the total area of the transistors 473a of the transistors 521b (the WL size of the transistors 473a in the transistor group 521b × the number of transistors 473a) is Sb. The total area of the transistors 472b of the transistors 521a (the WL size of the transistors 472b in the transistor group 521a × the number of transistors 472b) is defined as Sa. The total area of the unit transistor 484 having one output is Sd (the WL area of the unit transistor 484 × 63 in the embodiment of FIG. 48).
[0674]
It is preferable that the total area Sc and the total area Sb are formed to be substantially equal. It is preferable that the number of transistors 473a included in the transistor group 521b and the number of transistors 473b included in the transistor group 521c be the same. However, the number of transistors 473a forming the transistor group 521b is made smaller than the number of transistors 473b of the transistor group 521c due to restrictions on the layout of the source driver IC 14, and the size of the transistor 473a forming the transistor group 521b is reduced. The size may be larger than the size of the transistor 473b of the transistor 521c.
[0675]
This embodiment is illustrated in FIG. The transistor group 521a includes a plurality of transistors 472b. The transistor group 521a and the transistor 473a form a current mirror circuit. Transistor 473a generates current Ic. One transistor 473a drives a plurality of transistors 473b of a transistor group 521c (the current Ic from one transistor 473a is diverted to a plurality of transistors 473b. In general, the number of transistors 473a depends on the number of output circuits. For example, in the case of a QCIF + panel, 176 transistors 473a are formed or arranged in each of the R, G, and B circuits.
[0676]
The relationship between the total area Sd and the total area Sc has a correlation with the output variation. This relationship is illustrated in FIG. Refer to FIG. 121 for the variation ratio and the like. The variation ratio is set to 1 when the total area Sd: the total area Sc = 2: 1 (Sc / Sd = 1/2). As can be seen from FIG. 124, when Sc / Sd is small, the variation ratio suddenly worsens. In particular, it tends to be worse when Sc / Sd = 1/2 or less. When Sc / Sd is 以上 or more, output variation is reduced. The effect of the reduction is moderate. Further, when Sc / Sd = １ ／, the output variation becomes an allowable range. From the above, it is preferable to form them so as to satisfy the relationship of 1/2 <= Sc / Sd. However, as Sc increases, the IC chip size also increases. Therefore, the upper limit is preferably set to Sc / Sd = 4. That is, the relationship of 1/2 <= Sc / Sd <= 4 is satisfied.
[0677]
A> = B means that A is greater than or equal to B. A> B means that A is greater than B. A <= B means that A is B or less. A <B means that A is smaller than B.
[0678]
Further, it is preferable that the total area Sd and the total area Sc be substantially equal. Further, it is preferable that the number of unit transistors 484 having one output and the number of transistors 473b of the transistor group 521c be the same. That is, in the case of 64 gradation display, 63 unit transistors 484 each having one output are formed. Therefore, the number of transistors 473b constituting the transistor group 521c is 63.
[0679]
In addition, it is preferable that the transistor group 521a, the transistor group 521b, the transistor 521c, and the unit transistor 484 be formed of transistors having a WL area ratio within 4 times. More preferably, it is preferable to configure the transistor with a ratio of the WL area within 2 times. Further, it is preferable that all the transistors be formed of the same size. That is, it is preferable that the current mirror circuit and the output current circuit 654 be formed using transistors having substantially the same shape.
[0680]
The total area Sa is set to be larger than the total area Sb. Preferably, the configuration is such that the relationship of 200Sb >> = Sa >> = 4Sb is satisfied. In addition, the total area of the transistors 473a constituting all the transistor groups 521b is set to be substantially equal to Sa.
[0681]
In FIG. 60 and the like, a transistor or a transistor group is arranged at both ends of the gate wiring 581. Therefore, two transistors are arranged on both sides of the gate wiring 581, or two sets of transistors are provided. However, the present invention is not limited to this. As shown in FIG. 61, a transistor or a transistor group may be arranged or formed at the center of the gate wiring 581 or the like. In FIG. 61, three transistor groups 521a are formed. The present invention is characterized in that a plurality of transistors or transistor groups 521 are formed in the gate wiring 581. By forming a plurality, the impedance of the gate wiring 581 can be reduced, and the stability is improved.
[0682]
In order to further improve the stability, it is preferable to form or arrange a capacitor 661 on the gate wiring 581 as shown in FIG. The capacitor 661 may be formed in the source driver IC 14 or the source driver circuit 14, or may be disposed or mounted outside the chip as an external capacitor of the source driver IC 14. When the capacitor 661 is provided externally, a capacitor connection terminal is arranged at a terminal of the IC chip.
[0683]
The above embodiment has a configuration in which a reference current flows, the reference current is copied by a current mirror circuit, and transmitted to the last unit transistor 484. When the image display is a black display (complete black raster), no current flows through any of the unit transistors 484. This is because both switches 481 are open. Therefore, since the current flowing through the source signal line 18 is 0 (A), no power is consumed.
[0684]
However, even in the black raster display, the reference current flows. For example, the current Ib and the current Ic in FIG. This current becomes a reactive current. It is efficient if the reference current is configured to flow during current programming. Therefore, the reference current is restricted from flowing during the vertical blanking period and the horizontal blanking period of the image. Also, the flow of the reference current is restricted during a wait period or the like.
[0685]
To prevent the reference current from flowing, the sleep switch 631 may be opened as shown in FIG. The sleep switch 631 is an analog switch. The analog switch is formed in the source driver circuit or the source driver IC 14. Of course, the sleep switch 631 may be arranged outside the source driver IC 14 and the sleep switch 631 may be controlled.
[0686]
Turning off the sleep switch 631 prevents the reference current Ib from flowing. Therefore, since no current flows through the transistor 473a in the transistor group 521a1, the reference current Ic also becomes 0 (A). Therefore, no current flows through the transistor 473b of the transistor group 521c. Therefore, power efficiency is improved.
[0687]
FIG. 64 is a timing chart. A blanking signal is generated in synchronization with the horizontal synchronization signal HD. When the blanking signal is at the H level, it is a blanking period, and when it is at the L level, it is a period during which a video signal is applied. The sleep switch 631 is off (open) when it is at the L level, and is on when it is at the H level.
[0688]
Therefore, during the blanking period A, since the sleep switch 631 is off, no reference current flows. During the period D, the sleep switch 631 is on, and a reference current is generated.
[0689]
Note that on / off control of the sleep switch 631 may be performed according to image data. For example, when the image data of one pixel row is all black image data (the program current output to all the source signal lines 18 is 0 during the 1H period), the sleep switch 631 is turned off and the reference current (Ic , Ib, etc.). Alternatively, a sleep switch may be formed or arranged so as to correspond to each source signal line, and on / off control may be performed. For example, when the odd-numbered source signal lines 18 display black (vertical black stripe display), the sleep switch corresponding to the odd-numbered source signal line 18 is turned off.
[0690]
52 and 77 are configuration diagrams of the source driver IC (circuit) 14 having a multi-stage connection current mirror configuration. The present invention is not limited to the configuration of the multistage connection as shown in FIG. The source driver circuit 14 may be a single-stage connection. 166 to 172, FIG. 190, FIG. 191, FIG. 208, FIG. 211, FIG. 213, and FIG. 214 are configuration diagrams of a single-stage connected source driver IC (circuit). The one-stage configuration has a simple circuit configuration and small variations in output current. Also in this case, the unit transistor 484 is constituted by an N-channel transistor. Therefore, the program current from the source signal line 18 becomes a sink current. The gate terminal of the unit transistor 484 and the gate terminal of the transistor 473b are connected by a common gate wiring 581. FIG. 166 shows the unit transistor group 521c. It is arranged or formed within a dotted line indicating the unit transistor 521c in each drawing.
[0691]
Consider a case where a plurality of source driver ICs (14a, 14b) are arranged adjacent to each other as shown in FIGS. 207, 210, and 228. In the white raster display, it is preferable that the output currents of all terminals (Iout) match without variation. Even if the output current varies, if the output current difference between adjacent output terminals is small, it is not visually recognized as the variation. The variation between adjacent output terminals needs to be within 1%.
[0692]
When the display screen 50 is driven by one source driver IC 14, it is sufficient that the variation between adjacent output terminals is small. However, when one screen 50 is driven by a plurality of source driver ICs 14 as shown in FIG. This is because there is at least a difference between the absolute values of the output currents of the source driver IC 14a and the source driver IC 14b in the variation between the adjacent output terminals.
[0693]
This is because if the absolute value of the output current of the unit transistor group 521 of the source driver IC 14a is different from the absolute value of the output current of the unit transistor group 521 of the source driver IC 14b Iout (n + 1), a boundary occurs on the screen 50 due to the adjacent output difference. Hereinafter, a method for solving this problem will be described.
[0694]
In FIG. 167, a transistor 472b and two transistors 473a constitute a current mirror circuit. The transistors 473a1 and 473a2 have the same size. Therefore, the current Ic flowing from the transistor 473a1 and the current Ic flowing from the transistor 473a2 are the same.
[0696]
The transistor group 521c including the unit transistors 484 and the transistor 473b1 and the transistor group 521c including the unit transistors 484 and the transistor 473b2 in FIG. 167 form a current mirror circuit. The output current of the transistor group 521c varies. However, the current of the output of the transistor group 521 constituting the current mirror circuit in close proximity is precisely defined.
[0696]
In the source driver IC 14a, the transistor 473b1 and the transistor group 521c1 are arranged close to each other and form a current mirror circuit. Further, the transistor 473b2 and the transistor group 521cn are also arranged close to each other to form a current mirror circuit. Therefore, if the current flowing through the transistor 473b1 and the current flowing through the transistor 473b2 are equal, the output current of the transistor group 521c1 is equal to the output current of the transistor group 521cn.
[0697]
Similarly, in the source driver IC 14b, the transistor 473b1 and the transistor group 521c (n + 1) are arranged close to each other to form a current mirror circuit. Further, the transistor 473b2 and the transistor group 521c (2n) are also arranged close to each other to form a current mirror circuit. Therefore, if the current flowing through the transistor 473b1 and the current flowing through the transistor 473b2 are equal, the output current of the transistor group 521c (n + 1) is equal to the output current of the transistor group 521c (2n).
[0698]
In FIG. 228, the reference voltage Vs is applied to the positive terminal of the operational amplifier 522. An external resistor R1 is connected to a negative terminal of the operational amplifier 522. One terminal of the resistor R1 is connected to a stable voltage Vp. Therefore, the resistor R1, the operational amplifier 522, and the transistor 473 form a constant current circuit. The current Ic flowing through the transistor 473 is Ic = (Vs-Vp) / R1. Although the resistor R1 is an external resistor, the present invention is not limited to this. The resistor R1 may be built in the source driver IC (circuit) 14. For example, a diffusion resistance, a polysilicon resistance, and the like formed in the IC chip are exemplified. Of course, the resistors may be formed by low temperature polysilicon technology. Further, the reference voltages Vs, Vp and the like may be common to the power supply voltage Vcc of the source driver IC (circuit) 14. Further, it may be shared with the anode voltage Vdd of the panel.
[0699]
The same reference voltage Vs is applied to the source driver IC 14a and the source driver IC 14b, and the constant current circuit including the operational amplifier 552 generates a reference current Ic by the reference voltage Vs (see also FIG. 170). For the sake of simplicity, it is assumed that the resistor R1 is an external resistor of the source driver IC 14 and has a precision of 1% or less.
[0700]
With the above configuration, the current Ic flowing through the transistors 473b1 and 473b2 of the source driver IC 14a and the current Ic flowing through the transistors 473b1 and 473b2 of the source driver IC 14b can be equalized. Therefore, the current Ic flowing through the transistor 473b2 of the source driver IC 14a and the transistor 473b1 of the source driver IC 14b can be made equal.
[0701]
In the source driver IC 14a, since the transistor 473b2 and the transistor group 521cn are arranged close to each other, a highly accurate current mirror circuit is formed. Further, in the source driver IC 14b, since the transistor 473b1 and the transistor group 521c (n + 1) are arranged close to each other, they form a highly accurate current mirror circuit. From the above, the output current of the unit transistor group 521cn of the source driver IC 14a substantially matches the output current of the unit transistor 521c (n + 1) of the source driver IC 14b. Therefore, a boundary between the source driver IC 14a and the source driver IC 14b on the screen 50 does not occur.
[0702]
As described above, the source driver IC 14 of the present invention is greatly characterized in that the source driver IC 14 includes the transistor 473b for flowing the reference current to the left and right of the chip. For example, as shown in FIG. 207, it is apparent that the case where the source driver IC 14 includes the transistor 473b on only one side is considered. In the configuration of FIG. 207, as shown in FIG. 208, since the unit transistor group 521c1 is close to the transistor 473b, a high-accuracy current mirror circuit is configured. However, the unit transistor group 521cn separated by a distance D from the transistor 473b (D is close to the width of the IC chip) and the transistor 473b do not have the accuracy of the current mirror circuit.
[0703]
When a plurality of source driver ICs 14 having the configuration of FIG. 208 are arranged as shown in FIG. 207, for example, when a plurality of transistors 4 of the source driver IC 14a are arranged as shown in FIG. Even if the same reference current Ic flows through the transistor 473b of the IC 14b, as shown in FIG. 209, a gradient occurs in the magnitude of the output current at the terminals 681a and 681n. Therefore, a boundary occurs between the screen 50a driven by the source driver IC 14a and the screen 50b driven by the source driver IC 14b.
[0704]
In the present invention, as shown in FIG. 210, the source driver IC 14 is formed or arranged with transistors 473b (473b1, 473b2) for passing a reference current to the left and right of the chip. FIG. 211 shows a specific circuit configuration.
[0705]
In the embodiment of FIG. 228, the currents Ic1 and Ic2 flowing through the transistors 473a and 473b of the source driver IC 14 can be made equal by increasing the degree of the external resistance and the accuracy of the reference voltage Vs and the like. Therefore, the transistor 473b and the transistor groups 521c1, 521cn, 521c (n + 1), and 521c (2n) constituting the current mirror circuit can accurately make the same output current at the same gradation. Therefore, even when the screen 50 is driven by a plurality of source driver ICs (circuits) 14, boundaries between the source driver ICs (circuits) 14 are not visible. Needless to say, the currents Ic1 and Ic2 may be generated by a reference current circuit formed outside the IC chip and supplied to the transistor 473b.
[0706]
The resistors R11a and R12a are formed (designed) to have a predetermined ratio of resistance or preferably the same resistance. Similarly, the resistor R21a and the resistor R22a are formed (designed) to have a predetermined ratio of resistance or preferably the same resistance. The same applies to the set of the resistors R11b and R12b, and the set of the resistors R21b and R22b. Here, for ease of explanation, it is assumed that the resistors R11a, R12a, R21a, R22a, R11b, R12b, R21b, and R22b are designed (formed) to have the same resistance value. .
[0707]
The resistors R11a and R12a are formed or arranged close to each other. Similarly, the resistors R21a and R22a are formed or arranged close to each other, and the resistors R11b and R12b are formed or arranged close to each other. Similarly, the resistors R21b and R22b are formed or arranged close to each other. Each resistor is a polysilicon resistor or a diffusion resistor. The value of a resistor formed (configured) in an IC chip has a characteristic that the relative ratio of resistors arranged close to each other can be accurately formed. However, the absolute values often have no precision.
[0708]
The reference current source of the source driver IC 14 is often formed at both ends of the IC chip. However, the distance between the two reference current sources is at most about 20 mm. Therefore, the resistance difference between the resistors R11a and R21a of the source driver IC 14a is often small. However, in many cases, the absolute values of the resistances R11a and R21a of the source driver IC 14a and the resistances R11b and R21b of the source driver IC 14b differ greatly from each other. This is because, even if the source driver ICs 14a and 14b are formed on the same wafer, the formation positions of the ICs often differ greatly.
[0709]
In order to facilitate the description, as an example, the description will be made on the assumption that the resistance values of the resistance 11Ra, the resistance R12a, the resistance R21a, and the resistance R22a of the source driver IC 14a are equal and 50 (KΩ). Further, the description will be made on the assumption that the resistance values of the resistors R11b, R12b, R21b, and R22b of the source driver IC 14b are equal and 75 (KΩ). That is, it is assumed that the internal resistance of the source driver IC 14a and the internal resistance of the source driver IC 14b have different absolute values, and the relative resistance values of the internal resistances of the source driver ICs are equal.
[0710]
In FIG. 229, one terminal of the resistors R11a, R21a, R11b, and R21b is connected to the voltage Vp. The reference voltage Vs is applied to the operational amplifier 522. In this respect, the configuration is the same as that of FIG. 228. The difference between FIG. 229 and FIG. 228 is that in FIG. 228, the resistor R1 is an external resistor. 229 is that the built-in resistors of the adjacent source driver ICs are connected in cascade by the connection wiring 2291 in FIG.
[0711]
The resistor R22a of the source driver IC 14a and the resistor R11b of the source driver IC 14b are electrically connected by a connection line 2291. The connection wiring 2291c is, for example, a wiring pattern formed on the substrate 71. Therefore, the resistance connected to the operational amplifier 522b of the source driver IC 14a is R11b + R22a = 75 (KΩ) +50 (KΩ) = 125 (KΩ). Further, the resistor R21a of the source driver IC 14a and the resistor R12b of the source driver IC 14b are electrically connected by a connection wiring 2291b. Therefore, the resistance connected to the operational amplifier 522a of the source driver IC 14b is R11b + R22a = 75 (KΩ) +50 (KΩ) = 125 (KΩ).
[0712]
The resistance connected to the operational amplifier 522b of the source driver IC 14a and the operational amplifier 522a of the source driver IC 14b is equal to 125 (KΩ), and the applied reference voltages Vs and Vp are also the same. Therefore, the current Ic2 flowing to the transistor 473b2 of the source driver IC 14a in FIG. 229 is equal to the current Ic1 flowing to the transistor 473b1 of the source driver IC 14b. Therefore, the program current flowing through the transistor group 521cn of the source driver IC 14a is equal to the program current flowing through the transistor group 521c (n + 1) of the source driver IC 14b.
[0713]
With the configuration of FIG. 229, the program output current between the adjacent source driver ICs 14 can be equalized without using an external resistor as shown in FIG. That is, even if the absolute value of the resistor R in the source driver IC 14 varies, the reference current can be equalized by self-alignment. Therefore, even when a plurality of the source driver ICs 14 of the present invention are mounted on the substrate 71, cascade connection of the source driver ICs can be realized only by mounting, without any adjustment.
[0714]
Note that the resistance R in the source driver IC 14 may be adjusted by trimming so as to have a predetermined absolute resistance value. Further, it may be adjusted so that the relative resistance value of a set such as the resistors R11a and R12a and the resistors R21a and R22a becomes a predetermined relative value.
As shown in FIG. 229, the built-in resistor R11a and the resistor R12a at the end of the source driver 14a are short-circuited by a wiring 2291a. Further, the internal resistor R21b and the resistor R22b at the end of the source driver 14b are short-circuited by the wiring 2291d.
[0715]
The internal resistor R11a and the resistor R12a at the end of the source driver 14a are connected by a connection wiring 2291a. The resistance connected to the operational amplifier 522a of the source driver IC 14a is R11a + R12a = 50 (KΩ) +50 (KΩ) = 100 (KΩ). The resistance connected to the operational amplifier 522b of the source driver IC 14a is R21b + R22a = 75 (KΩ) +50 (KΩ) = 125 (KΩ). Therefore, the reference current Ic1 and the reference current Ic2 of the source driver IC 14a have different values. Therefore, the program output current of Iout1 of the source driver IC 14a and the program output current of Ioutn of the source driver IC 14a have different values. However, since Iout1 is located at the edge of the screen 50, it is not visually recognized even if the brightness of the edge of the screen 50 is different from the center of the screen 50. However, the brightness needs to change smoothly from the center to the edge of the screen 50.
[0716]
Similarly, the internal resistor 21b and the resistor 22b at the end of the source driver 14b are connected by a connection wiring 2291d. The resistance connected to the operational amplifier 522b of the source driver IC 14b is resistance 21b + resistance 22b = 75 (KΩ) +75 (KΩ) = 150 (KΩ). The resistance connected to the operational amplifier 522a of the source driver IC 14b is R11b + R12b = 75 (KΩ) +50 (KΩ) = 125 (KΩ). Therefore, the reference current Ic1 and the reference current Ic2 of the source driver IC 14b have different values. Therefore, the program output current of Iout (n + 1) of the source driver IC 14b is different from the program output current of Iout (2n) of the source driver IC 14b. However, since Iout (2n) is located at the edge of the screen 50, it is not visually recognized even if the brightness of the edge of the screen 50 is different from the center of the screen 50.
[0717]
As shown in FIG. 230, the program current from the transistor group 521c can be adjusted by connecting a resistor 491a to the resistor R12a and connecting a resistor 491b to the resistor R22b. Good. Further, the resistors R12a, R22a and the like may be electronic regulators or the like. Needless to say, the above items may be applied to the resistors R22a and R12b.
[0718]
FIGS. 228, 229, and 230 show a configuration in which each source driver circuit 14 has a built-in resistor. The present invention is not limited to this. For example, as shown in FIG. 231, the same resistance value R (R1, R2, R3, R4) may be built in the source driver IC 14a. The resistors R (R1, R2, R3, R4) are arranged close to each other. By arranging them close to each other, the relative value of the resistance value can be accurately formed. The resistors (R1, R2, R3, R4) may be adjusted by laser trimming so that the absolute values are equal. Further, the relative values of the resistors may be adjusted by trimming so as to be equal.
[0719]
The resistances R3 and R4 of the source driver IC 14a are output via terminals a2 and a4. This output is input to the source driver IC 14b from the terminals b2 and b3 of the source driver IV14b. With the above configuration, the resistor R3 in the source driver IC 14a is connected to the operational amplifier 522a of the source driver IC 14b, and a constant current circuit is configured. Further, the resistor R4 in the source driver IC 14a is connected to the operational amplifier 522b of the source driver IC 14b to form a constant current circuit.
[0720]
The reference voltage Vs is also input to the source driver IC 14a, and is output to the source driver IC 14b via the terminal a1 of the source driver IC 14a. The output reference voltage Vs is input from the terminal b1 of the source driver IC 14b to the source driver IC 14b.
[0721]
In the above embodiment, the currents flowing through the transistors 473b1 and 473b2 are assumed to be the same. However, in FIG. Give an explanation.
[0722]
In the configuration of FIG. 210, the unit transistor group 521cn of the source driver IC 14a is close to the transistor 473b2, so that an accurate current mirror circuit is configured. Further, since the unit transistor group 521c1 of the source driver IC 14b is close to the transistor 473b1, an accurate current mirror circuit is configured. Therefore, by adjusting the reference current Ic2 of the source driver IC 14a and the reference current Ic1 of the source driver IC 14b, the output current of the unit transistor group 521cn of the source driver IC 14a and the output current of the unit transistor group 521c1 of the source driver IC 14b are adjusted. be able to.
[0723]
Therefore, even when the output current of the source driver IC 14a and the output current of the source driver IC 14b have a gradient as shown in FIG. 209, the reference current Ic2 of the source driver IC 14a or (and) the reference current Ic1 of the source driver IC 14b is adjusted. Can be adjusted so that the output current is continuous between the screens 50a and 50b as shown in FIG. Of course, by making the reference current Ic1 and the reference current Ic2 the same, it is needless to say that the boundary between the screen 50a and the screen 50b can be prevented.
[0724]
That is, in the present invention, by configuring the reference current Ic1 of the transistor 473b1 and the reference current Ic2 of the transistor 473b2 to be adjustable, the boundary between the screens 50a and 50b can be prevented from occurring.
[0725]
Note that in the above description, the number of the transistor 473b is one. However, it is preferable that the transistor 473b be formed in a plurality to form the transistor group 521b. The transistor 521b includes a plurality of transistors 473b. Further, it is preferable that the size and shape of the transistor 473b of the transistor group 521b be the same shape and size as those of the unit transistor 484. Further, it is preferable that the number of the transistors 473b in the transistor group 521b be equal to the number of the unit transistors 484 in the transistor 521c. Further, it is preferable to form a plurality of blocks of the transistor group 521b.
[0726]
Alternatively, the total area of the transistors 473b in the transistor group 521b is preferably approximately equal to the total area of the unit transistors 484 included in the unit transistor group 521c. Further, it is preferable to form a plurality of blocks of the transistor group 521b.
[0727]
FIG. 215 shows an arrangement of the transistor 483b in the transistor group 521b. In one transistor group 521b, 63 transistors 473b of the same number as the unit transistors 484 of the unit transistor group 521c are formed. Of course, the number of transistors 473b in one transistor group 521b is not limited to 63. When the number of unit transistors 484 of the unit transistor group 521c is constituted by the number of gradations −1, the number of transistors 473b in the transistor group 521b is formed by the number of gradations −1 or the same or similar number. Further, the present invention is not limited to the configuration in FIG. 215, and may be formed or arranged in a matrix as shown in FIG.
[0728]
The above configuration is schematically shown in FIG. The unit transistor groups 521c are arranged in parallel by the number of output terminals. A plurality of transistor groups 521b are formed on both sides of the unit transistor group 521c. The gate terminal of the transistor 473b of the transistor group 521b and the gate terminal of the unit transistor 484 of the unit transistor group 521c are connected by a gate wiring 581.
[0729]
The above description has been made with reference to the single-color source driver IC 14 for the sake of simplicity, but it is originally configured as shown in FIG. That is, in the transistor group 521b and the unit transistor group 521c, red (R), green (G), and blue (B) transistor groups are alternately arranged (in FIG. 214, the transistor group with a suffix R is red). (R), the transistor group with the suffix G is for green (G), and the transistor group with the suffix B is for blue (B)). As described above, by arranging the RGB transistor groups alternately, output variations between RGB are reduced. This configuration is also an important requirement as a layout in the source driver IC 14.
[0730]
In FIG. 228, the reference current Ic is generated by the operational amplifier 552 or the like, but the present invention is not limited to this. Instead of the volume, the reference current Ic may be adjusted by the volume. The transistor 473b may be formed using a plurality of transistors as in FIG. 62, and may be a transistor group 521b1 and a transistor 521b2. Further, a fixed resistor may be used.
[0731]
Consideration is also given to the arrangement of the unit transistors 484 in the transistor group 521c. Note that the following items regarding the arrangement and configuration of the unit transistors 484 and the like also apply to the transistor 473a of the transistor group 521a and the transistor 473b of the transistor group 521b.
[0732]
The unit transistor group 521c needs to be arranged or formed regularly. Further, the unit transistors 484 in the unit transistor group 521c also need to be formed or arranged regularly. For example, if the unit transistor 484 is missing, the characteristics of the unit transistor 484 around the unit transistor 484 will be different from the characteristics of the other unit transistors 484. Further, it is necessary to form or arrange the layout on the gate line of the transistor in a regular manner.
[0733]
FIG. 217 schematically illustrates the arrangement of the unit transistors 484 in the unit transistor group 521c in the output stage. 63 unit transistors 484 expressing 64 gradations are regularly arranged in a matrix. However, if 64 unit transistors 484 are provided, they can be arranged in 4 columns × 16 rows. However, since there are 63 unit transistors 484, one portion is not formed (shaded portion). Then, the characteristics of the unit transistors 484a, 484b, 484c around the hatched portion are manufactured differently from the other unit transistors 484.
[0734]
In order to solve this problem, the present invention forms or arranges a dummy transistor 1341 in a hatched portion. Then, the characteristics of the unit transistors 484a, 484b, and 484c match those of the other unit transistors 484. That is, in the present invention, the unit transistors 484 are formed in a matrix by forming the dummy transistors 1341. Further, the unit transistors 484 are arranged so as not to be applied in a matrix. Alternatively, the unit transistors 484 are arranged so as to have line symmetry.
[0735]
In order to represent 64 gradations, 63 unit transistors 484 are arranged in the transistor group 521c, but the present invention is not limited to this. The unit transistor 484 may further include a plurality of sub-transistors.
[0736]
FIG. 218 (a) shows a unit transistor 484. FIG. 218 (b) shows a unit transistor 484 including four sub-transistors 12181. The output current obtained by adding the plurality of sub-transistors 2181 is set to be the same as that of the unit transistor 484. That is, the unit transistor 484 is constituted by four sub-transistors 2181.
[0737]
Note that the present invention is not limited to the configuration in which the unit transistor 484 includes four sub-transistors 2181, and may employ any configuration as long as the unit transistor 484 includes a plurality of sub-transistors 2181. However, the sub-transistors 2181 are configured to output the same size or the same output current.
[0738]
In FIG. 218, S indicates a source terminal of the transistor, G indicates a gate terminal of the transistor, and D indicates a drain terminal of the transistor. In FIG. 218 (b), the sub-transistors 2181 are arranged in the same direction. In FIG. 218 (c), the sub-transistors 2181 are arranged in different directions in the row direction. In FIG. 218 (d), the sub-transistors 2181 are arranged in different directions in the column direction and are arranged so as to be point-symmetric. 218 (b), FIG. 218 (c), and FIG. 218 (d) all have regularity.
[0739]
FIGS. 218 (a), (b), (c), and (d) are layouts, but the sub-transistor 2181 may be connected in series as the unit transistor 484 as shown in FIG. 218 (e). Further, the unit transistors 484 may be connected in parallel as shown in FIG.
[0740]
The characteristics often differ when the formation direction of the unit transistor 484 or the sub-transistor 2181 is changed. For example, in FIG. 218 (c), the unit transistor 484a and the sub-transistor 2181b have different output currents even if the voltage applied to the gate terminal is the same. However, in FIG. 218 (c), the same number of sub-transistors 2181 having different characteristics are formed. Therefore, variations in transistors (units) are reduced. Further, by changing the direction of the unit transistor 484 or the sub-transistor 2181 having a different forming direction, the characteristic difference is interpolated, and the effect of reducing the variation of the transistor (one unit) is exerted. Needless to say, the above matter also applies to the arrangement of FIG.
[0741]
Therefore, as illustrated in FIG. 219 and the like, the direction of the unit transistor 484 is changed, and the characteristics of the unit transistor 484 formed in the vertical direction as the transistor group 521c and the characteristics of the unit transistor 484 formed in the horizontal direction are interpolated. Thus, variation in the transistor group 521c can be reduced.
[0742]
FIG. 219 shows an embodiment in which the formation direction of the unit transistor 484 is changed for each column in the transistor group 521c. FIG. 220 shows an embodiment in which the formation direction of the unit transistors 484 is changed for each row in the transistor group 521c. FIG. 221 shows an embodiment in which the formation direction of the unit transistor 484 is changed for each row and column in the transistor group 521c. Note that the dummy transistor 1341 is also formed or arranged according to this configuration requirement.
[0734]
In the above embodiment, the unit transistors having the same size or the same current output are configured or formed in the transistor group 521c (see FIG. 222B). However, the present invention is not limited to this. As shown in FIG. 222A, the 0th bit (switch 641a) connects (forms) one unit transistor 484a. The first bit (switch 641b) connects (forms) two unit transistors 484b. The second bit (switch 641c) connects (forms) four unit transistors 484c. The third bit (switch 641d) connects (forms) eight unit transistors 484d. The fourth bit (not shown) connects (forms) 16 unit transistors 484a. The fifth bit (not shown) may connect (form) 32 unit transistors 484a. Note that, for example, a 16-unit transistor is a transistor that outputs 16 unit transistors 484 of current.
[0744]
The unit transistor of * unit (* is an integer) can be easily formed by proportionally changing the channel width W (keeping the channel length L constant). However, actually, even if the channel width W is doubled, the output current often does not double. In this method, a channel width W is determined by an experiment in which a transistor is actually manufactured. However, in the present invention, even when the channel width W deviates from the proportional condition, it is expressed as proportional.
[0745]
As shown in FIGS. 48 and 166, the present invention controls the current flowing through the unit current source 484 to generate the program current Iw according to the video data. The unit current source 484 includes a transistor. These transistors are densely formed or arranged as a transistor group 521 in an IC chip. A random variation occurs in the transistor 484 constituting the unit current. This random variation is caused by the variation (processing accuracy) of etching in the IC process and the shape of the transistor. Other variations in characteristics (especially output current) are caused by the distribution of transistors in the IC chip.
[0746]
In FIG. 64, the transistor group 521f is formed (arranged) of 32 transistors densely. The output current of the transistor group 521f tends to differ depending on the position of the IC chip. If the output currents of all 32 transistors are large (or small), the accuracy of the program current Iw is determined by the transistor group 521f. Therefore, even if the transistors 484 constituting each transistor group 521 have individual variations, the current value of the sum (for example, the addition of 32 unit current sources 484) is consistent between the terminals. preferable.
[0747]
In FIGS. 48 and 166, since the single transistor 484 is illustrated, the drawings are complicated. 48 and 166 are illustrated as in FIG. 299 for easy understanding. The number written in each transistor group 521 is the number of transistors through which a unit current flows. For example, the transistor group 521a (in this case, the number of transistors as the unit current source 484 is one, so it may not be appropriate to call it a group. However, for ease of explanation, it is called a transistor group). Has one unit transistor formed (formed).
[0748]
Similarly, the transistor group 521b has two transistors configured (formed). The transistor group 521c includes four transistors, the transistor group 521c includes four transistors, the transistor group 521d includes eight transistors, and the transistor group 521e includes sixteen transistors. , And 32 transistors are configured in the transistor group 521f.
[0749]
As the analog switch 481, a switch corresponding to D0 of video (image) data is referred to as a switch 481a, and a switch corresponding to D1 is referred to as a switch 481b. The switch corresponding to D2 is referred to as a switch 481c, and the switch corresponding to D3 is referred to as a switch 481d. Similarly, a switch corresponding to D4 is referred to as a switch 481e, and a switch corresponding to D5 is referred to as a switch 481f.
[0750]
As described above, when the switch 481 is turned on and off, the sum of the unit current sources corresponding to the image data flows through the internal wiring 483, which becomes the program current Iw. Note that, for easy understanding, the drawings are described as imagining an in-chip layout of each transistor group 521. That is, in FIG. 299, the transistor group 521f is arranged at a position near the output terminal 681 connected to the source signal line 18, and then the transistor group 521e, the transistor group 521d, the transistor group 521c, and the transistor group 521b are laid out. The transistor group 521a is laid out at a position farthest from the output terminal 681 (see FIG. 322). However, the above is for easy understanding, and it goes without saying that the layout design of the IC chip is more complicated.
[0751]
The transistor group 521 shown in FIG. 299 is connected to one output terminal (in the present invention, the transistor group 521 for flowing IwH in the high gradation region, IwL in the low gradation region, and IwK for the raising current is more complicated. For ease of explanation, it is assumed that the configuration in FIG. 299 is connected to one output terminal), which is the program current Iw. However, if the transistor groups 521 are arranged too regularly, there will be output terminals where the program current Iw becomes larger than specified.
[0752]
The configuration of the present invention that addresses this problem is the configuration in FIG. Specifically, it has two transistor groups 521f (521f1, 521f2) composed of 32 unit transistors. Further, there are also two transistor groups 521e (521e1, 521e2) each composed of 16 unit transistors. The arrangement of the transistor group 521 is, in order from the output terminal 681, a transistor group 521f1, a transistor group 521e1, a transistor group 521d, a transistor group 521c, a transistor group 521b, a transistor group 521a, a transistor group 521f2, and a transistor group 521e2 (see FIG. 323). FIG. 323 is a conceptual diagram of the layout of the source driver IC 14.)
[0753]
Further, as shown in FIG. 329, the R, G, and B transistor groups 521 may be arranged regularly. Further, as shown in FIG. 330, the transistor group 521H on the high gradation side and the transistor group 521L on the low gradation side may be arranged regularly in RGB.
[0754]
Switching between the transistor group 521f1 and the transistor group 521f2 is performed by the selection switch 3001a. When the selection switch 3001a is set to the a side, the transistor group 521f1 is selected, and when the selection switch 3001a is set to the b side, the transistor group 521f2 is selected.
When the selection switch 3001b is set to the a side, the transistor group 521e1 is selected, and when the selection switch 3001b is set to the b side, the transistor group 521e2 is selected.
In the above embodiment, two transistor groups 521f and 521e are formed or arranged. However, the present invention is not limited to this, and three or more transistor groups may be formed or arranged. In this case, the selection switch 3001 is a three-input one selection switch. The plurality of transistor groups 521 to be formed or arranged is not limited to the transistor group 521f and the transistor group 521e, and a plurality of other transistor groups 521 may be formed. However, as the number of the unit current sources 484 increases, the influence on the output variation due to the bias of the transistor characteristics increases. Therefore, it is preferable to form or arrange a plurality of transistor groups 521 having a large number of unit transistors. Further, the image is easily noticeable when there is a variation in the halftone display. Therefore, it is preferable to form or arrange a plurality of transistor groups 521 that contribute to halftone display. In the case of 64 gradation display (the total number of transistors is 63 (1 + 2 + 4 + 8 + 16 + 32)) in FIG. 299, the transistor group 521e (the number of unit current sources is 16) and the transistor group 521f (the number of unit current sources is 32) Applicable. The transistor group 521e outputs a current at a gray scale of 16 or higher, and the transistor group 521f outputs a current at a gray scale of 32 or higher. This is because this range corresponds to the halftone display. Therefore, assuming that the number of gray scales is Y, it is preferable to form or arrange at least one or more of the transistor groups 521 among the transistor groups 521 that operate at Y / 5 or more and (2Y) / 3 gray scales or less.
[0755]
The selection switch 3001 is switched for each field (one frame) (expressed as 1F) on the a side (select the transistor group 521f1 and the transistor group 521e1) and on the b side (select the transistor group 521e1 and the transistor group 521f2). Switch. This conceptual diagram is shown in FIG. Note that FIG. 324 shows a display in which the transistor group 521f1 and the transistor group 521f2 are switched for ease of description. The description of the transistor group 521f1 or the transistor group 521f2 on the display screen 50 illustrates a state in which the program current Iw from the transistor group 521f1 or the transistor group 521f2 is output to the source signal line 18 and written to the pixel 16. ing. Of course, in the display of a natural image, the other transistor groups 521 also operate, so that the state is not as shown in FIG. For the sake of explanation, FIG. 324 shows that the screen is a white raster display, and further, that the grayscale white raster display of the transistor group 521f and the like is performed. Note that the description of the above drawings is the same in other drawings (FIGS. 325 and 326) and the like.
[0756]
In FIG. 324, an image is displayed by selecting the transistor group 521f1 in the first F and selecting the transistor group 521f2 in the second F. Also, the transistor group 521f1 is selected in the third and subsequent steps, and the transistor group 521f2 is displayed in the fourth step. As described above, the variation of the output current can be averaged by operating the plurality of transistor groups 521 alternately and writing the program current Iw to the pixels, and uniform image display can be realized.
In the embodiment of FIG. 324, an image is displayed with the output current of the transistor group 521f1 in the first F, and the transistor group 521f2 is displayed in the second F. However, the present invention is not limited to this. For example, an image is displayed by the output current of the transistor group 521f1 in the first F and the second F, an image is displayed by the output current of the transistor group 521f2 in the third F and the fourth F, and the output current of the transistor group 521f1 is displayed in the fifth F and the sixth F. May be used to display an image. That is, in the present invention, by operating the plurality of transistor groups 521 alternately, the currents written to the pixels 16 are averaged, and variations in image display are reduced.
[0757]
FIG. 324 realizes uniform display by selecting and switching the transistor group 521 to be written to the pixel 16 for each field (frame). However, the present invention is not limited to this. As illustrated in FIG. 325, the transistor group 521 that outputs the program current Iw to be written to the pixel may be switched for each pixel row (or a plurality of pixel rows). (A) of FIG. 325 conceptually illustrates a writing state of the first F screen 50. In (a) of FIG. 325, the output current of the transistor group 521f1 is written to the odd pixel row, and the output current of the transistor group 521f2 is written to the even pixel row. In the second F, as shown in FIG. 325 (b), the output current of the transistor group 521f1 is written to the even-numbered pixel row, and the output current of the transistor group 521f2 is written to the odd-numbered pixel row. This operation is alternately repeated in the subsequent fields (frames).
[0758]
In FIG. 325, the transistor group 521 to be written to the pixel 16 is switched every one pixel row or a plurality of pixel rows, and the transistor group 521 to be written to the pixel 16 is switched every one frame (field) or a plurality of frames (fields). By operating as described above, the current written to the pixel 16 can be averaged, and the variation in image display can be reduced. That is, in FIG. 325, the transistor group 521 to be written to the pixel row 16 is changed every horizontal scanning period (the transistor group 521 is changed in synchronization with the horizontal synchronization signal). Of course, the transistor group 521 may be changed for each of a plurality of pixel rows (a plurality of horizontal scanning periods) (that is, the cycle is two horizontal scanning periods). The above is the same in FIG.
[0759]
In FIG. 325, uniform display is realized by selecting and switching the transistor group 521 to be written to the pixel 16 for each pixel row and switching the transistor group 521 to be written to the pixel 16 for each frame (field). However, the present invention is not limited to this. As shown in FIG. 326, the transistor group 521 that outputs the program current Iw to be written to the pixel may be switched for each pixel column (or a plurality of pixel columns).
[0760]
FIG. 326 (a) conceptually illustrates the writing state of the first F screen 50. In (a) of FIG. 326, the output current of the transistor group 521e1 is written to the odd pixel column, and the output current of the transistor group 521e2 is written to the even pixel column. In the second F, as shown in FIG. 326 (b), the output current of the transistor group 521e1 is written to the even pixel column, and the output current of the transistor group 521e2 is written to the odd pixel column. This operation is alternately repeated in the subsequent fields (frames). In FIG. 326, the transistor group 521 written to the pixel row 16 is changed every one vertical synchronization period (the transistor group 521 is changed in synchronization with the vertical synchronization signal). The cycle is two vertical scanning periods. Needless to say, the transistor group 521 may be changed every plural vertical scanning periods. The above is the same in FIG.
[0761]
In FIG. 326, the transistor group 521 to be written to the pixel 16 is switched for each pixel column or a plurality of pixel columns, and the transistor group 521 to be written to the pixel 16 is switched for each frame (field) or each of a plurality of frames (fields). By operating as described above, the current written to the pixel 16 can be averaged, and the variation in image display can be reduced.
Note that FIG. 325 switches the transistor group 521 to be written to the pixel 16 for each pixel row, and FIG. 326 switches the transistor group 521 to be written to the pixel 16 for each pixel column. However, the present invention is not limited to this. For example, FIG. 325 and FIG. 326 may be combined. That is, the transistor group 521 to be written to an adjacent pixel row is changed, and the transistor group 521 to be written to an adjacent pixel column is changed. Needless to say, the present invention is not limited to adjacent pixel rows or pixel columns, and the transistor group 521 to be written to the pixel 16 may be changed in a group of a plurality of pixel rows or a plurality of pixel columns. Further, the transistor group 521 written to the pixel 16 by R, G, and B may be changed.
[0762]
It is needless to say that the concept of switching the transistor group 521 between a field (frame), a pixel row, and a pixel column can be applied to other embodiments of the present invention.
[0763]
In the embodiment of FIG. 300, the transistor group 521 including the unit current sources 484 having the number of gradations or more is formed or arranged (that is, a plurality of transistor groups 521 overlapping the gradation display are formed). The reason why the output variation of the transistor group 521 is unevenly generated is that the unit transistors constituting the transistor group 521 are arranged too densely in the chip. Needless to say, the characteristics of the unit transistors become more uniform due to the denseness. However, there are cases where mobility or the like is specifically formed at a certain position in the chip. In this case, if one transistor group 521 is arranged at this unique location, the grayscale output current becomes abnormal. When the number of unit transistors constituting the transistor group 521 is small, the output current is small even if the transistor group 521 is arranged in this unique place, and therefore, the transistor group 521 does not stand out in natural image display. However, when the number of unit transistors 484 included in the transistor group 521 is large (in FIG. 299, the transistor group 521f, the transistor group 521e, and the like), the output current is large, and an unnatural image display is performed.
[0764]
The embodiment in FIG. 301 is an embodiment in which a transistor group 521f having a large number of unit transistors 484 is divided into a plurality and arranged. FIG. 327 shows a conceptual diagram of the layout in the chip 14. That is, the transistor group 521 corresponding to the one-bit grayscale signal is divided into a plurality of sub-transistor groups 521. Note that the sub-transistor group 521 to be divided is not limited to being equally divided (in FIG. 301, the unit transistor 484 is divided into 16 by 16). For example, the transistor group 521f1 may be configured from 20 unit transistors, and the transistor group 521f2 may be configured from the remaining 12 unit transistors. Needless to say, the above items can be applied to other embodiments of the present invention.
[0765]
The transistor group 521f includes 32 unit transistors 484. In FIG. 301, the transistor is divided into two, and divided into a transistor group 521f1 and a transistor group 521f2 each including 16 unit transistors. Further, the formation positions of the transistor group 521f1 and the transistor group 521f2 are laid out separately in the chip. Specifically, as shown in FIG. 327, a transistor group 521e is arranged between the transistor group 521f1 and the transistor group 521f2.
Note that the division is preferably performed in multiples of eight. This is because the layout becomes easy and the gradation control becomes easy.
[0766]
The operation in FIG. 301 is the same as in FIGS. 299 and 300. When the switch 481f is turned on, the program current Iw flows through the transistor groups 521f1 and 521f2. When the switch 481e is turned on, the program current Iw flows through the transistor group 521e. As described above, the corresponding switch 481 is ON / OFF controlled according to the image data, and the program current Iw flows through the corresponding transistor group 521 and is applied to the source signal line 18.
The embodiment of FIG. 302 is an embodiment in which the transistor group 521 is further divided into a larger number compared to FIG. The transistor group 521f includes 32 unit transistors 484. In FIG. 302, it is divided into four, and divided into a transistor group 521f1, a transistor group 521f2, a transistor group 521f3, and a transistor group 521f4 each including eight unit transistors. The transistor group 521e is also divided into a transistor group 521e1 and a transistor group 521e2. The layout positions of the transistor groups 521a, 521b, 521c, and 521d are also changed from those in FIG.
[0767]
The operation in FIG. 302 is the same as in FIGS. 299 and 300. When the switch 481f is turned on, the program current Iw flows through the transistor group 521f1, the transistor group 521f2, the transistor group 521f3, and the transistor group 521f4. When the switch 481e is turned on, a program current Iw flows through the transistor group 521e1 and the transistor group 521e2. As described above, the corresponding switch 481 is ON / OFF controlled according to the image data, and the program current Iw flows through the corresponding transistor group 521 and is applied to the source signal line 18.
[0768]
The above embodiment has been described by exemplifying a case of a single color display for easy explanation. Hereinafter, a description will be given by exemplifying color display using R, G, and B. In the following embodiments, three primary colors of RGB are illustrated, but the present invention is not limited to this, and may be replaced with three primary colors of cyan, yellow, and magenta. It goes without saying that the present invention can be applied to two-color display. Further, the present invention can be applied to six-color display of R, G, B, cyan, yellow, and magenta.
The following embodiments illustrate the case of color display, but it goes without saying that the layout, drive method, configuration, operation, and the like described in FIGS. 299, 300, and 301 can be combined. In addition, although the layout is expressed by R, G, and B, it can be considered as a single color. For example, the neighbor of R in FIG. 303 is G, and the neighbor is B. However, all of them may be considered as a single-color transistor group 521. In other words, the present invention reduces the output variation by dispersing the unit transistors constituting the transistor group 521 under certain conditions. Therefore, if it is considered that the output variation can be reduced by replacing the layout of the adjacent transistor group 521, the effect is exhibited even if it is not distinguished by RGB.
[0769]
FIG. 303 is a diagram in which the arrangements of FIGS. 48 and 166 are expressed in RGB. FIG. 328 shows a conceptual diagram of the layout. Note that the switches 481 and the like are omitted for ease of illustration. In addition, for ease of explanation, the symbol “abcdeff” is added to the layout position in the horizontal direction (short side direction of the chip) and “1 2 3” in the vertical direction (long side direction of the chip). The symbol "4 5 6" is added. Layout positions for explanation are expressed as “a1”, “d3”, and the like.
[0770]
FIG. 304 shows an embodiment of the present invention. RGB transistor groups 521 are arranged at three positions 1, 2, and 3, and are repeatedly laid out. For red (R), the transistor group 521f is arranged at “f1”, the transistor group 521e is arranged at “e2”, the transistor group 521d is arranged at “d3”, the transistor group 521c is arranged at “c1”, The transistor group 521b is arranged at “b2”, and the transistor group 521a is arranged at “a3”. As described above, the layout position is changed.
[0771]
For green (G), the transistor group 521f is arranged at "f2", the transistor group 521e is arranged at "e3", the transistor group 521d is arranged at "d1", and the transistor group 521c is arranged at "c2". The transistor group 521b is arranged at “b3”, and the transistor group 521a is arranged at “a1”. As described above, the layout position is changed.
[0772]
Similarly, for blue (B), the transistor group 521f is arranged at “f3”, the transistor group 521e is arranged at “e1”, the transistor group 521d is arranged at “d2”, and the transistor group 521c is arranged at “c3”. The transistor group 521b is arranged at “b1”, and the transistor group 521a is arranged at “a2”. As described above, the layout position is changed.
[0773]
As described above, the layout position of the transistor group 521 is not linearized as shown in FIG. 303, but is replaced by the “1”, “2”, and “3” positions. The bias of the characteristics of the transistor 484 is eliminated, and the variation of the program current Iw from each output terminal can be reduced.
Alternatively, as shown in FIG. 300, a plurality of transistor groups 521 may be formed or arranged and switched and selected at a 1F cycle or the like. Alternatively, the transistor group 521 may be divided as shown in FIGS. Needless to say, the arrangement of the transistor groups 521 may be interchanged. Needless to say, the above items can be applied to other embodiments of the present invention.
[0774]
Note that, as described above, the effect of reducing the variation of the output current by replacing the layout position is an effect that can be exhibited without using RGB as in FIG. Therefore, if it is considered that the output variation can be reduced by replacing the layout of the adjacent transistor group 521, the effect is exhibited even if it is not distinguished by RGB.
[0775]
FIG. 304 shows an embodiment in which the transistor group 521 is replaced with a set of three layout lines “1 2 3”, “4, 5, 6”. FIG. 305 shows an embodiment in which the transistor group 521 to be selected line by line is changed.
[0776]
Explaining by exemplifying red (R), the transistor group 521f is arranged at “f1”, the transistor group 521e is arranged at “e2”, the transistor group 521d is arranged at “d3”, and the transistor group 521c is “ The transistor group 521b is located at "b5", and the transistor group 521a is located at "a6". As described above, the layout position is changed.
[0777]
Similarly, by explaining green (G) as an example, the transistor group 521f is arranged at “f2”, the transistor group 521e is arranged at “e3”, the transistor group 521d is arranged at “d4”, and the transistor group 521c is arranged. Are arranged at “c5”, the transistor group 521b is arranged at “b6”, and the transistor group 521a is arranged at “a7”. As described above, the layout position of the transistor group 521 to be selected row by row is changed.
[0778]
The embodiment of FIG. 306 mainly includes a transistor group 521L (unit transistors 484 controlled by terminals L0 to L4 in FIG. 56) operating in low gray scale display and a transistor group 521H (H0 in FIG. 57) operating in high gray scale display. The layout positions of the unit transistors 484) controlled by the terminals H5 to H5 are changed.
[0779]
In FIG. 306, the red (R) transistor group 521L is arranged at the “a1” position, and the transistor group 521H is arranged at “b1”. The green (G) transistor group 521L is arranged at the “a2” position, and the transistor group 521H is arranged at the “b2” position. The blue (B) transistor group 521L is arranged at the “a3” position, and the transistor group 521H is arranged at the “b3” position.
[0780]
The next red (R) transistor group 521H is arranged at the “a4” position, and the transistor group 521L is arranged at “b4”. The green (G) transistor group 521H is arranged at the “a5” position, and the transistor group 521L is arranged at the “b5” position. The blue (B) transistor group 521H is arranged at the “a6” position, and the transistor group 521L is arranged at the “b6” position. The following is the repetition.
[0781]
In the layout of FIG. 306, when observing focusing on R, it can be seen that the arrangement of the transistor group 521H and the transistor group 521L of the output current circuit of the adjacent R is alternately changed (replaced). As described above, the output variation can be reduced by replacing the layout of the adjacent transistor group 521.
[0782]
The above is the case of RGB. If it is to be considered as a single color (if it is simply considered to change the layout position), the transistor group 521L is arranged at the “a1” position, the transistor group 521H is arranged at the “b1” position, and the transistor group 521H is arranged at the “b1” position. The layout may be such that the transistor group 521L is arranged at the “b2” position, the transistor group 521L is arranged at the “a3” position, and the transistor group 521H is arranged at the “b3” position (FIG. 308 shows the case of RGB). This is the case where RGB is not considered in FIG. 308).
[0783]
FIG. 307 shows an embodiment in which a plurality of sets of the transistor group 521L and the transistor group 521H are laid out in one row (“1 2 3 4 5...”). The transistor group 521 at the “a1” position and the “b1” position becomes an output of the source signal line 18 of R1 (red 1). The transistor group 521 at the “c1” position and the “d1” position becomes the output of the source signal line 18 of R2 (red 2). The transistor group 521 at the “e1” position and the “f1” position becomes the output of the source signal line 18 of R3 (red 3).
[0784]
Similarly, the transistor group 521 at the “a2” position and the “b2” position becomes the output of the source signal line 18 of G1 (green 1). The transistor group 521 at the “c2” position and the “d2” position becomes an output of the source signal line 18 of G2 (green 2). The transistor group 521 at the “e2” position and the “f2” position becomes the output of the source signal line 18 of G3 (green 3).
[0785]
Further, the transistor group 521 at the “a3” position and the “b3” position becomes the output of the source signal line 18 of B1 (blue 1). The transistor group 521 at the “c3” position and the “d3” position becomes the output of the source signal line 18 of B2 (blue 2). The transistor group 521 at the “e3” position and the “f3” position becomes the output of the source signal line 18 of B3 (blue 3). The following is similarly laid out repeatedly.
[0786]
The embodiment in FIG. 308 is an embodiment in which a transistor group 521L in a low gradation region and a transistor group 521H in a high gradation region are arranged in combination. FIG. 309 shows that unit transistors corresponding to each bit of the transistor group 521L in the low gradation region and unit transistors corresponding to each bit of the transistor group 521H in the high gradation region are alternately (distributed). This is an example. As described above, there are a variety of configurations for dispersing the arrangement of the transistor groups 521 of the present invention. By implementing the configuration of the present invention, variations in the output current Iw are eliminated, and uniform image display can be realized.
[0787]
As described above, a uniform image display can be realized by considering the arrangement of the transistor group 521 and the like. Further, even more uniform image display can be realized by implementing the driving method described below. However, it goes without saying that the driving method described below is effective even when implemented alone.
[0788]
First, description will be made with reference to FIG. The program current Iw is output by the number of the unit transistors 484 of the transistor group 521 that are in the operating state. When all the unit transistors 484 are off, the gray scale is 0. When all the unit transistors of the transistor group 521 are on, the gray scale is 63.
[0789]
In the gradation 32, the unit transistor 484 of the transistor group 521f is on (the switch 481f is on, and the other switches 481 are off). In the gradation 31, the unit transistors 484 of the transistor group 521a, the transistor group 521b, the transistor group 521c, the transistor group 521d, and the transistor group 521e are on (the switch 481f is off, and the other switches 481 are on). ).
[0790]
Therefore, the unit transistor 484 to be turned on is completely different between the gradation 32 and the gradation 31. Therefore, if there is a characteristic difference between a unit transistor of the transistor group 521f and a unit transistor of another transistor group 521, a gradation jump occurs. Further, the variation of the output current to each source signal line 18 becomes more noticeable.
[0791]
To address this problem, the present invention implements the driving method shown in FIG. Note that, for easy understanding, the gray scale 32 is illustrated as an example. The description “32” on the display screen 50 indicates that the display is a white raster display with a gradation of 32 (only the transistor group 521f is operating). The description “31” on the display screen 50 indicates that the display is a white raster display with a gradation of 31 (other than the transistor group 521f is operating). That is, in the first F, the gray scale 32 is displayed, in the second F, the gray scale 31 is displayed, and the gray scale 32 and the gray scale 31 are alternately and repeatedly displayed. In other words, image display is performed by operating another transistor group 521 without being fixed to one transistor group 521 to perform gradation display. As described above, by operating a large number of unit transistors 484 using a plurality of fields (frames) to display an image, output variation does not occur and uniform image display can be realized.
[0792]
The above operation is generally expressed as follows. In the first F, the video signal data is directly converted into on / off data of the switch 481. In the next 2F, after the data of the video signal is decremented by 1, the data is converted into the on / off data of the switch 481. In the next third F, the video signal data is directly converted into on / off data of the switch 481. In the next fourth F, the data of the video signal is decremented by 1, and then converted into ON / OFF data of the switch 481. The above operation is repeated to display an image. That is, the transistor group 521 that contributes to image display operates uniformly. In the gray scale 32, the transistor group 521f operates, and in the gray scale 31 decremented by 1, the other than the transistor group 521f operates. Therefore, the unit transistors 484 of all the transistor groups 521 operate, and the variation in output current in image display is greatly reduced. Further, the driving method is also simple because it is only necessary to determine whether or not the video signal is decremented by 1 in synchronization with the 1F signal. However, the gradation 0 cannot be decremented by 1 (the unit transistors 484 of all the transistor groups 521 are off). Therefore, the gray level 0 remains 0.
[0793]
The image display is an intermediate image display between the video signal and the minus one video signal. However, this difference is small. The image display is only in a state where the luminance is slightly lowered. As an effect, it is possible to realize a very uniform image display without displaying the characteristic variation of the transistor group 521.
[0794]
In the embodiment, the video signal is set to −1, but the present invention is not limited to this. The video signal may be incremented by one. That is, in the first F, the video signal data is directly converted into the on / off data of the switch 481. In the next second F, the data of the video signal is converted into ON / OFF data of the switch 481 after adding +1. In the next third F, the video signal data is directly converted into on / off data of the switch 481. In the next fourth F, the data of the video signal is converted into ON / OFF data of the switch 481 after adding +1. The above operation is repeated to display an image.
[0795]
Further, -1 and +1 may be combined. That is, in the first F, the video signal data is directly converted into the on / off data of the switch 481. In the next 2F, after the data of the video signal is decremented by 1, the data is converted into the on / off data of the switch 481. In the next third F, the video signal data is directly converted into on / off data of the switch 481. In the next fourth F, the data of the video signal is converted into ON / OFF data of the switch 481 after adding +1. An image is displayed by repeating the above operation in a 4F cycle.
[0796]
In addition, although the video signal is assumed to be -1, it is not limited to this. It may be -2 or more or +2 or more. The purpose of the present invention is to realize uniform image display by averaging over a plurality of fields (frames) by operating unit transistors 484 other than the unit transistors 484 of the transistor group 521 corresponding to a video signal. is there. Therefore, the present invention is not limited to the size that changes the original video signal.
[0797]
In FIG. 310, an image is displayed by selecting the transistor group 521f in the first F and selecting the transistor group 521 other than the transistor group 521f in the second F. Further, the transistor group 521f is repeatedly selected in the third and subsequent steps, and the transistor groups 521 other than the transistor group 521 are operated in the fourth F. As described above, the variation of the output current can be averaged by operating the plurality of transistor groups 521 alternately and writing the program current Iw to the pixels, and uniform image display can be realized.
[0798]
In FIG. 310, it is more appropriate to select and switch (or rather, change the unit transistors of the transistor group 521 to be turned on) the transistor group 521 to be written to the pixel 16 for each field (frame). It is more appropriate to operate the transistor 521 or add another transistor group 521. However, in order to facilitate the description, the expression “switching” is adopted) to realize uniform display. Was. However, the present invention is not limited to this. As illustrated in FIG. 311, the transistor group 521 that outputs the program current Iw to be written to the pixel may be switched for each pixel row (or a plurality of pixel rows). FIG. 311 (a) conceptually illustrates the writing state of the first F screen 50. FIG. In (a) of FIG. 311, the output current of the transistor group 521 f is written in the odd pixel row, and the output current of the transistor group 521 other than the transistor group 521 f is written in the even pixel row. In the second F, as shown in FIG. 311 (b), the output current of the transistor group 521f is written to the even-numbered pixel row, and the output current of the transistor group 521 other than the transistor group 521f is written to the odd-numbered pixel row. This operation is alternately repeated in the subsequent fields (frames).
It should be noted that the above embodiment only illustrates the gradation 32 for easy understanding. Generally, the video signal conversion described with reference to FIG. 310 is performed.
[0799]
In FIG. 311, the transistor group 521 to be written to the pixel 16 is switched for each pixel row or a plurality of pixel rows, and the transistor group 521 to be written to the pixel 16 is switched for each frame (field) or each of a plurality of frames (fields). By operating as described above, the current written to the pixel 16 can be averaged, and the variation in image display can be reduced.
[0800]
FIG. 311 realizes uniform display by selecting and switching the transistor group 521 to be written to the pixel 16 for each pixel row and switching the transistor group 521 to be written to the pixel 16 for each frame (field). However, the present invention is not limited to this. As illustrated in FIG. 312, the transistor group 521 that outputs the program current Iw to be written to the pixel may be switched for each pixel column (or a plurality of pixel columns). FIG. 311 (a) conceptually illustrates the writing state of the first F screen 50. FIG. In (a) of FIG. 311, the output current of the transistor group 521 f is written to the odd pixel column, and the output current of the transistor group 521 other than the transistor group 521 f is written to the even pixel column. In the second F, as shown in FIG. 311 (b), the output current of the transistor group 521f is written in the even pixel column, and the output current of the transistor group 521 other than the transistor group 521f is written in the odd pixel column. This operation is alternately repeated in the subsequent fields (frames).
[0801]
In FIG. 311, the transistor group 521 to be written to the pixel 16 is switched for each pixel column or a plurality of pixel columns, and the transistor group 521 to be written to the pixel 16 is switched for each frame (field) or each of a plurality of frames (fields). By operating as described above, the current written to the pixel 16 can be averaged, and the variation in image display can be reduced.
Note that FIG. 311 changes the transistor group 521 to be written to the pixel 16 for each pixel row, and FIG. 326 changes the transistor group 521 to be written to the pixel 16 for each pixel column. However, the present invention is not limited to this. For example, FIG. 311 and FIG. 312 may be combined. That is, the transistor group 521 to be written to an adjacent pixel row is changed, and the transistor group 521 to be written to an adjacent pixel column is changed. Needless to say, the present invention is not limited to adjacent pixel rows or pixel columns, and the transistor group 521 to be written to the pixel 16 may be changed in a group of a plurality of pixel rows or a plurality of pixel columns. Further, the transistor group 521 written to the pixel 16 by R, G, and B may be changed.
[0802]
It is needless to say that the concept of switching the transistor group 521 between a field (frame), a pixel row, and a pixel column can be applied to other embodiments of the present invention.
[0803]
Further, in the above-described embodiment, the description has been made as to the source driver IC 14, but the present invention is not limited to this. It goes without saying that the present invention can be applied to the source driver circuit 14 directly formed on the substrate 71 by the low-temperature polysilicon technology, the high-temperature polysilicon technology, the CGS technology, or the like.
[0804]
In the above embodiment, uniform display is realized by the source driver circuit (IC) 14 or by the driving method. The embodiment described below is a system in which a characteristic variation is insignificant by mainly considering a pixel arrangement of a display panel. Of course, further characteristic effects can be exhibited by combining with the manufacturing method described with reference to FIG. Further, by combining with the configuration and the driving method described in FIGS. 299 to 312 and the like, further characteristic effects can be exhibited. Further, by combining with other driving methods, configurations, specifications, and the like described in this specification, further characteristic effects can be exhibited.
[0805]
FIG. 313 is a pixel layout in the embodiment of the present invention. For ease of explanation, only one gate signal line 17a (G1, G2, G3,...) Is shown in the pixel 16. The source signal lines 18 (S1, S2, S3, S4,...) Are used. The pixel 16 is described as P, and its pixel position is indicated by (m, n). In addition, RGB is not expressed.
[0806]
In FIG. 313, the source signal lines 18 and the gate signal lines 17a are arranged linearly and in a matrix. The pixel P is connected to the gate signal line G3 with P (3,1), P (2,2), P (3,3), P (2,4), P (3,5). . Further, the gate signal line G4 is connected to P (4,1), P (3,2), P (4,3), P (3,4), P (4,5). FIG. 314 shows the pixel 16 to which the program current is written when the gate signal line 17a is selected in FIG. 313 for easy understanding.
[0807]
That is, in FIG. 314, when one gate signal line G is selected, the program current Iw is written into the pixels 16 at positions alternately shifted by one pixel row. The video current output from the source driver circuit 14 is controlled according to the pixel position to be written, as well as the source driver circuit 14.
[0808]
As shown in FIG. 313, the pixel row to be written is not linear (it is written in alternate vertical positions over two pixel rows). Therefore, even if the program current Iw output from the source driver circuit 14 varies, the staggered ( In FIG. 314, since the data is written in a staggered manner in two pixel rows, the variation is not conspicuous.
[0809]
FIG. 315 is a pixel layout according to the second embodiment of the present invention. In FIG. 315, the source signal lines 18 and the gate signal lines 17a are arranged linearly and in a matrix. Pixel P is connected to gate signal line G3 by P (3,1), P (3,2), P (2,3), P (2,4), P (3,5), P (3,6).・ ・ Connected to Also, P (4,1), P (4,2), P (3,3), P (3,4), P (4,5), P (4,6).・ Connected to FIG. 316 shows the pixel 16 to which the program current is written when the gate signal line 17a is selected in FIG.
[0810]
That is, in FIG. 316, when one gate signal line G is selected, the program current Iw is written to the pixel 16 which is alternately shifted by one pixel row every two pixel columns. The video current output from the source driver circuit 14 is controlled according to the pixel position to be written, as well as the source driver circuit 14.
[0811]
As shown in FIG. 315, the pixel row to be written is not linear (it is written in alternate vertical positions over two pixel rows). Therefore, even if the program current Iw output from the source driver circuit 14 varies, the staggered ( In FIG. 316, the data is written in a zigzag pattern in two pixel rows, so that the variation is not noticeable.
[0812]
FIG. 317 shows a case where the positions of the pixels 16 are delta-arranged in the direction of the gate signal line 17a. FIG. 317 shows that the source signal line 18 is formed linearly. The gate signal lines 17a are formed zigzag so as to be shifted by 1/2 pixel. Pixel P is connected to gate signal line G2 by P (2,1), P (2,2), P (2,3), P (2,4), P (2,5), P (2,6).・ ・ Connected to Also, P (3,1), P (3,2), P (3,3), P (3,4), P (3,5), P (3,6).・ Connected to FIG. 318 shows the pixel 16 to which the program current is written when the gate signal line 17a is selected in FIG. 317 for easy understanding.
[0813]
That is, in FIG. 318, when one gate signal line G is selected, the program current Iw is written to the pixel 16 at a position shifted by 1/2 pixel row alternately. The video current output from the source driver circuit 14 is controlled according to the pixel position to be written, as well as the source driver circuit 14.
[0814]
In FIG. 318, since the pixel row to be written is not linear (the pixel row is written in alternate vertical positions over 1/2 pixel row), even if the program current Iw output from the source driver circuit 14 varies, the variation does not occur. Inconspicuous.
[0815]
FIG. 319 shows an arrangement in which the position of the pixel 16 is shifted by one pixel in the direction of the gate signal line 17a. FIG. 319 shows that the source signal line 18 is formed linearly. The gate signal line 17a is formed in a zigzag manner for each pixel. The pixel P is connected to the gate signal line G3 by P (3,1), P (2,2), P (3,3), P (2,4), P (3,5), P (2,6). )... The gate signal line G3 includes P (4,1), P (3,2), P (4,3), P (3,4), P (4,5), P (3,6) ... are connected.
[0816]
That is, in FIG. 319, when one gate signal line G is selected, the program current Iw is written to the pixels 16 which are alternately shifted by one pixel row. The video current output from the source driver circuit 14 is controlled according to the pixel position to be written, as well as the source driver circuit 14. In FIG. 319, the pixel row to be written is not linear (it is written in alternate upper and lower positions). Therefore, even if there is a variation in the program current Iw output from the source driver circuit 14, the variation is inconspicuous.
[0817]
FIG. 320 shows a case where the positions of the pixels 16 are delta-arranged in the direction of the source signal line 17a. In FIG. 320, the gate signal line 17a is formed linearly. The source signal lines 18 are formed zigzag so as to be shifted by 1/2 pixel. Pixel P is connected to source signal line S2 by P (1,2), P (2,2), P (3,2), P (4,2), P (5,2), P (6,3).・ ・ Connected to Also, P (1,3), P (2,3), P (3,3), P (4,3), P (5,3), P (6,3)... Are connected to the source signal line S3.・ Connected to
[0818]
That is, in FIG. 320, when one gate signal line G is selected, the program current Iw is written to the pixel 16 at a position shifted by 1/2 pixel row alternately by one pixel row in the left-right direction. The video current output from the source driver circuit 14 is controlled according to the pixel position to be written, as well as the source driver circuit 14. FIG. 320 shows that the program row Iw output from the source driver circuit 14 varies because the pixel row to be written is not linear (the pixel row is written with a shift of 1/2 pixel in the horizontal direction over two pixel rows). Variation is not noticeable.
[0819]
FIG. 321 shows an arrangement in which the position of the pixel 16 is shifted by one pixel in the direction of the source signal line 18. In FIG. 321, the gate signal line 17a is formed linearly. The source signal lines 18 are formed in a zigzag manner for each pixel. Pixel P is connected to source signal line S3 by P (1,2), P (2,2), P (3,2), P (4,3), P (5,2), P (6,3). )... The source signal line S4 includes P (1,3), P (2,4), P (3,3), P (4,4), P (5,3), P (6,4) ... are connected.
[0820]
That is, in FIG. 321, when one gate signal line G is selected, the program current Iw is written to the pixel 16 at a position shifted by one pixel column alternately. The video current output from the source driver circuit 14 is controlled according to the pixel position to be written, as well as the source driver circuit 14. In FIG. 321, since the pixel column to be written is not linear (written at alternate left and right positions), even if the program current Iw output from the source driver circuit 14 varies, the variation is not conspicuous.
[0821]
Note that, as shown in FIGS. 174 and 175, it is needless to say that the transistor groups 521 may be replaced with each other.
[0822]
In FIGS. 167, 168, and 169, the current of the transistor 472b is defined by the resistor R1, but the present invention is not limited to this. The electronic regulators 451a and 451b may be used as shown in FIG. In the configuration of FIG. 170, the electronic regulator 451a and the electronic regulator 451b can be operated independently. Therefore, the value of the current flowing through the transistors 472a1 and 472a2 can be changed. Therefore, it is possible to adjust the output current gradient of the left and right output stages 521c of the chip. The electronic regulator 451 may be configured as one as shown in FIG. 171 so as to control two operational amplifiers 722. The sleep switch 631 has been described with reference to FIG. Similarly, it goes without saying that a sleep switch may be arranged or formed as shown in FIG.
[0823]
Since the number of unit transistors 484 is very large in the one-stage configuration of the current mirror in FIGS. 166 to 172, the driver circuit output stage of the source driver IC (circuit) 14 will be additionally described. 168 and 169 will be described for ease of explanation. However, since the description relates to the number and total area of the transistors 473b and the number and total area of the unit transistors 484, it goes without saying that the description can be applied to other embodiments.
[0824]
168 and 169, the total area of the transistors 473b in the transistor group 521b (the WL size of the transistors 473b in the transistor group 521b × the number of transistors 473b) is denoted by Sb. Note that when the transistor group 521b is provided on the left and right of the gate wiring 581 as shown in FIGS. 168 and 169, the area is doubled. In the case of two as shown in FIG. 167, the area is 2 × the area of the transistor 473b. Note that when the transistor group 521b includes one transistor 473b, it is needless to say that the size is one transistor 473b.
[0825]
The total area of the unit transistors 484 in the transistor group 521c (the WL size of the transistors 484 in the transistor group 521c × the number of transistors 484) is Sc. It is assumed that the number of the transistor groups 521c is n. n is 176 in the case of the QCIF + panel (when a reference current circuit is formed for each of RGB).
[0826]
The horizontal axis of FIG. 165 is Sc × n / Sb. The vertical axis indicates the fluctuation ratio, and the worst situation is 1 for the fluctuation ratio. As shown in FIG. 165, the variation ratio becomes worse as Sc × n / Sb increases. An increase in Sc × n / Sb indicates that the total area of the unit transistors 484 of the transistor group 521c is larger than the total area of the transistors 473b of the transistor group 521b, when the number of output terminals n is fixed. In this case, the fluctuation ratio becomes worse.
[0827]
The decrease in Sc × n / Sb indicates that the total area of the unit transistors 484 of the transistor group 521c is smaller than the total area of the transistors 473b of the transistor group 521b, when the number of output terminals n is constant. In this case, the fluctuation ratio becomes small.
[0828]
The allowable variation range is Sc × n / Sb of 50 or less. If Sc × n / Sb is 50 or less, the fluctuation ratio is within the allowable range, and the fluctuation in the potential of the gate wiring 581 becomes extremely small. Therefore, there is no occurrence of horizontal crosstalk, the output variation is within the allowable range, and good image display can be realized. If Sc × n / Sb is 50 or less, it is within the allowable range, but if Sc × n / Sb is 5 or less, there is almost no effect. Conversely, Sb increases and the chip area of the source driver IC 14 increases. Therefore, Sc × n / Sb is preferably set to 5 or more and 50 or less.
[0829]
FIG. 185 illustrates the relationship between the IC breakdown voltage and the output variation of the unit transistor. The variation ratio on the vertical axis indicates that the variation of the unit transistor 484 is 1 manufactured by a 1.8 (V) withstand voltage process. FIG. 185 shows the output variation of the unit transistor 484 manufactured by each withstand voltage process, with the shape L / W of the unit transistor 484 set to 12 (μm) / 6 (μm). In addition, a plurality of unit transistors are formed in each IC withstand voltage process, and variations in output current are determined. However, the breakdown voltage process is 1.8 (V) breakdown voltage, 2.5 (V) breakdown voltage, 3.3 (V) breakdown voltage, 5 (V) breakdown voltage, 8 (V) breakdown voltage, 10 (V) breakdown voltage, 15 (V) breakdown voltage. V) The pressure resistance is discrete. However, for ease of explanation, the variation of transistors formed at each breakdown voltage is plotted on a graph and connected by a straight line.
[0830]
From FIG. 185, the increase ratio of the variation ratio (the variation in the output current of the unit transistor 484) to the IC process is small until the IC breakdown voltage is about 9 (V). However, when the IC breakdown voltage is 10 (V) or more, the gradient of the variation ratio with respect to the IC breakdown voltage increases.
[0831]
In FIG. 185, the variation ratio within 3 is an allowable variation range in the range from 64 gradations to 256 gradations. However, this variation ratio differs depending on the area and L / W of the unit transistor 484. However, even if the shape and the like of the unit transistor 484 are changed, there is almost no change in the variation ratio of the variation ratio with respect to the IC breakdown voltage.
When the IC breakdown voltage is 9 to 10 (V) or more, the variation ratio tends to increase.
[0832]
On the other hand, the potential of the output terminal 681 of the source driver IC (circuit) 14 changes according to the program current of the driving transistor 11 a of the pixel 16. The gate terminal potential Vw when the driving transistor 11a of the pixel 16 supplies a current of white raster (maximum white display) is set. The gate terminal potential Vb when the driving transistor 11a of the pixel 16 flows a current of black raster (complete black display). The absolute value of Vw-Vb needs to be 2 (V) or more. When the voltage Vw is applied to the output terminal 681, the voltage between channels of the unit transistor 484 needs to be 0.5 (V).
[0832]
Therefore, the output terminal 681 (the terminal 681 is connected to the source signal line 18 and the gate terminal voltage of the driving transistor 11a of the pixel 16 is applied at the time of current programming) from 0.5 (V) to ((Vw −Vb) +0.5) (V). Since Vw-Vb is 2 (V), a maximum of 2 (V) +0.5 (V) = 2.5 (V) is applied to the terminal 681. Therefore, even if the output voltage (current) of the source driver IC 14 is a rail-to-rail output, the IC withstand voltage needs to be 2.5 (V). The required amplitude range of the output terminal 681 needs to be 2.5 (V) or more.
[0834]
From the above, it is preferable to use a process in which the withstand voltage of the source driver IC 14 is 2.5 (V) or more and 10 (V) or less. More preferably, the withstand voltage of the source driver IC 14 preferably uses a process of 3 (V) or more and 9 (V) or less. The IC withstand voltage is equal to the maximum value of the power supply voltage that can be used. The power supply voltage that can be used is a voltage that can always be used and is not an instantaneous withstand voltage.
[0835]
In the above description, the withstand voltage process of the source driver IC 12 uses a process of 2.5 (V) or more and 10 (V) or less. However, this withstand voltage is also applied to the embodiment in which the source driver circuit 14 is formed directly on the array substrate 71 (such as a low-temperature polysilicon process). The withstand voltage of the source driver circuit 14 formed on the array substrate 71 may be as high as 15 (V) or more. In this case, the power supply voltage used for the source driver circuit 14 may be replaced with the IC breakdown voltage shown in FIG. Further, even in the case of the source driver IC 14, the power supply voltage to be used may be replaced without using the IC withstand voltage.
[0836]
The area of the unit transistor 484 has a correlation with the variation of the output current. FIG. 186 is a graph when the area of the unit transistor 484 is fixed and the transistor width W of the unit transistor 484 is changed. In FIG. 186, the variation of the channel width W of the unit transistor 484 is 2 (μm) is 1.
[0837]
As shown in FIG. 186, the variation ratio tends to increase gradually from 2 (μm) to 9 to 10 (μm) from the unit transistor W, and the variation ratio tends to increase more than 10 (μm). In addition, the variation ratio tends to increase when the channel width W is 2 (μm) or less.
[0838]
The variation ratio in FIG. 186 within 3 is the variation allowable range in the 64-gradation to 256-gradation display. However, the variation ratio differs depending on the area of the unit transistor 484. However, even if the area of the unit transistor 484 is changed, there is almost no change in the variation ratio of the variation ratio with respect to the IC breakdown voltage.
[0839]
From the above, it is preferable that the channel width W of the unit transistor 484 be greater than or equal to 2 (μm) and less than or equal to 10 (μm). More preferably, the channel width W of the unit transistor 484 is preferably 2 (μm) or more and 9 (μm) or less. In addition, it is preferable that the channel width W of the unit transistor 484 be formed in the above range in order to suppress linking of the gate wiring 581 in FIG.
[0840]
FIG. 187 is a graph of the L / W of the unit transistor 484 and the deviation (variation) from the target value. When the L / W ratio of the unit transistor 484 is 2 or less, the deviation from the target value is large (the slope of the straight line is large). However, as L / W increases, the deviation of the target value tends to decrease. When the L / W of the unit transistor 484 is 2 or more, the change in deviation from the target value becomes small. The deviation (variation) from the target value is L / W = 2 or more and 0.5% or less. Therefore, the accuracy of the transistor can be adopted in the source driver circuit 14.
[0841]
From the above, it is preferable that L / W of the unit transistor 484 be 2 or more. However, a large L / W means that L is long, so that the transistor size is large. Therefore, L / W is preferably set to 40 or less.
[0842]
Further, the magnitude of L / W also depends on the number of gradations. When the number of gradations is small, the difference between the gradations is large, so that there is no problem even if the output current of the unit transistor 484 varies due to the effect of kink. However, in a display panel having a large number of gradations, the difference between the gradations is small. Therefore, if the output current of the unit transistor 484 varies even slightly due to the effect of kink, the number of gradations is reduced.
[0843]
In consideration of the above, in the source driver circuit 14 of the present invention, the number of gradations is K, and the L / W of the unit transistor 484 (L is the channel length of the unit transistor 484, and W is the channel width of the unit transistor). Time,
It is configured (formed) so as to satisfy the relationship of (√ (K / 16)) ≦ L / W ≦ and (√ (K / 16)) × 20.
[0844]
In FIG. 169 and the like, when the total area Sa of the transistors 473a in the transistor group 521a is set to the total area Sb of the transistors 473b in the transistor group 521b, the relationship between the total area Sa and the total area Sb has a correlation with the output variation. This relationship is illustrated in FIG. See FIG. 185 for the variation ratio and the like.
[0845]
The variation ratio is set to 1 when the total area Sb: the total area Sa = 2: 1 (Sa / Sb = 1/2). As can be seen from FIG. 188, when Sa / Sb is small, the variation ratio rapidly deteriorates. Especially when Sa / Sb = 1/2 or less, it tends to be worse. When Sa / Sb is １ ／ or more, output variation is reduced. The effect of the reduction is moderate. Further, when Sa / Sb = １ ／, the output variation becomes an allowable range. From the above, it is preferable to form them so as to satisfy the relationship of 1/2 <= Sa / Sb. However, as Sa increases, the IC chip size also increases. Therefore, the upper limit is preferably set to Sa / Sb = 4. That is, the relationship of 1/2 <= Sa / Sb <= 4 is satisfied.
[0846]
Note that A> = B means that A is greater than or equal to B. A> B means that A is greater than B. A <= B means that A is B or less. A <B means that A is smaller than B.
[0847]
Further, it is preferable that the total area Sb and the total area Sa be substantially equal. Further, it is preferable that the number of unit transistors 484 having one output and the number of transistors 633b of the transistor group 521c be the same. That is, in the case of 64 gradation display, 63 unit transistors 484 each having one output are formed. Therefore, 63 transistors 633b forming the transistor group 521c are formed.
[0848]
In addition, it is preferable that the transistor group 521a, the transistor group 521b, the unit transistor group 521c, and the unit transistor 484 be formed of transistors whose WL area is four times or less. More preferably, it is preferable that the transistor be formed of a transistor having a WL area of not more than twice. Further, it is preferable that all the transistors be formed of the same size. That is, it is preferable to form the current mirror circuit and the output current circuit 704 with transistors having substantially the same shape.
[0849]
The total area Sa is set to be larger than the total area Sb. Preferably, the configuration is such that the relationship of 200Sb >> = Sa >> = 4Sb is satisfied. In addition, the total area of the transistors 633a included in all the transistor groups 521b is set to be substantially equal to Sa.
[0850]
In a single-stage connected source driver circuit as shown in FIG. 191, particularly when an image is displayed on a display panel, the current applied to the source signal line 18 causes the source signal line potential to fluctuate. There is a problem that the gate wiring 581 of the source driver IC 14 which is good for the potential fluctuation is displaced (see FIG. 184). As shown in FIG. 184, linking occurs in the gate wiring 581 at a point where the video signal applied to the source signal line 18 changes. Since the potential of the gate wiring 581 changes due to the linking, the gate potential of the unit transistor 484 changes, and the output current fluctuates. In particular, a potential change of the gate wiring 581 causes crosstalk (lateral crosstalk) along the gate signal line 17.
[0851]
This fluctuation (linking of the gate wiring 581 (see FIG. 184)) is affected by the power supply voltage of the source driver IC14. This is because the peak value of the linking increases as the power supply voltage increases. At worst, it swings up to the power supply voltage. The voltage of the gate wiring 581 has a steady value of 0.55 to 0.65 (V). Therefore, the fluctuation value of the magnitude of the output current is large even when a slight linking occurs.
[0852]
FIG. 163 shows the potential fluctuation ratio of the gate wiring based on the case where the power supply voltage of the source driver IC 14 is 1.8 (V). The fluctuation ratio increases as the power supply voltage of the source driver IC 14 increases. The allowable range of the variation ratio is about 3. If the fluctuation ratio is larger than this, horizontal crosstalk occurs. In addition, the variation ratio tends to increase when the IC power supply voltage is 10 to 12 (V) or more. Therefore, the power supply voltage of the source driver IC 14 needs to be 12 (V) or less.
[0853]
On the other hand, in order for the driving transistor 11a to flow a current from white display to black display, it is necessary to change the potential of the source signal line 18 by a certain amplitude. The required amplitude range is 2.5 (V) or more. The required amplitude range is less than the power supply voltage. This is because the output voltage of the source signal line 18 cannot exceed the power supply voltage of the IC.
[0854]
From the above, the power supply voltage of the source driver IC 14 needs to be 2.5 (V) or more and 12 (V) or less. By setting this range, the fluctuation of the gate wiring 581 is suppressed to a specified range, and horizontal crosstalk does not occur, and a good image display can be realized.
[0855]
The wiring resistance of the gate wiring 581 is also an issue. In FIG. 167, the wiring resistance R (Ω) of the gate wiring 581 is the resistance of the entire wiring from the transistor 473b1 to the transistor 473b2. Alternatively, it is the resistance of the entire length of the gate wiring. The magnitude of the transient phenomenon of the gate wiring 581 also depends on one horizontal scanning period (1H). This is because if the 1H period is short, the influence of the transient phenomenon is large. The higher the wiring resistance R (Ω), the more likely a transient phenomenon occurs. This phenomenon becomes a problem particularly in the configuration of the one-stage current mirror connection shown in FIGS. 166 to 172. This is because the gate wiring 581 is long and the number of the unit transistors 484 connected to one gate wiring 581 is large. Needless to say, even the multi-stage connection shown in FIG. 162 is a problem.
[0856]
FIG. 164 is a graph in which the horizontal axis represents the wiring resistance R (Ω) of the gate wiring 581, the 1H period T (sec), and the multiplication (RT), and the vertical axis represents the variation ratio. The variation ratio 1 is based on R · T = 100. As can be seen from FIG. 164, the variation ratio tends to increase when R · T is 5 or less. Further, when R · T is 1000 or more, the variation ratio tends to increase. Therefore, it is preferable that R · T is 5 or more and 1000 or less.
[0857]
The duty ratio is also an issue. This is because the fluctuation of the source signal line 18 is also increased by the duty ratio. Here, Sc is the total area of the unit transistors 484 of the transistor group 521c (the WL size of the transistors 484 in the transistor group 521c × the number of transistors 484).
[0858]
In FIG. 189, the horizontal axis represents Sc × Duty ratio, and the vertical axis represents variation ratio. As can be seen from FIG. 189, the variation ratio tends to increase when the Sc × Duty ratio is 50 or more. When the variation ratio is 3 or less, the variation is within the allowable range. Therefore, it is preferable to control the driving so that the Sc × Duty ratio is 50 or less.
[0859]
In the variation allowable range, the Sc × Duty ratio b is 50 or less. If the Sc × Duty ratio is 50 or less, the fluctuation ratio is within the allowable range, and the fluctuation in the potential of the gate wiring 581 becomes extremely small. Therefore, there is no occurrence of horizontal crosstalk, the output variation is within the allowable range, and good image display can be realized. If the Sc × Duty ratio is 50 or less, it is within the allowable range, but setting the Sc × Duty ratio to 5 or less has little effect. Conversely, the chip area of the source driver IC 14 increases. Therefore, the Sc × Duty ratio is preferably set to 5 or more and 50 or less.
[0860]
In FIG. 211, by adjusting the reference current Ic1 flowing to the transistor 473b1 and the reference current Ic2 flowing to the transistor 473b2, it is explained that the cascade connection between the source driver ICs 14a and 14b can be favorably performed as shown in FIG. did.
[0861]
In FIG. 211, the reference currents Ic1 and Ic2 are adjusted. However, when the gate wiring 581 has a resistance value equal to or higher than a predetermined value, even if the reference current Ic1 flowing through the transistor 473b1 is the same as the reference current Ic2 flowing through the transistor 473b2, as shown in FIG. The tilt is corrected. This is because the correction current Id for correcting the inclination flows through the gate wiring 581 as shown in FIG.
[0862]
In order to facilitate understanding, specific numerical values will be described. It is assumed that Ic1 = Ic2 = 10 (μA), and at this time, the gate terminal voltage V1 of the transistor 473b1 = 0.60 (V) and the gate terminal voltage V2 of the transistor 473b2 = 0.61 (V). Since the difference between the reference current flowing through the transistor 473b2 and the reference current flowing through the transistor 473b1 needs to be within 1%, 1% of the reference current = 10 (μA) is 0.1 (μA). Therefore, (V2−V1) /0.1 (μA) = (0.61−0.60) (V) /0.1 (μA) = 100 (KΩ). Therefore, by setting the resistance value of the gate wiring 581 to 100 (KΩ), the slope of the output current is adjusted, and the difference between the output currents of the adjacent source driver ICs 14 is within 1%.
[0863]
The higher the resistance of the gate wiring 581, the smaller the magnitude of the correction current Id. However, if the resistance value of the gate wiring 581 is too high, the peak value of the linking in FIG. 184 also increases, and the occurrence of horizontal crosstalk becomes remarkable. Therefore, there is an appropriate range for the resistance value of the gate wiring 581.
[0864]
The present invention is characterized in that all or at least a part of the gate wiring 581 is formed of a wiring made of polysilicon. Preferably, the portion other than the contact portion with or near the gate terminal of the unit transistor 484 is formed of polysilicon. The gate wiring 581 is formed or configured to have a target resistance value by adjusting the wiring width or meandering.
[0865]
The occurrence of linking of the gate wiring can be suppressed by setting the resistance of the gate wiring 581 to a predetermined value or less. Further, this can be achieved by increasing the total area Sb of the transistor 473b (the total area Sb of the transistor group 521b).
Further, this can be achieved by increasing the reference current Ic.
[0866]
The area of the unit transistor 484 having one output (the total area of the unit transistors 484 in one transistor group 521c) is S0, and the total area Sb of the transistors 473b of the transistor group 521b (when there are a plurality of transistor groups 521b as shown in FIG. 213). Is the total area of the transistors 473b of the plurality of transistor groups 521b). FIG. 192 shows the relationship when Sb / S0 is plotted on the horizontal axis and allowable gate wiring resistance (KΩ) is plotted on the vertical axis. The range below the solid line in FIG. 192 is the allowable range (the range that is not affected by the occurrence of linking). In other words, the horizontal crosstalk is in a practically acceptable range.
[0867]
The horizontal axis of FIG. 192 is the size S0 of the unit transistor 484 per one output with respect to the size Sb of the total transistor group 521b (for 64 gradations, 63 unit transistors 484). Assuming that S0 is a fixed value, the larger Sb is, the larger the resistance that the gate wiring 581 can tolerate. This is because the larger the Sb, the lower the impedance with respect to the gate wiring 581 and the higher the stability.
[0868]
S0 is for generating an output current (program current) and the output variation must be kept below a certain value, so that the size of S0 has a narrow design change range. On the other hand, there is a design constraint for setting the resistance value of the gate wiring 581 to a predetermined value. In order to increase the resistance of the gate wiring 581, there are a problem that the wiring becomes thin and disconnection occurs, and a problem of stability. Also, when Sb is increased, the chip area is increased, and the cost is increased. Therefore, Sb / S0 is preferably set to 50 or less from the viewpoint of the chip size of the source driver IC 14, and Sb / S0 is set to 5 or more due to the problem of stable design of the gate wiring 581 and linking. Is preferred. Therefore, it is necessary to satisfy the condition of 5 <= Sb / S0 <= 50.
[0869]
From the graph (solid line) in FIG. 192, the slope of the solid line curve becomes gentler as Sb / S0 decreases. When Sb / S0 is 15 or more, the inclination tends to be constant. Therefore, when Sb / S0 is 5 or more and 15 or less, the resistance value of the gate wiring 581 needs to be 400 (KΩ) or less. When Sb / S0 is 15 or more and 50 or less, it is necessary to set Sb / S0 × 24 (KΩ) or less. For example, when Sb / S0 = 50, it is necessary to make 50 × 24 = 1200 (KΩ) or less.
[0870]
There is a correlation between the reference current Ic flowing through the transistor 473b and the allowable gate wiring resistance. This is because the larger the reference current Ic, the lower the impedance when the gate wiring 581 is viewed from the transistor 473b. FIG. 193 shows the relationship. 193 shows the reference current Ic (μA) flowing through the transistor 473b (or the transistor group 521b) on the horizontal axis. The vertical axis indicates the allowable gate wiring resistance (KΩ). The range below the solid line in FIG. 193 is the allowable range (the range that is not affected by the occurrence of linking). In other words, the horizontal crosstalk is in a practically acceptable range.
[0871]
When the reference current Ic is increased, the stability of the gate wiring 581 is improved. However, the reactive current consumed by the source driver IC 14 increases, and the potential of the gate wiring 581 also increases. For this reason, the reference current Ic needs to be 50 (μA) or less.
[0873]
If the reference current Ic is reduced, the stability of the gate wiring 581 is reduced. Therefore, it is necessary to reduce the resistance value of the gate wiring 581. However, when the reference current is reduced below a certain value, the variation in the output current from the unit transistor 521c increases. That is, the stability of the output current is lost. For this reason, the reference current Ic needs to be 2 (μA) or more. From the above, the reference current Ic flowing through the transistor 473b needs to be 2 (μA) or more and 50 (μA) or less.
[0873]
The graph (solid line) in FIG. 193 can be approximated to two straight lines. When Ic is 2 (μA) or more and 15 (μA) or less, the resistance value (MΩ) of the gate wiring 581 needs to be 0.04 × Ic (MΩ) or less. For example, if Ic = 15 (μA), the resistance value of the gate wiring 581 needs to satisfy the condition of 0.04 × 15 = 0.6 (MΩ) or less.
[0874]
When Ic is 15 (μA) or more and 50 (μA) or less, the resistance value (MΩ) of the gate wiring 581 needs to be 0.025 × Ic (MΩ) or less. For example, if Ic = 50 (μA), the resistance value of the gate wiring 581 needs to satisfy the condition of 0.025 × 50 = 1.25 (MΩ) or less.
[0875]
There is also a correlation between the period in which one pixel row is selected (one horizontal scanning period (1H)) and the resistance R (KΩ) of the gate wiring 581 x the length D (m) of the gate wiring 581. This is because the shorter the 1H period, the shorter the period required for the potential of the gate wiring 581 to return to a normal value. Further, as shown in FIG. 211, when the length D of the gate wiring 581 (= the chip length of the driver IC) is increased, the potential fluctuation of the unit transistor group 521c farthest from the transistor 473b exceeds the allowable range. This phenomenon is presumed to be due to the influence of the parasitic capacitance between the unit transistor 484 and the source signal line 18. That is, when the chip length D of the source driver IC 14 is increased, it is necessary to consider not only the resistance value of the simple gate wiring 581 but also the potential fluctuation of the gate wiring 581 due to the parasitic capacitance.
[0876]
In FIG. 195, the horizontal axis represents one horizontal scanning period (μ second). The vertical axis represents the product of the gate wiring resistance (KΩ) and the chip length D (m). The range below the solid line in FIG. 195 is the allowable range. R · D is 9 (KΩ · m), which is the manufacturing limit of the source driver IC. Above this, the cost increases and is not practical. On the other hand, when RD is 0.05 or less, the current Id in FIG. 191 becomes too large, and the deviation between adjacent output currents becomes too large. Therefore, R · D (KΩ · m) needs to be 0.05 or more and 9 or less.
[0877]
When the transistor 11 forming the pixel 16 is configured with a P channel, the program current flows in the direction from the pixel 16 to the source signal line 18. Therefore, the unit transistor 484 (see FIGS. 48 and 57) of the source driver circuit needs to be configured with an N-channel transistor. That is, the source driver circuit 14 needs to be configured to draw the program current Iw.
[0878]
Therefore, when the driving transistor 11a (in the case of FIG. 1) of the pixel 16 is a P-channel transistor, the source driver circuit 14 always configures the unit transistor 484 with an N-channel transistor so as to draw the program current Iw. In order to form the source driver circuit 14 on the array substrate 71, it is necessary to use both an N-channel mask (process) and a P-channel mask (process). To describe conceptually, the display panel (display device) of the present invention has a configuration in which the pixel 16 and the gate driver circuit 12 are configured by P-channel transistors, and the transistors of the source current of the source driver are configured by N channels.
[0877]
Therefore, the transistor 11 of the pixel 16 is formed by a P-channel transistor, and the gate driver circuit 12 is formed by a P-channel transistor. In this way, by forming both the transistor 11 and the gate driver circuit 12 of the pixel 16 with P-channel transistors, the cost of the substrate 71 can be reduced. However, the source driver 14 needs to form the unit transistor 484 with an N-channel transistor. Therefore, the source driver circuit 14 cannot be formed directly on the substrate 71. Therefore, the source driver circuit 14 is separately manufactured using a silicon chip or the like and mounted on the substrate 71. That is, the present invention has a configuration in which the source driver IC 14 (means for outputting a program current as a video signal) is externally provided.
[0880]
Note that the source driver circuit 14 is configured by a silicon chip, but the invention is not limited to this. For example, a large number of pieces may be simultaneously formed on a glass substrate by low-temperature polysilicon technology, cut into chips, and stacked on the substrate 71. Although the description has been made assuming that the source driver circuit is mounted on the substrate 71, the present invention is not limited to this. Any form may be used as long as the output terminal 681 of the source driver circuit 14 is connected to the source signal line 18 of the substrate 71. For example, a method of connecting the source driver circuit 14 to the source signal line 18 by TAB technology is exemplified. By separately forming the source driver circuit 14 on a silicon chip or the like, variation in output current can be reduced, and favorable image display can be realized. Further, cost reduction is possible.
[0881]
The configuration in which the selection transistor of the pixel 16 is formed by a P-channel transistor and the gate driver circuit is formed by a P-channel transistor is not limited to a self-luminous device (display panel or display device) such as an organic EL. For example, the present invention can be applied to a liquid crystal display device and an FED (field emission display).
[0882]
When the switching transistors 11b and 11c of the pixel 16 are formed by P-channel transistors, the pixel 16 is selected at Vgh. The pixel 16 is in a non-selected state at Vgl. As described above, when the gate signal line 17a changes from on (Vgl) to off (Vgh), the voltage penetrates (penetration voltage). If the driving transistor 11a of the pixel 16 is formed of a P-channel transistor, the current will not flow through the transistor 11a due to the penetration voltage in the black display state. Therefore, good black display can be realized. It is difficult to realize a black display, which is a problem of the current driving method.
[0883]
According to the present invention, the ON voltage is Vgh by configuring the gate driver circuit 12 with a P-channel transistor. Therefore, matching with the pixel 16 formed by the P-channel transistor is good. Further, in order to exhibit the effect of improving the black display, as shown in the configuration of the pixel 16 in FIGS. 1, 2, 32, 113, and 116, the driving transistor 11a and the source signal are converted from the anode voltage Vdd. It is important that the configuration is such that the program current Iw flows into the unit transistor 484 of the source driver circuit 14 via the line 18. Therefore, configuring the gate driver circuit 12 and the pixel 16 with P-channel transistors, mounting the source driver circuit 14 on a substrate, and configuring the unit transistors 484 of the source driver circuit 14 with N-channel transistors has an excellent synergistic effect. Demonstrate. Further, the unit transistor 484 formed with an N-channel has a smaller variation in output current than the unit transistor 484 formed with a P-channel. When compared with the transistor 484 having the same area (W · L), the variation in the output current of the N-channel unit transistor 484 is reduced from 1 / 1.5 to 1/2 as compared with the P-channel unit transistor 484. . For this reason, it is preferable that the unit transistor 484 of the source driver IC 14 is formed of an N channel.
[0884]
The same applies to FIG. 42 (b). In FIG. 42B, current does not flow into the unit transistor 484 of the source driver circuit 14 via the driving transistor 11b. However, the configuration is such that the program current Iw flows from the anode voltage Vdd to the unit transistor 484 of the source driver circuit 14 via the programming transistor 11a and the source signal line 18. Therefore, similarly to FIG. 1, the gate driver circuit 12 and the pixel 16 are constituted by P-channel transistors, the source driver circuit 14 is mounted on a substrate, and the unit transistors 484 of the source driver circuit 14 are constituted by N-channel transistors. Exerts an excellent synergistic effect.
[0885]
In the present invention, the driving transistor 11a of the pixel 16 is configured with a P-channel, and the switching transistors 11b and 11c are configured with a P-channel. Further, the unit transistor 484 in the output stage of the source driver IC 14 is configured to have N channels. Preferably, the gate driver circuit 12 is configured by a P-channel transistor.
[0886]
It goes without saying that the reverse configuration described above is also effective. The driving transistor 11a of the pixel 16 is constituted by N channels, and the switching transistors 11b and 11c are constituted by N channels. Further, the unit transistor 484 in the output stage of the source driver IC 14 is configured to be a P-channel. Preferably, the gate driver circuit 12 is formed of an N-channel transistor. This configuration is also a configuration of the present invention.
[0887]
Hereinafter, the reference current circuit will be described. As shown in FIG. 68, the reference current circuit 691 is formed (arranged) for each of R, G, and B. The reference current circuits 691R, 691G, 691B are arranged close to each other.
[0888]
A regulator (electronic regulator) 491R for adjusting the reference current is arranged in the R reference current circuit 654R, and a regulator (electronic regulator) 491G for adjusting the reference current is arranged in the G reference current circuit 654G. A circuit (electronic volume) 491B for adjusting the reference current is arranged in the circuit 654B.
[0889]
The volume 491 and the like are preferably configured to change with temperature so as to compensate for the temperature characteristics of the EL element 15. As shown in FIG. 69, the reference current circuit 691 is controlled by a current control circuit 692. By controlling (adjusting) the reference current, the unit current output from the unit transistor 484 can be changed.
[0890]
In the above-described current output method of the present invention (the source driver of the liquid crystal display panel is a voltage output method (signal is a voltage step)), a plurality of unit currents proportional to the reference current are combined based on the reference current. And outputs the program current Iw. Therefore, it is important that the reference current can be accurately generated without variation between chips.
[0891]
FIG. 331 shows the embodiment. 49 and 162, the reference current is created by the resistor 471. In FIG. 167, the reference current is created by the resistor R1. In FIG. 331, the resistor 471 in FIG. 68 is replaced with a transistor, and the current flowing through the transistor 3314 forming a current mirror circuit with this transistor is controlled using an operational amplifier 722 or the like (see also FIG. 170 and the like). The transistor 3314 and the transistor form a current mirror circuit. If the current mirror magnification is 1, the current flowing through the transistor 3313 becomes the reference current. Note that 654 described in FIG. 331 and the like is a circuit for generating the program current Iw.
[0892]
The output voltage of the operational amplifier 722 is input to the N-channel transistor 3313, and the current flowing through the transistor 3313 flows through the external resistor 531a. Note that the resistor 531a is a fixed chip resistor. Basically, only the resistor 531a is required. The resistance 531b is a resistance element such as a posistor or thermistor whose resistance value changes with temperature. This resistor 531a is used to compensate for the temperature characteristic of the EL element 15. The resistor 531a is inserted or arranged in parallel or in series with the resistor 531b in accordance with the temperature of the EL element 15 (for compensation). In FIG. 170 and the like, the resistor 531b may be formed or arranged in parallel or in series with the resistor R1. In the following, for ease of description, the description will be made assuming that the resistor 531a and the resistor 531b are one resistor 531.
[0893]
The resistor 531a is a chip resistor. Therefore, those having an accuracy of 1% or more can be easily obtained. If a resistor is formed in an IC using a diffusion resistance technique or a polysilicon pattern, the accuracy of the resistance value is very poor. Therefore, it is preferable that the resistor 531a that determines the reference current be an external resistor with high accuracy. The chip resistor 531a is attached to the input terminal 681a. Particularly, in the EL display panel, the temperature characteristics of the EL element 15 are different for each of RGB. Therefore, three external resistors 531a are required for each of RGB.
[0894]
The terminal voltage of the resistor 531 becomes the negative input of the operational amplifier 722, and the voltage of this negative terminal and the positive terminal of the operational amplifier 722 become the same voltage. Therefore, assuming that the + input voltage of the operational amplifier 722 is V1, a value obtained by dividing this voltage by the resistance 531 becomes a current flowing through the transistor 3314. This current becomes the reference current.
[0895]
Now, if the resistance value of the resistor 531 is 100 KΩ and the input voltage of the + terminal of the operational amplifier 722 is V1 = 1 (V), a reference current of 1 (V) / 100 KΩ = 10 (μA) flows through the resistor 531. . The magnitude of the reference current is preferably set to 2 μA or more and 30 μA or less. More preferably, it is set to 5 μA or more and 20 μA or less. When the reference current flowing through the parent transistor 63 is small, the accuracy of the unit current source 484 deteriorates. If the reference current is too large, the current mirror magnification (in this case, the decreasing direction) to be converted inside the IC increases, the variation in the current mirror circuit increases, and the accuracy of the unit current source 484 deteriorates as before. Needless to say, the above items are also applied to other embodiments of the present invention. The same applies to the items described below.
[0896]
According to the above configuration, if the accuracy of the + input terminal of the operational amplifier 722 is good and the resistance value accuracy 531 is good, an extremely accurate reference current (magnitude, variation accuracy) can be formed. The reference voltage Vref from the reference voltage circuit 3311 is applied to the + terminal of the operational amplifier 722. Many types of ICs of the reference voltage circuit 3311 for outputting the reference voltage are sold by Maxim or the like. Further, the reference voltage Vref can be formed in the source driver circuit 14 (incorporation of the reference voltage Vref). It is preferable that the range of the reference voltage Vref be 1 (V) or more and 3 (V) or less.
[0897]
The reference voltage is input from the connection terminal 681a. Basically, this Vref voltage may be input to the + terminal of the operational amplifier 722. The electronic volume circuit 451 is arranged between the connection terminal 681a and the + terminal because the EL elements 15 have different luminous efficiencies of RGB. In other words, it is to adjust the current flowing through each of the RGB EL elements 15 to obtain a white balance. Of course, if the adjustment can be made with the resistor 531, the adjustment with the electronic regulator 451 is not necessary. Use of the electronic regulator 451 is white balance adjustment again because the deterioration speed of the EL element 15 is different between RGB. In the EL element 15, B is particularly liable to deteriorate. Therefore, when the EL display panel is used, the B EL element 15 becomes dark for many years, and the screen becomes yellow. In this case, the electronic volume 451 for B is adjusted to execute white balance. Of course, the brightness adjustment or the white balance compensation of the EL element may be performed by linking the electronic regulator 451 with the temperature sensor 781 (see FIG. 78 and the description thereof).
[0898]
The electronic regulator 451 is built in the IC (circuit) 14 (formed directly on the substrate 71). A plurality of unit resistors (R1, R2, R3, R4,..., Rn) are formed by patterning polysilicon and connected in series. Further, an analog switch (S1, S2, S2,..., Sn + 1) is arranged between the unit resistors to divide the reference voltage Vref and output a voltage.
[0899]
In FIG. 331, the transistor 3313 is illustrated as a bipolar transistor; however, the invention is not limited to this. FIG. 332A shows an embodiment in which the transistor 3313 is an FET. It is needless to say that the transistor 3313 does not need to be built in the IC 14 and may be arranged outside the IC.
Further, a generation circuit such as a power supply may be built in the gate driver circuit 12, and a transistor 3313 may be built therein.
[0900]
Also, as shown in FIG. 332 (b), a reference voltage Vref may be generated by a Zener diode 3321 and a resistor 531 instead of the reference voltage circuit 3311 as shown in FIG. Of course, the operational amplifier 722 need not be used as shown in FIG. The Zener diode 3321 may employ a variable reference voltage type.
[0901]
When the number of pixels of the EL display panel is large, it is necessary to stack a plurality of source driver ICs (circuits) 14 on one EL display panel. In this case, it is necessary to use the reference voltage so as to be common to a plurality of source driver ICs. Simply, the reference voltage Vref from one reference voltage circuit 3311 may be input to a plurality of source driver ICs 14 using the reference voltage Vref. The problem arises when the electronic regulator 451 in FIG. 331 is operated (controlled) and the reference voltage input to the operational amplifier 722 changes.
To facilitate the following description, the voltage input to the + terminal of the operational amplifier will be referred to as an adjustment reference voltage Vrs. Vrs is a voltage obtained by adjusting the reference voltage Vref to a voltage used inside the source driver IC 14.
[0902]
As described above, according to the present invention, in a current output (source) driver circuit (IC), a reference voltage is generated internally or externally input, and a reference current is generated from the reference voltage. A plurality of unit current sources 484 are formed, and the current to be output (absorbed) is changed by switching the number of the unit current sources 484 according to an external video (image) data signal.
[0903]
When the adjustment reference voltage Vrs is used, it is necessary to use this adjustment reference voltage Vrs in another source driver 14. FIG. 333 shows the embodiment. The reference voltage Vref from the reference voltage circuit 3311 is adjusted by the electronic volume circuit 451a to become the adjusted reference voltage Vrs. The adjustment reference voltage Vrs is input to the buffer circuit 3332. The buffer circuit 3332 is provided in order to suppress a change in the Vrs voltage due to the connection of another source driver 14 to the adjustment reference voltage output wiring 1453. The output Vrs of the buffer circuit 3332 is applied to the + terminal of the operational amplifier 722 and to the adjustment reference voltage output wiring 3333.
[0904]
The adjustment reference voltage output wiring 3333 is connected to the adjustment reference voltage output terminal 3341. A wiring 3331 is connected to the adjustment reference voltage output terminal 3341, and the adjustment reference voltage Vrs is supplied to another source driver circuit 14 via the wiring 3331.
In FIG. 333, the electronic regulator 451b is formed or arranged between the terminal 681b and the emitter terminal of the transistor 3313. The structure of the electronic regulator 451b is the same as that of the electronic regulator 451a. However, the electronic regulator 451b changes the magnitude of the reference current according to the magnitude of the resistance value. That is, the electronic regulator 451b changes the number of series resistors by turning on and off the internal switch.
The magnitude of the reference current changes depending on the resistance value of the electronic regulator 451b + the resistance 531 and the Vrs voltage. The maximum resistance of the electronic regulator 451b is set to 1/5 or less of the resistance of the resistor 531. This is because variation in the resistance value of the electronic regulator 451b results in variation in the reference current. The electronic regulator 451b is mainly used for temperature compensation of the EL element 15.
[0905]
In order to realize full color display on the EL display panel, it is necessary to form (create) a reference current for each of RGB. The white balance can be adjusted by the ratio of the RGB reference currents. In the case of the current driving method, as shown in FIG. 251, the current I and the luminance B have a linear relationship. In addition, according to the present invention, a current value that the unit current source 484 flows from one reference current is determined. Therefore, if the magnitude of the reference current is determined, the current flowing by the unit current source 484 can be determined. Therefore, if the respective reference currents of R, G, and B are set, white balance can be obtained for all gradations. The above matter is a major feature of the source driver circuit 14 being a current step output (current drive). Therefore, the point is how the magnitude of the RGB reference current can be set.
[0906]
The luminous efficiency of an EL element is determined (is dominant) by the thickness of the EL material deposited or applied. The film thickness is almost constant for each lot. Therefore, if the formed film thickness of the EL element 15 is managed in lots, the relationship between the current flowing through the EL element 15 and the light emission luminance is determined. That is, the current value for obtaining the white balance is fixed for each lot. For example, if the current flowing to the R EL element 15 is Ir (A), the current flowing to the G EL element 15 is Ig (A), and the current flowing to the B EL element 15 is Ib (A), Ir: Ig : Ib = 1: 2: 4, white balance can be obtained. Therefore, the value of fixed resistor 531 is determined so that this current flows. If the resistance 531R of the R circuit is Rr (Ω), the resistance 531G of the G circuit is Rg (Ω), the resistance 531B of the B circuit is Rb (Ω), and the adjustment reference voltage Vrs is common to RGB, Rr: Rg: What is necessary is just to set the value of the resistance value 531 so that Rb = 4: 2: 1. By simply setting in this way, the EL display panel of the present invention can achieve white balance over all gradations. This is a very effective effect of the present invention.
[0907]
The adjustment reference voltage VrsR of the R circuit is connected to the adjustment reference voltage output terminal 3341R for cascade connection with another source driver circuit 14. Similarly, the adjustment reference voltage VrsG of the G circuit is connected to the adjustment reference voltage output terminal 3341G for cascade connection with another source driver circuit 14. The adjustment reference voltage VrsB of the B circuit is also connected to the adjustment reference voltage output terminal 3341B in order to cascade-connect with another source driver circuit 14. The other points are the same as those in FIG.
[0908]
In the embodiment of FIG. 334, the adjustment reference voltages (VrsR, VrsG, VrsB) are output from the adjustment reference voltage output 3341 for each of RGB, but the present invention is not limited to this. When adjustment is not necessary in the electronic regulator circuit 451a (451Ra, 451Ga, 451Ba) for each of RGB (for example, when white balance adjustment, temperature compensation, etc. can be performed by the fixed resistor 531 arranged or formed for each of RGB). , RGB, the output of the adjustment reference voltage Vrs is not required. Further, when the external reference voltage Vref can be used as it is (for example, when the + terminal input of the operational amplifier 722 is Vref), it is needless to say that the electronic regulator circuits 451a (451Ra, 451Ga, 451Ba) for each of RGB are not required. .
[0909]
The source driver circuit (IC) 14 needs to switch between using the reference voltage Vref and using the adjusted reference voltage Vrs for cascade connection. FIG. 335 is an embodiment of the source driver circuit (IC) 14 of the present invention having a built-in reference voltage switch 3352.
[0910]
In order to set whether to use the reference voltage Vref or the adjustment reference voltage Vrs, in the present invention, a switching terminal (not shown) of the switch 3352 is provided as an IC terminal, and a logic voltage to this terminal is used. The switch 3352 can be switched. This means that the source driver IC 14 is also used as a master / slave switch. The master / slave function is also described in FIG.
[0911]
The configuration described above is illustrated in FIG. The reference voltage Vref from one reference voltage circuit 3311 is input to the source driver circuit 14 from the terminal 681a. This voltage is adjusted by an electronic regulator circuit 451a (451Ra, 451Ga, 451Ba) of each RGB as required, and an adjustment reference voltage Vrs (VrsR for the R circuit, VrsG for the G circuit, VrsB for the B circuit) is converted to each RGB. Is input to the operational amplifier 722.
[0912]
The reference voltage switch 3352 determines whether the output voltage V2 of the electronic regulator circuit 451 inside the source driver IC 14 is used as an input of the operational amplifier 722 or the external reference voltage V1 applied to the terminal 3353 is used as an input of the operational amplifier 722. Switch. When the voltage V2 is used as the input of the operational amplifier 722, this IC (circuit) 14 is used in the master mode. In this case, the V2 voltage is output from the adjustment reference voltage output 3341, and the adjustment reference voltage input terminal 3353 of the slave source driver IC (circuit) 14 is connected to the wiring 3331 connected to the adjustment reference voltage output 3341. Will be. As described above, when a plurality of source driver circuits (ICs) 14 operate with the reference voltage Vref from one reference voltage circuit 3311 as an input without distinguishing between master and slave, the changeover switch 3352 is set to Not required. This is because the reference voltage Vref or the adjustment reference voltage Vrs generated inside the IC is input to the + terminal of the operational amplifier 722 of each IC. In addition, other items have already been described, and thus description thereof is omitted.
[0913]
An important matter in FIG. 335 is that two adjustment reference voltage input terminals 3353 are provided. The terminals 3353a and 3353b are connected inside the source driver IC 14. This will be described with reference to FIG.
[0914]
FIG. 336 conceptually illustrates a state in which a plurality of source driver circuits (ICs) 14 are mounted. The drawing shows a state observed through the back surface of the substrate 71 (observed from the back surface of the source driver IC 14). Note that items related to the base anode wiring 2631, the common anode wiring 2642, and the like are described in FIGS. 263, 264, 267, and the like, and thus description thereof is omitted. The above is also the same for FIGS. 337 and 338.
[0915]
In FIG. 336, the adjustment reference voltage outputs 3341 and 3353 are arranged at the center of the source driver IC 14 chip and are parallel to the direction in which the source signal line 18 is formed (parallel to the short side direction of the IC chip). It is arranged (formed). As described above, the wiring is formed so that the wiring 3331 connected to the terminal does not cross.
[0916]
A reference voltage Vref is applied to the source driver IC 14a from the reference voltage circuit 3311 to the terminal 681a by wiring. Therefore, the source driver IC 14a operates as a master. The changeover switch 3352 in the IC is set to the input state of the V2 voltage (see FIG. 335). The source driver ICs 14b and 14c mounted adjacent to the source driver IC 14a operate as slaves. The selector switch 3352 of the source driver IC 14b and the source driver IC 14c is in the V1 voltage input state (see FIG. 335).
[0917]
In FIG. 336, the adjustment voltage Vrs from the source driver IC 14a is output from the RGB adjustment reference voltage output terminals 3341 (3341R, 3341G, 3341B), and is adjusted via the wiring 3331 or 3351 to adjust the source driver IC 14b and the source driver IC 14c. The voltage is input to voltage input terminals 3353 (3353R, 3353G, 3353B). This voltage becomes the voltage V2.
[0918]
As shown in FIG. 336, if the adjustment reference voltage outputs 3341 and 3353 of each RGB are arranged, the wirings 3351 and 3331 do not cross each RGB. Therefore, the wiring layout becomes easy. Further, since only the reference current flows through the adjustment reference voltage outputs 3341 and 3351, there is no potential change unlike the video signal line. Therefore, it can be used as a light-shielding pattern like the base anode line 2631. That is, even if it is arranged on the back surface of the source driver IC 14, no noise or the like is generated and does not affect the source driver IC 14. This effect can be applied as it is by replacing the base anode line 2631 with the adjustment reference voltage output 3341 (3351) in the items described with reference to FIGS.
[0919]
FIG. 337 is an explanatory diagram of the effect of forming a plurality of adjustment reference voltage input terminals 3353 described in FIG. 337 is different from FIG. 336 in that the adjustment reference voltage outputs 3341 and 3353 are formed at the edge of the source driver IC 14. That is, they are formed or arranged on the same side as the video signal input terminal and the control terminal of the IC.
[0920]
The reference voltage Vref from the reference voltage circuit 3311 is applied to the terminal 681a by wiring to the source driver IC 14a. Therefore, the source driver IC 14a operates as a master. The changeover switch 3352 in the IC is set to the input state of the V2 voltage (see FIG. 335). The source driver ICs 14b and 14c mounted adjacent to the source driver IC 14a operate as slaves. The selector switch 3352 of the source driver IC 14b and the source driver IC 14c is in the V1 voltage input state (see FIG. 335).
[0921]
In FIG. 337, the adjustment voltage Vrs from the source driver IC 14a is output from the adjustment reference voltage output terminal 3341. Although not shown in FIG. 335, one adjustment reference voltage output terminal 3341 is formed on each of the left and right sides of the reference voltage input terminal 681a (3341a, 3341b). The adjustment reference voltage Vrs is input to the adjustment voltage input terminals 3353 (3353a, 3353b) of the source driver IC 14b and the source driver IC 14c via the wiring 3331 or 3351. This voltage becomes the voltage V2.
[0922]
The adjustment reference voltage input terminals 3353a and 3353b are electrically connected as shown in FIG. Therefore, the voltage Vrs output from the adjustment reference voltage output 3341a of the source driver IC 14a is applied to the terminal 3353b of the source driver IC 14b, and this voltage Vrs is output to the terminal 3353a via the inside of the IC 16b. The terminal 3353a is input to the terminal 3353 to the source driver IC 14 mounted adjacent to another terminal. Similarly, the voltage Vrs output from the adjustment reference voltage output 3341b of the source driver IC 14a is applied to the terminal 3353a of the source driver IC 14c, and this voltage Vrs is output to the terminal 3353b via the inside of the IC 16c. The terminal 3353b is input to the terminal 3353 to the source driver IC 14 mounted adjacent to another terminal. By arranging or connecting the terminals 3353 and 3341 as described above, ICs can be connected in cascade.
[0923]
If the adjustment reference voltage outputs 3341 and 3353 are arranged as shown in FIG. 337 and the wirings 3351 and 3331 are formed on the back surface of the IC, the wirings 3351 and 3331 do not intersect. Therefore, the wiring layout becomes easy. Also, as in FIG. 336, the adjustment reference voltage outputs 3341 and 3351 only flow the reference current, so that there is no potential change unlike the video signal line. Therefore, it can be used as a light-shielding pattern similarly to the base anode line 2631. That is, even if it is arranged on the back surface of the source driver IC 14, no noise or the like is generated and does not affect the source driver IC 14. This effect can be directly applied by replacing the base anode line 2631 with the adjustment reference voltage output 3341 (3351) in the matters described with reference to FIG.
[0924]
FIG. 337 illustrates the EL display device as a single color for ease of explanation. The EL display device is composed of three colors of RGB. Therefore, adjustment reference voltage outputs 3341 and 3353 are required for each RGB. FIG. 338 is a configuration diagram in which adjustment reference voltage outputs 3341 and 3353 are arranged for each RGB.
[0925]
The source driver IC 14a operates as a master, and the reference voltage Vref from the reference voltage circuit 3311 is applied to the terminal 681a of the source driver IC 14a. Adjustment reference voltage output terminals 3341 are arranged on the left and right of the reference voltage input terminal 681a. The adjustment reference voltage output terminal 3341 of each RGB is disposed at a line-symmetric position with respect to the reference voltage input terminal 681a. That is, the left and right terminals of the input terminal 681a are 3341Ra and 3341Rb, and 3341Ga and 3341Gb are arranged outside thereof. Further, 3341Ba and 3341Bb are arranged outside thereof. The adjustment reference voltage outputs 3341Ra and 3341Rb are connected inside the source driver IC 14a. Similarly, the adjustment reference voltage outputs 3341Ga and 3341Gb are also connected inside the source driver IC 14a. The adjustment reference voltage outputs 3341Ba and 3341Bb are also connected inside the source driver IC 14a.
[0926]
The source driver IC 14b operates as a slave, and the adjustment reference voltage Vrs from the source driver IC 14a is input to the source driver IC 14b. Adjustment reference voltage input terminals 3353 are arranged on the left and right of the reference voltage input terminal 681a. The adjustment reference voltage input terminal 3353 of each RGB is arranged at a position symmetrical with respect to the reference voltage input terminal 681a. That is, the left and right terminals of the input terminal 681a are 3353Ra and 3353Rb, and 3353Ga and 3353Gb are arranged outside thereof. Further, 3353Ba and 3353Bb are arranged outside thereof. The terminals 3353Ra and 3353Rb are connected inside the source driver IC 14a. Similarly, terminals 3353Ga and 3353Gb are also connected inside the source driver IC 14a. The terminals 3353Ba and 3353Bb are also connected inside the source driver IC 14a (see FIG. 335).
[0927]
The voltage Vrs output from the adjustment reference voltage output 3341Bb of the source driver IC 14a is applied to the terminal 3353Ba of the source driver IC 14b, and the voltage Vrs is output to the terminal 3353Bb via the inside of the IC 16b. The terminal 3353Bb is input to the terminal 3353 to the source driver IC 14 mounted adjacent to another terminal. The voltage Vrs output from the adjustment reference voltage output 3341Gb of the source driver IC 14a is applied to the terminal 3353Ga of the source driver IC 14b, and this voltage Vrs is output to the terminal 3353Gb via the inside of the IC 16b. Further, the terminal 3353Gb is input to the terminal 3353 to the source driver IC 14 mounted adjacent to another terminal. Similarly, the voltage Vrs output from the adjustment reference voltage output 3341Rb of the source driver IC 14a is applied to the terminal 3353Ra of the source driver IC 14b, and this voltage Vrs is output to the terminal 3353Rb via the inside of the IC 16b. In addition, the terminal 3353Rb is input to the terminal 3353 to the source driver IC 14 mounted adjacent to another terminal. By arranging or connecting the terminals 3353 and 3341 as described above, the IC can be easily connected to the cascade.
[0928]
If the adjustment reference voltage outputs 3341 and 3353 are arranged as shown in FIG. 338 and the wirings 3351 and 3331 are formed on the back surface of the IC, the wirings 3351 and 3331 do not intersect. Therefore, the wiring layout becomes easy. Also, as in FIG. 336, the adjustment reference voltage outputs 3341 and 3351 only flow the reference current, so that there is no potential change unlike the video signal line. Therefore, it can be used as a light-shielding pattern similarly to the base anode line 2631. That is, even if it is arranged on the back surface of the source driver IC 14, no noise or the like is generated and does not affect the source driver IC 14. This effect can be applied as it is by replacing the base anode line 2631 with the adjustment reference voltage output 3341 (3351) in the items described with reference to FIGS.
[0929]
The gamma current ratio has been described in FIGS. 77, 78, 79, 80, 81 and the like. This is the ratio of the current flowing through the unit current source 484 in the low gradation section in FIG. 56 to the current flowing through the unit current source 484 in the high gradation section in FIG. It is preferable that the reference current of the high gradation part is set to INH and the reference current of the low gradation part is set to INL so that this ratio (gamma current ratio) is within a predetermined range. Therefore, it is preferable to use one current as much as possible and to reduce the number of adjustments. (If the reference current for the high gradation part is INH and the reference current for the low gradation part is INL, two reference currents for each RGB are used.) Adjustment is required).
[0930]
FIG. 339 shows a configuration in which the reference current Ib is one for each of RGB. The upper circuit in FIG. 339 is a current source for high gradation, and the lower circuit is a current source for low gradation (exactly, in a high gradation part, a current of a low gradation current source also flows). 339 is the circuit configuration of FIGS. 333 and 335.
[0931]
The original reference current Ib flows through the transistor 3313. At least one or more magnification varying transistors 3392 are formed or arranged in parallel with the high gradation parent transistor 471aH. The low-gradation parent transistor 471aL forms a current mirror circuit together with the transistor 3314 as it is. Therefore, the current mirror circuit for high gradation is formed by the transistor 3314, the transistor 3392, and the transistor 471aH. A variable magnification switch 3391 is formed or arranged in series with the transistor 3392. An example of the switch 3391 is an analog switch.
[0932]
By controlling the switch 3391 to be on / off, the current flowing to the transistor 471bH can be changed. When the switch 3391b is turned on, two transistors 3392 + current flowing through the transistor 471aH flows through the transistor 471bH. When the switch 3391a is turned on, one transistor 3392 + current flowing through the transistor 471aH flows through the transistor 471bH. When the switches 3391a and 3391b are turned on at the same time, the current flowing through the three transistors 3392 and the transistor 471aH flows through the transistor 471bH. The switch 3391 is switched by a command to the source driver IC 14. As described above, the gamma current ratio can be changed by controlling the switch 3391. Further, since the reference current is only Ib, the adjustment of the white balance becomes very easy. Other configurations have been described in FIG. 48, FIG. 333, FIG. 335, FIG. 79, FIG. 80, FIG.
[0933]
An output pad 681 is formed or arranged at an output terminal of the IC chip. This output pad is connected to the source signal line 18 of the display panel. The output pad 681 has bumps (projections) formed by a plating technique or a nail head bonder technique. The height of the projection is set to be 10 μm or more and 40 μm or less.
[0934]
The bump and each source signal line 18 are electrically connected via a conductive bonding layer (not shown). The conductive bonding layer is made of an epoxy-based or phenol-based adhesive as an adhesive, and a mixture of flakes such as silver (Ag), gold (Au), nickel (Ni), carbon (C), and tin oxide (SnO2). Or an ultraviolet curable resin. The conductive bonding layer is formed on the bump by a technique such as transfer. The connection between the bump or the output pad 681 and the source signal line 18 is not limited to the above method. Further, the film carrier technology may be used without mounting the source driver IC 14 on the array substrate. Further, it may be connected to the source signal line 18 or the like using a polyimide film or the like.
[0935]
In the present invention, since the reference current circuit 691 is divided into three systems for R, G, and B, the light emission characteristics and the temperature characteristics can be adjusted by R, G, and B, respectively. A white balance can be obtained (see FIG. 70).
[0936]
Next, the precharge circuit will be described. As described above, in the current driving method, the current to be written to the pixel during black display is small. Therefore, if there is a parasitic capacitance in the source signal line 18 or the like, there is a problem that a sufficient current cannot be written to the pixel 16 during one horizontal scanning period (1H). In general, in a current-driven light-emitting element, the current value at the black level is as weak as about several nA, and it is difficult to drive a parasitic capacitance (wiring load capacitance) which is considered to be about several tens pF with the signal value. .
In order to solve this problem, before writing image data to the source signal line 18, a precharge voltage is applied, and the potential level of the source signal line 18 is changed to a black display current (basically, a transistor) of the transistor 11a of the pixel. It is effective to set 11a to an off state). In forming (creating) the precharge voltage, it is effective to decode the upper bits of the image data to output a black-level constant voltage.
[0937]
FIG. 65 shows an example of the current output type source driver IC (circuit) 14 having the precharge function of the present invention. FIG. 65 shows a case where a precharge function is mounted on the output stage of a 6-bit constant current output circuit. In FIG. 65, the precharge control signal is a dot clock CLK having a function of resetting the horizontal synchronization signal HD by decoding the case where the upper three bits D3, D4, and D5 of the image data D0 to D5 are all 0 and decoding by the NOR circuit 652. An AND circuit 653 with the output of the counter circuit 651 is output to output the black level voltage Vp for a certain period. In other cases, the output current from the current output stage 654 (specifically, the configuration shown in FIGS. 48, 56, 57, etc.) is applied to the source signal line 18 (from the source signal line 18 to the program current Iw). To absorb). With this configuration, when the image data is the 0th to 7th gradations close to the black level, the voltage corresponding to the black level is written only for a certain period at the beginning of one horizontal period, and the load of current driving is reduced. It is possible to make up for insufficient writing. Note that the complete black display is set to the 0th gradation and the complete white display is set to the 63rd gradation (in the case of the 64th gradation display).
[0938]
In FIG. 65, when the precharge voltage is applied, the precharge voltage is applied to the point B of the internal wiring 483. Therefore, the precharge voltage is also applied to the current output stage 654. However, since the current output stage 654 is a constant current circuit, it has high impedance. Therefore, even if a precharge voltage is applied to the constant current circuit 654, no problem occurs in the operation of the circuit. Note that in order to prevent the precharge voltage from being applied to the current output stage 654, the current output stage 654 may be disconnected at the point A in FIG. 65 and a switch 655 may be disposed (see FIG. 66). The switch is linked with the precharge switch 481a, and is controlled to be off when the precharge switch 481a is on.
[0939]
The precharge may be performed in the entire gradation range, but preferably, the gradation for performing the precharge should be limited to the black display region. In other words, the image data to be written is determined, and a black area gradation (low luminance, that is, in the current driving method, a small (small) write current) is selected and precharged (referred to as selective precharge). When all the gradation data is precharged, a decrease in luminance (not reaching the target luminance) occurs in the white display area. Further, there may be a problem that a vertical streak is displayed on an image.
[0940]
Preferably, the selective precharge is performed in a gray scale region of gray scale 0 to 1/8 of all gray scales of the gray scale data (for example, in the case of 64 gray scales, 0th to 7th gray scales). In the case of the image data up to, the precharge is performed and then the image data is written). Further, it is preferable that the selective precharge is performed at a gray level in a range from gray level 0 to 1/16 of the gray scale data (for example, in the case of 64 gray levels, the image from the 0th gray level to the 3rd gray level is selected). Data and time, precharge, then write image data).
[0941]
In particular, in order to increase the contrast in black display, a method of detecting and precharging only gradation 0 is also effective. Extremely good black display is obtained. The method of precharging only the gradation 0 has little adverse effect on the image display. Therefore, it is most preferable to employ it as a precharge technique.
[0942]
It is also effective to make the precharge voltage and the gradation range different for R, G, and B. This is because the EL display element 15 has different light emission start voltages and light emission luminances for R, G, and B. For example, R is a gradation in a range of gradations 0 to 1/8 of gradation data, and performs selective precharge (for example, in the case of 64 gradations, an image from the 01st gradation to the 7th gradation is performed). At the time of data, precharge is performed, and then image data is written). The other colors (G, B) are selectively precharged at gradations in the region from gradation 0 to gradation 1/16 of the gradation data (for example, in the case of 64 gradations, from the 0th gradation to the third gradation). The image data up to the adjustment and the precharging are performed, and then the image data is written). As for the precharge voltage, if R is 7 (V), a voltage of 7.5 (V) is written to the source signal line 18 for the other colors (G, B). The optimal precharge voltage often differs depending on the manufacturing lot of the EL display panel. Therefore, it is preferable that the precharge voltage is configured to be adjustable with an external volume or the like. This adjustment circuit can also be easily realized by using an electronic volume circuit.
[0943]
It is preferable that the precharge voltage is equal to or lower than the anode voltage Vdd-0.5 (V) in FIG. 1 and within the anode voltage Vdd-2.5 (V).
[0944]
Even in the method of precharging only gradation 0, a method of precharging by selecting one or two colors of R, G, and B is also effective. Less adverse effects on image display. It is also effective to precharge when the screen luminance is equal to or lower than the predetermined luminance or higher than the predetermined luminance. In particular, when the luminance of the screen 50 is low, black display is difficult. At the time of low luminance, the contrast feeling of the image is improved by performing the precharge driving such as the 0 gradation precharge.
[0945]
Also, a 0th mode in which no precharge is performed at all, a first mode in which only grayscale 0 is precharged, a second mode in which precharge is performed in grayscale 0 to grayscale 3, and a precharge in a grayscale 0 to grayscale 7 range It is preferable to set a third mode in which charging is performed, a fourth mode in which precharging is performed in a range of all gradations, and the like, and to switch between these by a command. These can be easily realized by configuring (designing) a logic circuit in the source driver IC (circuit) 14.
[0946]
FIG. 66 is a specific configuration diagram of the selection precharge circuit unit. PV is a precharge voltage input terminal. Individual precharge voltages are set for R, G, and B by an external input or an electronic volume circuit. Although the individual precharge voltages are set for R, G, and B, the present invention is not limited to this. R, G, and B may be common. The precharge voltage is related to the Vt of the driving transistor 11a of the pixel 16, and the pixel 16 is the same for the R, G, and B pixels.
If the W / L ratio and the like of the driving transistor 11a of the pixel 16 are different for R, G, and B (different designs), the precharge voltage should be adjusted according to the different designs. Is preferred. For example, if the channel length L of the driving transistor 11a increases, the diode characteristics of the transistor 11a deteriorate, and the source-drain (SD) voltage increases. Therefore, the precharge voltage needs to be set lower than the source potential (Vdd).
[0947]
The precharge voltage PV is input to the analog switch 561. The W (channel width) of this analog switch needs to be 10 μm or more in order to reduce the on-resistance. However, if W is too large, the parasitic capacitance also increases. More preferably, the channel width W is preferably 15 μm or more and 60 μm or less.
[0948]
This selective precharge may be performed by precharging only gray level 0 or precharging in the range of gray level 0 to gray level 7 or fixed. (R1 or gradation (R1-1)) may be linked to a low gradation area, such as preselection. That is, the selective precharge is performed in this range when the low gradation region is from gradation 0 to gradation R1, and is performed in this range when the low gradation region is from gradation 0 to gradation R2. Implement in conjunction. Note that this control method has a smaller hardware scale than the other methods.
[0949]
The on / off control of the switch 481a is performed according to the above signal application state, and the precharge voltage PV is applied to the source signal line 18 when the switch 481a is on. The time for applying the precharge voltage PV is set by a separately formed counter (not shown). This counter is configured to be set by a command. Further, it is preferable that the application time of the precharge voltage is set to a time equal to or more than 1/100 and equal to or less than 1/5 of one horizontal scanning period (1H). For example, if 1H is 100 μsec, it is 1 μsec to 20 μsec (1/100 of 1H to 1/5 of 1H). More preferably, it is 2 μsec or more and 10 μsec (2/100 of 1H or more and 1/10 or less of 1H).
[0950]
FIG. 67 is a modification of FIG. 65 or FIG. FIG. 67 shows a precharge circuit that determines whether or not to precharge according to input image data and performs precharge control. For example, a setting to perform precharge when the image data is only the gradation 0, a setting to perform the precharge when the image data is only the gradation 0 and 1, the gradation 0 is always precharged, and the gradation 1 is continuous for a predetermined time or more. If it occurs, the setting for precharging can be made.
[0951]
FIG. 67 shows an example of a current output type source driver IC (circuit) 14 having a precharge function according to the present invention. FIG. 67 shows a case where a precharge function is mounted on the output stage of a 6-bit constant current output circuit. In FIG. 67, the coincidence circuit 671 decodes according to the image data D0 to D5, and determines whether or not to precharge with the REN terminal input and the dot clock CLK terminal input having the reset function by the horizontal synchronization signal HD. The matching circuit 671 has a memory, and holds a precharge output result based on several H or several fields (frames) of image data. It has a function of determining whether or not to precharge based on the holding result and performing precharge control. For example, it is possible to set so that the gradation 0 is always precharged and the gradation 1 is precharged when the gradation 1 continuously occurs for 6H (six horizontal scanning periods) or more. Further, it is possible to set to precharge the gradations 0 and 1 without fail and to precharge when the gradation 2 continuously occurs for 3F (three frame periods) or more.
[0952]
The output of the coincidence circuit 671 and the output of the counter circuit 651 are ANDed by an AND circuit 653 to output the black level voltage Vp for a certain period. In other cases, the output current from the current output stage 654 described in FIG. 52 and the like is applied to the source signal line 18 (absorbs the program current Iw from the source signal line 18).
The other configurations are the same as or similar to those in FIGS. Although the precharge voltage is applied to point A in FIG. 67, it is needless to say that the precharge voltage may be applied to point B (see also FIG. 66).
As described above, a good result can be obtained by changing the precharge application time for R, G, and B. For example, the precharge time of R is made longer than the precharge time of G and B. This is because, in an organic EL or the like, the light emission start time and the like are different for each of the RGB materials. Good results can also be obtained by varying the precharge voltage PV application time according to the image data to be applied to the source signal line 18 next. For example, the application time is lengthened at gray level 0 of complete black display, and shorter than that at gray level 4. Further, setting the application time in consideration of the difference between the image data before 1H and the image data to be applied next can also provide a favorable result. For example, when writing a current to make a pixel white display to the source signal line before 1H and writing a current to make black display to the pixel in the next 1H, the precharge time is lengthened. This is because the current for black display is very small. Conversely, when writing a current to make a pixel black display to the source signal line 1H before and writing a current to make black display to white pixel to the next 1H, shorten the precharge time or change the precharge time. Stop (do not do). This is because the write current for white display is large.
[0953]
It is also effective to change the precharge voltage according to the applied image data. This is because the write current for black display is very small and the write current for white display is large. Accordingly, the precharge voltage is increased (with respect to Vdd; when the pixel TFT 11a is a P-channel) as the gradation area becomes lower, and the precharge voltage is decreased as the pixel area becomes higher (the pixel TFT 11a). Is the P channel).
[0954]
When the program current open terminal (PO terminal) is “0”, the switch 481b is turned off, and the IL terminal and the IH terminal are disconnected from the source signal line 18 (the Iout terminal is connected to the source signal line 18). There). Therefore, the program current Iw does not flow through the source signal line 18. The PO terminal is set to “1” when the program current Iw is applied to the source signal line, turns on the switch 481b, and flows the program current Iw to the source signal line 18.
[0955]
When "0" is applied to the PO terminal to open the switch 481b, no pixel row in the display area is selected. The current source 484 draws current from the source signal line 18 constantly based on the input data (D0 to D5). This current is a current flowing from the Vdd terminal of the selected pixel 16 to the source signal line 18 via the TFT 11a. Therefore, when no pixel row is selected, there is no path for current to flow from the pixel 16 to the source signal line 18. The case where no pixel row is selected occurs when an arbitrary pixel row is selected and the next pixel row is selected. Note that such a state in which none of the pixels (pixel rows) is selected and there is no path flowing into (or flowing out to) the source signal line 18 is referred to as an all non-selection period.
[0956]
In this state, when the IOUT terminal is connected to the source signal line 18, the unit current source 484 that is turned on (the switch 481 that is actually turned on is controlled by the data of the D0 to D5 terminals). Current flows through Therefore, the electric charge charged in the parasitic capacitance of the source signal line 18 is discharged, and the potential of the source signal line 18 drops rapidly.
[0957]
As described above, when the potential of the source signal line 18 decreases, it takes time to recover to the original potential due to the current originally written to the source signal line 18.
[0958]
In order to solve this problem, the present invention applies "0" to the PO terminal during all non-selection periods, turns off the switch 481b in FIG. 66, and disconnects the IOUT terminal from the source signal line 18. By disconnecting, no current flows from the source signal line 18 to the current source 484, so that the potential change of the source signal line 18 does not occur during the entire non-selection period. As described above, by controlling the PO terminal during the entire non-selection period and disconnecting the current source from the source signal line 18, it is possible to perform good current writing.
[0959]
In addition, the area (white area) of the white display area (area having a certain luminance) and the area (black area) of the black display area (area of a predetermined luminance or less) are mixed on the screen. It is effective to add a function of stopping precharge when the ratio is within a certain range (appropriate precharge). This is because vertical streaks occur in the image in this certain range. Of course, conversely, precharging may be performed within a certain range.
[0960]
Another reason is that when the image moves, the image becomes noise-like. The appropriate precharge can be easily realized by counting (calculating) the data of the pixels corresponding to the white area and the black area in the arithmetic circuit. It is also effective to make the appropriate precharge different for R, G, and B. This is because the EL display element 15 has different light emission start voltages and light emission luminances for R, G, and B. For example, R stops or starts precharging when the ratio of white area of predetermined luminance: black area of predetermined luminance is 1:20 or more, and G and B indicate the ratio of white area of predetermined luminance: black area of predetermined luminance. Is configured to stop or start the precharge at 1:16 or more. According to the results of experiments and studies, in the case of the organic EL panel, the ratio of the white area of the predetermined luminance to the black area of the predetermined luminance is 1: 100 or more (that is, the black area is 100 times or more the white area), and the precharge is performed. Is preferably stopped. Further, it is preferable to stop the precharge when the ratio of the white area of the predetermined luminance: the black area of the predetermined luminance is 1: 200 or more (that is, the black area is 200 times or more of the white area).
[0961]
When the driving TFT 11a of the pixel 16 is a P channel, the precharge voltage PV needs to output a voltage close to Vdd (see FIG. 1) from the source driver circuit (IC) 14. However, as the precharge voltage PV is closer to Vdd, the driver circuit (IC) 14 needs to use a semiconductor with a high withstand voltage process (even with a high withstand voltage, 5 (V) to 10 (V)). However, the problem is that the semiconductor process price increases when the breakdown voltage exceeds 5 (V), so that a higher-definition, lower-cost process using a 5 (V) breakdown voltage process is used. be able to).
[0962]
If the diode characteristic of the driving TFT 11a of the pixel 16 is good and the on-current for white display is ensured, if the voltage is 5 (V) or less, no problem occurs because the source driver IC 14 can also use the 5 (V) process. However, when the diode characteristic exceeds 5 (V), there is a problem. In particular, the precharge requires application of a precharge voltage PV close to the source voltage Vdd of the TFT 11a, so that output from the source driver IC 14 cannot be performed.
[0963]
FIG. 260 shows a panel configuration that solves this problem. In FIG. 260, a switch circuit 481 is formed on the array 71 side. The source driver IC 14 outputs an on / off signal of the switch 481. This on / off signal is boosted by the level shift circuit 2591 formed in the array 71, and turns on / off the switch 481. Note that the switch 481 and the level shift circuit 2591 are formed simultaneously or sequentially in a process of forming a TFT of a pixel. Of course, it may be separately formed by an external circuit (IC) and mounted on the array 71.
[0964]
The on / off signal is output from the terminal 761a of the source driver IC 14 based on the precharge condition described above. Therefore, it goes without saying that the method of applying and driving the precharge voltage is also applicable to the embodiment of FIG. The voltage (signal) output from the terminal 761a is as low as 5 (V) or less. The amplitude of this voltage (signal) is increased by the level shifter circuit 2591 to the on / off logic level of the switch 481.
[0965]
With the configuration described above, the source driver circuit (IC) 14 suffices with the power supply voltage in the operating voltage range capable of driving the program current Iw. The precharge voltage PV has no problem in the array substrate 71 having a high operation voltage. Therefore, the precharge can be sufficiently applied up to the Vdd voltage.
[0967]
If the switch circuit 481a in FIG. 66 is also formed (arranged) in the source driver circuit (IC) 14, the withstand voltage becomes a problem. For example, if the Vdd voltage of the pixel 16 is higher than the power supply voltage of the source driver IC 14, there is a risk that a voltage that may damage the source driver IC 14 is applied to the terminal 761 of the source driver IC 14.
[0967]
An embodiment that solves this problem is the configuration shown in FIG. The switch circuit 481 is formed (arranged) on the array substrate 71. The configuration and the like of the switch circuit 481 are the same as or similar to the configuration and specifications described in FIG.
[0968]
In FIGS. 91 and 92, the switch 481 is disposed before the output of the source driver IC 14 and in the middle of the source signal line 18. When the switch 481 is turned on, a current Iw for programming the pixel 16 flows into the source driver circuit (IC) 14. When the switch 481 is turned off, the source driver circuit (IC) 14 is disconnected from the source signal line 18.
[0969]
As in FIG. 260, the voltage (signal) output from the terminal 761a is as low as 5 (V) or less. The amplitude of this voltage (signal) is increased by the level shifter circuit 2591 to the on / off logic level of the switch 481.
[0970]
With the configuration described above, the source driver circuit (IC) 14 suffices with the power supply voltage in the operating voltage range capable of driving the program current Iw. Further, since the switch 481 also operates with the power supply voltage of the array 71, the switch 481 does not break even when the Vdd voltage is applied from the pixel 16 to the source signal line 18, and the source driver circuit (IC) 14 breaks. It will not be done.
[0971]
It goes without saying that both the switch 481 and the switch 481 for applying the precharge voltage PV arranged (formed) in the middle of the source signal line 18 in FIG. 259 may be formed (arranged) on the array substrate 71 (see FIG. 259). 259 + the configuration of FIG. 260).
[0972]
FIG. 223 shows an embodiment in which, in addition to FIG. 67, the precharge voltage can be changed according to the gradation. In FIG. 223, the precharge voltage can be easily changed according to the applied image data. The precharge voltage can be changed by the electronic regulator 451 according to the image data (D3 to D0). In FIG. 223, since the bits D3 to D0 are connected to the electronic regulator, it can be seen that the precharge voltage of the low gradation can be changed. This is because the write current for black display is very small and the write current for white display is large. Therefore, the precharge voltage is increased as the gray scale region becomes lower. Since the driving transistor 11a of the pixel 16 is a P-channel, the anode voltage (Vdd) is a black display voltage. The precharge voltage is lowered (when the pixel transistor 11a is a P-channel) as the gradation area becomes higher. That is, in the low gradation display, the voltage programming method is performed, and in the high gradation display (white display), the current programming method is performed.
[0973]
In the precharge circuit in FIG. 223, it is possible to select whether to precharge only the gradation 0 or to perform precharge in the range of the gradation 0 to the gradation 7. Also, the pre-charge voltage for each gradation can be changed by the electronic regulator 451. Other configurations are the same as those in FIG. 65, FIG. 66, and FIG.
[0974]
Good results can also be obtained by varying the precharge voltage PV application time depending on the image data applied to the source signal line 18. For example, the application time is lengthened at gray level 0 of complete black display, and shorter than that at gray level 4. Also, setting the application time in consideration of the difference between the image data before 1H and the image data to be applied next can provide a favorable result. For example, when writing a current for making a pixel white display to the source signal line before 1H and writing a current for making black display to the pixel in the next 1H, the precharge time is lengthened. This is because the current for black display is very small. Conversely, when a current for writing a pixel to black display is written to the source signal line 1H before and a current for making black display to white pixel is written to the next 1H, the precharge time is shortened or the precharge is performed. Stop (do not do). This is because the write current for white display is large.
[0975]
It is also effective to change the precharge voltage according to the applied image data. This is because the write current for black display is very small and the write current for white display is large. Therefore, the precharge voltage is increased (with respect to Vdd; when the pixel transistor 11a is a P-channel) as the gradation area becomes lower, and the precharge voltage is decreased as the pixel area becomes higher (pixels). A control method of performing the control (when the transistor 11a is a P-channel) is also effective.
[0976]
Hereinafter, in order to facilitate understanding, description will be made mainly with reference to FIG. It goes without saying that the items described below can also be applied to the precharge circuits of FIGS. 65 and 67.
[0977]
When the program current open terminal (PO terminal) is “0”, the switch 655 is turned off, and the IL terminal and the IH terminal are disconnected from the source signal line 18 (the Iout terminal is connected to the source signal line 18. There). Therefore, the program current Iw does not flow through the source signal line 18. The PO terminal is set to “1” when the program current Iw is applied to the source signal line, turns on the switch 655, and flows the program current Iw to the source signal line 18.
[0978]
When "0" is applied to the PO terminal to open the switch 655, no pixel row in the display area is selected. The unit transistor 484 continuously draws current from the source signal line 18 based on the input data (D0 to D5). This current is a current flowing from the Vdd terminal of the selected pixel 16 to the source signal line 18 via the transistor 11a. Therefore, when no pixel row is selected, there is no path for current to flow from the pixel 16 to the source signal line 18. The case where no pixel row is selected occurs when an arbitrary pixel row is selected and the next pixel row is selected. Note that such a state in which none of the pixels (pixel rows) is selected and there is no path flowing into (or flowing out to) the source signal line 18 is referred to as an all non-selection period.
[0979]
In this state, when the output terminal 681 is connected to the source signal line 18, the unit transistor 484 that is turned on (actually, the switch 481 that is controlled by the data of the D0 to D5 terminals is turned on). Current flows through Therefore, the electric charge charged in the parasitic capacitance of the source signal line 18 is discharged, and the potential of the source signal line 18 drops rapidly. As described above, when the potential of the source signal line 18 decreases, it takes time to recover to the original potential due to the current originally written to the source signal line 18.
[0980]
In order to solve this problem, the present invention applies "0" to the PO terminal during all non-selection periods, turns off the switch 655 in FIG. 66, and disconnects the output terminal 681 from the source signal line 18. By disconnecting, no current flows from the source signal line 18 to the unit transistor 484, so that the potential change of the source signal line 18 does not occur during the entire non-selection period. As described above, by controlling the PO terminal during the entire non-selection period and disconnecting the current source from the source signal line 18, it is possible to perform good current writing.
[0981]
In addition, the area (white area) of the white display area (area having a certain luminance) and the area (black area) of the black display area (area of a predetermined luminance or less) are mixed on the screen. It is effective to add a function of stopping precharge when the ratio is within a certain range (appropriate precharge). This is because vertical streaks occur in the image in this certain range. Of course, conversely, precharging may be performed within a certain range. Another reason is that when the image moves, the image becomes noise-like. The appropriate precharge can be easily realized by counting (calculating) the data of the pixels corresponding to the white area and the black area in the arithmetic circuit.
[0982]
It is also effective to make the precharge control different for R, G, and B. This is because the EL display element 15 has different light emission start voltages and light emission luminances for R, G, and B. For example, R stops or starts precharging when the ratio of white area of predetermined luminance: black area of predetermined luminance is 1:20 or more, and G and B indicate the ratio of white area of predetermined luminance: black area of predetermined luminance. A method of stopping or starting the precharge at 1:16 or more is exemplified. According to the results of experiments and studies, in the case of the organic EL panel, the ratio of the white area of the predetermined luminance to the black area of the predetermined luminance is 1: 100 or more (that is, the black area is 100 times or more the white area), and the precharge is performed. Is preferably stopped. Further, it is preferable to stop the precharge when the ratio of the white area of the predetermined luminance: the black area of the predetermined luminance is 1: 200 or more (that is, the black area is 200 times or more of the white area).
[0983]
Further, the precharge will be described. FIG. 232 shows another embodiment of the precharge circuit. The difference from the embodiment of FIG. 66 is that the precharge switch 481a is controlled by a precharge enable (PEN) and a precharge select (PSL). The control switch is OPV. The switch 656 of the current output stage is controlled by the PO signal.
[0984]
In this embodiment of the present invention, whether to precharge or not is determined by image data. As this control, the PSL signal and the PEN signal exhibit important functions.
[0985]
As described above, as shown in FIG. 235, the RGB image data (RDATA, GDATA, BDATA) is 8 bits each. The 8-bit RGB image data is gamma-converted by a gamma circuit 834 to be a 10-bit signal. The gamma-converted signal is subjected to FRC processing by a frame rate control (FRC) circuit 835 to be converted into 6-bit image data. A precharge control circuit (PC) 2351 generates a precharge control signal (H level when precharging and L level when not precharging) from the converted 6-bit image data. The method for generating the precharge will be described later.
[0986]
FIG. 236 is a block diagram mainly showing the precharge circuit 2363 of the source driver IC (circuit) 14. The precharge circuit 2363 corresponds to the circuits in FIGS. 66, 232, 233, and the like. The precharge control circuit 2351 outputs a precharge control signal PC signal (red (RPC), green (GPC), blue (BPC)). This PC signal is generated by the precharge control circuit 2351 of the control IC 81 shown in FIG. 235, and the PC signal is input to the selector circuit 2362 of the source driver IC 14 shown in FIG. 236.
[0987]
The selector circuit 2362 sequentially latches in the latch circuit 2361 corresponding to the output stage in synchronization with the main clock. The latch circuit 2361 has a two-stage structure of a latch circuit 2361a and a latch circuit 2361b. The latch circuit 2361b sends data to the precharge circuit 2363 in synchronization with the horizontal scanning clock (1H). That is, the selector sequentially latches the image data and PC data for one pixel row, and stores the data in the latch circuit 2361b in synchronization with the horizontal scanning clock (1H).
[0988]
In FIG. 236, R, G, and B of the latch circuit 2361 are latch circuits for 6-bit RGB image data, and P is a latch circuit for latching 3 bits of a precharge signal (RPC, GPC, BPC). .
[0989]
When the output of the latch circuit 2361b is at the H level, the precharge circuit 2363 turns on the switch 481a and outputs a precharge voltage to the source signal line 18. The current output circuit 654 outputs a program current to the source signal line 18 according to the image data.
[0990]
If the configuration of FIGS. 235 and 236 is schematically illustrated, the configuration of FIG. 237 is obtained. 237 and 238 show a configuration in which a plurality of source driver ICs (circuits) 14 are mounted on one display panel (cathode connection of the source driver IC) as shown in FIG. Further, CSEL1 and CSEL2 in FIGS. 237 and 238 are select signals of the IC chip. The IC chip is selected based on the CSEL signal, and it is determined whether to input the image data and the PC signal.
[0991]
In the configurations of FIGS. 236 and 237, a PC signal is generated corresponding to each of the RGB image data. It is preferable to apply the precharge for each of RGB as described above. However, in moving image display and natural image display, it is often not necessary to determine whether or not to precharge each RGB. That is, RGB may be converted (converted) into a luminance signal, and whether or not to perform precharge may be determined based on the luminance. This is the configuration of FIG. 238. In the configuration of FIG. 237, the PC signal requires three bits (RPC, GPC, BPC), but in the configuration of FIG. 238, the PC signal may be one bit of RGBPC. Therefore, in the latch circuit 2361 of FIG. 236, P may be a 1-bit latch. In the following description, from the viewpoint of facilitating the description and facilitating the drawing, the description will be made without considering the RGB.
[0992]
The configuration of the present invention described above is characterized in that the controller 81 generates a PC signal (precharge control signal) based on image data, and the source driver IC 14 latches the PC signal and synchronizes with the 1H synchronization signal to generate the source signal line 18. It is characterized in that it is applied to Further, as shown in FIG. 235, the controller 81 can easily change the generation of the precharge signal by the precharge mode (PMODE) signal. For example, PMODE refers to a mode in which only gradation 0 is precharged, a mode in which a predetermined gradation range such as gradations 0-7 is precharged, and a case in which image data changes from bright image data to dark image data. A mode, a mode for precharging when low gradation display is continuously performed in a certain frame, and the like are exemplified.
[0993]
Note that the present invention is not limited to determining whether to precharge data of one pixel. For example, a precharge determination may be made based on image data of a plurality of pixel rows. Further, the precharge determination may be performed in consideration of the image data of the peripheral pixels to be precharged (for example, weighting processing). Also, a method of changing the precharge judgment between a moving image and a still image is exemplified. It is important that the controller generates a precharge signal based on image data, thereby exhibiting good versatility. Hereinafter, the precharge determination and the precharge mode will be mainly described.
[0994]
In the present invention, the precharge driving is described as outputting a precharge voltage, but the present invention is not limited to this. A method in which a current shorter than one horizontal scanning period and larger than the program current is written to the source signal line 18 may be employed. That is, a method of writing a precharge current to the source signal line 18 and then writing a program current to the source signal line 18 may be employed. There is no difference that the precharge current physically causes the voltage change. A method of performing precharge with a precharge current is also a category of the precharge drive of the present invention. For example, in FIG. 223, the precharge voltage changes by switching the electronic regulator 451. The electronic volume 451 may be changed to a current output electronic volume. The change can be easily realized by combining a plurality of current mirror circuits. In FIGS. 232 and 233, the precharge voltage Vp may be changed to a current output composed of a current mirror circuit. In the present invention, for the sake of simplicity, the description will be made assuming that precharge driving is performed with a precharge voltage.
[0995]
Further, the application of the precharge voltage (current) is not limited to applying a constant precharge voltage (current). For example, a plurality of precharge voltages may be applied to the source signal line. For example, a method in which a first precharge voltage 5 (V) is applied for 5 (μsec) and then a second precharge voltage 4.5 (V) is applied for 5 (μsec). After that, the program current Iw is applied to the source signal line 18. Further, the precharge voltage may be changed in a sawtooth shape. Further, a rectangular wave may be applied. Further, a precharge voltage (current) may be superimposed on a regular program current (voltage). Further, the magnitude of the precharge voltage (current) and the application period of the precharge voltage (current) may be changed in accordance with the image data.
[0996]
Although the present invention is described on the assumption that a precharge voltage (current) is applied in a current drive system, the precharge drive is also effective in a voltage drive system. In the voltage driving method, since the size of the driving transistor for driving the EL element 15 is large, the gate capacitance is large. Therefore, there is a problem that it is difficult to write a regular program voltage. In order to solve this problem, by performing precharge before applying the program voltage, the driving transistor can be reset and good writing can be realized. Therefore, the precharge driving method of the present invention is not limited to the current program driving. In the embodiment of the present invention, for ease of explanation, a description will be given by exemplifying a pixel configuration (see FIG. 1 and the like) driven by current programming.
[0997]
In the embodiment of the present invention, the precharge driving method does not operate only on the driving transistor 11a. For example, in the pixel configuration shown in FIG. 38, it also acts on the transistor 11a forming the current mirror circuit to exert an effect. The precharge drive method of the present invention has one object of charging and discharging the parasitic capacitance of the source signal line 18 viewed from the source driver IC (circuit) 14. It is also intended to charge and discharge the parasitic capacitance of the device.
[0998]
The precharge voltage (current) has one purpose of improving black display, but is not limited to this. By applying a white writing precharge voltage (current) for facilitating writing of white display, good white display can be realized. In other words, the precharge driving of the present invention is to apply a predetermined voltage (current) to facilitate writing of the program current (program voltage) before writing the program current (program voltage), and to perform precharge. It is.
[0999]
The present invention will be described on the assumption that precharging is performed in black display, but this is basically a case where the operation is performed with a sink current from the driving transistor 11a to the source driver IC (circuit) 14. When the driving transistor 11a or the like is an N-channel transistor, programming is performed with a source current from the source driver IC (circuit) 14. In this case, a pixel configuration in which white display is difficult to write occurs. Therefore, the precharge driving method of the present invention changes the source signal line 18 and the like to a predetermined potential, and the precharge in white display or the precharge in black display is only an embodiment. Therefore, it is not limited to these.
[1000]
The application timing of the precharge voltage (current) is preferably such that the precharge voltage (current) is written in a state where the pixel row to which the program voltage (current) is to be written is selected. However, the present invention is not limited to this. In the selected state, a precharge voltage (current) may be applied to the source signal line 18 to perform a precharge, and thereafter, a pixel row to which a program current (voltage) is to be written may be selected.
[1001]
Also, the precharge voltage is applied to the source signal line 18, but other methods are also exemplified. For example, the applied voltage (Vdd) to the anode terminal or the applied voltage (Vss) to the cathode terminal may be changed (precharge voltage is applied). By changing the anode voltage or the cathode voltage, the writing capability of the driving transistor 11a is expanded. Therefore, a precharge effect is exhibited. In particular, the effect of implementing the method of changing the anode voltage (Vdd) in a pulsed manner is high.
[1002]
FIG. 239A is an explanatory diagram when only the gradation 0 is precharged. The precharge of only the gradation 0 is a preferable method since there is no gradation jump and a good black display can be realized. In FIG. 239, the row number indicates a pixel row number. In the pixel rows, when the image data is sequentially rewritten from the first pixel row to the n-th pixel row, and the current programming is performed to the last pixel row n, the current programming is started from the first pixel row.
[1003]
The image data is 64-gradation image data. The image data takes values from 0 to 63. As a matter of course, in the case of 256 gradations, values from 0 to 255 are taken. PSL is a precharge select signal, and when H level (symbol H), output of the precharge voltage is permitted. At the time of the L level, the precharge voltage is not output. PEN is a precharge enable signal. This PEN is a signal output by the judgment of the controller 81. That is, the controller sets the PEN signal to the H or L level based on the image data. When PEN is at an H level, it is a determination signal to precharge, and when it is at an L level, it is a determination signal not to precharge. In FIG. 239, the PEN signal is at the H level only when the gradation is 0. The P output is an on / off state of the switch 481a (see FIGS. 232 and 233). In the table, .largecircle. Indicates that the switch 481a is on (the state in which the precharge voltage Vp is applied to the source signal line 18). X indicates that the switch 481a is off (a state in which the precharge voltage is not applied to the source signal line 18).
[1004]
In (a) of FIG. 239, the PEN signal is at H at locations corresponding to pixel row number 3 and pixel row number 8. At the same time, in the pixel row numbers 3 and 8, the PSL signal is also at the H level, so that the P output is ○ (the state in which the precharge voltage Vp is output. In FIG. 239 (b), the PEN signal is 239 is the same as (a) of Fig. 239, but the PSL signal is at the L level, so that the P output is constantly in the state of x (the precharge voltage Vp is not output). Is also output from the controller 81. However, it is preferred that the PEN signal be adjustable by the user.
[1005]
The period during which the precharge voltage Vp is output can be set by the counter 651 in FIG. This counter is a programmable counter, and operates based on a set value from a controller or a user set value. The counter 651 is configured to operate in synchronization with the main clock (CLK).
[1006]
FIG. 240A is an explanatory diagram when only gradation 0 to gradation 7 are precharged. The method of precharging only in the low gradation area is effective as a measure for solving the problem that current driving is difficult to write in the black display area. The range of the precharge can be set by the controller 81.
[1007]
In FIG. 240, the PEN signal is at the H level only when the gradation is 0-7.
The P output is an on / off state of the switch 481a (see FIGS. 232 and 233). In FIG. 240A, the PEN signal is H because the image data is 7 or less at the locations corresponding to the pixel row numbers 3, 5, 6, 7, 11, 12, and 13. At the same time, since the PSL signal is also at the H level in the above locations, the P output is ○ (the state in which the precharge voltage Vp is output). In (b) of FIG. 240, since the PSL signal is at the L level, all the P outputs are × (the state in which the precharge voltage is not applied).
[1008]
FIG. 241 is an explanatory diagram of a driving method for performing precharge when the luminance of the pixel 16 decreases. In the current programming method, the programming current Iw when the luminance of the pixel 16 is increased (white display) is large. Therefore, even if the source signal line 18 has a parasitic capacitance, the parasitic capacitance can be sufficiently charged and discharged. However, when the pixel 16 is programmed for black display, the programming current is small, and the parasitic capacitance of the source signal line 18 cannot be sufficiently charged and discharged. Therefore, when the program current to be written to the pixel 16 becomes large, it is often unnecessary to precharge. Conversely, when the current written to the pixel 16 becomes small (when black display is performed), it is necessary to precharge.
[1009]
FIG. 241 is an explanatory diagram of a driving method for performing precharge when the luminance of the pixel 16 decreases. The image data of the first pixel row is 39. Therefore, the source signal line 18 holds a potential for current programming the pixel 16 to image data 39. The image data of the second pixel row is 12. Therefore, the source signal line 18 needs to be set to a potential corresponding to the image data 12. However, the program current decreases from gradation 39 to gradation 12. Therefore, a state where the source signal line 18 cannot be sufficiently charged and discharged may occur. In order to cope with this problem, precharging is performed (the PEN signal becomes H level). Similar determination results are obtained for pixel rows 3, 5, 6, 8, 11, 12, 13, and 15.
[1010]
The image data in the third pixel row is 0. Therefore, the source signal line 18 holds a potential for current programming the pixel 16 to image data 0. The image data of the fourth pixel row is 21. Therefore, it is necessary to set the source signal line 18 to a potential corresponding to the image data 21. The program current increases from gradation 0 to gradation 21. Therefore, the source signal line 18 can be charged and discharged sufficiently. Therefore, there is no need to precharge in the fourth pixel row.
[1011]
The above determination is performed by the controller 81. As a result of the implementation, as shown in FIG. 241 (a), the PEN signal becomes H level in the pixel rows 2, 3, 5, 6, 8, 11, 12, 13, and 15. That is, the result is that the pixel rows are precharged. In FIG. 241 (a), the PSL signal is also at the H level, and therefore, as can be seen from the column of P output, the P output is generated in pixel rows 2, 3, 5, 6, 8, 11, 12, 13, and 15. ○ (Precharge). Note that precharge is not performed in other pixel rows.
[1012]
In FIG. 241 (b), the PEN signal is the same as in FIG. 241 (a), but the PSL signal is at the L level. Therefore, the P output is constantly in the state of x (the precharge voltage Vp is not output). Basically, the PEN signal is also output from the controller 81. However, it is preferred that the PEN signal be user adjustable.
[1013]
FIG. 242 shows a method in which the precharge methods shown in FIGS. 240 and 241 are combined. In this method, precharging is performed when the luminance of the pixel 16 decreases, and precharging is performed when the program current of the pixel 16 has a low luminance of 0-7 gradations.
It is possible to change which gray level or lower the precharge is based on a set value of the controller IC81. It is also possible for the user to change it. Changes are made to the table inside the controller from the microcomputer via the serial interface.
[1014]
The image data is the same as in the embodiment of FIG. However, in FIG. 242, since the image data is 12 in the second pixel row and 12 in the fifteenth pixel row, the PEN signal is the L level determination result. As described above, if the magnitude of the program current Iw is equal to or larger than a certain value, the parasitic capacitance of the source signal line 18 can be charged and discharged. Therefore, there is no need to precharge. Conversely, when precharging, the potential of the source signal line 18 changes to the black display potential, and it takes time to return to the halftone display potential.
[1015]
The above determination is performed by the controller 81. As a result of the implementation, as shown in FIG. 242 (a), the PEN signal becomes H level in the pixel rows 3, 5, 6, 8, 11, 12, and 13. That is, the result is that the pixel rows are precharged.
In FIG. 242 (a), since the PSL signal is also at the H level, as can be seen from the P output column, the P output is ○ (precharged) in pixel rows 3, 5, 6, 8, 11, 12, and 13. Do). Note that precharge is not performed in other pixel rows. In FIG. 242 (b), the PEN signal is the same as in FIG. 242 (a), but the PSL signal is at the L level. Therefore, the P output is constantly in the state of x (the precharge voltage Vp is not output).
[1016]
Although the above embodiment does not describe the precharge of each RGB, it goes without saying that it is preferable to perform the precharge determination for each RGB as shown in FIG. This is because image data is different for each RGB. Particularly, as shown in FIGS. 41, 125, and 126, good results can be obtained when the RGB pixels are arranged in the column direction. This is because pixel data of the same color is continuously applied to each source signal line.
[1017]
FIG. 243 shows a driving method for performing precharge in the range of gradation 0-7 as in FIG. The controller 81 determines the precharge of each RGB. As a result of the implementation, as shown in FIG. 243, in the R image data, the PEN signal goes to the H level in the pixel rows 3, 5, 6, 7, 8, 11, 12, and 13. That is, the result is that the pixel rows are precharged. In the G image data, the PEN signal becomes H level in the pixel rows 3, 7, 9, 11, 12, 13, and 14. That is, the result is that the pixel rows are precharged. In the B image data, the PEN signal becomes H level in pixel rows 1, 2, 3, 6, 7, 8, 9, and 15. That is, the result is that the pixel rows are precharged.
[1018]
In the above embodiment, it was determined whether or not to perform precharge corresponding to a pixel row.
However, the present invention is not limited to this. It goes without saying that the size or change of the image data applied to each pixel may be determined on a frame (field) basis to determine whether or not to precharge. FIG. 244 shows the embodiment.
[1019]
FIG. 244 shows a change in image data focusing on a certain pixel 16. The first row of the table in FIG. 244 indicates the frame number. The second row of the table shows a change in image data programmed in a certain pixel 16. FIG. 244 is a modified example of the driving method of precharging at gradation 0 as in FIG. In FIG. 239, the precharge is always performed at the gradation 0. FIG. 244 shows a method of precharging when gradation 0 is continuous for a certain number of frames. The continuation is indicated by a counter.
[1020]
In FIG. 244 (a), the gradation is 0 in frames 3, 4, 5, 6, 11, and 12. Therefore, the count value is sequentially counted from the third frame to the sixth frame. Also, it is counted in frames 11 and 12. In (a) of FIG. 244, the control is performed so that the precharge is performed when the gradation 0 continues for three frames. Therefore, the P output becomes ○ (precharge voltage is output) in frames 5 and 6. In the frames 11 and 12, the gradation 0 is continuous only in two frames, so that no precharge is performed.
[1021]
In (b) of FIG. 244, the count control is performed by the PSL signal. When the PSL signal is at the H level, the count value is increased. In (b) of FIG. 244, since the PSL signal is at the L level in frames 5 and 12, the count is not incremented. Therefore, the precharge voltage is output only in frame 6.
[1022]
Note that in FIG. 244, precharge is performed when gradation 0 continues for a fixed frame. However, the present invention is not limited to this. As described with reference to FIG. 240, a predetermined gradation range (for example, gradation 0 It may be controlled so that precharging is performed when −7) continues. Further, the present invention is not limited to continuous frames, and may be discrete. In addition, the control may be performed such that the precharge is performed when a certain gradation range (for example, only gradation 0, gradation 0-7, etc.) is continuous in continuous pixel rows.
[1023]
As described above, in the precharge driving method of the present invention, it is determined whether or not to perform precharge based on a value of image data or a change state of image data or an image data value in the vicinity of a pixel to be precharged and its change. Apply a precharge voltage (current). Information on whether to apply a precharge is held in a source driver IC (circuit). Therefore, the configuration is easy because the source driver IC (circuit) 14 only includes the latch circuit 2361 (holding circuit or storage means (memory)) that latches the precharge signal. In addition, any of the precharge methods can be dealt with only by changing the program of the controller IC, so that there is versatility.
[1024]
In FIG. 232, by turning on / off the switch 481a, the precharge voltage Vp is output from the terminal 681, and the switch 655 is turned on / off by the PO signal to apply the program current Iw from the terminal 681 to the source signal line 18. However, in the configuration of FIG. 232, when the switch 481a is closed and the precharge voltage Vp is applied to the terminal 681, the precharge voltage Vp is also applied to the current output circuit 654 (unit transistor group 521c). When a precharge voltage is applied to the current output circuit 654, an abnormal operation may occur in the current output circuit 654.
[1025]
To solve this problem, as shown in FIG. 233, the switch 655 is arranged between the current output circuit 654 and the point A, and the switch 656 is controlled by inverting the logic of the OPV signal by the inverter 62. I do. That is, when the switch 481a is closed, the switch 656 is opened (opened). With this configuration, when the precharge voltage Vp is applied to the terminal 681, the switch 655 is open, so that the precharge voltage is not applied to the current output circuit 654. This timing chart is shown in FIG. In FIG. 234 (a), the PO signal is at L during the period t when the OPV signal is at H. More preferably, the switch 655 is off (open) before and after the period during which the switch 481a is closed. That is, as shown in FIG. 234 (b), the PO signal is at the L level during the period of t2 including before and after the period when the OPV signal is at the H level. This is to prevent the adverse effect of the transient phenomenon due to the on / off of the switch 481a.
[1026]
As shown in FIG. 1, when the driving transistor 11a and the selection transistors (11b, 11c) of the pixel 16 are P-channel transistors, a punch-through voltage is generated.
This is because the potential fluctuation of the gate signal line 17a penetrates to the terminal of the capacitor 19 via the GS capacitance (parasitic capacitance) of the selection transistor (11b, 11c). When the P-channel transistor 11b turns off, the voltage becomes Vgh. Therefore, the terminal voltage of the capacitor 19 slightly shifts to the Vdd side. Therefore, the gate (G) terminal voltage of the transistor 11a increases, and the display becomes more black. Therefore, good black display can be realized.
[1027]
However, although a complete black display of the 0th gradation can be realized, it is difficult to display the 1st gradation and the like. Alternatively, a large gradation jump from the 0th gradation to the first gradation occurs, or blackout occurs in a specific gradation range.
[1028]
The configuration that solves this problem is the configuration in FIG. It has a function of raising the output current value. The main purpose of the raising circuit 541 is to compensate for the penetration voltage. Further, even if the image data has the black level 0, the current can flow to some extent (several tens of nA) and can be used for adjusting the black level.
[1029]
Basically, FIG. 54 is obtained by adding a raising circuit (a portion surrounded by a dotted line in FIG. 54) to the output stage in FIG. FIG. 54 assumes three bits (K0, K1, K2) as the current value raising control signal, and outputs a current value of 0 to 7 times the current value of the grandchild current source by using the three-bit control signal. It can be added to the current.
[1030]
The above is the basic outline of the source driver IC (circuit) 14 of the present invention. Hereinafter, the source driver IC (circuit) 14 of the present invention will be described in further detail.
[1031]
There is a linear relationship between the current I (A) flowing through the EL element 15 and the light emission luminance B (nt). That is, the current I (A) flowing through the EL element 15 is proportional to the light emission luminance B (nt). In the current driving method, one step (gradation) is a current (unit transistor 484 (one unit)).
[1032]
Human visual perception of luminance has a squared characteristic. In other words, when changing according to the square curve, the brightness is recognized as changing linearly. However, according to the relationship in FIG. 83, the current I (A) flowing through the EL element 15 and the emission luminance B (nt) are proportional to both the low luminance region and the high luminance region. Therefore, when the gradation is changed in steps of one step (one gradation), the luminance change for one step is large (blackout occurs) in the low gradation part (black area). Since the high gradation part (white area) substantially coincides with the linear area of the square curve, the luminance change for one step is recognized as changing at equal intervals. From the above, in the current driving method (in the case where the current step is one step) (in the current driving method of the source driver IC (circuit) 14), the display of the black display area is particularly problematic.
[1033]
In order to solve this problem, the gradient of the current output in the low gradation area (gradation 0 (complete black display) to gradation (R1)) is reduced, and the high gradation area (gradation (R1) to maximum gradation (R1) )) To increase the slope of the current output. That is, in the low gradation area, the current amount that increases per gradation (one step) is set to be small. In the high gradation area, the amount of current increases per gradation (one step). By making the amount of current changing per step different between the high gradation region and the low gradation region, the gradation characteristic becomes close to a square curve, and no blackout occurs in the low gradation region.
[1034]
In the above-described embodiment, the current gradient has two levels of the low gradation area and the high gradation area. However, the present invention is not limited to this. It goes without saying that three or more stages may be used. However, it is needless to say that the two-stage configuration is preferable because the circuit configuration is simplified. Preferably, the gamma circuit is configured to generate five or more gradients.
[1035]
The technical idea of the present invention is a circuit for performing gray scale display by current output in a current driver type source driver IC (circuit) or the like. Therefore, the display panel is limited to an active matrix type. However, a simple matrix type is also included.) This means that a plurality of current increases per gradation step exist.
[1036]
In a current-driven display panel such as an EL, the display luminance changes in proportion to the amount of current applied. Therefore, in the source driver IC (circuit) 14 of the present invention, the luminance of the display panel can be easily adjusted by adjusting the reference current that flows through one current source (one unit transistor) 484. .
[1037]
In the EL display panel, the luminous efficiencies are different among R, G, and B, and the color purity is different from the NTSC standard. Therefore, in order to optimize the white balance, it is necessary to appropriately adjust the RGB ratio. The adjustment is performed by adjusting the respective reference currents of RGB. For example, the reference current of R is 2 μA, the reference current of G is 1.5 μA, and the reference current of B is 3.5 μA. As described above, among the reference currents of at least a plurality of display colors, it is preferable that at least one of the reference currents can be changed, adjusted, or controlled.
[1038]
In the current driving method, the relationship between the current I flowing through the EL and the luminance has a linear relationship. Therefore, adjustment of the white balance by mixing RGB only requires adjusting the RGB reference current at one point of a predetermined luminance. In other words, if the RGB reference current is adjusted at one point of the predetermined luminance and the white balance is adjusted, the white balance is basically obtained over all gradations. Therefore, the present invention is characterized in that it has an adjusting means capable of adjusting the RGB reference currents, and that it has a one-point or multi-point gamma curve generating circuit (generating means). The above is a circuit method specific to the current control EL display panel.
[1039]
In the gamma circuit of the present invention, as an example, the gradation is increased by 10 nA per gradation in the low gradation region (the gradient of the gamma curve in the low gradation region). In addition, in the high gradation region, the value increases by 50 nA per gradation (the slope of the gamma curve in the high gradation region).
[1040]
The amount of current increase per gradation in the high gradation region / the amount of current increase per gradation in the low gradation region is called a gamma current ratio. In this embodiment, the gamma current ratio is 50 nA / 10 nA = 5. The gamma current ratio of RGB is the same. That is, in RGB, the current (= program current) flowing through the EL element 15 is controlled with the gamma current ratio kept the same.
[1041]
If the gamma current ratio is adjusted while maintaining the same value for RGB, the circuit configuration becomes easy. For each color, a constant current circuit that generates a reference current to be applied to the low gradation part and a constant current circuit that generates a reference current to be applied to the high gradation part are manufactured, and a volume that adjusts the current flowing relatively therebetween Is to be manufactured (arranged).
[1042]
FIG. 56 is a configuration diagram of the constant current generation circuit section in the low current region. FIG. 57 is a configuration diagram of a constant current circuit portion and a raised current circuit portion in a high current region. As shown in FIG. 56, the reference current INL is applied to the low current source circuit section, and this current basically becomes a unit current, and the required number of unit transistors 484 operate according to the input data L0 to L4. The program current IwL of the low current section flows.
[1043]
Further, as shown in FIG. 57, the reference current INH is applied to the high current source circuit section, and this current basically becomes a unit current, and the required number of unit transistors 484 operate according to the input data H0 to L5. The program current IwH of the low current portion flows as a sum.
[1044]
The same applies to the raising current circuit section. As shown in FIG. 57, the reference current INH is applied, and this current basically becomes a unit current, and the required number of unit transistors 484 operate according to the input data AK0 to AK2. , A current IwK corresponding to the raising current flows as a sum thereof
The program current Iw flowing through the source signal line 18 is Iw = IwH + IwL + IwK. The ratio between IwH and IwL, that is, the gamma current ratio is set to satisfy the first relationship described above.
[1045]
As shown in FIGS. 56 and 57, the on / off switch 481 includes an inverter 562 and an analog switch 561 including a P-channel transistor and an N-channel transistor. By configuring the switch 481 with the analog switch 561 including the inverter 562, the P-channel transistor, and the N-channel transistor, the on-resistance can be reduced, and the voltage drop between the unit transistor 484 and the source signal line 18 can be reduced. It can be extremely small. It goes without saying that this applies to other embodiments of the present invention.
[1046]
The operation of the low current circuit section of FIG. 56 and the high current circuit section of FIG. 57 will be described. The source driver IC (circuit) 14 of the present invention is composed of five bits of the low current circuit parts L0 to L4 and six bits of the high current circuit parts H0 to H5. The data input from outside the circuit is 6 bits D0 to D5 (64 gradations for each color). The 6-bit data is converted into 5 bits L0 to L4 and 6 bits of the high current circuit units H0 to H5, and a program current Iw corresponding to the image data is applied to the source signal line.
That is, the input 6-bit data is converted into 5 + 6 = 11-bit data.
Therefore, a highly accurate gamma curve can be formed.
[1047]
As described above, input 6-bit data is converted into 5 + 6 = 11-bit data. In the present invention, the number of bits (H) of the circuit in the high current region is made equal to the number of bits of the input data (D), and the number of bits (L) of the circuit in the low current region is the number of bits of the input data (D). -1. Note that the number of bits (L) of the circuit in the low current region may be the number of bits -2 of the input data (D). With this configuration, the gamma curve in the low current region and the gamma curve in the high current region are optimized for displaying an image on the EL display panel.
[1048]
In the current driving method, the relationship between the current I flowing through the EL and the luminance has a linear relationship. Therefore, adjustment of the white balance by mixing RGB only requires adjusting the RGB reference current at one point of a predetermined luminance. In other words, if the RGB reference current is adjusted at one point of the predetermined luminance and the white balance is adjusted, the white balance is basically obtained over all gradations. This point is also a characteristic effect of the current driving method of the present invention.
[1049]
In the case of a gamma curve of a broken line (having a bent position) as shown in FIG. First, in order to obtain RGB white balance, it is necessary to make the bending position (gradation R1) of the gamma curve the same for RGB. By making them the same, in the current driving method, the relative relationship of the gamma curves can be made the same in RGB. Further, it is necessary to make the ratio of the inclination of the low gradation area to the inclination of the high gradation area constant in RGB. By making them constant, in the current drive method, the relative relationship of the gamma curves can be made the same for RGB.
[1050]
For example, an increase of 10 nA per gradation in a low gradation region (a gradient of a gamma curve in a low gradation region) and an increase of 50 nA per gradation in a high gradation region (a gradient of a gamma curve in a high gradation region). The amount of current increase per gradation in the high gradation region / the amount of current increase per gradation in the low gradation region is called a gamma current ratio. In this embodiment, the gamma current ratio is 50 nA / 10 nA = 5. In RGB, the current flowing through the EL element 15 is adjusted with the gamma current ratio kept the same.
[1051]
FIG. 248 shows an example of the gamma curve. In (a) of FIG. 248, the current increase per gradation is large in both the low gradation part and the high gradation part. In FIG. 248 (b), the increase in current per gradation in the low gradation part and the high gradation part is smaller than that in FIG. 248 (a). However, the gamma current ratio is the same in both (a) of FIG. 248 and (b) of FIG. As described above, adjusting the gamma current ratio while maintaining the same ratio for RGB involves generating, for each color, a constant current circuit that generates a reference current to be applied to the low gradation portion and a reference current to be applied to the high gradation portion. This is because it is only necessary to produce a constant current circuit and to produce (arrange) a volume for adjusting a current flowing relatively between them.
[1052]
FIG. 245 shows a circuit configuration that varies the output current while maintaining the gamma current ratio. The current flowing through the current sources 473L and 473H is changed by the current control circuit 692 while maintaining the gamma current ratio between the reference current source 691L in the low current region and the reference current source 691H in the high current region.
[1053]
As shown in FIG. 246, it is preferable to detect a relative temperature of the display panel by a temperature detection circuit 701 formed in the IC chip (circuit) 14. This is because the EL elements have different temperature characteristics depending on the materials constituting RGB. This temperature detection utilizes the fact that the state of the junction of the bipolar transistor changes with temperature and the output current changes with temperature. The detected temperature is fed back to the temperature control circuit 702 arranged (formed) for each color, and the current control circuit 692 performs temperature compensation.
[1054]
It is appropriate that the gamma ratio has a relationship of 3 or more and 10 or less. More preferably, a relationship of 4 or more and 8 or less is appropriate. In particular, the gamma current ratio preferably satisfies the relationship of 5 or more and 7 or less. This is called a first relationship.
[1055]
Further, it is appropriate that the change point (the gradation R1 in FIG. 247) between the low gradation part and the high gradation part is set to 1/32 or more and 1/4 or less of the maximum gradation number K. For example, if the maximum number of gradations K is 64 gradations of 6 bits, 64/32 = 2nd gradation or more and 64/4 = 16th gradation or less. More preferably, the change point (the gradation R1 in FIG. 247) between the low gradation part and the high gradation part is appropriately set to be 1/16 or more and 1/4 or less of the maximum gradation number K. For example, assuming that the maximum number of gradations K is 64 gradations of 6 bits, 4816 = fourth gradation or more and 64/4 = 16th gradation or less. More preferably, it is appropriate to set the maximum gradation number K to 1/10 or more and 1/5 or less. If the calculation results in a fractional part, it is rounded down. For example, assuming that the maximum number of gradations K is 64 gradations of 6 bits, 4810 = 6th gradation or more and 64/5 = 12th gradation or less. The above relationship is called a second relationship.
[1056]
The above description relates to the relationship between the gamma current ratios of the two current regions. However, the above second relationship is also applied to a case where there are gamma current ratios in three or more current regions (that is, there are two or more bending points). That is, it is only necessary to apply the relationship to any two inclinations for three or more inclinations.
[1057]
By simultaneously satisfying both the first relationship and the second relationship, it is possible to realize good image display without blackout.
[1058]
FIG. 250 shows an embodiment in which a plurality of current driver type source driver circuits (ICs) 14 of the present invention are used for one display panel. The source driver IC of the present invention includes a slave / master (S / M) terminal 2502 on the assumption that a plurality of source driver ICs 14 are used. By setting the S / M terminal 2502 to the H level, the chip operates as a master chip, and outputs a reference current from a reference current output terminal (not shown). This current is a current flowing to the INL and INH terminals of the slave source driver IC 14 (14a, 14c) in FIGS. 56 and 57. By setting the S / M terminal 2502 to L level, the source driver IC 14 operates as a slave chip and receives a reference current of the master chip from a reference current input terminal (not shown).
[1059]
The reference current passed between the reference current input terminal and the reference current output terminal is of two systems: a low gradation region and a high gradation region for each color. Note that the reference current is transmitted through the reference current transfer wiring 2501. Therefore, for three colors of RGB, there are 6 systems of 3 × 2. In the above embodiment, two systems are used for each color. However, the present invention is not limited to this, and three or more systems may be used for each color.
[1060]
In the current driving method according to the present invention, as shown in FIG. 249, a bending point (gradation R1 or the like) can be changed. In FIG. 249 (a), the gradation R1 changes the low gradation part and the high gradation part, and in FIG. 249 (b), the gradation R2 changes the low gradation part and the high gradation part. I have. Thus, the bending position can be changed at a plurality of locations.
[1061]
Specifically, the present invention can realize 64 gradation display. The bending point (R1) is none, the second gradation, the fourth gradation, the eighth gradation, and the sixteenth gradation. In addition, since the completely black display has the gradation 0, the bending points are 2, 4, 8, and 16. If the gradation of the completely black display is the gradation 1, the bending point is 3, 5, 9, 17, and 33. As described above, the circuit configuration can be facilitated by configuring such that the bend position can be set at a location that is a multiple of 2 (or a location that is a multiple of 2 + 1: when complete black display is set to gradation 1). The effect occurs.
[1062]
FIG. 56 is a configuration diagram of the current source circuit section in the low current region. FIG. 57 is a configuration diagram of a current source section and a raised current circuit section in a high current region. As shown in FIG. 56, the reference current INL is applied to the low current source circuit section, and this current basically becomes a unit current, and the required number of current sources 484 operate according to the input data L0 to L4. The program current IwL of the low current section flows.
[1063]
Further, as shown in FIG. 57, the reference current INH is applied to the high current source circuit section, and this current basically becomes a unit current, and the required number of current sources 484 operate according to the input data H0 to L5. The program current IwH of the high current portion flows as a sum.
[1064]
The same applies to the raising current circuit section, in which a reference current INH is applied as shown in FIG. 57, and this current basically becomes a unit current, and the required number of current sources 484 operate according to the input data AK0 to AK2. , A current IwK corresponding to the raising current flows as a sum thereof
The program current Iw flowing through the source signal line 18 is Iw = IwH + IwL + IwK. The ratio between IwH and IwL, that is, the gamma current ratio is set to satisfy the first relationship described above.
[1065]
As shown in FIGS. 56 and 57, the on / off switch 481 includes an inverter 562 and an analog switch 561 including a P-channel transistor and an N-channel transistor. By configuring the switch 481 with the analog switch 561 including the inverter 562, the P-channel transistor, and the N-channel transistor, the on-resistance can be reduced, and the voltage drop between the current source 484 and the source signal line 18 can be reduced. It can be extremely small.
[1066]
The operation of the low current circuit section of FIG. 56 and the high current circuit section of FIG. 57 will be described. The source driver circuit (IC) 14 of the present invention is composed of five bits of low current circuit parts L0 to L4 and six bits of high current circuit parts H0 to H5. The data input from outside the circuit is 6 bits D0 to D5 (64 gradations for each color). The 6-bit data is converted into 5 bits L0 to L4 and 6 bits of the high current circuit units H0 to H5, and a program current Iw corresponding to the image data is applied to the source signal line.
That is, the input 6-bit data is converted into 5 + 6 = 11-bit data.
Therefore, a highly accurate gamma curve can be formed.
[1067]
As described above, input 6-bit data is converted into 5 + 6 = 11-bit data. In the present invention, the number of bits (H) of the circuit in the high current region is made equal to the number of bits of the input data (D), and the number of bits (L) of the circuit in the low current region is the number of bits of the input data (D). -1. Note that the number of bits (L) of the circuit in the low current region may be the number of bits -2 of the input data (D). With this configuration, the gamma curve in the low current region and the gamma curve in the high current region are optimized for displaying an image on the EL display panel.
[1068]
Hereinafter, a method of controlling the circuit control data (L0 to L4) in the low current region and the circuit control data (H0 to H4) in the high current region will be described with reference to FIGS. 252 to 254.
[1069]
The present invention is characterized by the operation of the current source 484a connected to the L4 terminal in FIG. 56 of FIG. This 484a is constituted by one transistor serving as one unit of current source. By turning on / off the transistor, control (on / off control) of the program current Iw is facilitated.
[1070]
FIG. 252 shows the signals applied to the low current side signal line (L) and the high current side signal line (H) when the low current region and the high current region are switched by gradation 4. Although FIGS. 252 to 254 show gradations 0 to 18, actually there are 63 gradations. Therefore, in each drawing, gradations of 18 or more are omitted. Further, the switch 481 is turned on when the value is "1" in the table, the current source 484 is connected to the source signal line 18, and the switch 481 is turned off when the value is "0" in the table. Note that the present invention is not limited to the 63rd gradation, and may be 255 gradations or more.
[1071]
In FIG. 252, in the case of gradation 0 of the complete black display, (L0 to L4) = (0, 0, 0, 0, 0) and (H0 to H5) = (0, 0, 0, 0, 0). Therefore, all the switches 481 are off, and the source signal line 18 has the program current Iw = 0.
[1072]
At gradation 1, (L0 to L4) = (1, 0, 0, 0, 0) and (H0 to H5) = (0, 0, 0, 0, 0). Therefore, one unit current source 484 in the low current region is connected to the source signal line 18. The unit current source in the high current region is not connected to the source signal line 18.
[1073]
At gradation 2, (L0 to L4) = (0, 1, 0, 0, 0) and (H0 to H5) = (0, 0, 0, 0, 0). Therefore, the two unit current sources 484 in the low current region are connected to the source signal line 18. The unit current source in the high current region is not connected to the source signal line 18.
[1074]
At gradation 3, (L0 to L4) = (1, 1, 0, 0, 0) and (H0 to H5) = (0, 0, 0, 0, 0). Therefore, the two switches 481La and 481Lb in the low current region are turned on, and the three unit current sources 484 are connected to the source signal line 18. The unit current source in the high current region is not connected to the source signal line 18.
[1075]
At gradation 4, (L0-L4) = (1,2681) and (H0-H5) = (0,0,0,0,0). Therefore, the three switches 481La, 481Lb, and 481Le in the low current region are turned on, and the four unit current sources 484 are connected to the source signal line 18. The unit current source in the high current region is not connected to the source signal line 18.
[1076]
At gradation 5 or higher, there is no change in the low current region (L0 to L4) = (1,2681). However, in the high current region, (H0 to H5) = (1, 0, 0, 0, 0) in gradation 5, the switch 481Ha is turned on, and one unit current source 481 in the high current region is supplied with the source signal. Connected to line 18. In gradation 6, (H0 to H5) = (0, 1, 0, 0, 0), the switch 481Hb is turned on, and the two unit current sources 481 in the high current region are connected to the source signal line 18. You. Similarly, at gradation 7, (H0 to H5) = (1, 1, 0, 0, 0), the two switches 481Ha and the switch 481Hb are turned on, and the three unit current sources 481 in the high current region are connected to the source signal 481. Connected to line 18. Further, in gradation 8, (H0 to H5) = (0, 0, 1, 0, 0), one switch 481Hc is turned on, and the four unit current sources 481 in the high current region are connected to the source signal line 18 and Connected. Thereafter, the switches 481 are sequentially turned on and off as shown in FIG. 252, and the program current Iw is applied to the source signal line 18.
[1077]
A characteristic of the above operation is an operation at a bending point. However, the bending point is a switching point between the low current region and the high current region. To be more precise, in the case of the gradation in the high current region, the low current IwL is added as the program current Iw. The expression point is not correct. That is, in the gradation of the high gradation part, the current corresponding to the step (gradation) of the high gradation part is added to the current of the low gradation part and becomes the program current Iw. The point is that the control bit (L) in the low current region does not change at the boundary of the one-step gradation (which may be a point or a point or a position where the current changes). At this time, "1" is set to the terminal L4 in FIG. 56, the switch 481e is turned on, and the current is flowing through the transistor 484a.
[1078]
Therefore, in gray level 4 in FIG. 252, four unit transistors (current sources) 484 in the low gray level portion operate. In the gray scale 5, four unit transistors (current sources) 484 in the low gray scale section operate and one transistor (current source) 484 in the high gray scale section operates. Thereafter, similarly, at the gradation 6, four unit transistors (current sources) 484 in the low gradation part operate and two transistors (current sources) 484 in the high gradation part operate. Therefore, at gradation 5 or more, which is a bending point, the current sources 484 in the low gradation area below the bending point are turned on for the number of gradations (four in this case). The sources 484 are turned on sequentially according to the number of gradations.
[1079]
Therefore, it can be seen that one of the transistors 484a having the L4 terminal in FIG. 56 functions effectively. If there is no transistor 484a, one transistor 484 in the high gradation part is turned on after gradation 3. Therefore, the switching point does not become a multiplier of 2, such as 4, 8, and 16. The multiplier of 2 is a state where only one signal is "1".
[1080]
Therefore, it is easy to determine the condition that the signal line with the weight of 2 has become "1". Therefore, the hardware scale of the condition determination can be reduced. That is, the logic circuit of the IC chip is simplified, and as a result, an IC with a small chip area can be designed (cost reduction is possible).
[1081]
FIG. 253 is an explanatory diagram of applied signals to the low current side signal line (L) and the high current side signal line (H) when the low current region and the high current region are switched by gradation 8.
[1082]
In FIG. 253, in the case of the gradation 0 of the complete black display, the same as in FIG. 252, (L0 to L4) = (0, 0, 0, 0, 0), and (H0 to H5) = (0) , 0, 0, 0, 0). Therefore, all the switches 481 are off, and the source signal line 18 has the program current Iw = 0.
[1083]
Similarly, at gradation 1, (L0 to L4) = (1, 0, 0, 0, 0) and (H0 to H5) = (0, 0, 0, 0, 0). Therefore, one unit current source 484 in the low current region is connected to the source signal line 18. The unit current source in the high current region is not connected to the source signal line 18.
[1084]
At gradation 2, (L0 to L4) = (0, 1, 0, 0, 0) and (H0 to H5) = (0, 0, 0, 0, 0). Therefore, the two unit current sources 484 in the low current region are connected to the source signal line 18. The unit current source in the high current region is not connected to the source signal line 18.
[1085]
At gradation 3, (L0 to L4) = (1, 1, 0, 0, 0) and (H0 to H5) = (0, 0, 0, 0, 0). Therefore, the two switches 481La and 481Lb in the low current region are turned on, and the three unit current sources 484 are connected to the source signal line 18. The unit current source in the high current region is not connected to the source signal line 18.
[1086]
Similarly, for gradation 4, (L0 to L4) = (0, 0, 1, 0, 0) and (H0 to H5) = (0, 0, 0, 0, 0). At gradation 5, (L0 to L4) = (1, 0, 1, 0, 0) and (H0 to H5) = (0, 0, 0, 0, 0). At gradation 6, (L0 to L4) = (0, 1, 1, 0, 0) and (H0 to H5) = (0, 0, 0, 0, 0). At gradation 7, (L0 to L4) = (1, 1, 1, 0, 0) and (H0 to H5) = (0, 0, 0, 0, 0).
[1087]
The gradation 8 is a switching point (bending position). At gradation 8, (L0-L4) = (1,1,1,0,1) and (H0-H5) = (0,0,0,0,0). Therefore, the four switches 481La, 481Lb, 481Lc, and 481Le in the low current region are turned on, and the eight unit current sources 484 are connected to the source signal line 18. The unit current source in the high current region is not connected to the source signal line 18.
[1088]
At gradation 8 or higher, there is no change in the low current region (L0 to L4) = (1, 1, 1, 0, 1). However, in the high current region, (H0 to H5) = (1, 0, 0, 0, 0) at gradation 9, the switch 481Ha is turned on, and one unit current source 481 in the high current region is supplied with the source signal. Connected to line 18.
[1089]
Hereinafter, similarly, the number of transistors 484 in the high current region increases by one according to the gradation step. That is, (H0 to H5) = (0, 1, 0, 0, 0) at gradation 10, the switch 481Hb is turned on, and the two unit current sources 481 in the high current region are connected to the source signal line 18. You. Similarly, at gradation 11, (H0 to H5) = (1, 1, 0, 0, 0), the two switches 481Ha and the switch 481Hb are turned on, and the three unit current sources 481 in the high current region are connected to the source signal 481. Connected to line 18. Further, in the gradation 12, (H0 to H5) = (0, 0, 1, 0, 0), one switch 481Hc is turned on, and the four unit current sources 481 in the high current region are connected to the source signal line 18 and Connected. Thereafter, the switches 481 are sequentially turned on and off as shown in FIG. 252, and the program current Iw is applied to the source signal line 18.
FIG. 254 is an explanatory diagram of applied signals to the low current side signal line (L) and the high current side signal line (H) in the case where the low current region and the high current region are switched by gradation 16. In this case, the basic operation is the same as in FIGS. 252 and 253.
[1090]
That is, in FIG. 254, in the case of the gradation 0 of the complete black display, it is the same as FIG. 253, (L0 to L4) = (0, 0, 0, 0, 0), and (H0 to H5) = (0,0,0,0,0). Therefore, all the switches 481 are off, and the source signal line 18 has the program current Iw = 0. Similarly, from gradation 1 to gradation 16, (H0 to H5) = (0, 0, 0, 0, 0) in the high gradation region. Therefore, one unit current source 484 in the low current region is connected to the source signal line 18. The unit current source in the high current region is not connected to the source signal line 18. That is, only (L0 to L4) in the low gradation area changes.
[1091]
In other words, (L0 to L4) = (1, 0, 0, 0, 0) at gradation 1 and (L0 to L4) = (0, 1, 0, 0, 0) at gradation 2. Yes, at gradation 3, (L0-L4) = (1,1,0,0,0), and at gradation 2, (L0-L4) = (0,0,1,0,0). is there. Thereafter, the count is sequentially performed up to gradation 16. That is, at gradation 15, (L0-L4) = (1,1,1,1,0), and at gradation 16, (L0-L4) = (1,1,1,1,1). is there. At the gray level 16, only one of the fifth bits (D4) of D0 to D5 indicating the gray level is turned on, so that the content expressed by the data D0 to D5 is 16 in one data signal line ( It can be determined by the determination of D4). Therefore, the hardware scale of the logic circuit can be reduced.
[1092]
The gradation 16 is a switching point (a bent position) (or the gradation 17 may be a switching point). At gradation 16, (L0 to L4) = (1, 1, 1, 1, 1) and (H0 to H5) = (0, 0, 0, 0, 0). Accordingly, the four switches 481La, 481Lb, 481Lc, 481d, and 481Le in the low current region are turned on, and the 16 unit current sources 484 are connected to the source signal line 18. The unit current source in the high current region is not connected to the source signal line 18.
[1093]
At gradation 16 or higher, there is no change in the low current region (L0 to L4) = (1, 1, 1, 0, 1). However, in the high current region, (H0 to H5) = (1, 0, 0, 0, 0) at gradation 17, the switch 481Ha is turned on, and one unit current source 481 in the high current region is supplied with the source signal. Connected to line 18. Hereinafter, similarly, the number of transistors 484 in the high current region increases by one according to the gradation step. That is, (H0 to H5) = (0, 1, 0, 0, 0) at gradation 18, the switch 481Hb is turned on, and the two unit current sources 481 in the high current region are connected to the source signal line 18. You. Similarly, at gradation 19, (H0 to H5) = (1, 1, 0, 0, 0), the two switches 481Ha and the switch 481Hb are turned on, and the three unit current sources 481 in the high current region are connected to the source signal 481. Connected to line 18. Further, at the gray level 20, (H0 to H5) = (0, 0, 1, 0, 0), one switch 481Hc is turned on, and the four unit current sources 481 in the high current region are connected to the source signal line 18 and Connected.
[1094]
As described above, at the switching point (bending position), the current sources (one unit) 484 having a power of 2 are turned on or connected to the source signal line 18 (inversely, a configuration in which the current source is turned off is also conceivable). Logic processing becomes extremely easy. For example, as shown in FIG. 252, if the bending position is gradation 4 (4 is a power of 2), four current sources (one unit) 484 are configured to operate. Then, in the case of a higher gray scale, the current source (one unit) 484 in the high current region is configured to be added. Further, as shown in FIG. 253, when the bending position is gradation 8 (8 is a power of 2), eight current sources (one unit) 484 are configured to operate. Then, in the case of a higher gray scale, the current source (one unit) 484 in the high current region is configured to be added. If the configuration of the present invention is adopted, a gamma control circuit with a small hardware configuration can be configured with any gradation expression, not limited to 64 gradations (16 gradations: 4096 colors, 256 gradations: 16.7 million colors, etc.).
[1095]
In the embodiments described with reference to FIGS. 252, 253, and 254, the gray level at the switching point is a power of 2, but this is the case where the gray level is 0 for the complete black gray level. If the gradation 1 is to be displayed completely black, it is necessary to add +1. However, these are matters of convenience.
[1096]
What is important in the present invention is to have a configuration in which a plurality of current regions (low current region, high current region, etc.) are provided, and switching points thereof can be determined (processed) with less signal input. As an example, a technical idea is that if a power of 2 is used, only one signal line needs to be detected, so that the hardware scale becomes extremely small. Further, a current source 484a is added to facilitate the processing.
[1097]
Therefore, in the case of negative logic, the switching point may be set at gradations 1, 3, 7, 15,... Instead of 2, 4, 8,. Further, the gray level 0 is set to a completely black display, but the present invention is not limited to this. For example, in the case of 64 gradation display, gradation 63 may be set to a completely black display state, and gradation 0 may be set to the maximum white display. In this case, the switching point may be processed in the reverse direction. Therefore, the configuration may be different from the multiplier 2 in terms of processing.
[1098]
Further, the switching point (bending position) is not limited to one gamma curve. The circuit of the present invention can be configured even if there are a plurality of bending positions. For example, the bending position can be set to gradation 4 and gradation 16. Further, it is also possible to set three or more points such as gradation 4, gradation 16, and gradation 32.
[1099]
In the above embodiments, the gray scale is set to a power of 2, but the present invention is not limited to this. For example, a bending point may be set at a power of 2 of 2 and 8 (2 + 8 = 10th gradation, that is, two signal lines required for determination). The bend point may be set at 2 to 8 and 16 (2 + 8 + 16 = 26th gradation, that is, three signal lines required for the determination) of the power of two. In this case, although the hardware scale required for the determination or the processing is slightly increased, it is possible to sufficiently cope with the circuit configuration. Needless to say, the matters described above are included in the technical category of the present invention.
[1100]
As shown in FIG. 255, the source driver circuit (IC) 14 of the present invention includes a current output circuit 654 of three parts. It is a high current region current output circuit 654a that operates in a high gradation region, a low current region current output circuit 654b that operates in a low current region and a high gradation region, and a current raising current output circuit 654b that outputs a raising current.
[1101]
The high current region current output circuit 654a and the current raising current output circuit 654c operate using a reference current source 691a that outputs a high current as a reference current, and the low current region current output circuit 654b uses a reference current source 691b that outputs a low current. It operates as a current.
[1102]
As described above, the current output circuit 654 is not limited to the high current region current output circuit 654a, the low current region current output circuit 654b, and the current raising current output circuit 654c. The current output circuit 654a and the low current area current output circuit 654b may be used, or three or more current output circuits 654 may be used. Of course, one current output circuit 654 may be provided. Further, the reference current source 691 may be arranged or formed corresponding to each current region current output circuit 654, or may be common to all current region current output circuits 654.
[1103]
The above current output circuit 654 operates the internal unit transistor 484 in accordance with the grayscale data, and absorbs current from the source signal line 18. The unit transistor 484 operates in synchronization with a signal for one horizontal scanning period (1H). That is, during the 1H period, a current based on the corresponding gradation data is input (when the unit transistor 484 is an N-channel).
[1104]
On the other hand, the gate driver circuit 12 also basically selects one gate signal line 17a in synchronization with the 1H signal. That is, in synchronization with the 1H signal, the gate signal line 17a (1) is selected in the first H period, the gate signal line 17a (2) is selected in the second H period, and the gate signal line 17a is selected in the third H period. (3) is selected, and the gate signal line 17a (4) is selected in the fourth H period.
[1105]
However, after the first gate signal line 17a is selected, a period during which the next second gate signal line 17a is selected is a period during which no gate signal line 17a is selected (non-selection period, t1 in FIG. 256). See). The non-selection period requires a rising period and a falling period of the gate signal line 17a, and is provided to secure an on / off control period of the TFT 11d.
[1106]
When an ON voltage is applied to any one of the gate signal lines 17a and the TFTs 11b and 11c of the pixel 16 are ON, a program current Iw is applied to the source signal line 18 from the Vdd power supply (anode voltage) via the driving TFT 11a. Flows. This program current Iw flows through the transistor 484 (t2 period in FIG. 256). Note that a parasitic capacitance C is generated in the source signal line 18 (a parasitic capacitance is generated due to a capacitance at a cross point between the gate signal line and the source signal line).
[1107]
However, when none of the gate signal lines 17a is selected (non-selection period: period t1 in FIG. 256), there is no current path flowing through the TFT 11a. Since the transistor 484 flows a current, it absorbs electric charge from the parasitic capacitance of the source signal line 18. Therefore, the potential of the source signal line 18 decreases (A portion in FIG. 256). When the potential of the source signal line 18 decreases, it takes time to write a current corresponding to the next image data.
[1108]
To solve this problem, as shown in FIG. 257, a switch 481a is formed at the output terminal of the source terminal 681. Also, a switch 481b is formed or arranged at the output stage of the raising current output circuit 654c.
[1109]
During the non-selection period t1, a control signal is applied to the control terminal S1 to turn off the switch 481a. In the selection period t2, the switch 481a is turned on (conducting state). In the on state, the program current Iw = IwH + IwL + IwK flows. When the switch 481a is turned off, no Iw current flows. Therefore, as shown in FIG. 258, the potential decreases as A in FIG. 256 (no change). Note that the channel width W of the analog switch 561 of the switch 481 is set to 10 μm or more and 100 μm or less. The W (channel width) of this analog switch needs to be 10 μm or more in order to reduce the on-resistance. However, if W is too large, the parasitic capacitance also increases. More preferably, the channel width W is preferably 15 μm or more and 60 μm or less.
[1110]
The switch 481b is a switch for controlling only the low gradation display. At the time of low gradation display (black display), the gate potential of the TFT 11a of the pixel 16 needs to be close to the anode voltage Vdd. Therefore, in black display, the potential of the source signal line 18 needs to be close to the anode voltage Vdd. In the black display, the program current Iw is small, and once the potential decreases as shown in A of FIG. 256, it takes a long time to return to the normal potential.
[1111]
Therefore, in the case of the low gradation display, the occurrence of the non-selection period t1 must be avoided. Conversely, in the high gradation display, since the program current Iw is large, there is often no problem even if the non-selection period t1 occurs. Therefore, in the present invention, in writing an image for high gradation display, both the switch 481a and the switch 481b are turned on even during the non-selection period. It is also necessary to cut off the raising current IwK. This is to achieve black display as much as possible. In image writing for low gradation display, the switch 481a is turned on in a non-selection period, and the switch 481b is turned off. The switch 481b is controlled by the terminal S2.
[1112]
Needless to say, in both the low gradation display and the high gradation display, the drive may be performed such that the switch 481a is turned off (non-conducting state) and the switch 481b is kept on (conducting) during the non-selection period t1. Of course, in both the low gradation display and the high gradation display, driving in which both the switch 481a and the switch 481b are turned off (non-conducting) during the non-selection period t1 may be performed.
[1113]
In any case, the switch 481 can be controlled by controlling the control terminals S1 and S2. The control terminals S1 and S2 are controlled by command control.
[1114]
For example, the control terminal S2 sets the time period t3 to “0” logic level so as to overlap the non-selection period t1. With this control, the state of A in FIG. 256 does not occur. When the gray level is equal to or higher than the black display level, the control terminal S1 is set to the logic level "0". Then, the raising current IwK stops, and good black display can be realized.
[1115]
The above embodiment has been described on the premise that one source driver IC 14 is mounted on the display panel. However, the present invention is not limited to this configuration. A configuration in which a plurality of source driver ICs 14 are stacked on one display panel may be employed. For example, FIG. 261 shows an embodiment of a display panel on which three source driver ICs 14 are mounted.
[1116]
As described in FIG. 56, FIG. 57, FIG. 245, and the like, the source driver IC 14 of the present invention includes, for example, at least two systems of a reference current in a low gradation region and a reference current in a high gradation region.
[1117]
As described with reference to FIG. 250, the current-driven source driver circuit (IC) 14 of the present invention includes a slave / master (S / M) terminal 2502 on the assumption that a plurality of source driver ICs 14 are used. . By setting the S / M terminal 2502 to the H level, the chip operates as a master chip, and outputs a reference current from a reference current output terminal (not shown). Of course, the logic of the S / M terminal may have the opposite polarity. Further, the switching may be performed by a command to the source driver IC 14. The reference current is transmitted on the cascade current connection line 2611. By setting the S / M terminal 2502 to L level, the source driver IC 14 operates as a slave chip and receives a reference current of the master chip from a reference current input terminal (not shown). This current becomes a current flowing to the INL and INH terminals in FIGS.
[1118]
The reference current is generated by a reference current generating circuit 1691 in the central part (middle part) of the source driver IC 14. The reference current of the master chip is adjusted and applied from the outside by an external resistor or a current step-type electronic volume arranged or arranged inside the IC.
[1119]
Note that a control circuit (such as a command decoder) and the like are also formed (arranged) in the center of the source driver IC 14. The reason why the reference current source is formed at the center of the chip is to minimize the distance between the reference current generation circuit and the program current output terminal.
[1120]
In the configuration of FIG. 261, the reference current is transmitted from the master chip 14b to the two slave chips (14a, 14c). The slave chip receives the reference current and generates parent, child, and grandchild currents based on the current. Note that the reference current passed by the master chip 14b to the slave chip is performed by passing current through a current mirror circuit. By performing the current transfer, the reference current is not shifted between the plurality of chips, and the dividing line on the screen is not displayed.
[1121]
FIG. 262 conceptually illustrates the positions of the reference current transfer terminals. A reference current signal line 2501 is connected to the signal input terminal 2621i, which is arranged at the center of the IC chip. The current applied to the reference current signal line 2501 is compensated for the temperature of the EL material. In addition, compensation is made by the deterioration of the life of the EL material.
[1122]
Each current source (471, 472, 473, 484) is driven in the chip 14 based on the current (voltage) applied to the reference current signal line 2501. This reference current is output as a reference current to the slave chip via the current mirror circuit. The reference current to the slave chip is output from a terminal 2621o. At least one terminal 2621o is arranged (formed) on the left and right of the reference current generation circuit 1691. In FIG. 262, two pieces are arranged (formed) on the left and right. This reference current is transmitted to the slave chip 14 via the cascade signal lines 2611a1, 2611a2, 2611b1, and 2611b2. Note that the circuit may be configured so that the reference current applied to the slave chip 14a is fed back to the master chip 14b to correct the shift amount.
[1123]
The current drive type EL display panel has a very small program current of 100 nA or less in black display. Therefore, if a parasitic capacitance exists in the source signal line 18 or the like, the charging and discharging of the parasitic capacitance cannot be performed in one horizontal scanning period (1H) (the effect of the parasitic capacitance cannot be sufficiently eliminated). Therefore, insufficient writing occurs. Insufficient writing causes a decrease in display contrast and a decrease in resolution.
[1124]
The parasitic capacitance includes the parasitic capacitance of the display area and the parasitic capacitance of the output circuit of the source driver IC14. The parasitic capacitance of the output circuit is mainly the parasitic capacitance 3751b of the protection diode 3751a connected to the internal wiring 3752 of the output stage, as shown in FIG. The protection diode 3751a is an important circuit as a countermeasure against static electricity of the source driver IC 14, but as shown in FIG. 375 (b), the protection diode 3751a is equivalent to a capacitor 3751b (parasitic capacitance). Note that the parasitic capacitance caused by a protection diode or the like is called a protection capacitance.
[1125]
When the source driver IC 14 outputs a voltage, even if the protection capacitance is relatively large, there is no effect because the output impedance of the source driver IC 14 is low. However, when the source driver IC 14 outputs a current, the magnitude of the protection capacitance greatly affects the time constant because the output impedance of the source driver IC 14 is high. That is, the program current Iw cannot be written to the pixel 16 within one horizontal scanning period (1H).
However, the protection diode cannot be deleted due to measures against static electricity or the like.
[1126]
The present invention solves this problem. FIG. 376 shows the embodiment. The protection diode 3751a as shown in FIG. 375 (a) is not formed. Instead, a switch 3761 (short circuit) for short-circuiting between adjacent source signal lines 18 is formed in the source driver IC 14. The short circuit 3761 is a very small switch. By switching, a MOS transistor is exemplified. In addition, a bipolar transistor or an analog switch including P-channel and N-channel transistors may be used. The W (channel width) and L (channel length) of the transistor are designed so that the switch exhibits a resistance value of 100 MΩ or more when in the open state. The switch 3761 is configured to be closed when the source driver IC 14 is formed (normally closed). A signal (voltage) applied to a control terminal (not shown) opens as shown in FIG. 377. The control terminal is connected to a gate terminal of a transistor included in the switch 3761.
[1127]
The embodiment in FIG. 378 is an embodiment in which a short-circuit portion 3781 is formed between the adjacent source signal lines 18. It is formed of a high impedance wiring of 100 MΩ or more. Although a small leak occurs between the adjacent source signal lines 18, the small current does not affect the program current Iw. The short-circuit portion is formed of polysilicon.
[1128]
FIG. 379 (a) shows an embodiment in which a complete short-circuit portion 3781 is formed between adjacent source signal lines 18. The short-circuit portion is formed by metal wiring or the like. Until the source driver IC 14 is mounted on the substrate 71, the short-circuit portion 3781 is left. After mounting, the substrate 71 and the source driver IC 14 are immersed in an etchant or the like, and the short-circuit portion 3781 is etched and separated. In the above embodiment, the short-circuit portion 3781 is separated by etching, but may be cut by irradiating the short-circuit portion 3781 with a laser or the like.
[1129]
FIG. 382 shows the embodiment. As described above, in the present invention, the base anode line 2631 is formed on the back surface of the source driver IC 14. Further, the base anode line 2631 is formed on the substrate 71 so as to shield the circuit forming portion from light in order to prevent the IC from malfunctioning due to a photo controller (see FIG. 102 and its description).
[1130]
In FIG. 382, a slit 3821 is provided in the base anode line 2631 at a position where the short-circuit portion 3781 is formed in the source driver IC 14. The slit 3821 is a portion through which light can pass. As shown in FIG. 383, a laser beam 3831 is incident from the slit 3821 to cut the short-circuit portion 3781. The wavelength of the laser beam is preferably around 1 μm. As a laser having this wavelength, a YAG laser is exemplified. Of course, other lasers may be used. For example, carbon dioxide laser, excimer laser, neon helium laser, white laser, dye laser and the like are exemplified. In addition, a light collected by an argon lamp or a xenon lamp may be used. That is, any material can be used as long as it has optical energy and can process wiring and the like.
[1131]
The laser light 3831 is transmitted through the glass substrate 71 and is applied to the short-circuit portion 3781 and the like. The laser beam 3831 enters from a slit 3821 formed in the base anode line 2631. Although the slit 3821 is formed, the invention is not limited to this. What is important is that the cut portion such as the short-circuit portion 3781 is configured to be processed by the laser light 3831 or the like.
[1132]
FIG. 380 shows an embodiment in which a protection diode 3751 connected to the internal wiring 3752 is formed. 375 is different from (a) of FIG. 375 in that a short-circuit portion (that is, a cut portion) 3781b is formed so that the protection diode 3751 can be separated from the internal wiring 3751a. Further, a short-circuit portion 3781a is formed or arranged so that the Vss voltage source and the Vdd voltage source can be disconnected. In FIG. 381, the cross section is marked with a cross. Note that the disconnection of the short-circuit portion 3781 has been described with reference to FIGS.
[1133]
One problem that arises when the organic EL display panel is modularized is the problem of the resistance of the layout (arrangement) of the anode wiring 2631 and the cathode wiring. In the organic EL display panel, the current flowing through the EL element 15 is large instead of the drive voltage of the EL element 15 being relatively low. Therefore, it is necessary to make the anode wiring and the cathode wiring that supply current to the EL element 15 thicker. As an example, even with a 2-inch class EL display panel, a current of 200 mA or more needs to flow through the anode wiring 2631 with a polymer EL material. Therefore, in order to prevent a voltage drop of the anode wiring 2631, it is necessary to lower the resistance of the anode wiring to 1Ω or less. However, in the array substrate 71, since the wiring is formed by thin-film deposition, it is difficult to reduce the resistance. Therefore, it is necessary to increase the pattern width. However, in order to transmit a current of 200 mA with almost no voltage drop, there is a problem that the wiring width becomes 2 mm or more.
[1134]
FIG. 273 shows a configuration of a conventional EL display panel. Built-in gate driver circuits 12a and 12b are formed (arranged) on the left and right of the display screen 50. The source driver circuit 14p is also formed by the same process as the TFT of the pixel 16 (built-in source driver circuit).
[1135]
The anode wiring 2631 is arranged on the right side of the panel. The Vdd voltage is applied to the anode wiring 2631. The width of the anode wiring 2631 is, for example, 2 mm or more. The anode wiring 2631 is branched from the lower end of the screen to the upper end of the screen. The number of branches is the number of pixel columns. For example, in a QCIF panel, 176 columns × RGB = 528 lines. On the other hand, the source signal line 18 is output from the built-in source driver 14p. The source signal lines 18 are arranged (formed) from the upper end of the screen to the lower end of the screen. The power supply wiring 2731 of the built-in gate driver circuit 12 is also arranged on the left and right sides of the screen.
[1136]
Therefore, the right frame of the display panel cannot be narrowed. At present, in display panels used for mobile phones and the like, it is important to narrow the frame. It is also important to make the left and right frames of the screen even. However, in the configuration of FIG. 273, it is difficult to narrow the frame.
[1137]
In order to solve this problem, in the display panel of the present invention, as shown in FIG. 274, the anode wiring 2631 is arranged (formed) on a position located on the back surface of the source driver IC 14 and on the array surface. The source driver circuit (IC) 14 is formed (manufactured) by a semiconductor chip and mounted on the substrate 71 by COG (chip-on-glass) technology. The anode wiring 2631 can be arranged (formed) in the source driver IC 14 because the back surface of the chip 14 has a space of 10 μm to 30 μm perpendicular to the substrate.
[1138]
As shown in FIG. 273, when the source driver circuit 14p is formed directly on the array substrate 71, the anode wiring (base anode line, anode) is formed below or above the source driver circuit 14p due to the problem of the number of masks, the problem of yield, and the problem of noise. It is difficult to form the voltage line and the basic anode line) 2631.
[1139]
As shown in FIG. 274, a common anode line 2642 is formed, and the base anode line 2631 and the common anode line 2642 are short-circuited by the connection anode line 2641. In particular, the point at which the connection anode line 2641 at the center of the IC chip is formed is a point. By forming the connection anode line 2641, the potential difference between the base anode line 2631 and the common anode line 2642 is eliminated. The point is that the anode wiring 2632 is branched from the common anode line 2642. By employing the above configuration, the layout of the anode wiring 2631 is eliminated as shown in FIG. 273, and the frame can be narrowed.
[1140]
The above items will be described in more detail with reference to other drawings. FIG. 263 is an explanatory diagram of a part of the display panel of the present invention. In FIG. 263, the dotted line is the position where the source driver IC 14 is arranged. That is, a base anode line (anode voltage line, that is, an anode wiring before branching) is formed (arranged) on the back surface of the source driver IC 14 and on the array substrate 71. In the embodiment of the present invention, it is assumed that the anode wiring 2631 before branching is formed on the back surface of the IC chip (12, 14), but this is for ease of explanation. For example, a cathode wiring or a cathode film before branching may be formed (arranged) instead of the anode wiring 2631 before branching. In addition, the power supply wiring 1051 of the gate driver circuit 12 may be arranged or formed.
[1141]
In the source driver IC 14, a current output (current input) terminal and a connection terminal 2633 formed in the array 71 are connected by COG technology. The connection terminal 2633 is formed at one end of the source signal line 18. The connection terminals 2633 are arranged in a staggered manner, such as 2633a and 2633b. A connection terminal 2633 is formed at one end of the source signal line, and a check terminal electrode is formed at the other end.
[1142]
In the present invention, the IC chip is a current-driven driver IC (a method of programming pixels with current), but the present invention is not limited to this. For example, the present invention can be applied to an EL display panel (apparatus) on which a voltage-driven driver IC for driving pixels of a voltage program as shown in FIG. 43 is mounted.
[1143]
An anode wiring 2632 (branched anode wiring) is arranged between the connection terminals 2633a and 2633b. That is, an anode wiring 2632 branched from a thick, low-resistance base anode line 2631 is formed between the connection terminals 2633, and is arranged along 16 columns of pixels. Therefore, the anode wiring 2632 and the source signal line 18 are formed (arranged) in parallel. With the configuration (formation) as described above, the Vdd voltage can be supplied to each pixel without routing the base anode line 2631 to the side of the screen as shown in FIG.
[1144]
FIG. 264 is further specifically illustrated. 263 is different from FIG. 263 in that the anode wiring is not arranged between the connection terminals 2633, but is branched from a separately formed common anode line 2642. The common anode line 2642 and the base anode line 2631 are connected by a connection anode line 2641.
[1145]
FIG. 264 illustrates the state of the back surface as viewed from the perspective of the source driver IC 14. In the source driver IC 14, a current output circuit 654 for outputting a program current Iw to an output terminal 681 is arranged. Basically, the output terminal 681 and the current output circuit 654 are arranged regularly. At the center of the source driver IC 14, a circuit for producing a basic current of the parent current source and a control (control) circuit are formed. Therefore, the output terminal 681 is not formed at the center of the IC chip (because the current output circuit 654 cannot be formed at the center of the IC chip).
[1146]
In the present invention, the output terminal 681 is not formed on the IC chip at the central portion 654a in FIG. This is because there is no output circuit. In many cases, a control circuit or the like is formed in the center of an IC chip such as a source driver and an output circuit is not formed. The IC chip of the present invention focuses on this point, and does not form (arrange) the output terminal 681 at the center of the IC chip. Even when a control circuit or the like is formed in the center of an IC chip such as a source driver and an output circuit is not formed, a dummy pad is provided in the center to form an output terminal 681 (pad). It is common that it is. The common anode line 2641 is formed at this position (however, the common anode line 2641 is formed on the surface of the array substrate 71). The width of the connection anode line 2641 is set to 50 μm or more and 1000 μm or less. Further, the resistance (maximum resistance) value with respect to the length is set to 100Ω or less.
[1147]
By short-circuiting the base anode line 2631 and the common anode line 2642 with the connection anode line 2641, a voltage drop caused by a current flowing through the common anode line 2642 is suppressed as much as possible. In other words, the connection anode line 2641, which is a component of the present invention, effectively utilizes the fact that there is no output circuit at the center of the IC chip. Further, conventionally, the output terminal 681 formed as a dummy pad in the center of the IC chip is deleted, so that the dummy chip comes into contact with the connection anode line 2641, so that the IC chip is electrically affected. Is preventing that. However, when the dummy pad is electrically insulated from the base substrate (chip ground) of the IC chip and other components, there is no problem even if the dummy pad contacts the connection anode line 2641. Therefore, it goes without saying that the dummy pad may be formed at the center of the source driver IC 14.
[1148]
More specifically, the connection anode line 2641 and the common anode line 2642 are formed (arranged) as shown in FIG. First, the connection anode wire 2641 has a thick portion (2641a) and a thin portion (2641b). The thick portion (2641a) is for reducing the resistance value. The thin portion (2641b) is for forming a connection anode line 2641b between the output terminals 963 and connecting to the common anode line 2642.
[1149]
The connection between the base anode line 2631 and the common anode line 2642 is short-circuited not only at the center connection anode line 2641b but also at the left and right connection anode lines 2641c. Therefore, the common anode line 2642 and the base anode line 2631 are short-circuited by the three connection anode lines 2641. Therefore, even when a large current flows through the common anode line 2642, a voltage drop does not easily occur in the common anode line 2642. This is because the source driver IC 14 usually has a width of 2 mm or more, and the line width of the base anode line 2631 formed below the source driver IC 14 can be increased (impedance can be reduced). Therefore, since the low impedance base anode line 2631 and the common anode line 2642 are short-circuited at a plurality of points by the connection anode line 2641, the voltage drop of the common anode line 2642 is reduced.
[1150]
As described above, the voltage drop at the common anode line 2642 can be reduced because the base anode line 2631 can be arranged (formed) under the source driver IC 14 and the connection anode line 2641c is formed by using the left and right positions of the source driver IC 14. Can be arranged (formed), and the connection anode line 2641b can be arranged (formed) at the center of the source driver IC 14.
[1151]
In FIG. 267, a base anode line 2631 and a cathode power supply line (base cathode line) 2671 are stacked via an insulating film 2661. This laminated portion forms a capacitor (this configuration is called an anode capacitor configuration). This capacitor functions as a power supply pass capacitor. Therefore, a sudden current change of the base anode line 2631 can be absorbed. Further, by applying the above configuration, it can be used as a power supply pass capacitor of the source driver IC 14 and the like.
[1152]
The capacitance of the capacitor preferably satisfies the relationship of M / 200 ≦ C ≦ M / 10 when the display area of the EL display device is S square millimeter and the capacitance of the capacitor is C (pF). Further, it is preferable to satisfy the relationship of M / 100 ≦ C ≦ M / 20 or less. If C is small, it is difficult to absorb a change in current, and if C is large, the formation area of the capacitor becomes too large to be practical.
[1153]
In the embodiment shown in FIG. 267 and the like, the base anode line 2631 is arranged (formed) under the source driver IC 14, but it goes without saying that the anode line may be a cathode line. In FIG. 267, the base cathode line 2671 and the base anode line 2631 may be exchanged. The technical idea of the present invention is that a driver is formed of a semiconductor chip, the semiconductor chip is mounted on an array substrate 71 or a flexible substrate, and a power supply such as the EL element 15 or a ground potential (current) is supplied to the lower surface of the semiconductor chip. The point is to arrange (form) wiring and the like.
[1154]
Therefore, the semiconductor chip is not limited to the source driver 14, but may be the gate driver circuit 12 or the power supply IC 82. Further, a configuration is also included in which a semiconductor chip is mounted on a flexible substrate, and a power supply or a ground pattern such as the EL element 15 is wired (formed) on the flexible substrate surface and the lower surface of the semiconductor chip. Of course, both the source driver IC 14 and the gate driver IC 12 may be formed of semiconductor chips, and COG mounting may be performed on the substrate 71.
A power supply or ground pattern may be formed on the lower surface of the chip. Further, the power supply or the grant pattern to the EL element 15 is used, but the present invention is not limited to this, and a power supply wiring to the source driver 14 and a power supply wiring to the gate driver circuit 12 may be used. Further, the present invention is not limited to the EL display device, but can be applied to a liquid crystal display device. In addition, the present invention can be applied to a display panel such as an FED and a PDP.
The above is the same in other embodiments of the present invention.
[1155]
FIG. 265 shows another embodiment of the present invention. 263, 264, and 267 is different from FIG. 263 in that the anode wiring 2632 is arranged between the output terminals 2633, whereas in FIG. The point is that the connection anode line 2641d is branched and the common anode line 2642 is short-circuited. Another difference is that the thin connection anode line 2641d and the source signal line 18 connected to the connection terminal 2633 are stacked via an insulating film 2661.
[1156]
The anode line 2641d is connected to the base anode line 2631 by a contact hole 2651a, and the anode wiring 2632 is connected to the common anode line 2642 by a contact hole 2651b. Other points (connection anode lines 2641a, 2641b, 2641c, anode capacitor configuration, and the like) are the same as those in FIGS. 264 and 267, and thus description thereof is omitted.
[1157]
FIG. 266 is a cross-sectional view taken along line aa ′ of FIG. In FIG. 266 (a), the source signal lines 18 having substantially the same width are connected to each other, and the anode lines 2641d are stacked via the insulating film 2661a.
The thickness of the insulating film 2661a is greater than or equal to 500 angstroms and less than or equal to 3000 angstroms (Å). More preferably, the thickness is set to 800 Å to 2000 Å (オ ン). If the film thickness is small, the parasitic capacitance between the connection anode line 2641d and the source signal line 18 increases, and a short circuit between the connection anode line 2641d and the source signal line 18 is likely to occur, which is not preferable. If the thickness is large, a long time is required for forming the insulating film, and the manufacturing time is long and the cost is high. Further, it becomes difficult to form the upper wiring.
Note that the insulating film 2661 is made of the same material as an organic material such as a polybiphenyl alcohol (PVA) resin, an epoxy resin, a polypropylene resin, a phenol resin, an acrylic resin, or a polyimide resin. Inorganic materials are exemplified. In addition, it goes without saying that Al2O3, Ta2O3 and the like may be used. Further, as shown in FIG. 266 (a), an insulating film 2661b is formed on the outermost surface to prevent corrosion and mechanical damage of the wiring 2641 and the like.
[1158]
In FIG. 266 (b), a connection anode line 2641d having a smaller line width than the source signal line 18 is stacked on the source signal line 18 via an insulating film 2661a.
With the configuration described above, a short circuit between the source signal line 18 and the connection anode line 2641d due to a step of the source signal line 18 can be suppressed. In the configuration of FIG. 266 (b), the line width of the connection anode line 2641d is preferably smaller than the line width of the source signal line 18 by 0.5 μm or more. Further, it is preferable that the line width of the connection anode line 2641d be smaller than the line width of the source signal line 18 by 0.8 μm or more.
[1159]
In FIG. 266 (b), the connection anode line 2641d having a smaller line width than the source signal line 18 is stacked on the source signal line 18 via the insulating film 2661a. As shown in the figure, the source signal line 18 having a smaller line width than the connection anode signal line 2641d may be stacked on the connection anode line 2641d via the insulating film 2661a. Other items are the same as those of the other embodiments, and the description is omitted.
[1160]
FIG. 268 is a sectional view of the source driver IC 14 part. Basically, the configuration of FIG. 267 is used as a reference, but the same can be applied to FIGS. 264, 265, and the like. Or it can be applied analogously.
[1161]
FIG. 268 (b) is a cross-sectional view taken along AA ′ of FIG. 267. As is clear from FIG. 268 (b), no output pad 681 is formed (arranged) at the center of the IC chip 14. This output pad is connected to the source signal line 18 of the display panel. The output pad 681 has bumps (projections) formed by a plating technique or a nail head bonder technique. The height of the projection is set to be 10 μm or more and 40 μm or less. Of course, it goes without saying that the protrusions may be formed by a gold plating technique (electrolysis, electroless).
[1162]
The protrusion and each source signal line 18 are electrically connected via a conductive bonding layer (not shown). The conductive bonding layer is made of an epoxy-based or phenol-based adhesive as an adhesive, and a mixture of flakes such as silver (Ag), gold (Au), nickel (Ni), carbon (C), and tin oxide (SnO2). Or an ultraviolet curable resin.
The conductive bonding layer (connection resin) 2681 is formed on the bump by a technique such as transfer. Alternatively, the protrusion and the source signal line 18 are thermocompression-bonded with the ACF resin 2681. The connection between the projection or the output pad 681 and the source signal line 18 is not limited to the above method. Further, the film carrier technology may be used without mounting the source driver IC 14 on the array substrate. Further, it may be connected to the source signal line 18 or the like using a polyimide film or the like. FIG. 268 (a) is a cross-sectional view of a portion where the source signal line 18 and the common anode line 2642 overlap (see FIG. 266).
[1163]
An anode wiring 2632 is branched from the common anode line 2642. In the case of the QCIF + panel, the number of the anode wirings 2632 is 176 × RGB = 528. A Vdd voltage (anode voltage) illustrated in FIG. 1 and the like is supplied through the anode wiring 2632. When the EL element 15 is made of a low molecular material, a current of about 200 μA flows through one anode wiring 2632 at the maximum. Therefore, a current of about 100 mA at 200 μA × 528 flows through the common anode wiring 2642.
[1164]
Therefore, in order to keep the voltage drop across the common anode wiring 2642 within 0.2 (V), the resistance of the maximum path through which the current flows must be 2 Ω (assuming 100 mA flows) or less. In the present invention, since the connection anode lines 2641 are formed at three locations as shown in FIG. 267, the resistance value of the common anode line 2642 can be easily designed to be extremely small when the circuit is replaced with a concentrated distribution circuit. If a number of connection anode lines 2641d are formed as shown in FIG. 265, the voltage drop on the common anode line 2642 is almost eliminated.
[1165]
The problem is the effect of the parasitic capacitance (referred to as common anode parasitic capacitance) at the overlapping portion between the common anode line 2642 and the source signal line 18. Basically, in the current driving method, it is difficult to write the black display current if there is a parasitic capacitance in the source signal line 18 into which the current is written. Therefore, it is necessary to minimize the parasitic capacitance.
[1166]
The common anode parasitic capacitance needs to be at least 1/10 or less of the parasitic capacitance (referred to as display parasitic capacitance) generated in the display region by one source signal line 18. For example, if the display parasitic capacitance is 10 (pF), it must be 1 (pF) or less.
More preferably, it is required to be 1/20 or less (referred to as display parasitic capacitance).
If the display parasitic capacitance is 10 (pF), it must be 0.5 (pF) or less.
In consideration of this point, the line width of the common anode line 2642 (M in FIG. 271) and the thickness of the insulating film 2661 (see FIG. 269) are determined.
[1167]
The base anode line 2631 is formed (arranged) under the source driver IC 14. Needless to say, the line width to be formed is preferably as large as possible from the viewpoint of reducing the resistance. In addition, it is preferable that the base anode wiring 2631 has a light shielding function. This explanatory diagram is shown in FIG. 270. Needless to say, if the base anode wiring 2631 is formed with a predetermined thickness with a metal material, there is a light shielding effect. When the base anode line 2631 cannot be made thick, or when the base anode line 2631 is formed of a transparent material such as ITO, a light absorbing film or a light reflecting film is laminated on the base anode line 2631 or in a multilayer structure under the source driver IC 14 ( Basically, it is formed on the surface of the array 71). The light-shielding film (base anode line 2631) in FIG. 270 does not need to be a complete light-shielding film. The part may have an opening. Further, a material exhibiting a diffraction effect and a scattering effect may be used. Further, a light-shielding film made of an optical interference multilayer film may be formed or arranged so as to be stacked on the base anode line 2631.
[1168]
Of course, it is needless to say that a reflecting plate (sheet) and a light absorbing plate (sheet) made of metal foil, plate or sheet may be arranged, inserted or formed in the space between the array substrate 71 and the source driver IC 14. Further, the present invention is not limited to the metal foil, and it goes without saying that a reflecting plate (sheet) and a light absorbing plate (sheet) made of an organic material or an inorganic material, or a plate or sheet, may be arranged, inserted, or formed.
[1169]
Further, a light absorbing material or a light reflecting material made of gel or liquid may be injected or arranged in the space between the array substrate 71 and the source driver IC 14. Further, it is preferable that the light absorbing material or the light reflecting material made of the gel or liquid is cured by heating or light irradiation. Note that, here, for ease of explanation, the description will be made assuming that the base anode line 2631 is a light-shielding film (reflection film).
[1170]
As shown in FIG. 270, the base anode line 2631 may be formed on the surface of the array substrate 71 (the surface is not limited to the surface. Should not be incident.
Therefore, it goes without saying that the base anode wire 2631 and the like may be formed on the inner surface or inner layer of the substrate 71. In addition, by forming the base anode line 2631 (a structure or a structure functioning as a reflection film or a light absorption film) on the back surface of the substrate 71, if light can be prevented or suppressed from being incident on the source driver IC 14, The rear surface of the array substrate 71 may be used.
[1171]
In FIG. 270 and the like, the light-shielding film and the like are formed on the array substrate 71. However, the invention is not limited to this, and the light-shielding film and the like may be formed directly on the back surface of the source driver IC 14. In this case, an insulating film 2661 (not shown) is formed on the back surface of the source driver IC 14, and a light-shielding film or a reflective film is formed on the insulating film. In the case of a configuration in which the source driver circuit 14 is formed directly on the array substrate 71 (low-temperature polysilicon technology, high-temperature polysilicon technology, solid-phase growth technology, amorphous silicon technology), a light-shielding film, a light-absorbing film, The reflection film may be formed on the substrate 71, and the source driver circuit 14 may be formed (arranged) thereon.
[1172]
The source driver IC 14 is formed with a number of transistor elements such as a current source 484 for flowing a small current (a circuit forming portion 2701 in FIG. 270). When light is incident on a transistor element through which a minute current flows, a photoconductor phenomenon occurs, and the output current (program current Iw), the amount of parent current, the amount of child current, and the like become abnormal values (variation occurs, for example). In particular, in a self-luminous element such as an organic EL, since light generated from the EL element 15 is irregularly reflected in the substrate 71, strong light is emitted from a portion other than the display screen 50. When the emitted light is incident on the circuit forming portion 1021 of the source driver IC 14, a photoconductor phenomenon occurs. Therefore, the countermeasure against the photoconductor phenomenon is a countermeasure unique to the EL display device.
[1173]
In order to solve this problem, in the present invention, the base anode line 2631 is formed on the substrate 71 to shield light. The formation region of the base anode line 2631 covers the circuit forming portion 2701 as shown in FIG. As described above, by forming the light shielding film (base anode line 2631), the photoconductor phenomenon can be completely prevented. In particular, in the EL power supply line such as the base anode wiring 2631, a current flows and the potential slightly changes due to screen rewriting. However, since the amount of change in the potential changes little by little at the 1H timing, it can be regarded as a ground potential (meaning that the potential does not change). Therefore, the base anode line 2631 or the base cathode line exerts not only a light shielding function but also a shielding effect.
[1174]
In a self-luminous element such as an organic EL, light generated from the EL element 15 is irregularly reflected in the substrate 71, so that strong light is emitted from portions other than the display screen 50. In order to prevent or suppress the irregularly reflected light, as shown in FIG. 269, a light absorbing film 2691 is formed at a location (ineffective area) where light effective for image display does not pass (in contrast, the effective area is a display screen). 50 near it). The light absorbing film is formed on the outer surface of the sealing lid 85 (light absorbing film 2691a), the inner surface of the sealing lid 85 (light absorbing film 2691c), the side surface of the substrate 71 (light absorbing film 2691d), and image display of the substrate. Other than the region (light absorbing film 2691b). Note that the present invention is not limited to the light absorbing film 2691, and a light absorbing sheet may be attached or a light absorbing wall may be used. In addition, the concept of light absorption includes a method or structure for diverging light rather than scattering light, and in a broad sense also includes a method or structure for containing light by reflection.
[1175]
The light-absorbing film 2691 may be made of, for example, an organic material such as an acrylic resin containing carbon, a black pigment or pigment dispersed in an organic resin, or gelatin or casein black as in a color filter. Dyed with an acidic dye of the formula (1). In addition, a single fluoran dye that is black may be used by coloring, or a black color mixture of a green dye and a red dye may be used. Further, a PrMnO3 film formed by sputtering, a phthalocyanine film formed by plasma polymerization, and the like are exemplified.
[1176]
The above materials are all black materials, but the light absorbing film 2691 may be made of a material having a complementary color to the light color generated by the display element. For example, a light absorbing material for a color filter may be modified so as to obtain desired light absorbing characteristics and used. Basically, a dye obtained by dyeing a natural resin with a dye may be used as in the case of the above-described black absorbing material. Alternatively, a material in which a dye is dispersed in a synthetic resin can be used. The range of selection of the dye is wider than the black dye, and may be an appropriate one of azo dyes, anthraquinone dyes, phthalocyanine dyes, triphenylmethane dyes, and the like, or a combination of two or more thereof.
[1177]
Further, a metal material may be used as the light absorbing film. For example, hexavalent chromium is exemplified. Hexavalent chromium is black and functions as a light absorbing film. In addition, light scattering materials such as opal glass and titanium oxide may be used. This is because scattering of light is equivalent to absorbing light as a result.
[1178]
Note that the sealing lid 85 bonds the substrate 71 and the sealing lid 85 by using a sealing resin 2693 containing resin beads 2692 of 4 μm or more and 15 μm or less. The sealing lid 85 and the substrate 71 are attached with a sealing resin 2693 containing resin beads 2682. The lid 85 is arranged and fixed without applying pressure.
[1179]
In the embodiment of FIG. 267, the common anode line 2642 is shown (formed) near the source driver IC 14, but the present invention is not limited to this. For example, as shown in FIG. 271, it may be formed near the display screen 50. In addition, it is preferable to form them. This is because the portion where the source signal line 18 and the anode wiring 2632 are arranged (formed) in a short distance and in parallel is reduced. This is because if the source signal line 18 and the anode wiring 2632 are arranged in a short distance and in parallel, a parasitic capacitance occurs between the source signal line 18 and the anode wiring 2632. If the common anode line 2642 is arranged near the display screen 50 as shown in FIG. 271, the problem disappears. It is preferable that the distance K (see FIG. 271) between the screen display screen 50 and the common anode line 2642 be 1 mm or less.
[1180]
The common anode line 2642 is preferably formed of a metal material forming the source signal line 18 in order to reduce the resistance as much as possible. In the present invention, it is formed of a Cu thin film, an Al thin film, a laminated structure of Ti / Al / Ti, or a metal material (SD metal) made of an alloy or amman gum. Therefore, the portion where the source signal line 18 and the common anode line 2642 intersect is replaced with a metal material (GE metal) forming the gate signal line 17 in order to prevent a short circuit. The gate signal line is formed of a metal material having a Mo / W laminated structure.
[1181]
Generally, the sheet resistance of the gate signal line 17 is higher than the sheet resistance of the source signal line 18. This is common in liquid crystal display devices. However, in the organic EL display panel and in the current driving method, the current flowing through the source signal line 18 is as small as 1 to 5 μA. Therefore, even if the wiring resistance of the source signal line 18 is high, almost no voltage drop occurs, and a good image display can be realized. In the liquid crystal display device, image data is written to the source signal line 18 with a voltage. Therefore, if the resistance value of the source signal line 18 is high, an image cannot be written in one horizontal scanning period.
[1182]
However, in the current driving method of the present invention, even if the resistance value of the source signal line 18 is high (that is, the sheet resistance value is high), there is no problem. Therefore, the sheet resistance of the source signal line 18 may be higher than the sheet resistance of the gate signal line 17. Therefore, in the EL display panel of the present invention (conceptually, in a current driving type display panel or display device), as shown in FIG. 272, the source signal line 18 is formed (formed) of GE metal, and the gate is formed. The signal line 17 may be made (formed) of SD metal. This is the reverse configuration of the liquid crystal display panel.
[1183]
FIG. 275 shows a configuration in which a power supply wiring 2731 for driving the gate driver circuit 12 is arranged in addition to the configurations in FIGS. 267 and 271. The power supply wiring 2731 is routed from the right end of the display screen 50 of the panel to the lower side to the left end of the display screen 50. That is, the power supplies of the gate driver circuits 12a and 12b are the same.
[1184]
However, a gate driver circuit 12a that selects the gate signal line 17a (the gate signal line 17a controls the TFTs 11b and 11c) and a gate driver circuit 12b that selects the gate signal line 17b (the gate signal line 17b controls the TFT 11d, It is preferable to make the power supply voltage different from “controlling the current flowing through the EL element 15”. In particular, it is preferable that the amplitude (ON voltage-OFF voltage) of the gate signal line 17a is small. This is because as the amplitude of the gate signal line 17a decreases, the penetration voltage of the pixel 16 to the capacitor 19 decreases (see FIG. 1 and the like). On the other hand, the amplitude of the gate signal line 17b cannot be reduced because the EL element 15 needs to be controlled.
[1185]
Therefore, as shown in FIG. 276, the applied voltages of the gate driver circuit 12a are Vha (the off voltage of the gate signal line 17a) and Vla (the on voltage of the gate signal line 17a).
The voltages applied to the gate driver circuit 12a are Vhb (off voltage of the gate signal line 17b) and Vla (on voltage of the gate signal line 17b). It is assumed that Vla <Vlb. Note that Vha and Vhb may be substantially matched.
[1186]
The gate driver circuit 12 usually includes an N-channel transistor and a P-channel transistor. However, it is preferable to form only the P-channel transistor. This is because the number of masks required for manufacturing an array is reduced, and an improvement in manufacturing yield and an improvement in throughput are expected. Therefore, as exemplified in FIGS. 1 and 2, the transistors forming the pixels 16 are P-channel transistors, and the gate driver circuit 12 is also formed or configured by P-channel transistors. When the gate driver circuit is configured by the N-channel transistor and the P-channel transistor, the required number of masks is ten, but when the gate driver circuit is formed only by the P-channel transistor, the required number of masks is five.
[1187]
However, if the gate driver circuit 12 and the like are constituted only by the P-channel transistors, the level shifter circuit cannot be formed on the array substrate 71. This is because the level shifter circuit is composed of an N-channel transistor and a P-channel transistor.
[1188]
To solve this problem, in the present invention, the level shifter circuit function is built in the power supply IC 82. FIG. 277 shows the embodiment. The power supply IC 82 generates a drive voltage for the gate driver circuit 12, an anode and cathode voltage of the EL element 15, and a drive voltage for the source driver circuit 14.
[1189]
The power supply IC 82 needs to use a high withstand voltage semiconductor process in order to generate the anode and cathode voltages of the EL element 15 of the gate driver circuit 12. With this breakdown voltage, the level can be shifted to the signal voltage driven by the gate driver circuit 12.
[1190]
Therefore, the level shift and the driving of the gate driver circuit 12 are performed with the configuration of FIG. Input data (image data, command, control data) 2672 is input to the source driver IC 14. The input data also includes control data for the gate driver circuit 12. The source driver IC 14 has a withstand voltage (operating voltage) of 5 (V). On the other hand, the operating voltage of the gate driver circuit 12 is 15 (V). The signal output from the source driver circuit 14 and output to the gate driver circuit 12 needs to be level-shifted from 5 (V) to 15 (V). This level shift is performed by the power supply circuit (IC) 82. In FIG. 277, the data signal for controlling the gate driver circuit 12 is also the power supply IC control signal 2772.
[1191]
The power supply circuit 82 shifts the level of the input data signal 2772 for controlling the gate driver circuit 12 by a built-in level shifter circuit, and outputs it as a gate driver circuit control signal 2773 to control the gate driver circuit 12.
[1192]
Hereinafter, the gate driver circuit 12 according to the present invention, in which the gate driver circuit 12 built in the substrate 71 is composed of only P-channel transistors, will be described. As described above, the pixel 16 and the gate driver circuit 12 are formed only by P-channel transistors (that is, all transistors formed on the substrate 71 are P-channel transistors. Conversely, N-channel transistors are formed). This is because the number of masks required for manufacturing an array is reduced, and an improvement in manufacturing yield and an improvement in throughput are expected. In addition, since it is possible to improve only the performance of the P-channel transistor, the characteristics can be easily improved as a result. For example, the Vt voltage can be reduced (closer to 0 (V), etc.) and the Vt variation can be reduced more easily than in a CMOS structure (a configuration using P-channel and N-channel transistors).
[1193]
As an example, as shown in FIG. 274, in the present invention, the gate driver circuits 12 are arranged, formed, or configured on the left and right sides of the display screen 50 one by one (shift register). The gate driver circuit 12 and the like (including the transistor of the pixel 16) are described as being formed or constituted by a low-temperature polysilicon technology having a process temperature of 450 degrees Celsius or less, but the present invention is not limited to this. A high-temperature polysilicon technique with a process temperature of 450 degrees Celsius or higher may be used, or a TFT or the like formed using a semiconductor film grown by solid phase (CGS) may be used. In addition, it may be formed of an organic TFT. Further, the TFT may be formed or configured by amorphous silicon technology.
[1194]
One is a gate driver circuit 12a on the selection side. An on / off voltage is applied to the gate signal line 17a to control the pixel TFT 11. The other gate driver circuit 12b controls (turns on and off) a current flowing through the EL element 15.
[1195]
In the embodiment of the present invention, description will be made mainly by exemplifying the pixel configuration of FIG. 1, but the present invention is not limited to this. Needless to say, the present invention can be applied to other pixel configurations such as FIGS. 2, 42, 43, 115, 116, and 117. Further, the configuration of the gate driver circuit 12 of the present invention or the driving method thereof exhibits more distinctive effects in combination with the display panel, the display device, or the information display device of the present invention. However, it goes without saying that a characteristic effect can be exerted in other configurations.
[1196]
In the embodiment of the present invention, the pixel configuration of FIG. 1 will be mainly described by way of example, but the present invention is not limited to this, and it goes without saying that another pixel configuration may be used. The configuration or arrangement of the gate driver circuit 12 described below is not limited to a self-luminous device such as an organic EL display panel. The present invention can be applied to a liquid crystal display panel, an electromagnetic floating display panel, or an FED (field emission display). For example, in a liquid crystal display panel, the configuration or method of the gate driver circuit 12 of the present invention may be employed for controlling the selection switching element of the pixel. When two phases are used for the gate driver circuit 12, one phase may be used for selecting a switching element of the pixel, and the other phase may be connected to one terminal of the storage capacitor in the pixel. This method is called independent CC driving. It is needless to say that the configurations described with reference to FIGS. 71 and 73 can be employed not only in the gate driver circuit 12 but also in the shift register circuit of the source driver circuit 14 and the like.
[1197]
FIG. 71 is a block diagram of the gate driver circuit 12 of the present invention. Although only four stages are shown for ease of description, basically, unit gate output circuits 711 corresponding to the number of gate signal lines 17 are formed or arranged.
[1198]
As shown in FIG. 71, in the gate driver circuit 12 (12a, 12b) of the present invention, four clock terminals (SCK0, SCK1, SCK2, SCK3), one start terminal (data signal (SSTA)), shift It is composed of signal terminals of two inversion terminals (DIRA and DIRB, which apply signals of opposite phases) for controlling the direction upside down. Further, the power supply terminal includes an L power supply terminal (VBB), an H power supply terminal (Vd), and the like.
[1199]
Since the pixel 16 is formed of a P-channel transistor, matching with the gate driver circuit 12 formed of a P-channel transistor is improved. P-channel transistors (the transistors 11b, 11c, and 11d in the pixel configuration of FIG. 1) are turned on by the L voltage. On the other hand, the gate driver circuit 12 also has the L voltage as the selection voltage. Although the P-channel gate driver can be understood from the configuration shown in FIG. 73, matching is good when the L level is the selected level. This is because the L level cannot be maintained for a long time. On the other hand, the H voltage can be held for a long time.
[1200]
By configuring the driving transistor (the transistor 11a in FIG. 1) for supplying a current to the EL element 15 with a P-channel, the cathode of the EL element 15 can be configured as a solid metal thin-film electrode. In addition, a current can flow to the EL element 15 in the forward direction from the anode potential Vdd. From the above, it is preferable that the transistor of the pixel 16 be P-channel and the transistor of the gate driver circuit 12 be P-channel. From the above, it is not merely a matter of design that the transistors (the driving transistor and the switching transistor) forming the pixel 16 of the present invention are formed by the P channel and the transistors of the gate driver circuit 12 are formed by the P channel. .
[1201]
Note that the level shifter (LS) circuit may be formed directly on the substrate 71. That is, a level shifter (LS) circuit is formed by N-channel and P-channel transistors. A logic signal from a controller (not shown) is boosted by a level shifter circuit directly formed on the substrate 71 so as to conform to the logic level of the gate driver circuit 12 formed by P-channel transistors. The boosted logic voltage is applied to the gate driver circuit 12.
[1202]
Note that the level shifter circuit may be formed of a semiconductor chip and mounted on the substrate 71 by COG. The source driver circuit 14 is formed of a semiconductor chip and mounted on the substrate 71 by COG. However, the source driver circuit 14 is not limited to being formed by a semiconductor chip, but may be formed directly on the substrate 71 using polysilicon technology.
[1203]
When the transistor 11 forming the pixel 16 is configured with a P channel, the program current flows in the direction from the pixel 16 to the source signal line 18. Therefore, the unit current circuit 484 (see FIGS. 56 and 57) of the source driver circuit needs to be formed with N-channel transistors. That is, the source driver circuit 14 needs to be configured to draw the program current Iw.
[1204]
Therefore, when the driving transistor 11a (in the case of FIG. 1) of the pixel 16 is a P-channel transistor, the source driver circuit 14 always configures the unit transistor 484 with an N-channel transistor so as to draw the program current Iw. In order to form the source driver circuit 14 on the array substrate 71, it is necessary to use both an N-channel mask (process) and a P-channel mask (process). To describe conceptually, the display panel (display device) of the present invention has a configuration in which the pixel 16 and the gate driver circuit 12 are configured by P-channel transistors, and the transistors of the source current of the source driver are configured by N channels.
[1205]
Therefore, the transistor 11 of the pixel 16 is formed by a P-channel transistor, and the gate driver circuit 12 is formed by a P-channel transistor. In this way, by forming both the transistor 11 and the gate driver circuit 12 of the pixel 16 with P-channel transistors, the cost of the substrate 71 can be reduced. However, the source driver 14 needs to form the unit transistor 484 with an N-channel transistor. Therefore, the source driver circuit 14 cannot be formed directly on the substrate 71. Therefore, the source driver circuit 14 is separately manufactured using a silicon chip or the like and mounted on the substrate 71. Note that the source driver circuit 14 is configured by a silicon chip, but the invention is not limited to this. For example, a large number of pieces may be simultaneously formed on a glass substrate by low-temperature polysilicon technology, cut into chips, and stacked on the substrate 71. Although the description has been made assuming that the source driver circuit is mounted on the substrate 71, the present invention is not limited to this. Any form may be used as long as the output terminal 681 of the source driver circuit 14 is connected to the source signal line 18 of the substrate 71. For example, a method of connecting the source driver circuit 14 to the source signal line 18 by TAB technology is exemplified. By separately forming the source driver circuit 14 on a silicon chip or the like, variation in output current can be reduced, and favorable image display can be realized. Further, cost reduction is possible.
[1206]
The configuration in which the selection transistor of the pixel 16 is formed by a P-channel transistor and the gate driver circuit is formed by a P-channel transistor is not limited to a self-luminous device (display panel or display device) such as an organic EL. For example, the present invention can be applied to a liquid crystal display device and an FED (field emission display).
[1207]
A common signal is applied to the inverting terminals (DIRA, DIRB) for each unit gate output circuit 711. As can be understood from the equivalent circuit diagram of FIG. 73, the inverting terminals (DIRA, DIRB) receive voltage values of opposite polarities. When reversing the scan direction of the shift register, the polarity of the voltage applied to the reversal terminals (DIRA, DIRB) is reversed.
[1208]
In the circuit configuration of FIG. 71, the number of clock signal lines is four. Four is the optimal number in the present invention, but the present invention is not limited to this. The number may be four or less or four or more.
[1209]
Inputs of the clock signals (SCK0, SCK1, SCK2, SCK3) are made different between adjacent unit gate output circuits 711. For example, in the unit gate output circuit 711a, the clock terminal SCK0 is input to the OC and the SCK2 is input to the RST. This state is the same for the unit gate output circuit 711c. In the unit gate output circuit 711b (the next unit gate output circuit) adjacent to the unit gate output circuit 711a, the clock terminal SCK1 is input to the OC and the SCK3 is input to the RST. Therefore, the clock terminal input to the unit gate output circuit 711 is such that SCK0 is input to OC, SCK2 is input to RST, and the next stage is that the clock terminal SCK1 is input to OC, SCK3 is input to RST, and the next stage is The clock terminals input to the unit gate output circuit 711 are alternately different, for example, SCK0 is input to OC, SCK2 is input to RST, and so on.
[1210]
FIG. 73 shows a circuit configuration of the unit gate output circuit 711. The transistors to be configured are composed of only the P channel. FIG. 74 is a timing chart for explaining the circuit configuration of FIG. 73. FIG. 72 is a timing chart for a plurality of stages in FIG. Therefore, the entire operation can be understood by understanding FIG. 73. The operation can be understood by understanding the timing chart of FIG. 74 with reference to the equivalent circuit diagram of FIG. 73 rather than the explanation in the text. Therefore, detailed description of the operation of each transistor is omitted.
[1211]
If a driver circuit configuration is created using only the P channel, it is basically possible to maintain the gate signal line 17 at the H level (Vd voltage in FIG. 73). However, it is difficult to maintain the L level (the VBB voltage in FIG. 73) for a long time. However, it can be sufficiently maintained for a short period of time such as when a pixel row is selected.
[1212]
When the switching transistors 11b and 11c of the pixel 16 are formed by P-channel transistors, the pixel 16 is selected at Vgh. The pixel 16 is in a non-selected state at Vgl. As described above, when the gate signal line 17a changes from on (Vgl) to off (Vgh), the voltage penetrates (penetration voltage). If the driving transistor 11a of the pixel 16 is formed of a P-channel transistor, the current will not flow through the transistor 11a due to the penetration voltage in the black display state. Therefore, good black display can be realized. It is difficult to realize a black display, which is a problem of the current driving method. However, when the gate driver circuit 12 is configured by a P-channel transistor, the ON voltage becomes Vgh. Therefore, matching with the pixel 16 formed by the P-channel transistor is good. 1, 2, 32, 113, and 116, the unit transistor 484 of the source driver circuit 14 is programmed from the anode voltage Vdd via the driving transistor 11a and the source signal line 18. It is important that the configuration is such that the current Iw flows. Therefore, configuring the gate driver circuit 12 and the pixel 16 with P-channel transistors, mounting the source driver circuit 14 on a substrate, and configuring the unit transistors 484 of the source driver circuit 14 with N-channel transistors has an excellent synergistic effect. Demonstrate.
[1213]
The same applies to FIG. 42 (b). In FIG. 42B, current does not flow into the unit transistor 484 of the source driver circuit 14 via the driving transistor 11b. However, the configuration is such that the program current Iw flows from the anode voltage Vdd to the unit transistor 484 of the source driver circuit 14 via the programming transistor 11a and the source signal line 18. Therefore, similarly to FIG. 1, the gate driver circuit 12 and the pixel 16 are constituted by P-channel transistors, the source driver circuit 14 is mounted on a substrate, and the unit transistors 484 of the source driver circuit 14 are constituted by N-channel transistors. Exerts an excellent synergistic effect.
[1214]
In response to the signal input to the IN terminal and the SCK clock input to the RST terminal, n1 changes, and n2 becomes an inverted signal state of n1. The potential of n2 and the potential of n4 have the same polarity, but the potential level of n4 is further lowered by the SCK clock input to the OC terminal. In response to this lowering level, the Q terminal is maintained at the L level during that period (ON voltage is output from the gate signal line 17). The signal output to the SQ or Q terminal is transferred to the next unit gate output circuit 711.
[1215]
In the circuit configurations of FIGS. 71 and 73, one gate signal line 17 is selected as shown in FIG. 75 (a) by controlling the timing of the signals applied to the IN (INA, INB) terminals and the clock terminals. 75 and the state of selecting the two-gate signal line 17 as shown in FIG. 75B can be realized using the same circuit configuration.
[1216]
In the gate driver circuit 12a on the selection side, the state shown in FIG. 75A is a driving method for simultaneously selecting one pixel row (51a) (normal driving). Also, the selected pixel row is shifted one row at a time. FIG. 75B shows a configuration in which two pixel rows are selected. This driving method is a simultaneous selection driving (a method of forming a dummy pixel row) for a plurality of pixel rows (51a, 51b) described with reference to FIGS. 27, 28, and 29. The selected pixel row is shifted by one pixel row, and two adjacent pixel rows are simultaneously selected. In particular, in the driving method of FIG. 75 (b), the pixel row 51b is precharged with respect to the pixel row (51a) holding the final video. Therefore, the pixel 16 becomes easy to write. That is, the present invention can be realized by switching between the two driving methods by the signal applied to the terminal.
[1217]
Although FIG. 75 (b) shows a method of selecting 16 rows of adjacent pixels, as shown in FIG. 76, 16 rows of pixels other than the adjacent rows may be selected. This is an example in which a pixel row at a position apart from the row is selected). In the configuration shown in FIG. 73, control is performed by a set of four pixel rows. It is possible to control whether one pixel row is selected or four consecutive pixel rows are selected from the four pixel rows. This is a limitation of using four clocks (SCK). If the number of clocks (SCK) is eight, control can be performed with a set of eight pixel rows.
[1218]
The operation of the gate driver circuit 12a on the selection side is the operation of FIG. As shown in FIG. 75A, one pixel row is selected, and the selected position is shifted one pixel row at a time in synchronization with one horizontal synchronization signal. As shown in FIG. 75 (b), two pixel rows are selected, and the selected position is shifted one pixel row at a time in synchronization with one horizontal synchronization signal.
In (a) of FIG. 279, one pixel row can be selected as a set of four pixel rows (one pixel row is selected in a set of four pixel rows. Input state and shift state). In (b) of FIG. 279, it is possible to select two consecutive pixel rows in a set of four pixel rows. (In a set of four pixel rows, two pixel rows are selected. It is determined by the data input state and the shift state). Further, according to the present invention, a set of pixel rows equal to the number of clocks is set, and in this set of pixel rows, the number of one pixel row or half or less of the set of pixel rows (for example, a set of four pixel rows is used. , 4/2 = 2 pixel rows). Therefore, an unselected pixel row always occurs in a set of pixel rows.
In the method of selecting one pixel row, the program current Iw flows through one pixel 16 as shown in FIG. The driving method for simultaneously selecting two pixel rows is the same as the driving method described with reference to FIGS. The program current Iw is divided into two pixel rows and written into the pixels 16 as shown in FIG. However, it is not limited to this. For example, as shown in FIG. 278 (b), a configuration may be adopted in which a current of the program current Iw × 2 is applied and the same current flows to the two selected pixels (16a, 16b).
[1219]
The operation of the gate driver circuit 12a on the selection side is the operation of FIG. As shown in FIG. 75A, one pixel row is selected, and the selected position is shifted one pixel row at a time in synchronization with one horizontal synchronization signal. As shown in FIG. 75 (b), two pixel rows are selected, and the selected position is shifted one pixel row at a time in synchronization with one horizontal synchronization signal.
[1220]
FIG. 279 is an explanatory diagram illustrating the operation of the gate driver circuit 12b that controls the gate signal line 17b that turns on and off the EL element 15. (A) of FIG. 279 shows a state in which an ON voltage is applied to the gate signal line 17b of one pixel row to a set of four pixel rows (hereinafter, such a set of pixel rows is referred to as a pixel row set). The position of the display pixel row 53 is shifted one pixel row at a time in synchronization with the horizontal synchronization signal (HD). Of course, an on-voltage is applied to the gate signal line 17b corresponding to one pixel row in the four-pixel row group (an off-voltage is applied to the gate signal lines 17b corresponding to the other three pixel rows) or four pixels Whether the off voltage is applied to all of the row sets (the off voltage is applied to the gate signal lines 17b corresponding to the four pixel rows) can be arbitrarily selected. Since the shift register has the configuration, the set selection state is shifted in synchronization with the horizontal synchronization signal.
[1221]
(B) of FIG. 279 shows a state in which an ON voltage is applied to the gate signal lines 17b of two pixel rows of a four-pixel row set. The position of the display pixel row 53 is shifted one pixel row at a time in synchronization with the horizontal synchronization signal (HD). Of course, an ON voltage is applied to the gate signal lines 17b corresponding to two pixel rows in the four pixel row set (an OFF voltage is applied to the gate signal lines 17b corresponding to the other two pixel rows) or four pixels Whether the off voltage is applied to all of the row sets (the off voltage is applied to the gate signal lines 17b corresponding to the four pixel rows) can be arbitrarily selected. Since the shift register has the configuration, the set selection state is shifted in synchronization with the horizontal synchronization signal.
[1222]
FIG. 279 (a) shows a state in which an ON voltage is applied to the gate signal line 17b of one pixel row in a four pixel row set. (B) of FIG. 279 shows a state in which an ON voltage is applied to the gate signal lines 17b of two pixel rows of a four-pixel row set. However, the present invention is not limited to this configuration (system). For example, an on-voltage may be applied to the gate signal line 17b of one pixel row for a set of six pixel rows.
[1223]
FIG. 280 shows the state of the voltage output to the gate signal line 17b in the driving state shown in FIG. As described above, the suffixes described in parentheses of the signal lines 17b indicate pixel rows. Note that, for ease of explanation, the pixel row starts from (1). The numbers at the top of the table indicate the numbers of the horizontal scanning periods.
[1224]
As shown in FIG. 280, the gate signal lines 17b (1) to 17b (4) and the gate signal lines 17b (5) to 17b (8) have the same waveform. That is, the same operation is performed in the 4-pixel row set.
FIG. 281 shows the state of the voltage output to the gate signal line 17b in the driving state of FIG. 279 (b). As shown in FIG. 281, the gate signal lines 17b (1) to 17b (4) and the gate signal lines 17b (5) to 17b (8) have the same waveform. That is, the same operation is performed in the 4-pixel row set.
[1225]
In the embodiment of FIG. 279, the brightness of the display screen 50 can be adjusted at any time by increasing or decreasing the number of pixels in the display state. In the case of the QCIF + panel, the number of vertical pixels is 220 dots. Therefore, in (a) of FIG. 279, 220/4 = 55 pixel rows can be displayed. That is, in the white raster display, the maximum brightness is obtained when 55 pixel rows are displayed. The brightness of the screen is determined by changing the number of display pixel rows from 55 lines to 54 lines to 53 lines to 52 lines to 51 lines to 5 lines to 4 lines to 3 lines to 2 lines to 1 line to 0 lines. , The display screen can be darkened. Conversely, by changing 0 → 1 → 2 → 3 → 4 → 5 → ... 50 → 51 → 52 → 53 → 54 → 55 , Can make the screen brighter. Therefore, multi-step brightness adjustment can be realized.
[1226]
In this brightness adjustment, the brightness of the screen is proportional to the number of display pixels, and the change is linear. In addition, there is no change in the gamma characteristic corresponding to brightness (the number of tones is maintained whether the screen is bright or dark).
[1227]
In the above embodiment, the number of display pixel rows for adjusting the brightness of the display screen 50 is changed every line. However, the present invention is not limited to this. 54 → 52 → 50 → 48 → 46 → 6 → 4 → 2 → 0 Alternatively, the number may be changed from 55 lines → 50 lines → 45 lines → 40 lines → 35 lines →... 15 lines → 10 lines → 5 lines → 0 lines.
[1228]
Similarly, in FIG. 279 (b), 220/2 = 110 pixel rows can be displayed on the QCIF + panel. That is, in the white raster display, the maximum brightness is obtained when 110 pixel rows are displayed. The screen brightness is as follows: the number of display pixel rows is 110 → 108 → 106 → 104 → 102 → ... 10 → 8 → 6 → 4 → 2 → 0 , The display screen can be darkened. On the other hand, by changing 0 → 2 → 4 → 6 → 8 → 10 → ... 100 → 102 → 104 → 106 → 108 → 110 , Can make the screen brighter. Therefore, multi-step brightness adjustment can be realized. Note that the number of display pixel rows for adjusting the brightness of the display screen 50 is changed every two lines, but is not limited to this. The number may be every four, or four or more. Also, in order to adjust the brightness, it is preferable to thin out the display pixel rows so as to disperse as much as possible, instead of focusing on one place. This is for suppressing the generation of flicker.
[1229]
The brightness adjustment is performed not in the unit of the number of pixel rows (the driving of turning on or off the pixel rows for substantially the entire horizontal scanning period) but also in the lighting time per horizontal scanning period. Can be. That is, the brightness of the display screen is adjusted by lighting a part of one horizontal scanning period (for example, a period of 1/8 of 1H and a period of 15/16 of 1H).
[1230]
This adjustment (control) is performed using the main clock (MCLK) of the display panel. For QCIF + panels, MCLK is about 2.5 MHz. That is, 176 clocks can be counted in one horizontal scanning period (1H). Therefore, by counting the MCLK and controlling the period during which the on-voltage (Vgl) is applied to the gate signal line 17b based on the count value, the EL element 15 of each pixel row can be turned on and off.
[1231]
Specifically, in the timing charts shown in FIGS. 72 and 74, it can be realized by controlling the position of the clock (SCK) at the L level and the L level period. The shorter the period during which SCK is at L level, the shorter the period during which the output Q terminal is at L level (Vgl).
[1232]
In the driving method shown in FIG. 279 (a), as shown in FIG. 282, the period in which Vgl (ON voltage) is symmetrically shorter in the 1H period is shortened. In FIG. 282, (a) is a period during which Vgl (ON voltage) is output during the entire 1H period (however, in the configuration of the P-channel gate driver circuit 12 in FIG. 73, an L level output is performed during the entire 1H period). It is impossible to perform the following operation.A period of the Vgh voltage (off voltage) occurs between 1H and the next 1H. FIG. 282 is shown as (a) in FIG. ing.
[1233]
Similarly, FIG. 282 (b) shows that the period during which Vgl is output to the gate signal line 17b is shorter than MCLK by 2 clocks (compared to (a)). . Further, FIG. 282 (c) shows that the period during which Vgl is output to the gate signal line 17b is shorter than MCLK by two clocks (compared to (b)). Hereinafter, the description is omitted because it is the same.
In the driving method shown in FIG. 279 (b), as shown in FIG. 283, the period during which Vgl (on voltage) is left and right symmetrically in the 2H period is shortened. In FIG. 283, (a) is a period in which Vgl (on voltage) is output during the entire 1H period (however, in the configuration of the P-channel gate driver circuit 12 in FIG. 73, an L level output is output during the entire 2H period). A period of the Vgh voltage (off voltage) occurs between 2H and the next 2H, which is the same as in FIG.
[1234]
Similarly, FIG. 283 (b) shows that the period during which Vgl is output to the gate signal line 17b is shorter by 2 clocks (compared to (a)) with MCLK in the 2H period. Is shown. Further, FIG. 283 (c) shows that the period during which Vgl is output to the gate signal line 17b is shorter by two clocks of MCLK (compared to (b)). Hereinafter, the description is omitted because it is the same.
[1235]
If the clock is adjusted by slightly changing the configuration of the gate driver circuit 12, the application period of the gate signal line 17b in FIG. 282 can be continuously performed for 2H periods as shown in FIG.
[1236]
In FIGS. 13 and 14, the driving method for solving moving image blur has been described.
In this method, the image is intermittently displayed, so that the outline of the image is not blurred and a good display state can be realized. In other words, a display state close to that of a CRT is realized, and good moving image display is realized.
[1237]
Even with the driving method shown in FIG. 279, good moving image display can be realized. However, in FIG. 13, the display area 53 is continuous and the non-display area 52 is also continuous, whereas in FIG. 279, the display area 53 is not continuous. Whether the ON voltage is applied to one pixel row in the 4-pixel row set ((a) in FIG. 279) or the ON voltage is applied to two consecutive pixel rows in the 4-pixel row set ((b) in FIG. 279) This is because the display state is set. Of course, by changing or improving the circuit configurations illustrated in FIGS. 71 and 73, the display pixel row for the clock (SCK) can be changed or changed. For example, display can be performed with one pixel line skipped. In addition, it is also possible to light up by skipping six pixel rows. However, in a driver circuit (shift register) constituted or formed by P-channel transistors, a non-lighted display pixel row 52 is arranged (inserted) at least between the display pixel rows 53.
[1238]
FIG. 285 shows a driving method for displaying a moving image when the gate driver circuit 12 is formed with the P channel as shown in FIG. As described above, in order to prevent image display deterioration due to moving image blur, it is necessary to perform intermittent display. That is, it is necessary to insert black (display a black or low-luminance display screen). It is driven (displayed) like a CRT display. That is, when an image is displayed on an arbitrary pixel row, black (low luminance) display is performed after a predetermined period of display. This pixel row blinks (image display and non-display (black display or low-luminance display) are alternately repeated). The black display period needs to be 4 msec or more. Alternatively, black display (low-brightness display) is performed for a period of 1/4 or more of one frame (one field). Preferably, black display (low-brightness display) is performed for a half or more of one frame (one field) or more. This condition depends on the afterimage characteristics of the human eye. That is, the image that blinks faster than the predetermined cycle appears to be continuously lit due to the afterimage characteristics of the human eye. This leads to video blur. However, an image blinking later than a predetermined period visually appears to be continuous, but a non-lighting (black display) state inserted therebetween can be recognized, and the display image becomes It is a jumpy state (although it doesn't look strange visually). For this reason, in moving image display, images are skipped, and image blur does not occur. That is, there is no moving image blur.
[1239]
In (a) of FIG. 285, in the area A, one pixel row is displayed (lit) in four pixel rows. Therefore, the light is lit once in four horizontal scanning periods (4H) (lighted during the 1H period in the 4H period). This period (period from the time when the pixel row is turned on to the time when the pixel row is turned off to the time when it is turned on) is 4 msec or less. Therefore, to the human eye, it looks as if the image is displayed completely continuously (an arbitrary pixel row is constant and there is not much difference from being lit). In the area B of FIG. 285 (a), black is inserted (low-brightness display) so as to be 4 msec or more, preferably 8 msec or more after the pixel row is displayed until the next display. Therefore, images are skipped, and good moving image display can be realized.
[1240]
In the above description, the region A or the region B has been described. However, the above items are for ease of description. In FIG. 285, the area A is sequentially scanned in the direction of the arrow (from top to bottom of the screen). Just like scanning an electron beam on a CRT. That is, the image is sequentially rewritten (see FIG. 286 for (a) in FIG. 285. Scanning (driving) is performed as shown in (a) → (b) → (c) → (a) in FIG. 286. (See FIG. 287 for (b) of FIG. 285. Scanning (driving) is performed as in (a) → (b) → (c) → (a) of FIG. 287).
[1241]
As described above, in the driving method of the present invention, an arbitrary pixel row is displayed for 4Hsec (preferably 8msec) or more for one field (one frame) in FIG. In the other period (the remaining period of one field (one frame)), the non-lighting state (black display (black insertion) or low luminance display) is continuously maintained. Therefore, for ease of explanation, the term is described as the area A or the area B, but from the viewpoint of time, it is more appropriate to express the term as the period A or the period B. That is, the region A (period A) is a period during which images are continuously lit, and the region B (period B) is a period during which the pixel rows (screen 50) are intermittently displayed.
The same applies to FIG. 285 (b) or other embodiments of the present invention.
[1242]
In FIG. 285 (b), the two pixel rows are continuously turned on, and the two pixel rows are subsequently turned off. That is, in the region A (period A), lighting is repeated for 2H, and non-lighting is repeated for 2H. In the B region (B period), the non-lighting state is continuously maintained for a predetermined period. In the driving method shown in FIG. 285 (b), the area A is apparently in a continuous display state, and the area B is apparently intermittent.
[1243]
As described above, according to the driving method of the present invention, when a display state is observed by focusing on an arbitrary pixel row (pixel), a period of less than 4 msec (or a period of less than 1/4 of one frame (one field)) A first period in which image display and non-display (black display or low-brightness display below a predetermined level) are repeated at least once or more, and the pixel row (pixel) is switched from a display state to non-display (black display or low-level display below predetermined level) A second period (or a period of 1/4 or more of one frame (one field)) in which the display state is changed to the next display state is 4 msec or more. By performing the above-described driving, good moving image display can be realized, and the configuration of the control circuit (such as the gate driver circuit 12) is easy, so that cost reduction can be realized.
[1244]
Also in FIG. 285, the brightness of the screen 50 can be adjusted (changed) by changing the number of lighting pixel rows (similar to FIG. 279, the number of display pixels 53 may be changed or adjusted). In addition, by changing the ratio of the black insertion area (area B in FIG. 285), it is possible to achieve an optimum state according to the image display state. For example, in a still image, the B region should be prevented from becoming long. This is because it causes flicker. In the case of a still image, the display pixel rows 53 should be dispersedly displayed (arranged in the screen 50). For example, in the case of a QCIF + panel, the number of pixel rows is 220. Among them, if a 55-pixel row is displayed as a still image, 220/44 = 4, so one pixel row may be displayed every 4 pixel rows. To display 10 pixel rows out of 220 pixel rows, one pixel row may be displayed in 220/10 = 22 pixel rows. In FIG. 285, the number of the B region (B period) is one, but it is not limited to this, and it goes without saying that it may be divided or dispersed into two or more (a plurality).
[1245]
However, in (a) of FIG. 285, only display of whether or not to light one pixel row in a four-pixel row set can be realized. Therefore, one pixel row cannot be turned on for every 22 pixel rows. Therefore, four pixel row sets are displayed five times = one pixel row is displayed in 20 pixel rows (that is, one pixel row is displayed in 20 pixel rows. In other words, four of the four pixel row sets have no pixel rows at all). Instead of the lighting state, one pixel row of one pixel row set is turned on).
The remaining 20 pixel rows (220−4 × 5 = 200) are all turned off. In other words, in the present invention, the number of pixel rows in a block (pixel) within a combination (block) of the pixel row sets is defined as the number of the pixel rows in the combination (block or restriction) as one unit. Control of whether or not to do so. The above items are applied to FIG. 285 (b) and also to other embodiments of the present invention.
[1246]
In the case of displaying a moving image, as described in FIG. 285, it is necessary to insert black for at least 4 msec or more. Also, by changing the ratio of black insertion (continuous time of black display, black display area with respect to the display screen), the moving image display state can be changed (adjusted to the optimum state). For very high-speed moving image display (such as when the image moves rapidly), it is preferable to increase the black insertion area. At this time, the decrease in the luminance due to the decrease in the number of pixels for displaying the image is dealt with by increasing the emission luminance of one pixel row. In addition, it is preferable that the period during which the black display is continued be lengthened. If the ratio of the moving image display area to the entire screen is relatively small, or if the moving image moves relatively slowly, the ratio of black insertion may be reduced. In this case, the increase in the display luminance due to the increase in the number of lighting pixel rows 53 can be easily adjusted by reducing the light emission luminance per pixel row. This is because this adjustment can be changed by the program current Iw or the like. Alternatively, the black insertion period may be dispersed into a plurality of periods. Flicker is reduced and good image display can be realized.
[1247]
By changing or adjusting the black insertion state even in the moving image display as described above, a more optimal image display can be realized. Needless to say, the above items are also applied to the following embodiments.
Moving image detection (ID detection) of the input video signal is performed, and in the case of a moving image or an image having many moving images, the driving method (intermittent display by black insertion) in FIG. 285 is performed. In the case of a still image, the driving method shown in FIG. 279 (the lighting pixel row positions are dispersed as much as possible) is implemented. Of course, the switching may be performed according to the use of the display panel or the display device of the present invention. For example, in the case of a still image such as a computer monitor, the driving method shown in FIG. 279 is adopted. In the case of an AV application such as a television, the driving method shown in FIG. 285 is adopted. This switching of the driving method can be easily changed based on the SSTA data of the gate driver circuit 12b. This is because it only controls the TFT that turns on and off the current flowing through the EL element 15 in FIG. Switching between FIG. 285 and FIG. 279 (corresponding to video or still image, or more video or still image), a switch that can be operated by the user may be implemented according to the situation, The present invention may be implemented by the display panel manufacturer. Further, the surrounding environment state may be detected using a photo sensor or the like, and the switching may be performed automatically. Further, a control signal (switching signal) may be pre-loaded on the video signal received by the present invention, and the display state (driving method) may be switched by detecting the control signal.
[1248]
FIG. 288 shows an output waveform of the gate signal line 17b in the case of the driving method shown in FIG. In the pixel configuration in FIG. 1, the TFT 11 d is turned on / off by an on / off signal (Vgh is an off voltage, Vgl is an on voltage) applied to the gate signal line 17 b, and a current flowing through the EL element 15 is turned on and off. In FIG. 1, the upper part shows the horizontal scanning period, and the symbol L indicates the number of pixel rows L (L = 220 in the case of the QCIF + panel). In FIGS. 279 and 285, the driving method of the present invention is not limited to the pixel configuration in FIG. For example, it goes without saying that the present invention can be applied to other pixel configurations (FIG. 54 and the like).
[1249]
As can be seen from FIG. 288, in the A period (A region), the ON voltage (Vhl) is applied to each gate signal line 17b at a rate of 1H period to 4H period. In the period B (region B), the off-voltage (Vgh) is continuously applied. Therefore, no current flows through the EL element 15 during this period. Then, the ON voltage position of each gate signal line 17b is scanned one pixel row at a time.
[1250]
In the above embodiment, scanning is performed one pixel row at a time, but the present invention is not limited to this. For example, in interlaced scanning, scanning is performed skipping one pixel line. That is, even-numbered pixel rows are scanned in the first frame. In the second frame, the odd pixel rows are scanned. When rewriting the first frame, the image written in the second frame is held as it is. However, a blinking operation is performed (it does not need to be performed). When rewriting the second frame, the image written in the first frame is kept as it is. Of course, the blinking operation may be performed as in the embodiment of FIG.
[1251]
In the interlaced scanning, one field is usually a CRT with two frames. However, the present invention is not limited to this. For example, 4 frames = 1 field may be used. In this case, in the first frame, the image of (4N + 1) pixel rows (where N is the above integer) is rewritten. In the second frame, the image of the (4N + 2) pixel row is rewritten. In the next third frame, the image of the (4N + 3) pixel row is rewritten. In the last fourth frame, the image of the (4N + 4) pixel row is rewritten. As described above, in the present invention, writing to a pixel row is not limited to only sequential scanning. The above is also applied to other embodiments. Further, in the present invention, the interlaced scanning means a wide and general interlaced scanning, and is not limited to 2 frames = 1 field. That is, a plurality of frames = 1 field.
[1252]
Note that in FIGS. 288 and 289 as well, controlling the current flowing through the EL element 15 during one horizontal scanning period (1H) or a plurality of horizontal scanning periods as shown in FIGS. It is needless to say that the driving method for adjusting the brightness of the display screen 50 can be used together with the control method.
[1253]
289 shows the waveform applied to the gate signal line 17b in FIG. 285 (b), similarly to FIG. 288. The difference from FIG. 288 is that in the period A (region A, see FIG. 279 (b)), the ON voltage (Vgl) is applied to each gate signal line 17b for two horizontal scanning periods (2H). After that, the off voltage (Vgh) is applied for a period of 2H. The ON voltage and the OFF voltage are alternately repeated. In the period B (region B), an off-voltage is continuously applied. The application position of the ON voltage of each gate signal line 17b is scanned every 1H.
[1254]
FIG. 288 shows the output waveform of the gate signal line 17b in the case of the driving method shown in FIG. In the pixel configuration in FIG. 1, the TFT 11 d is turned on / off by an on / off signal (Vgh is an off voltage, Vgl is an on voltage) applied to the gate signal line 17 b, and a current flowing through the EL element 15 is turned on and off. In FIG. 1, the upper part shows the horizontal scanning period, and the symbol L indicates the number of pixel rows L (L = 220 in the case of the QCIF + panel). In FIGS. 279 and 285, the driving method of the present invention is not limited to the pixel configuration in FIG. For example, it goes without saying that the present invention can be applied to other pixel configurations (FIG. 54 and the like).
[1255]
As can be seen from FIG. 288, in the A period (A region), the ON voltage (Vhl) is applied to each gate signal line 17b at a rate of 1H period to 4H period. In the period B (region B), the off-voltage (Vgh) is continuously applied. Therefore, no current flows through the EL element 15 during this period. Then, the ON voltage position of each gate signal line 17b is scanned one pixel row at a time.
[1256]
In the above embodiment, scanning is performed one pixel row at a time, but the present invention is not limited to this. For example, in interlaced scanning, scanning is performed skipping one pixel line. That is, even-numbered pixel rows are scanned in the first frame. In the second frame, the odd pixel rows are scanned. When rewriting the first frame, the image written in the second frame is held as it is. However, a blinking operation is performed (it does not need to be performed). When rewriting the second frame, the image written in the first frame is kept as it is. Of course, the blinking operation may be performed as in the embodiment of FIG.
[1257]
In the interlaced scanning, one field is usually a CRT with two frames. However, the present invention is not limited to this. For example, 4 frames = 1 field may be used. In this case, in the first frame, the image of (4N + 1) pixel rows (where N is the above integer) is rewritten. In the second frame, the image of the (4N + 2) pixel row is rewritten. In the next third frame, the image of the (4N + 3) pixel row is rewritten. In the last fourth frame, the image of the (4N + 4) pixel row is rewritten. As described above, in the present invention, writing to a pixel row is not limited to only sequential scanning. The above is also applied to other embodiments. Further, in the present invention, the interlaced scanning means a wide and general interlaced scanning, and is not limited to 2 frames = 1 field. That is, a plurality of frames = 1 field.
[1258]
Note that in FIGS. 288 and 289 as well, controlling the current flowing through the EL element 15 during one horizontal scanning period (1H) or a plurality of horizontal scanning periods as shown in FIGS. It is needless to say that the driving method for adjusting the brightness of the display screen 50 can be used together with the control method.
[1259]
289 shows the waveform applied to the gate signal line 17b in FIG. 285 (b), similarly to FIG. 288. The difference from FIG. 288 is that in the period A (region A, see FIG. 279 (b)), the ON voltage (Vgl) is applied to each gate signal line 17b for two horizontal scanning periods (2H). After that, the off voltage (Vgh) is applied for a period of 2H. The ON voltage and the OFF voltage are alternately repeated. In the period B (region B), an off-voltage is continuously applied. The application position of the ON voltage of each gate signal line 17b is scanned every 1H. Other items are the same as or similar to those in FIG. 288, and a description thereof will not be repeated.
[1260]
In the above-described embodiment, the driving method in which the area A and the area B are mixed in the display screen 50 is used. That is, in any period of the screen display state, the area A always includes the area B (the location of the area A is different, of course). This means that there is an A period and a B period within one field (one frame, that is, a screen rewriting cycle). However, in order to improve the display of a moving image, black insertion (black display or low-luminance display) may be performed. Therefore, the driving method is not limited to the driving method shown in FIG.
[1261]
For example, the driving method shown in FIG. 290 is exemplified. For ease of understanding, it is assumed that FIG. 290 includes four display periods ((a), (b), (c), and (d)). 290 (a) is the first frame, FIG. 290 (b) is the second frame, FIG. 290 (c) is the third frame, and FIG. 290 (d) is the first frame. There are four frames. The display is repeated in the order of (a) → (b) → (c) → (d) → (a) → (b) →.
[1262]
In the first frame, as shown in FIG. 290 (a), the even-numbered pixel rows are sequentially selected, and the image is rewritten. When the rewriting of the first frame is completed, black display is sequentially performed from the top of the screen 50 as shown in (b) of FIG. 290 ((b) of FIG. 290 is a state where black display writing has been completed). In the next third frame, as shown in (c) of FIG. 290, an odd-numbered pixel row is sequentially written with an image from the top of the screen 50. That is, odd-numbered images are sequentially displayed from the top of the screen. In the next fourth frame, the image is turned off (black display) from the top of the screen 50 ((d) in FIG. 290 also shows the state when the light is completely turned off).
[1263]
In FIG. 290, in (a) and (c), it is described that an image is written and an image is displayed. However, the present invention is basically characterized in that an image is displayed (lighted). . Therefore, writing an image (executing a program) and displaying an image need not be the same. That is, in (a) and (c) of FIG. 290, it may be considered that the current flowing through the EL element 15 is controlled by controlling the gate signal line 17b, and the EL element 15 is turned on or off. Therefore, switching between the state of FIG. 290 (a) and the state of FIG. 290 (b) can be performed collectively (for example, during the 1H period). For example, it can be implemented by controlling the enable terminal (an on / off state is stored in the shift register of the gate driver circuit 12b (in FIG. 290 (a), the shift register corresponding to the even-numbered pixel row is on data). When the terminal is off, the states of (b) and (d) of FIG. 290 are displayed, and by turning on the enable terminal, the display state of (a) of FIG. 290 is displayed). Therefore, the display of (a) and (c) of FIG. 290 can be performed while the gate signal line 17b is on / off (the image data is stored in the capacitor 19 in advance in the case of the pixel configuration of FIG. 1). In the above description, it is assumed that the states (a), (b), (c), and (d) of FIG. 290 are performed during each 11 frame period.
[1264]
However, the present invention is not limited to this display state. This is because at least the moving image display state can be improved or improved by executing a black insertion state such as (b) and (d) in FIG. 290 for a period of 4 msec. Therefore, in the embodiment of the present invention, it is limited that the shift register circuit of the gate driver circuit 12b is used to scan the gate signal line 17b to realize the display states (a) and (c) of FIG. is not. Odd-numbered gate signal lines 17b (referred to as an odd-numbered gate signal line set) are collectively connected, and even-numbered gate signal lines 17b (referred to as an even-numbered gate signal line set) are collectively connected to form an odd-numbered gate signal line. The on / off voltage may be applied alternately to the signal line group and the even gate signal line group. If the ON voltage is applied to the odd gate signal line set and the OFF voltage is applied to the even gate signal line set, the display state of (c) in FIG. 290 is realized. If the ON voltage is applied to the even-numbered gate signal lines and the OFF-voltage is applied to the odd-numbered gate lines, the display state of FIG. 290 (a) is realized. By applying an off-voltage to both the odd gate signal line set and the even gate signal line set, the display states of (b) and (d) of FIG. 290 are realized. Each of the states (a), (b), (c), and (d) in FIG. 290 may be performed for a period of 4 msec or more (particularly, in (b) and (d) in FIG. 290).
[1265]
In the driving method shown in FIG. 290, the screen display state ((a) and (c) in FIG. 290) and the black display state (black insertion, (b) and (d) in FIG. 290) are alternately repeated. Therefore, the image display is intermittent, and the moving image display performance is improved (moving image blur does not occur).
[1266]
In the embodiment of FIG. 290, in the first frame and the third frame, an image is displayed on an odd pixel row or an even pixel row, and a black screen ((b) and (d) of FIG. 290) is inserted between these two screens. Drive method. However, the present invention is not limited to this, and the display state of FIG. 279 may be implemented in the first frame and the third frame, and a black display may be inserted between the two frames. FIG. 291 shows a timing chart in the above embodiment. FIG. 291 (a) is the first frame, and FIG. 291 (b) is the second frame in the black inserted state. (C) of FIG. 291 is the third frame. Note that the fourth frame is the same as that shown in FIG. However, the fourth frame is not always necessary. A configuration of 3 frames = 1 field may be used. This is because a black screen is inserted in the second frame, and moving image blur is greatly improved. That is, (a) → (b) → (c) → (a) →... Of FIG.
[1267]
(A) of FIG. 291 displays an image for a period of 1H in four horizontal scanning periods (4H) in (a) of FIG. 279 (each gate signal line 17b has a Vgl voltage (ON voltage) for a period of 1H every 4H. In the next second frame, the off voltage (Vgh) is applied to all the gate signal lines 17b.This control is similar to that of the previous embodiment by controlling the enable terminal. 291 (b) is not limited to the one-frame period.To improve the moving image display, a state of 4 msec or more is required. However, if the image is sequentially rewritten from the top of the screen (although not limited to from the top) in FIG. 291 (a), the image will be skipped. Like, Of collectively connecting the gate signal line 17b, also, according to the controlling the enable terminal, it can be easily performed.
[1268]
In FIG. 291, each pixel row regularly performs image display, such as lighting during a 1H period during a 4H period. However, each pixel row only needs to have the same lighting (display) period in a unit period (for example, one frame, one field, or the like).
That is, it is not necessary to regularly perform the lighting state and the non-lighting state.
[1269]
FIG. 292 is an example in the case of an irregularly lit state. On-voltage is applied to the gate signal line 17b (1) at the 1H, 5H, 6H, 9H, 13H, 14H, .... In other periods, the off-voltage is applied. Therefore, the on-state voltage is not applied periodically (although the cycle is long in the long term), but is random. The sum of the period during which the ON voltage is applied to each gate signal line 17b during this one frame period (unit period) may be made substantially coincident with the other gate signal lines 17b. As described above, the lighting time of each pixel row (it is assumed that the pixel row is lit (displayed) by applying the ON voltage to the gate signal line 17b) substantially coincides. Note that in FIG. 292, the signal waveform applied to each gate signal line 17b is such that it is scanned by 1H. In this way, by scanning (applying) the basic pattern waveform by shifting each gate signal line 17b by 1H (predetermined clock or unit), the brightness of the display screen can be made uniform over the entire screen. In FIG. 292, it is needless to say that the brightness of the screen can be controlled (adjusted) by adjusting the application period of the on-voltage (Vgl).
[1270]
In the above embodiment, the same on / off voltage pattern is applied to the gate signal line 17b in each frame (unit period). However, in the present invention, the period in which each pixel row (pixel) is lit (displayed) or not lit (non-display) in the predetermined period is made substantially equal. Therefore, in the driving method of 2 frames = 1 field, the signal waveform of each gate signal line 17b applied to the first frame and the second frame may be different. For example, an arbitrary pixel row may be driven such that an ON voltage is applied during a period of 10H in the first frame and an ON voltage is applied during a period of 20H in the second frame (referred to as two frames). In a unit period, an ON voltage is applied for a period of 10H + 20H). The ON voltage is applied to the other pixel rows for a period of 30H.
[1271]
This embodiment is illustrated in FIG. In (a) of FIG. 293 (referred to as the first frame), an on-voltage is applied to the gate signal line 17b corresponding to each pixel row for one horizontal scanning period (1H) every four horizontal scanning periods (4H). . In (b) of FIG. 293 (referred to as a second frame), an on-voltage is applied to the gate signal line 17 corresponding to each pixel row in a 4H cycle for a period of 2H. That is, in the two frames, the ON voltage is applied for a period of (1 + 2) H in a (4 + 4) H cycle. Even in such a drive, in the unit period (two frames in FIG. 293), the ON voltage is applied to each gate signal line 17b for the same period. Therefore, each pixel row is displayed with the same luminance (assuming white raster display).
[1272]
In FIG. 291, the on-voltage is applied for a period of 1H in a 4H cycle, but the present invention is not limited to this. For example, as shown in FIG. 294, an on-voltage may be applied for a period of 1H at a period of 8H. Further, the signal waveform applied to each gate signal line 17b in each frame does not have periodicity and may be completely randomized. This is because it is only necessary that the total period in which the ON voltage is applied in the unit cycle (unit period) coincides in all the gate signal lines 17b.
[1273]
However, in the above embodiment, the total period during which the ON voltage is applied is matched in the unit period for all the gate signal lines 17b, but this is not applied in the following cases. This is a case where a plurality of screens 50 having different luminances are provided in one screen 50 (that is, one display panel). The screen 50 includes a first screen 50a and a second screen 50b, and the screens 50a and 50b have different luminances. The difference between the luminances of the two screens 50 can be changed by adjusting the program current Iw. However, the gate signal line 17b is scanned to turn on (display) each pixel row on the first screen 50a. ) It is easy to realize a method in which the period differs from the lighting (display) period of each pixel row on the second screen 50b. For example, in each pixel row of the first screen 50a, an ON voltage is applied to the gate signal line 17b for a period of 1H to 4H. In each pixel row of the second screen 50b, an ON voltage is applied to the gate signal line 17b for a period of 1H to 8H. As described above, the brightness of the screen can be adjusted by changing the period during which the ON voltage is applied in each screen, and the gamma curves at that time can be made similar.
[1274]
In the above embodiment, the current flowing through the EL element 15 is adjusted (turned on and off) by controlling the gate signal line 17b, and the brightness of the display screen 50 is adjusted, or the moving image display is improved. there were. FIG. 295 shows another embodiment of the present invention having the above-described effects.
[1275]
The pixel 16 in FIG. 295 is arranged or configured as in FIG. 296. The difference from the pixel configuration of FIG. 1 is that one terminal of the storage capacitor 19 (capacitor 19) is connected to the capacitance control line 2951. One capacitance control line 2951 is common to one pixel row. The capacity control line 2951 is connected to the capacity control common line 2953.
[1276]
In FIG. 296, one terminal of the capacitor 19 is connected to the capacitance control line 2951, and the other terminal is connected to the gate terminal of the TFT 11a. Now, it is assumed that the Va voltage is applied to the gate terminal (G) of the TFT 11a. It is also assumed that the voltage Vdd is applied to the source terminal (S) of the TFT 11a. It is assumed that Va <Vdd. It is assumed that the voltage Vc is applied to the capacitance control line 2951.
[1277]
In this state, when the Vc voltage of the capacitance control line 2951 is changed to the + side, the Va voltage is also shifted to the + side with this change. Since the TFT 11a is a P-channel transistor, when the gate terminal of the TFT 11a shifts to the + side (Vdd side), the TFT 11a is in a direction in which no current flows. Therefore, when the change of the Vc voltage to the + side is larger than a certain value, the TFT 11a is in a state where no current flows completely (cutoff state). That is, by controlling the potential applied to the capacitance control line 2951, the corresponding pixel row can be set to a black display state. Conversely, when the Vc voltage of the capacitance control line 2951 changes to the negative side, the potential of the gate terminal (G) of the TFT 11a also shifts to the negative side. Therefore, the TFT 11a flows more current. The above is the case where the driving TFT 11a is formed of a P-channel transistor. If the driving TFT 11a has N channels, the reverse is true. In other words, when the potential of the capacitance control line 2951 is shifted to the + side, the N-channel driving TFT 11a allows more current to flow to the EL element 15.
[1278]
By applying the above driving method to FIG. 296, the display screen 50 can be displayed in black. That is, the black insertion described with reference to FIG. 285 and the like can be realized.
[1279]
In FIG. 295, capacity control common lines 2953 (2953a, 2953b, 2953c, 2953d) are formed or arranged. The capacity control line 2951 of the (4N + 1) pixel row (where N is an integer of 0 or more) is connected to the capacity control common line 2953a. Further, the capacitance control line 2951 of the (4N + 2) pixel row is connected to the capacitance control common line 2953b. The (4N + 3) pixel row is connected to the capacitance control common line 2953c, and the capacitance control line 2951 of the (4N + 4) pixel row is connected to the capacitance control common line 2953d.
[1280]
With the above configuration, if the voltage applied to the capacitance control common line 2953a is shifted to the + side, the (4N + 1) pixel rows are not displayed (black display or low luminance display). Similarly, if the voltage applied to the capacitance control common line 2953b is shifted to the + side, the (4N + 2) pixel rows are not displayed (black display or low luminance display). When the applied voltage of the capacitance control common line 2953c is shifted to the + side, the (4N + 3) pixel row is not displayed. When the applied voltage of the capacitance control common line 2953d is shifted to the + side, the (4N + 4) pixels are displayed. Rows are hidden.
[1281]
By controlling the capacitance control common line 2953 as described above, a predetermined pixel row can be displayed in black. Therefore, the screen brightness can be adjusted by adjusting the control timing and control cycle of the capacity control common line 2953. Further, by setting the connection state between the capacitance control line 2951 and the capacitance control common line 2953, the number of connection lines, and the number of formed capacitance control common lines 2953 to a predetermined state, a concentrated black insertion portion is provided as shown in FIG. Can be. Therefore, it is possible to improve the moving image display.
[1282]
In FIG. 296 (a), odd-numbered pixel rows are connected to a capacitance control common line 2953a, and even-numbered pixel rows are connected to a capacitance control common line 2953b. Therefore, by alternately applying a voltage to the + side to the capacitance control common lines 2953a and 2953b, the display screen 50 can be made into a non-display pixel row in a comb shape. In (b) of FIG. 296, each pixel row is connected to a different capacitance control common line 2953. Therefore, lighting or non-lighting control can be performed in a three-pixel row cycle.
[1283]
When the voltage applied to the capacitance control line 2951 and changed to the + side is comparatively small, the voltage applied to the capacitance control line 2951 is again shifted to the-side, so that the current flowing through the TFT 11a returns to the original current. (However, the addition of the compensation voltage is necessary.) However, if the voltage shifted to the + side is larger than a predetermined value, the current flowing through the TFT 11a cannot be restored (the required compensation voltage becomes large, and it is difficult to return to the original current value).
[1284]
In order to implement black insertion in the configuration of FIG. 296, it is basically not desirable to restore the image data held in the capacitor 19 (since it is difficult to completely restore the original holding voltage). is there). In other words, the image can be displayed in black.
[1285]
For example, as shown in FIG. 297, before writing an image, a positive voltage is applied to the capacitance control line 2951 at the R position to make a black display 52. That is, a positive voltage is applied to the capacitance control line 2951, and the screen 50 is set to the black display 52. Next, after a lapse of a predetermined period, an image is written (the image writing position is the pixel writing row 51). In FIG. 297, writing is performed at a position separated from the pixel row by K (K1 in (a) of FIG. 297, K2 in (b) of FIG. 297). K1 indicates the number of pixel rows. In other words, the time from black writing at the R position to image writing is the number of pixel rows × 1 horizontal scanning period. Therefore, as K is larger, the black writing period increases (K1 <K2), and the image display becomes darker. The screen becomes darker as the value of K increases, and the screen becomes brighter as the value of K decreases. By adjusting the value of K, the brightness of the image can be adjusted. In addition, the larger the value of K, the higher the effect of improving moving image blur.
[1286]
In the above embodiment, one source driver circuit (IC) 14 and one gate driver circuit (IC) 12 display an image on one screen 50. However, the present invention is not limited to this. For example, in the embodiment of FIG. 298, the screen 50 includes a screen 50a and a screen 50b. The source driver circuit 14a is connected to the source signal line 18a of the screen 50a. The source driver circuit 14b is connected to the source signal line 18b of the screen 50b. Gate signal lines (17a, 17b) for the screens 50a and 50b are connected to one built-in gate driver circuit 12.
[1287]
That is, in the embodiment of FIG. 298, the gate driver circuit (IC) 12 is common to the screens 50a and 50b, and the screen 50 is divided into two and driven by the two source driver circuits (14a and 14b). I have. The writing of the image is not limited to the downward direction (A direction) from the top of the screen 50. As shown in FIG. 298, scanning may be performed from below the screen 50 in the upward direction (B direction). Alternatively, the screen 50a may be scanned in the direction A, and the screen 50b may be scanned in the direction B. Although the screen 50 is divided into two in FIG. 298, it goes without saying that the screen 50 may be divided into three or more. Further, the source driver circuit 14a drives even-numbered source signal lines 18 in one display screen 50, and the source driver circuit 14b drives or drives the odd-numbered source signal lines 18 in the display screen 50. May be. The same applies to the gate driver circuit 12. Each screen (50a, 50b) may be driven by using a plurality of gate driver circuits 12. Also, the gate driver circuit 12a drives or drives the even-numbered gate signal lines 18 in one display screen 50, and the gate driver circuit 12b drives or drives the odd-numbered gate signal lines 18 in the display screen 50. May be. Note that protection diodes are preferably formed on the source signal lines 14 and the gate signal lines 12 for protection against static electricity. Needless to say, the above items can be applied to other embodiments of the present invention.
[1288]
Hereinafter, a high-quality display method using a current driving method (current programming method) will be described with reference to the drawings. In the current programming method, a current signal is applied to the pixel 16 so that the pixel 16 holds the current signal. Then, the current held by the EL element 15 is applied.
[1289]
The EL element 15 emits light in proportion to the magnitude of the applied current. That is, the emission luminance of the EL element 15 has a linear relationship with the value of the current to be programmed. On the other hand, in the voltage programming method, the applied voltage is converted into a current by the pixel 16. This voltage-current conversion is non-linear. The nonlinear conversion requires a complicated control method.
[1290]
In the current driving method, the value of video data is linearly converted as it is into a program current. As a simple example, in the case of 64-gradation display, video data 0 is set to a program current Iw = 0 μA, and video data 63 is set to a program current Iw = 6.3 μA (in a proportional relationship). Similarly, the video data 32 has a program current Iw = 3.2 μA, and the video data 10 has a program current Iw = 1.0 μA. That is, the video data is directly converted into the program current Iw in a proportional relationship.
For ease of understanding, description will be made on the assumption that video data and program current are converted in a proportional relationship. Actually, the video data and the program current can be more easily converted. This is because, as shown in FIG. 48, in the present invention, the unit current of the unit transistor 484 corresponds to 1 of the video data. Further, the unit current can be easily adjusted to an arbitrary value by adjusting the reference current circuit. Also, the reference current is provided for each of the R, G, and B circuits, and white balance can be obtained over the entire gradation range by adjusting the reference current circuit in the RGB circuit. This is a synergistic effect of the current program method and the configuration of the source driver circuit 14 and the display panel of the present invention.
[1291]
The EL display panel is characterized in that the program current and the emission luminance of the EL element 15 have a linear relationship. This is a major feature of the current programming method. In other words, by controlling the magnitude of the program current, the light emission luminance of the EL element 15 can be adjusted linearly.
[1292]
The voltage applied to the gate terminal of the driving transistor 11a and the current flowing through the driving transistor 11a are non-linear (often a square curve). Therefore, in the voltage program method, the program voltage and the light emission luminance have a non-linear relationship, and it is extremely difficult to control light emission. Light emission control is extremely easy with the current programming method as compared with the voltage programming. In particular, in the pixel configuration of FIG. 1, the program current and the current flowing through the EL element 15 are theoretically equal. Therefore, light emission control is very easy to understand and control. Also in the case of the N-fold pulse drive of the present invention, since the emission luminance can be grasped by calculating with the program current set to 1 / N, the emission control is excellent. In the case where the pixel configuration shown in FIG. 38 or the like is a current mirror configuration, the driving transistor 11b and the programming transistor 11a are different from each other, causing a shift in the current mirror magnification, and there is an error factor in light emission luminance. However, in the pixel configuration of FIG. 1, the driving transistor and the programming transistor are the same, and thus do not have this problem.
[1293]
The emission luminance of the EL element 15 changes in proportion to the applied current amount. The voltage (anode voltage) applied to the EL element 15 is a fixed value. Therefore, the emission luminance of the EL display panel is proportional to the power consumption.
[1294]
From the above, the video data is proportional to the program current, the program current is proportional to the emission luminance of the EL element 15, and the emission luminance of the EL element 15 is proportional to the power consumption. Therefore, if logic processing is performed on video data, it is possible to control the current consumption (power) of the EL display panel, the emission luminance of the EL display panel, and the power consumption of the EL display panel. That is, the luminance and power consumption of the EL display panel can be grasped by performing logic processing (addition, etc.) on the video data. Therefore, processing such as preventing the peak current from exceeding the set value is extremely easy.
[1295]
In particular, the EL display panel of the present invention is of a current drive type. Further, the image display control is easier with a characteristic configuration. There are two distinctive image display control methods. One is control of the reference current. The other is duty ratio control. By using the reference current control and the duty ratio control alone or in combination, it is possible to realize a wide dynamic range, high image quality display, and high contrast.
[1296]
First, in the reference current control, as shown in FIG. 77, the source driver IC (circuit) 14 includes a circuit for adjusting the reference current of each RGB. Further, the program current Iw from the source driver circuit 14 is determined by how many unit transistors 484 are flowing but are output. The current output from one unit transistor 484 is proportional to the magnitude of the reference current. Therefore, by adjusting the reference current, the current output from one unit transistor 484 is determined, and the magnitude of the program current is determined. Since the reference current and the output current of the unit transistor 484 have a linear relationship, and the program current and the luminance have a linear relationship, if the white balance is adjusted by adjusting the RGB reference currents in white raster display. , The white balance is maintained at all gradations.
[1297]
Although FIG. 77 shows a configuration in which current mirrors are connected in multiple stages, the present invention is not limited to this. It is needless to say that the reference current can be easily adjusted even with the single-stage source driver IC (circuit) 14 shown in FIGS. 166 to 170 and the white balance is maintained at all gradations. Needless to say, the luminance of the EL display panel can be controlled by adjusting the reference current.
[1298]
FIG. 78 shows a duty ratio control method. FIG. 78A shows a method of continuously inserting the non-display area 52. Suitable for video display. Further, (a1) in FIG. 78 has the darkest image, and (a4) in FIG. 78 has the brightest image. The duty ratio can be freely changed by controlling the gate signal line 17b. FIG. 78C shows a method of inserting the non-display area 52 by dividing it into a large number. Particularly suitable for still image display. Also, FIG. 78 (c1) has the darkest image, and FIG. 78 (c4) has the brightest image. The duty ratio can be freely changed by controlling the gate signal line 17b. FIG. 78B shows an intermediate state between FIG. 78A and FIG. 78C. Similarly, in FIG. 78B, the duty ratio can be freely changed by controlling the gate signal line 17b.
[1299]
The dispersion of the display area 53 is 220/4 = 55 if the number of pixel rows of the display panel is 220 and the duty is 1/4 Duty. Therefore, the dispersion is adjusted from 1 to 55 (from 1 to 55 times the brightness). it can). Also, if the display panel has 220 pixel rows and Ｄ duty, then 220/2 = 110, so 1 to 110 (the brightness can be adjusted from 1 to 110 times the brightness). Therefore, the adjustment range of the brightness of the screen luminance 50 is very wide (the dynamic range of image display is wide). In addition, regardless of the brightness, the number of expressible gradations can be maintained. For example, in the case of the 64-gradation display, the 64-gradation display can be realized regardless of whether the luminance of the screen 50 in the white raster is 300 nt or 3 nt.
[1300]
As described above, the duty can be easily changed by controlling the start pulse to the gate driver circuit 12b. Therefore, a variety of Duties such as 1/2 Duty, 1/4 Duty, 3/4 Duty, and 3/8 Duty can be easily changed.
[1301]
The duty ratio drive in one horizontal scanning period (1H) may be performed by applying an on / off signal of the gate signal line 17b in synchronization with the horizontal synchronization signal. Further, the duty ratio can be controlled even in units of 1H or less. 145 and 146 are the driving methods. By performing the OEV2 control within the 1H period, the brightness control (duty ratio control) of a minute step can be performed (see also FIG. 109 and its description, and see FIG. 175 and its description). .
[1302]
The duty ratio control within 1H is performed when the duty ratio is 1/4 Duty or less. If the number of pixel rows is 220 pixel rows, it is 55/220 Duty or less. In other words, it is performed in the range of 1/220 to 55/220 Duty. This is performed when the change of one step changes by 1/20 (5%) or more after the change before the change. More preferably, it is desirable to perform OEV2 control even with a change of 1/50 (2%) or less and to perform minute duty ratio drive control. In other words, in the duty ratio control by the gate signal line 17b, when the brightness change after the change becomes 5% or more before the change, the change is made little by little by controlling the OEV2 so that the change amount becomes 5% or less. Let it. It is preferable to introduce the Wait function described in FIG. 94 for this change.
The duty ratio control within 1H when the duty ratio is equal to or less than 1/4 Duty is performed because the amount of change per step is large. However, since the image is halftone, even a minute change is visually recognized. It is also easy. Human vision has a low ability to detect a change in brightness on a dark screen over a certain level. Further, even on a screen that is brighter than a certain level, the ability to detect a change in brightness is low. This is probably because human vision depends on the squared characteristic.
[1303]
FIG. 174 is a graph showing a detection function for a change in the screen. The horizontal axis is the brightness (nt) of the screen. The vertical axis indicates the allowable change (%). The permissible change (%) describes a limit point at which the change rate (%) of the brightness changed from an arbitrary Duty to the next Duty is permissible. However, the allowable change (%) has a large change ratio depending on the content of the image (change ratio, scene, etc.). In addition, it tends to depend on the ability to detect individual moving images.
[1304]
As can be seen from FIG. 174, when the luminance of the screen 50 is high, the allowable change with respect to the duty change is large. Further, even when the luminance of the screen 50 is dark, the allowable change with respect to the duty change tends to be large. However, in the case of the halftone display, the limit value (%) of the allowable change is small. This is because the image is halftone, and even a small change is easily recognized visually.
[1305]
For example, if the number of pixel rows of the panel is 200, OEV2 control is performed at 50/200 Duty or less (1/200 or more and 50/200 or less), and duty ratio control is performed for a period of 1H or less. When changing from 1/200 Duty to 1/200 Duty, the difference between 1/200 Duty and 2/200 Duty is 1/200, which is a 100% change. This change is completely visually recognized as flicker. Therefore, OEV2 control (see FIG. 175 and the like) is performed to control the current supply to the EL element 15 in a period of 1H (one horizontal scanning period) or less. Although the duty ratio control is performed in the 1H period or less (within the 1H period), the present invention is not limited to this. The non-display area 52 is continuous as can be seen in FIG. That is, control such as a 10.5H period is also within the scope of the present invention. That is, the present invention is not limited to the 1H period (a decimal part is generated) and performs the duty ratio drive.
[1306]
When changing from 40/200 Duty to 41/200 Duty, the difference between 40/200 Duty and 41/200 Duty is 1/200, which is (1/200) / (40/200), a change of 2.5%. Whether this change is visually recognized as flicker or not is highly likely to depend on the screen luminance 50. However, since 40/200 Duty is a halftone display, it is visually sensitive. Therefore, it is desirable to perform the OEV2 control (see FIG. 175 and the like) and control the current supply to the EL element 15 in a period of 1H (one horizontal scanning period) or less.
[1307]
As described above, the driving method and the display device of the present invention include a configuration in which the current value flowing to the EL element 15 in the pixel 16 (corresponding to the capacitor 19 in FIG. 1), the driving transistor 11a, and the light emitting element (EL). The display panel has a configuration that can turn on and off a current path (for example, the element 15) (corresponding to the pixel configuration in FIGS. 1, 43, 113, 114, and 117) and displays at least a display image. 19 is generated in the state (the screen 50 may be a display area 53 (Duty1 / 1 may be used depending on the brightness of the image), and the duty ratio drive (at least a part of the screen 50). Is a non-display area 53), the driving method or driving state is not more than a predetermined duty ratio, and is limited to one horizontal scanning period (1H period) or 1H period unit. By controlling the current applied to the element 15, and performs brightness control of the display screen 50. The control is carried out by OEV2 control (see Figure 175 and the description thereof with regard OEV2).
[1308]
The predetermined duty ratio for performing the duty ratio control other than the 1H unit is performed when the duty ratio is equal to or less than 1/4 Duty. Conversely, when the duty ratio is equal to or higher than the predetermined duty ratio, the duty ratio control is performed in 1H units. Alternatively, the OEV2 control is not performed. The duty ratio control other than the 1H period is performed when the change of one step changes by 1/20 (5%) or more after the change before the change. More preferably, it is desirable to perform OEV2 control even with a change of 1/50 (2%) or less and to perform minute duty ratio drive control. Alternatively, the processing is performed at a luminance of 1/4 or less of the maximum luminance of the white raster.
[1309]
According to the duty ratio control drive of the present invention, as shown in FIG. 79, if the number of gradations expressed on the EL display panel is 64, the display luminance (nt) of the display screen 50 is any luminance. However, 64 gradation display is maintained. For example, even when the number of pixel rows is 220 and only one pixel row is in the display area 53 (display state) (duty ratio 1/220), 64-gradation display can be realized. This is because an image is sequentially written in each pixel row by the program current Iw of the source driver circuit 14, and an image of one pixel row is sequentially displayed by the gate signal line 17b.
[1310]
Of course, even when all of the 220 pixel rows are in the display area 53 (display state) (Duty ratio 220/220 = Duty ratio 1/1), 64-gradation display can be realized. This is because an image is sequentially written to the pixel rows by the program current Iw of the source driver circuit 14, and all the pixel rows are simultaneously image-displayed by the gate signal line 17b. Further, even when only 20 pixel rows are in the display area 53 (display state) (Duty20 / 220 = Duty1 / 11), 64 gradation display can be realized. This is because an image is sequentially written in each pixel row by the program current Iw of the source driver circuit 14, and the 20 pixel rows are sequentially scanned and image-displayed by the gate signal line 17b.
[1311]
Since the duty ratio control drive of the present invention is control of the lighting time of the EL element 15, the brightness of the screen 50 with respect to the duty ratio has a linear relationship. Therefore, it is very easy to control the brightness of the image, the signal processing circuit is simple, and the cost can be reduced. As shown in FIG. 77, the RGB reference currents are adjusted to achieve white balance. In the duty ratio control, the white balance is maintained at any gradation and the brightness of the screen 50 in order to simultaneously control the brightness of R, G, and B.
[1312]
In the duty ratio control, the luminance of the screen 50 is changed by changing the area of the display area 53 with respect to the display screen 50. Naturally, the current flowing through the EL display panel changes almost in proportion to the display area 53. Accordingly, the total current consumption flowing through the EL elements 15 on the display screen 50 can be calculated by calculating the sum of the video data. Since the anode voltage Vdd of the EL element 15 is a DC voltage and is a fixed value, if the total current consumption can be calculated, the total power consumption can be calculated in real time according to the image data. When it is predicted that the calculated total power consumption exceeds the specified maximum power, the reference current in FIG. 77 may be adjusted by an adjustment circuit such as an electronic regulator, and the RGB reference current may be suppressed and controlled.
[1313]
Also, a predetermined luminance in the white raster display is set, and at this time, the duty ratio is set to be the minimum. For example, the duty ratio is set to 1/8. For a natural image, the duty ratio is increased. The maximum duty is 1/1. For example, a natural image in which an image is displayed only in 1/100 of the screen 50 is defined as Duty 1/1. The duty ratio of 1/1 to １ ／ is smoothly changed in the display state of the natural image on the screen 50.
[1314]
As described above, in one embodiment, the duty ratio is 1/8 in white raster display (in a natural image, all pixels are lit 100%), and 1/100 pixels of the screen 50 are lit. The state is set to Duty ratio 1/1. The approximate power consumption can be calculated by the number of pixels × the ratio of the number of lit pixels × the duty ratio.
[1315]
Assuming that the number of pixels is 100 for ease of explanation, the power consumption in white raster display is 100 × 1 (100%) × duty ratio 比 = 80. On the other hand, the power consumption of the natural image in which 1/100 is turned on is 100 × (1/100) (1%) × Duty ratio 1/1 = 1. The duty ratio is controlled smoothly so that flicker does not occur according to the number of lit pixels of the image (actually, the total current of the lit pixels = the sum of the program current of one frame). Is done.
As described above, the power consumption ratio of the white raster is 80, and the power consumption ratio of the natural image in which 1/100 is lit is 1. Therefore, the maximum current can be suppressed by setting the predetermined luminance in the white raster display and setting this time so that the duty ratio is minimized.
[1316]
In the present invention, the sum of the program currents for one screen is S, the duty ratio is D, and the drive control is performed by S × D. Also, the sum of the program currents in the white raster display is Sw, the maximum Duty ratio is Dmax (usually, the duty ratio 1/1 is the maximum), the minimum Duty ratio is Dmin, and any natural A driving method for maintaining a relationship of Sw × Dmin> = Ss × Dmax when a total sum of program currents in an image is Ss, and a display device for realizing the driving method.
[1317]
Note that the maximum duty ratio is 1/1. It is preferable that the minimum is set to a duty ratio of 1/16 or more. That is, the duty ratio is set to ８ or more and 1/1 or less. Needless to say, the use of 1/1 is not restricted. Preferably, the minimum duty ratio is 1/10 or more. This is because if the duty ratio is too small, the occurrence of flicker is conspicuous, and the change in screen luminance due to the image content becomes too large, making it difficult to see the image.
[1318]
As described above, the program current is proportional to the video data. Therefore, the sum of the program currents is synonymous with the sum of the program currents. Although the sum of the program currents in one frame (one field) period is calculated, the present invention is not limited to this. Pixels to which the program current is added at a predetermined interval or a predetermined period in one frame (one field) are described. May be sampled to obtain the sum of program currents (video data). Further, the total data before and after the frame (field) to be controlled may be used, or the duty ratio control may be performed using the total data estimated or predicted.
[1319]
In the above description, the duty ratio is controlled by the duty ratio D. However, the duty ratio is a predetermined period (usually one field or one frame. That is, generally, a period at which image data of an arbitrary pixel is rewritten) Or the lighting time of the EL element 15. That is, the duty ratio 1/8 means that the EL element 15 is lit during a 1/8 period (1F / 8) of one frame.
Therefore, the duty ratio can be read as Duty ratio = Ta / Tf, where Tf is the cycle time in which the pixel 16 is rewritten and Ta is the lighting period Ta of the pixel.
[1320]
Note that the cycle time at which the pixel 16 is rewritten is defined as Tf, and Tf is used as a reference. However, the invention is not limited to this. The duty ratio control drive of the present invention does not need to complete the operation in one frame or one field. That is, the duty ratio control may be performed using several fields or several frame periods as one cycle (see FIG. 104 and the like). Therefore, Tf is not limited to the cycle of rewriting pixels, but may be one frame or one field or more. For example, when the lighting period Ta is different for each field or frame, the repetition period (period) may be Tf, and the total lighting period Ta of this period may be employed. That is, the average lighting time of several fields or several frame periods may be set to Ta. The same applies to the duty ratio. When the duty differs for each frame (field), the average duty ratio of a plurality of frames (fields) may be calculated and used.
[1321]
Therefore, the sum of the program currents in white raster display is Sw, the sum of the program currents in an arbitrary natural image is Ss, the minimum lighting period is Tas, and the maximum lighting period is Tam (usually Tam = Tf). And Tam / Tf = 1), a driving method for maintaining a relationship of Sw × (Tas / Tf) >> = Ss × (Tam / Tf) and a display device realizing the driving method.
[1322]
As a method of controlling the brightness of the screen 50, there is a configuration described with reference to FIG. 77 and the like.
In other words, the screen brightness 50 is changed by adjusting the reference current to change the current flowing through the unit transistor 484 and adjusting the magnitude of the program current. The method of adjusting the reference current is described in FIG. 53 and the like.
[1323]
Reference numeral 491R in FIG. 77 denotes a regulator for adjusting the reference current of red (R). However, the expression “volume” is for ease of explanation, and is actually an electronic volume, and the reference current IaR of the R circuit can be linearly adjusted in 64 steps by a 6-bit digital signal from the outside. It is configured as follows. By adjusting the reference current IaR, the current flowing through the transistor 472a that forms a current mirror circuit with the transistor 471R can be changed linearly. Therefore, the current flowing through the transistor 472b of the transistor group 521a and the current passed to the transistor 472b changes, the transistor 473a of the transistor group 521b forming the current mirror circuit with the transistor 472b changes, and the transistor 473b of the current passed to the transistor 473a changes. Changes. Accordingly, since the drive current (unit current) of the unit transistor 484 changes, the program current can be changed. The same applies to the G reference current IaG and the B reference current IaB.
[1324]
FIG. 77 shows three-stage transistor connection of parent and offspring, but the present invention is not limited to this. For example, it goes without saying that the present invention can be applied to a single-stage configuration in which a circuit for generating a reference current and a unit transistor 484 are directly connected as shown in FIGS. That is, the present invention has a circuit configuration in which the program current or the program voltage can be changed by one reference current or the reference voltage, and is a method of changing the brightness of the screen 50 by the reference current or the reference voltage.
As shown in FIG. 77, the (electronic) volume 491 is formed in each of red (R), green (G), and B (blue) circuits. Therefore, by adjusting the volumes 491R, 491G, and 491B, the current of the unit transistor 484 connected to each can be changed (controlled or adjusted). Therefore, white (W) adjustment can be easily performed by adjusting the RGB ratio. Of course, if the RGB reference currents (the currents flowing through the transistors 472R, 472G, 472B) are adjusted in advance at the time of shipment, an electronic regulator that can change the RGB electronic regulators (491R, 491G, 491B) at once can be provided separately. Thus, white (W) balance adjustment can be performed. For example, in FIG. 169 and FIG. 170, the value of the resistor R1 is adjusted so that white balance can be obtained for each of the RGB circuits. In this state, if the switch S of the electronic volume 451 in FIGS. 169 and 170 is switched to the same RGB, the screen brightness can be adjusted while maintaining the white balance.
[1325]
As described above, the reference current driving method of the present invention adjusts the RGB reference current values so that white balance can be obtained. With this state as the center, the RGB reference currents are adjusted at the same ratio. Since the adjustment is performed at the same ratio, the white balance is maintained.
[1326]
As described above, by adjusting the electronic regulator 491, the program current can be changed linearly. For ease of explanation, the pixel configuration shown in FIG. 1 will be described as an example, but the present invention is not limited to this, and it goes without saying that another pixel configuration may be used.
[1327]
By controlling the reference current as shown or described in FIG. 77, the program current can be linearly adjusted. This is because the output current of one unit transistor 484 changes. When the output current of the unit transistor 484 changes, the program current Iw also changes. The larger the current programmed in the capacitor 19 of the pixel (actually, a voltage corresponding to the program current), the larger the current flowing in the EL element 15. The current flowing through the EL element 15 and the light emission luminance are linearly proportional. Therefore, the light emission luminance of the EL element 15 can be changed linearly by changing the reference current.
[1328]
In the present invention, the control of the screen brightness and the like is performed using at least one of the reference current control method described in FIG. 77 and the duty ratio control method described in FIG. 78. It is preferable to carry out the combination of the methods shown in FIGS. 77 and 78.
[1329]
Hereinafter, the driving method using the method described with reference to FIGS. 77 and 78 will be described in more detail. One purpose of the driving method of the present invention is to limit the current consumption of the EL display panel to the upper limit. The luminance of the EL display panel is proportional to the current flowing through the EL element 15. Therefore, if the current flowing through the EL element 15 is increased, the luminance of the EL display panel can be increased steadily. The current consumed (= power consumption) also increases in proportion to the luminance.
[1330]
When used in a portable device, there is a limit to the capacity of a battery or the like. Further, the power supply circuit also increases in scale when the consumed current increases. Therefore, it is necessary to set a limit on the consumed current. Providing this limit (peak current suppression) is one object of the present invention.
[1331]
In addition, the display is improved by increasing the contrast of the image. The display is improved by displaying the image after the image conversion so as to have a sharp edge. It is the second object of the present invention to improve image display as described above. The present invention that achieves the above two objects (or one of them) will be referred to as AI driving.
[1332]
First, for ease of explanation, it is assumed that the source driver IC 14 of the present invention has a 64-gradation display. In order to realize AI driving, it is desirable to expand the gradation expression range. For ease of explanation, it is assumed that the source driver IC (circuit) 14 of the present invention displays 64 gradations and the image data has 256 gradations. The image data is subjected to gamma conversion so as to conform to the gamma characteristics of the EL display device. The gamma conversion is performed by expanding the input 256 gradations to 1024 gradations. The gamma-converted image data is subjected to an error diffusion process or a frame rate control (FRC) process so as to conform to the 64 gradations of the source driver IC 14, and is applied to the source driver IC 14.
[1333]
The FRC realizes high gradation display by superimposing image displays for each field. In the error diffusion processing, as an example, as shown in FIG. 99, the image data of the pixel A is distributed to 7/16 to the right, 3/16 to the lower left, 5/16 to the lower, and 1/16 to the lower right in the processing direction. Is the way. High gradation display can be realized by distributed processing. This is a kind of area gradation.
[1334]
For ease of illustration, FIGS. 80 and 81 will be described assuming that 64 gradation display is converted to 512 gradation. The conversion is performed by an error diffusion processing method or frame rate control (FRC). However, in FIG. 80, it may be interpreted that the brightness of the image is converted, rather than performing the gradation conversion.
[1335]
FIG. 80 illustrates the image conversion processing by the driving method of the present invention. In FIG. 80, the horizontal axis is the gradation (number). The larger the gradation (number), the brighter the luminance of the screen 50 is. Conversely, the smaller the gradation (number), the darker the image. The vertical axis is the frequency. The frequency indicates a histogram of the brightness of the pixels constituting the image. For example, A1 in FIG. 80A indicates that the image has the largest number of pixels having the luminance of 24 gradation levels.
[1336]
FIG. 80A shows an example in which the display brightness is changed while the number of gradations of the image is maintained. Assuming that A1 is an original image, the original image has an expression range of approximately 64 gradations.
A2 is an example in which the center of brightness is converted into 256 gradations while maintaining the number of gradation representations. A3 is also an example in which the center of brightness is converted into 448 gradations while maintaining the number of gradation representations. Such conversion can be achieved by adding data of a predetermined size to the image data for conversion.
[1337]
However, it is difficult to realize the gradation conversion of FIG. 80A by the driving method of the present invention. In the driving method of the present invention, the gradation conversion shown in FIG.
[1338]
FIG. 80B is an example in which the frequency distribution of the original image is enlarged. Assuming that B1 is an original image, the original image has an expression range of approximately 64 gradations. B2 is an example in which the gradation expression range is expanded to 256 gradations. The brightness of the screen becomes brighter, and the gradation expression range is expanded. B3 is an example in which the gradation expression range is further expanded to 512 gradations. The screen display brightness is further increased, and the gradation expression range is expanded.
[1339]
80 (b) can be easily realized by the driving method of the present invention. This can be realized by changing the reference current described with reference to FIG. In addition, this can be realized by changing (controlling) the duty ratio in FIG. Alternatively, it can be realized by combining the methods of FIGS. 77 and 78. The brightness control of the image is easy by the reference current control or the duty ratio control. For example, if the duty ratio is 1/4 and the display state is B2 in FIG. 80 (b), if the duty ratio is 1/16, the display state is B1 in FIG. 80 (b). Further, if the duty ratio is set to １ ／, the display state of B3 in FIG. 80B is obtained. The same applies to the case of the reference current control. By making the magnitude of the reference current twice or one-fourth, the image display of FIG. 80B can be performed.
[1340]
The horizontal axis in FIG. 80B is the number of gradations. The driving method of the present invention does not increase the number of gradations. The driving method of the present invention is characterized in that the number of gradations is maintained even when the display luminance changes as described with reference to FIG. That is, in FIG. 80B, it is assumed that the number of 64 gradations of B1 has been converted to 256 gradations of B2. However, the number of gradations of B2 is 64 gradations. One gradation range is expanded four times compared to B1. The conversion from B1 to B2 is nothing but dynamic conversion of image display. Therefore, high gradation display is equivalent. Therefore, high-quality display can be realized.
[1341]
Similarly, in FIG. 80 (b), it is assumed that the number of 64 gradations of B1 has been converted to 512 gradations of B3. However, the number of gradations of B3 is 64 gradations. One gradation range is expanded eight times compared to B1. The conversion from B1 to B3 is nothing but dynamic conversion of the image display.
[1342]
In FIG. 80A, the brightness of the screen 50 can be improved. However, the entire screen 50 becomes whitish (white floating). However, the increase in current consumption is relatively small (although the current consumption increases in proportion to the screen luminance). In (b) of FIG. 80, the brightness of the screen 50 can be improved and the display range of gradation is expanded, so that there is no deterioration in image quality. However, the increase in current consumption is large.
[1343]
Assuming that the number of gradations and the screen luminance are proportional and the original image has 64 gradations, the increase in the number of gradations (expansion of the dynamic range) = the increase in luminance. Therefore, power consumption (current consumption) increases. In order to solve this problem, the present invention combines one or both of the method of adjusting (controlling) the reference current with FIG. 77 and the method of controlling the duty ratio of FIG. 78.
[1344]
When the image data of one screen is entirely large, the sum of the image data becomes large.
For example, the white raster has 63 image data in the case of 64 gradation display, so the number of pixels of the screen 50 × 63 is the total of the image data. In a 1/100 white window display and a white display where the white display section has the maximum luminance, the number of pixels of the screen 50 × (1/100) × 63 is the total sum of the image data.
[1345]
In the present invention, a value that can predict the sum of the image data or the current consumption of the screen is obtained, and the duty ratio control or the reference current control is performed based on the sum or the value.
Although the sum of the image data is determined, the present invention is not limited to this. For example, an average level of one frame of image data may be obtained and used. In the case of an analog signal, an average level can be obtained by filtering the analog image signal with a capacitor. A DC level may be extracted from an analog video signal through a filter, and the DC level may be AD-converted to obtain a sum of image data. In this case, the image data can also be called an APL level.
Further, it is not necessary to add all the data of the image forming the screen 50, and 1 / W (W is a value larger than 1) of the screen 50 may be picked up and extracted, and the sum of the picked up data may be obtained. .
[1346]
In order to facilitate the explanation, the above case will be described assuming that the sum of the image data is obtained. The sum of image data often coincides with the determination of the APL level of an image. In addition, there is a means of digitally adding the sum of image data, but the above-described method of calculating the sum of digital and analog image data is hereinafter referred to as an APL level for ease of explanation.
[1347]
At the time of the white raster, the APL level is 63 (since it is the 63rd gradation, the data is represented by 63 because the image is 6 bits each for RGB) × the number of pixels (176 × RGB × for the QCIF panel) 220). Therefore, the APL level becomes maximum. However, since the currents consumed by the RGB EL elements 15 are different, it is preferable to calculate the image data separately for RGB.
[1348]
For this problem, an arithmetic circuit shown in FIG. 84 is used. In FIG. 84, there are 841 and 842 multipliers. 841 is a multiplier for weighting the light emission luminance. R, G, and B have different luminosity. The visibility in NTSC is R: G: B = 3: 6: 1. Therefore, the R multiplier 841R multiplies the R image data (Rdata) by three times. The G multiplier 841G multiplies the G image data (Gdata) by a factor of six. Also, the B multiplier 841B multiplies the B image data (Bdata) by one time.
[1349]
The luminous efficiency of the EL element 15 differs between RGB. Usually, the luminous efficiency of B is the worst.
Next, G is bad. R has the best luminous efficiency. Therefore, the luminous efficiency is weighted by the multiplier 842. The R multiplier 842R multiplies the R image data (Rdata) by the R light emission efficiency. The G multiplier 842G multiplies the G image data (Gdata) by the G light emission efficiency. The B multiplier 842B multiplies the B image data (Bdata) by the B light emission efficiency.
The results of multipliers 841 and 842 are added in adder 843 and accumulated in summing circuit 844. Based on the result of the sum circuit 87, the duty ratio control of FIG. 77 and the reference current control of FIG. 78 are performed.
[1350]
With the control as shown in FIG. 84, the duty ratio control and the reference current control for the luminance signal (Y signal) can be performed. However, when a luminance signal (Y signal) is obtained and duty control or the like is performed, a problem may occur. For example, a blue-back display. In the blue-back display, the current consumed by the EL panel is relatively large. However, the display brightness is low. This is because the visibility of blue (B) is low. Therefore, since the total sum (APL level) of the luminance signal (Y signal) is calculated to be small, the duty control becomes high. Therefore, flicker occurs.
[1351]
To solve this problem, the multiplier 841 may be used in a through state. This is because the sum (APL level) for the consumed current is obtained. It is desirable that the total (APL level) based on the luminance signal (Y signal) and the total (APL level) based on the current consumption be calculated to take the total APL level into consideration. The duty ratio control and the reference current control are performed according to the total APL level.
[1352]
Since the black raster is the 0th gradation in the case of 64 gradation display, the APL level is 0 and the minimum value. In the driving method shown in FIG. 80, power consumption (current consumption) is proportional to image data. In the image data, it is not necessary to count all the bits of the data constituting the screen 50. For example, when the image is represented by 6 bits, only the upper bits (MSB) may be counted. In this case, one count is performed when the number of gradations is 32 or more. Therefore, the APL level changes according to the image data constituting the screen 50.
[1353]
In the present invention, the reference current control shown in FIG. 78 or the duty ratio control shown in FIG. 77 is performed according to the magnitude of the obtained APL level.
In order to facilitate understanding, specific numerical values will be described. However, this is virtual, and it is actually necessary to determine control data and a control method by experiments and image evaluation.
[1354]
The maximum current that can flow in the EL panel is assumed to be 100 (mA). In the case of white raster display, the sum (APL level) is assumed to be 200 (no unit). When the APL level is 200, if it is applied to the panel as it is, 200 (mA) flows through the EL panel. When the APL level is 0, the current flowing through the EL panel is 0 (mA). When the APL level is 100, the duty ratio is set to 1/2.
[1355]
Therefore, when the APL is 100 or more, it is necessary to make the limit 100 (mA) or less. In the simplest case, when the APL level is 200, the duty is (１ ／) × (１ ／) = １ ／, and when the APL level is 100, the duty is １ ／. When the APL level is 100 or more and 200 or less, the duty is controlled so as to be between 1/4 and 1/2. The duty ratio of 1/4 to 1/2 can be realized by controlling the number of gate signal lines 17b selected simultaneously by the gate driver circuit 12b on the EL selection side.
[1356]
However, if the duty ratio control is performed in consideration of only the APL level, the luminance of the screen 50 changes according to the average luminance (APL) of the screen 50 according to the image, and flicker occurs. In order to solve this problem, the APL level to be obtained is held for a period of at least 2 frames, preferably for 10 frames, and more preferably for 60 frames or more, and is calculated in this period to determine the duty ratio by the duty ratio control by the APL level. calculate. Further, it is preferable to perform duty ratio control by extracting image features such as the maximum luminance (MAX), the minimum luminance (MIN), and the luminance distribution state (SGM) of the screen 50. Needless to say, the above items are also applied to the reference current control.
[1357]
It is also important to carry out black extension and white extension by extracting image features.
This may be performed in consideration of the maximum luminance (MAX), the minimum luminance (MIN), and the distribution state of the luminance (SGM). For example, in (a) of FIG. 81, the center data Kb of the image is distributed near 256 tones, and the high luminance portion Kc is distributed near 320 tones.
Further, the low-luminance portions Ka are distributed around 128 gradations.
[1358]
FIG. 81B shows an example in which black stretching and white stretching are performed on the image shown in FIG. However, it is not necessary to perform black stretching and white stretching simultaneously, and only one of them may be performed. Also, the central part of the image (Kb in FIG. 81 (a) may be moved to the low gradation part or the high gradation part. These appropriate movement information include the APL level, the maximum luminance (MAX), and the minimum luminance. (MIN) and luminance distribution state (SGM), but may be empirical because human visibility is affected, so that image evaluation and experiment are repeated. However, image processing such as black expansion or white expansion can be easily realized because the gamma curve can be obtained by calculation or from a look-up table, and the processing is performed as shown in FIG. As a result, the image becomes sticky and good image display can be realized.
[1359]
The brightness of the screen 50 is changed by the duty ratio control as shown in FIG. FIG. 82A shows a driving method in which the display area 53 is continuously changed. The luminance of the screen 50 of (a2) of FIG. 82 is brighter than the luminance of the screen 50 of (a1) of FIG. The brightest is the state of (an) in FIG. The drive by the duty ratio control shown in FIG. 82A is suitable for displaying a moving image.
[1360]
FIG. 82 (b) shows a driving method in which the display area 53 is divided and changed. In (b1) of FIG. 82, display areas 53 are generated at two places on the screen 50 as an example. In FIG. 82 (b2), as in (b1) of FIG. 82, the display area 53 is generated in two places on the screen 50, but the number of pixel rows in the display area 53 is increased in one of the two places. (One is a display area 53 for one pixel row, and the other is a display area 53 for two pixel rows). In FIG. 82 (b3), as in (b2) of FIG. 82, the display area 53 is generated at two places on the screen 50, but the pixel rows of the display area 53 are increased at one of the two places. (In both cases, two pixel rows are the display area 53). As described above, the duty ratio control may be performed by dispersing the display area 53. Generally, FIG. 82B is suitable for displaying a still image.
[1361]
In FIG. 82B, the variance of the display area 53 is two variances. However, this is to make the drawing easier. In practice, the variance of the display area 53 is three or more.
[1362]
FIG. 83 is a block diagram of the drive circuit of the present invention. Hereinafter, the drive circuit of the present invention will be described. FIG. 83 is configured so that a Y / UV video signal and a composite (COMP) video signal can be input from outside. Which of the video signals is input is selected by the switch circuit 831.
[1363]
The video signal selected by the switch circuit 831 is decoded and A / D converted by a decoder and an A / D circuit, and is converted into digital RGB image data. Each of the RGB image data is 8 bits. The RGB image data is gamma-processed by a gamma circuit 834. At the same time, a luminance (Y) signal is obtained. The RGB image data is converted into 10-bit image data by gamma processing.
[1364]
After the gamma processing, the image data is subjected to FRC processing or error diffusion processing by the processing circuit 835. RGB image data is converted into 6 bits by FRC processing or error diffusion processing. This image data is subjected to AI processing or peak current processing by an AI processing circuit 836. In addition, a moving image detection circuit 837 detects a moving image. At the same time, the color management circuit 838 performs a color management process.
The processing results of the AI processing circuit 836, the moving image detection circuit 837, and the color management circuit 838 are sent to the arithmetic circuit 839, where they are converted into control arithmetic, duty ratio control, and reference current control data by the arithmetic processing circuit 839. Are transmitted as control data to the source driver circuit 14 and the gate driver circuit 12.
[1365]
The duty ratio control data is sent to the gate driver circuit 12b, and the duty ratio control is performed. On the other hand, the reference current control data is sent to the source driver circuit 14, and the reference current control is performed. The gamma-corrected image data subjected to FRC or error diffusion processing is also sent to the source driver circuit 14.
[1366]
The image data conversion of FIG. 81B needs to be performed by gamma processing of the gamma circuit 834. The gamma circuit 834 performs gradation conversion using a multi-point broken gamma curve. Image data of 256 gradations is converted to 1024 gradations by a multipoint broken gamma curve.
[1368]
Although the gamma circuit 834 performs gamma conversion using a multipoint broken gamma curve, the invention is not limited to this. As shown in FIG. 85, gamma conversion may be performed using a one-point broken gamma curve. Since the scale of the hardware constituting the gamma curve is small, the cost of the control IC can be reduced.
[1368]
In FIG. 85, a represents polygonal line gamma conversion at the 32nd gradation. b is a polygonal line gamma conversion at the 64th gradation. c is a polygonal line gamma conversion at the 96th gradation.
d is polygonal line gamma conversion at the 128th gradation. When the image data is concentrated on high gradations, the gamma curve d in FIG. 85 is selected to increase the number of high gradations. When the image data is concentrated on low gradations, the gamma curve of FIG. 85A is selected in order to increase the number of low gradations. If the distribution of the image data is dispersed, a gamma curve such as b or c in FIG. 85 is selected. In the above embodiment, the gamma curve is selected. However, in practice, the gamma curve is not selected because it is generated by calculation.
[1369]
The selection of the gamma curve is performed in consideration of the APL level, the maximum luminance (MAX), the minimum luminance (MIN), and the luminance distribution state (SGM). In addition, the duty ratio control and the reference current control are performed in consideration of the duty ratio control and the reference current control.
[1370]
FIG. 86 shows an example of a multi-point broken gamma curve. When the image data is concentrated on the high gradation, the gamma curve n in FIG. 85 is selected in order to increase the number of gradations in the high gradation. When the image data is concentrated on low gradations, the gamma curve of FIG. 85A is selected in order to increase the number of low gradations. If the distribution of the image data is scattered, the gamma curve from b to n-1 in FIG. 85 is selected. The selection of the gamma curve is performed in consideration of the APL level, the maximum luminance (MAX), the minimum luminance (MIN), and the luminance distribution state (SGM). In addition, the duty ratio control and the reference current control are performed in consideration of the duty ratio control and the reference current control.
[1371]
It is also effective to change the selected gamma curve according to the environment used by the display panel (display device). In particular, with an EL display panel, good image display can be realized indoors, but a low gradation portion cannot be seen outdoors. The EL display panel is for self light emission. Therefore, the gamma curve may be changed as shown in FIG. Gamma curve a is an indoor gamma curve. Gamma curve b is an outdoor gamma curve. Switching between the gamma curves a and b is performed by the user operating the switch. Alternatively, the brightness of the external light may be detected by a photo sensor and automatically switched. Although the gamma curve is switched, the present invention is not limited to this. It goes without saying that a gamma curve may be generated by calculation. In the case of outdoors, the low gradation display portion cannot be seen because the outside light is bright. Therefore, it is effective to select the gamma curve b that crushes the low gradation part.
[1372]
Outdoors, it is also effective to generate a gamma curve as shown in FIG. In the gamma curve a, the output gradation is set to 0 up to the 128th gradation. Gamma conversion is performed from 128 tones. As described above, the power consumption can be reduced by performing gamma conversion so that the low gradation part is not displayed at all. Also, gamma conversion may be performed as in a gamma curve b in FIG. In the gamma curve of FIG. 88, the output gradation is set to 0 up to the 128th gradation. For 128 or more, the output gradation is 512 or more. In the gamma curve b of FIG. 88, a high gradation portion is displayed, and by reducing the number of output gradations, there is an effect of making the image display easily visible even outdoors.
[1373]
In the driving method of the present invention, the image luminance is controlled by the duty ratio control and the reference current control, and the dynamic range is expanded. Further, a high contrast display is realized.
[1374]
In a liquid crystal display panel, white display and black display are determined by the transmittance from the backlight. Even when the non-display area 52 is generated on the screen 50 as in the duty ratio driving of the present invention, the transmittance in black display is constant. Conversely, by generating the non-display area 52, the white display luminance in one frame period is reduced, so that the display contrast is reduced.
[1375]
The EL display panel has a black display in which the current flowing through the EL element 15 is zero.
Therefore, even when the non-display area 52 is generated on the screen 50 as in the duty ratio driving of the present invention, the luminance of black display is zero. When the area of the non-display area 52 is increased, the white display luminance decreases. However, since the luminance of black display is 0, the contrast is infinite. Therefore, the duty ratio driving is a driving method most suitable for the EL display panel. The same applies to the reference current control. Even when the magnitude of the reference current is changed, the luminance of black display is zero. When the reference current is increased, the white display luminance increases. Therefore, good image display can be realized even in the reference current control.
[1376]
In the duty ratio control, the number of gradations is maintained in the entire gradation range, and the white balance is maintained in the entire gradation range. Further, the change in the brightness of the screen 50 can be changed by nearly 10 times by the duty ratio control. Further, since the change has a linear relationship with the duty ratio, control is easy. However, since the duty ratio control is N-times pulse driving, the magnitude of the current flowing through the EL element 15 is large, and the magnitude of the current constantly flowing through the EL element is large regardless of the luminance of the screen 50. There is a problem that the EL element 15 is easily deteriorated.
[1377]
The reference current control is to increase the reference current amount when increasing the screen luminance 50. Therefore, only when the screen 50 is high, the current flowing through the EL element 15 increases. Therefore, the EL element 15 does not easily deteriorate. The problem is that maintaining the white balance when the reference current is changed tends to be difficult.
[1378]
In the present invention, both the reference current control and the duty ratio control are used. When the screen 50 is close to white raster display, the reference current is fixed at a constant value, and only the duty ratio is controlled to change the display brightness and the like. When the screen 50 is close to black raster display, the duty ratio is fixed at a constant value, and only the reference current is controlled to change the display brightness and the like.
[1379]
The duty ratio control is performed when the data sum / maximum value is in the range of 1/10 to 1/1. More preferably, the processing is performed in a range where the sum of data / maximum value is 1/100 or more and 1/1. Further, the change in the magnification of the reference current (change in the output current of the unit transistor 484) is performed in a range where the data sum / maximum value is 1/10 or more and 1/1000. It is more preferable that the sum of data / maximum value is in the range of 1/100 to 1/2000. It is preferable that the reference current control and the duty ratio control do not overlap. In FIG. 89, when the data sum / maximum value is 1/100 or less, the magnification of the reference current is changed, and when it is 1/100 or more, the duty ratio is changed. Therefore, there is no overlap.
[1380]
Here, for ease of explanation, the maximum duty ratio is set to 1/1, and the minimum is set to 1/8. It is assumed that the reference current is changed from 1 to 3 times. The data sum means the sum of the data on the screen 50, and the maximum value (of the data sum) is the sum of the image data in the white raster display at the maximum luminance. Needless to say, it is not necessary to use the duty ratio up to 1/1. The duty ratio 1/1 is described as the maximum value. In the driving method of the present invention, it goes without saying that the maximum duty ratio may be set to 210/220 or the like. Reference numeral 220 indicates the number of pixel rows of the QCIF + display panel.
[1381]
Note that the maximum duty ratio is preferably set to 1/1, and the minimum is preferably set to within 1/16. More preferably, the duty ratio should be within 1/10. This is because generation of flicker can be suppressed. The change range of the reference current is preferably within four times. More preferably, it is within 2.5 times. If the multiple of the reference current is too large, the linearity of the reference current generation circuit is lost, and a white balance shift occurs.
[1382]
The data sum / the maximum value of the data sum = 1/100 is, for example, 1/100 white window display. In the case of a natural image, it means that the data sum of pixels to be displayed can be converted to 1/100 of white raster display. Therefore, the sum of data / maximum value of 1 white luminescent spot per 100 pixels is 1/100.
[1383]
In the following description, the maximum value is the added value of the image data of the white raster, but this is for ease of description. The maximum value is the maximum value generated in image data addition processing or APL processing. Therefore, the data sum / maximum value is a ratio to the maximum value of the image data of the screen to be processed.
[1384]
It should be noted that the data sum may be calculated based on the current consumption or the luminance. Here, for the sake of simplicity, the description will be made assuming that the addition is luminance (image data). Generally, the method of adding the luminance (image data) is easy, and the hardware scale of the controller IC can be reduced. Further, it is preferable because flicker does not occur due to the duty ratio control and the dynamic range can be widened.
[1385]
FIG. 89 shows an example in which the reference current control and the duty ratio control of the present invention are implemented. In FIG. 89, when the data sum / maximum value is 1/100 or less, the magnification of the reference current is changed up to three times. The duty ratio is changed from 1/1 to 1/8 at 1/100 or more.
Therefore, since the data sum / maximum value is 1/1 to 1/10000, the duty ratio control is 8 times, and the reference current control is 3 times, the change is 8 × 3 = 24 times. Since both the reference current control and the duty ratio control change the screen luminance, a dynamic range of 24 times is realized.
[1386]
When the data sum / maximum value is 1/1, the duty ratio is 1/8. Therefore, the display luminance is 1/8 of the maximum value. Since the data sum / maximum value is 1, white raster display is performed. That is, in white raster display, the display luminance is reduced to 1/8 of the maximum. 1/8 of the screen 50 is the image display area 53, and the non-display area 52 occupies 7/8. In an image in which the data sum / maximum value is close to 1/1, most of the pixels 16 are in a high gradation display. When represented by a histogram, the majority of data is distributed in the high gradation area of the histogram. In this image display, the image is in an overexposed state and there is no sharp feeling. Therefore, a gamma curve of n or close to n in FIG. 86 or the like is selected.
[1388]
When the data sum / maximum value is 1/100, the duty ratio is 1/1. The entire screen 50 is a display area 53. Therefore, the N-fold pulse driving is not performed.
The emission luminance of the EL element 15 becomes the display luminance of the screen 50 as it is. Most of the images are displayed in black, and the image is partially displayed. In terms of an image, an image display with a data sum / maximum value of 1/100 is an image in which the moon appears in a dark night sky. Making the duty ratio 1/1 in this image means that the moon portion is displayed with a luminance eight times the luminance of the white raster. Therefore, image display with a wide dynamic range can be realized. Since the image is displayed in the area of 1/100, even if the luminance of the area of 1/100 is increased eight times, the increase in power consumption is slight.
[1388]
In the image in which the data sum / maximum value is close to 1/100, most of the pixels 16 are in low gradation display. If represented by a histogram, the majority of data is distributed in the low gradation area of the histogram. In this image display, the image is in a blackened state and there is no sharp feeling. Therefore, a gamma curve b or a curve close to b in FIG. 86 is selected.
[1389]
As described above, the driving method of the present invention is a driving method that increases the x multiplier of gamma as the duty ratio increases. This is a driving method that reduces the x multiplier of gamma as the duty ratio decreases.
[1390]
In FIG. 89, when the data sum / maximum value is 1/100 or less, the magnification of the reference current is changed up to three times. When the data sum / maximum value is 1/100, the duty ratio is 1/1, and the screen luminance is increased by the duty ratio. As the data sum / maximum value becomes smaller than 1/100, the magnification of the reference current is increased. Therefore, the emitting pixel 16 emits light with higher luminance. For example, a data sum / maximum value of 1/1000 is an image in which stars appear in a dark night sky when expressed in a mage. Setting the duty ratio to 1/1 in this image means that the star portion is displayed at a luminance of 8 × 2 = 16 times the luminance of the white raster. Therefore, image display with a wide dynamic range can be realized. Since an image is displayed in an area of 1/1000, even if the luminance of the area of 1/1000 is increased 16 times, the increase in power consumption is slight.
[1391]
Control of the reference current is that it is difficult to maintain white balance. However, in an image in which stars appear in a dark night sky, even if the white balance is shifted, the white balance shift is not visually recognized. From the above, the present invention is an appropriate driving method for performing the reference current control in a range where the data sum / maximum value is very small.
[1392]
When the data sum / maximum value is 1/1000, the duty ratio is 1/1. The entire screen 50 is a display area 53. Therefore, the N-fold pulse driving is not performed. The emission luminance of the EL element 15 becomes the display luminance of the screen 50 as it is. Most of the images are displayed in black, and the image is partially displayed.
[1393]
In the image in which the data sum / maximum value is close to 1/1000, most of the pixels 16 are in low gradation display. If represented by a histogram, the majority of data is distributed in the low gradation area of the histogram. In this image display, the image is in a blackened state and there is no sharp feeling. Therefore, a gamma curve b or a curve close to b in FIG. 86 is selected.
[1394]
As described above, the driving method of the present invention is a driving method in which the x multiplier of gamma increases as the reference current decreases. This is a driving method in which the x multiplier of gamma is reduced as the reference current increases.
[1395]
In FIG. 89, the change in the reference current and the change in the duty ratio control are shown linearly. However, the present invention is not limited to this. As shown in FIG. 90, the magnification control and the duty ratio control of the reference current may be curved. In FIGS. 89 and 90, since the sum of data / maximum value on the horizontal axis is logarithmic, it is natural that the reference current control and the duty ratio control have curved lines. The relationship between the data sum / maximum value and the reference current magnification, and the relationship between the data sum / maximum value and the duty ratio control are preferably set according to the content of the image data, the image display state, and the external environment.
[1396]
FIGS. 89 and 90 show an embodiment in which the RGB duty ratio control and the reference current control are the same. The present invention is not limited to this. As shown in FIG. 91, the gradient of the reference current magnification may be changed in RGB. In FIG. 91, the gradient of the change in the reference current magnification for blue (B) is maximized, the gradient of the change in the reference current magnification for green (G) is increased next, and the gradient of the change in the reference current magnification for red (R) is increased. The inclination is minimized. When the reference current increases, the current flowing through the EL element 15 also increases. EL elements have different luminous efficiencies for RGB. When the current flowing through the EL element 15 increases, the luminous efficiency with respect to the applied current deteriorates. In particular, the tendency is remarkable in B. Therefore, white balance cannot be obtained unless the reference current amount is adjusted by RGB. Therefore, as shown in FIG. 91, when the reference current magnification is increased (the region where the current flowing through each of the RGB EL elements 15 is large), it is effective to make the RGB reference current magnifications different so that the white balance can be maintained. is there. The relationship between the data sum / maximum value and the reference current magnification, and the relationship between the data sum / maximum value and the duty ratio control are preferably set according to the content of the image data, the image display state, and the external environment.
[1397]
FIG. 91 shows an embodiment in which the reference current magnification is different between RGB. In FIG. 92, the duty ratio control is also different. The sum of data / maximum value is equal to or greater than 1/100 for B and G, and the slope of R is reduced. Also, G and R have a duty ratio of 1/1 at 1/100 or less, while B has a duty ratio of 1/2 at 1/100 or less. The above driving method can be implemented by the driving method described with reference to FIGS. By driving as described above, RGB white balance adjustment can be optimized. The relationship between the data sum / maximum value and the reference current magnification, and the relationship between the data sum / maximum value and the duty ratio control are preferably set according to the content of the image data, the image display state, and the external environment. In addition, it is preferable that the user can freely set or adjust.
[1398]
FIGS. 89 to 91 show a method in which the reference current magnification and the duty ratio are changed with the data sum / maximum value being 1/100 as an example. The reference current magnification and the duty ratio are changed at a fixed value of the data sum / maximum value so that the area where the reference current magnification changes and the area where the duty ratio changes do not overlap. With this configuration, it is easy to maintain the white balance. That is, the duty ratio is changed when the data sum / maximum value is 1/100 or more, and the reference current is changed when the data sum / maximum value is 1/100 or less. The region where the reference current magnification changes and the region where the duty ratio changes do not overlap. This method is a characteristic method of the present invention.
[1399]
Although the duty ratio is changed when the data sum / maximum value is 1/100 or more, and the reference current is changed when the data sum / maximum value is 1/100 or less, the reverse relationship may be used. That is, the duty ratio may be changed when the data sum / maximum value is 1/100 or less, and the reference current may be changed when the data sum / maximum value is 1/100 or more. Further, the duty ratio is changed when the data sum / maximum value is 1/10 or more, the reference current is changed when the data sum / maximum value is 1/100 or less, and the data sum / maximum value is 1/100 or more and 1/10 or less. Then, the reference current magnification and the duty ratio may be set to constant values.
[1400]
In some cases, the present invention is not limited to the above method. As shown in FIG. 93, the duty ratio may be changed when the data sum / maximum value is 1/100 or more, and the reference current of B may be changed when the data sum / maximum value is 1/10 or less. The change of the reference current change of B and the duty ratio of RGB overlap.
[1401]
When a bright screen and a dark screen are alternately repeated at a high speed, flicker occurs when the duty ratio is changed according to the change. Therefore, when changing from a certain duty ratio to another duty ratio, it is preferable to change the duty ratio by providing hysteresis (time delay). For example, assuming that the hysteresis period is 1 sec, the previous duty ratio is maintained even if the screen luminance is bright and dark several times within the 1 sec period. That is, the duty ratio does not change.
[1402]
This hysteresis (time delay) time is called a Wait time. Further, the duty ratio before the change is called a duty ratio before the change, and the duty ratio after the change is called a duty ratio after the change.
[1403]
When the duty ratio before change changes from a small state to another duty ratio, flicker due to the change is likely to occur. The state where the duty ratio before the change is small is a state where the data sum of the screen 50 is small or a state where the screen 50 has many black display portions. Therefore, it is considered that the screen 50 is a halftone display and the visibility is high. Also, in a region where the duty ratio is small, the difference from the change duty tends to be large. Of course, when the difference between the duty ratios becomes large, control is performed using the OEV2 terminal. However, there is a limit to OEV2 control. From the above, when the duty ratio before the change is small, it is necessary to lengthen the wait time.
[1404]
When the duty ratio before the change changes from a large state to another duty ratio, flicker due to the change hardly occurs. The state where the duty ratio before the change is large is a state where the data sum of the screen 50 is large or a state where the screen 50 has many white display portions. Therefore, it is considered that the entire screen 50 is displayed in white and the visibility is low. From the above, when the duty ratio before change is large, the wait time may be short.
[1405]
The above relationship is shown in FIG. The horizontal axis is the duty ratio before the change. The vertical axis is the Wait time (second). When the duty ratio is 1/16 or less, the wait time is extended to 3 seconds (sec). When the duty ratio is 1/16 or more and the duty ratio is 8/16 (= １ ／), the wait time is changed from 3 seconds to 2 seconds in accordance with the duty ratio. At a duty ratio of 8/16 or more and a duty ratio of 16/16 = 1/1, the duty is changed from 2 seconds to 0 seconds in accordance with the duty ratio.
[1406]
As described above, the duty ratio control of the present invention changes the wait time according to the duty ratio. When the duty ratio is small, the wait time is lengthened, and when the duty ratio is large, the wait time is shortened. That is, in the driving method in which at least the duty ratio is variable, the duty ratio before the first change is smaller than the duty ratio before the second change, and the Wait time of the first duty ratio before the change is equal to the second time. It is characterized in that it is set longer than the Wait time of the duty ratio before the change.
[1407]
In the above embodiment, the Wait time is controlled or specified based on the duty ratio before the change. However, the difference between the duty ratio before the change and the duty ratio after the change is small. Therefore, the duty ratio before the change may be read as the duty ratio after the change in the above-described embodiment.
[1408]
In the above embodiments, the description has been made based on the duty ratio before the change and the duty ratio after the change. When the difference between the duty ratio before the change and the duty ratio after the change is large, it goes without saying that it is necessary to increase the wait time. When the difference between the duty ratios is large, it is needless to say that it is preferable to change the duty ratio after the change via the duty ratio in the intermediate state.
[1409]
The duty ratio control method of the present invention is a driving method in which the Wait time is lengthened when the difference between the duty ratio before change and the duty ratio after change is large. That is, this is a driving method in which the Wait time is changed according to the difference in the duty ratio. Also, this is a driving method in which the Wait time is extended when the difference in the duty ratio is large.
[1410]
The duty ratio method according to the present invention is a driving method characterized in that when the difference between the duty ratios is large, the duty ratio is changed to the changed duty ratio via the duty ratio in an intermediate state.
[1411]
In the embodiment of FIG. 94, it has been described that the Wait time for the duty ratio is the same for R (red), G (green), and B (blue). However, in the present invention, it is needless to say that the Wait time may be changed in RGB as shown in FIG. This is because the visibility is different for RGB. By setting the Wait time in accordance with the visibility, a better image display can be realized.
[1412]
The data sum / the maximum value of the data sum = 1/100 is, for example, 1/100 white window display. In the case of a natural image, it means that the data sum of pixels to be displayed can be converted to 1/100 of white raster display. Therefore, the sum of data / maximum value of 1 white luminescent spot per 100 pixels is 1/100.
[1413]
In the following description, the maximum value is the added value of the image data of the white raster, but this is for ease of description. The maximum value is the maximum value generated in image data addition processing or APL processing. Therefore, the data sum / maximum value is a ratio to the maximum value of the image data of the screen to be processed.
[1414]
However, the data sum does not require that data of one screen be accurately added. A value obtained by estimating (predicting) the added value of one screen from the added value of the data of the pixels obtained by sampling one screen may be used. The same applies to the maximum value. Also, a predicted value or an estimated value from a plurality of fields or a plurality of frames may be used. In addition to the addition of image data, the APL level of video data may be obtained by a low-pass filter circuit, and the APL level may be used as the data sum. The maximum value at this time is the maximum value of the APL level when the video data having the maximum amplitude is input.
[1415]
The sum of the data may be calculated based on the current consumption of the display panel or the brightness. Here, for the sake of simplicity, the description will be made assuming that the addition is luminance (image data). Generally, the method of adding luminance (image data) is easy.
[1416]
In FIG. 197, the horizontal axis represents the data sum / maximum value. The maximum value is 1. The vertical axis is the duty ratio. Data sum = maximum value (data sum / maximum value = 1) is a white display state in which all the pixel rows are the maximum. When the data sum / maximum value is small, it is a dark screen or a screen with a small image display area. At this time, the duty ratio is increased. Therefore, the brightness of the pixel displaying the image is high. As a result, the dynamic range of the image is enlarged and a high quality image is displayed. When the data sum / maximum value is large (the maximum value is 1), the image is a bright screen or a screen with a wide image display area. At this time, the duty ratio is reduced. Therefore, the brightness of the pixel displaying the image is low. Therefore, low power consumption can be achieved. Since the amount of light emitted from the screen is large, the image does not feel dark.
[1417]
In FIG. 197, when the data sum / maximum value is 1.0, the DUTY ratio value to be reached is changed. For example, when the duty ratio is 1/2, half of the screen is in the image display state. Therefore, the image is bright. When the duty ratio is 1/8, 1/8 of the screen is in the image display state. Therefore, the brightness is 1/4 compared to the duty ratio = 1/2.
[1418]
In the driving method of the present invention, the image brightness is controlled by the sum of data and the like, and the dynamic range is expanded. Further, a high contrast display is realized.
[1419]
In a liquid crystal display panel, white display and black display are determined by the transmittance from the backlight. Even when a non-display area is generated on the screen as in the driving method of the present invention, the transmittance in black display is constant. Conversely, by generating a non-display area, the white display luminance in one frame period is reduced, so that the display contrast is reduced.
[1420]
The EL display panel has a black display in which the current flowing through the EL element is 0. Therefore, even if a non-display area is generated on the screen as in the driving method of the present invention, the luminance of black display is zero. When the area of the non-display area is increased, the white display luminance decreases. However, since the luminance of black display is 0, the contrast is infinite. Therefore, good image display can be realized.
[1421]
Further, in the driving method of the present invention, the number of gradations is maintained in the entire gradation range, and the white balance is maintained in the entire gradation range. Further, the luminance change of the screen can be changed by nearly 10 times by the duty ratio control. Further, since the change has a linear relationship with the duty ratio, the control is easy. Further, R, G, and B can be changed at the same ratio. Therefore, the white balance is maintained at any duty ratio.
[1422]
The relationship between the data sum / maximum value and the DUTY ratio is preferably set according to the content of the image data, the image display state, and the external environment. In addition, it is preferable that the user can freely set or adjust.
[1423]
The above switching operation is designed to display the display screen very brightly when the power of the mobile phone, monitor, etc. is turned on, and to reduce the display brightness after a certain period of time to save power. Used. It can also be used as a function to set the brightness desired by the user. For example, outdoors, the screen is made very bright. This is because the surroundings are bright outdoors and the screen is completely invisible. In other words, the curve a in FIG. 197 is selected outdoors. However, if the display is continued at a high luminance, the EL element rapidly deteriorates. For this reason, in the case of making the brightness very bright, it is configured to return to the normal brightness in a short time. For example, normally, the curve c is selected. Further, in the case where the display is performed at a high luminance, the display luminance is configured to be increased by the user pressing a button.
[1424]
Therefore, it is preferable that the user be able to switch with a button, change automatically in the setting mode, or detect the brightness of external light and switch automatically. Further, it is preferable that the display brightness is set to be 50%, 60%, 80% and the like so that the user can set the display brightness. Further, it is preferable that the duty ratio curve, the slope, and the like be rewritten by an external microcomputer or the like. Further, it is preferable that one of the duty curves stored in the memory can be selected.
[1425]
Needless to say, the selection of the duty ratio curve and the like is preferably performed in consideration of the APL level, the maximum luminance (MAX), the minimum luminance (MIN), and the luminance distribution state (SGM).
[1426]
As described above, for example, a is an outdoor curve. c is a curve for indoor use. b is a curve for an intermediate state between indoor and outdoor. Switching between the curves a, b, and c is performed by the user operating the switch. Alternatively, the brightness of the external light may be detected by a photo sensor and automatically switched. Although the gamma curve is switched, the present invention is not limited to this. It goes without saying that a gamma curve may be generated by calculation.
[1427]
Although the DUTY ratio in FIG. 197 is a straight line, it is not limited to this. As shown in FIG. 198, a one-point broken curve may be used.
[1428]
When the image data sum is small, the c-curve in FIG. 198 is selected. The effect of reducing power consumption is exhibited. There is no reduction in image display. When the image data sum is large, the a-curve is selected. The display of the image is not bright, and the occurrence of flicker is reduced.
[1429]
In another embodiment of the present invention, the change in the DUTY ratio is performed when the sum of data / maximum value is 1/10 or more (see FIG. 199). This is because an image having a data sum / maximum value close to 1 is rarely generated, and if the DUTY ratio is changed until the data sum / maximum value is 1 as shown in FIG. 197, the image display is felt dark. More preferably, the change in the DUTY ratio is performed when the sum of data / maximum value is 8/10 or more.
[1430]
In FIG. 199, when the data sum / maximum value is 0.9 or less, the DUTY ratio is changed from 1 to 1/5. Therefore, a five-fold dynamic range is realized.
[1431]
When the data sum / maximum value is 0.9 or more, it is 1/5. Therefore, the display luminance is 1/5 of the maximum value. Data sum / maximum value = 1 indicates white raster display. That is, in the white raster display, the display luminance is reduced to 1/5 of the maximum.
[1432]
When the data sum / maximum value is 0.1 or less, the DUTY ratio is 1/1. One tenth of the screen is a display area. The light emission luminance of the EL element directly becomes the display luminance of the pixel.
Most of the images are displayed in black, and the image is partially displayed.
In terms of an image, an image display in which the sum of data / maximum value is 0.1 or less is an image in which the moon appears in a dark night sky. Setting the DUTY ratio to 1/1 in this image means that the moon portion is displayed at a luminance five times the luminance of the white raster. Therefore, image display with a wide dynamic range can be realized. Since the image is displayed in the 1/10 area, even if the luminance of the 1/10 area is increased by a factor of 5, the increase in power consumption is slight.
[1433]
In an image in which the data sum / maximum value is close to 0, most of the pixels are in low gradation display. If represented by a histogram, the majority of data is distributed in the low gradation area of the histogram. In this image display, the image is in a blackened state and there is no sharp feeling. Therefore, the gamma curve is controlled to widen the dynamic range of the black display section.
[1434]
In the above embodiment, when the data sum / maximum value is 0, the duty ratio is set to 1, but the present invention is not limited to this. As shown in FIG. 200, it goes without saying that the duty ratio may be set to a value smaller than 1. Further, the duty ratio curve may be a curve as shown in FIG.
[1435]
As shown in FIG. 202, the duty ratio curve may be changed for red (R), green (G), and blue (B) pixels. In FIG. 202, the gradient of the change in the duty ratio of blue (B) is the largest, the gradient of the change of the duty ratio of green (G) is the next largest, and the gradient of the change of the duty ratio of red (R) is the largest. It is small. By driving as described above, RGB white balance adjustment can be optimized. The relationship between the data sum / maximum value and the DUTY ratio is preferably set according to the content of the image data, the image display state, and the external environment. In addition, it is preferable that the user can freely set or adjust.
[1436]
When a bright screen and a dark screen are alternately repeated at a high speed, a flicker occurs in which the duty ratio is changed according to the change. Therefore, when changing from a certain DUTY ratio to another DUTY ratio, it is preferable to provide a hysteresis (time delay) as shown in FIG. For example, assuming that the hysteresis period is 1 sec, the previous DUTY ratio is maintained even if the screen luminance is bright and dark several times within the 1 sec period. That is, the duty ratio does not change.
This hysteresis (time delay) time is called a Wait time. The DUTY ratio before the change is referred to as a DUTY ratio before the change, and the DUTY ratio after the change is referred to as a DUTY ratio after the change.
[1437]
When the duty ratio before change changes from a small state to another duty ratio, flicker due to the change is likely to occur. The state in which the duty ratio before the change is small is a state in which the data sum of the screen is small or a state in which the screen has many black display portions.
[1438]
Therefore, it is considered that the screen is a halftone display and the visibility is high. Also, in a region where the DUTY ratio is small, the difference from the changed DUTY ratio tends to be large. Of course, when the difference between the duty ratios becomes large, control is performed using OEV. However, there is a limit to OEV control. From the above, when the duty ratio before change is small, it is necessary to lengthen the wait time.
[1439]
When the duty ratio before the change changes from the large state to another duty ratio, flicker due to the change hardly occurs. The state in which the duty ratio before change is large is a state in which the data sum of the screen is large or a state in which the screen has many white display portions. Therefore, it is considered that the entire screen is displayed in white and the visibility is low. From the above, when the duty ratio before change is large, the wait time may be short.
[1440]
The above relationship is shown in FIG. The horizontal axis is the duty ratio before change. The vertical axis is the Wait time (second). When the duty ratio is 1/16 or less, the wait time is extended to 3 seconds (sec). When the duty ratio is 1/16 or more and the duty ratio is 8/16 (= 1/2), the wait time is changed from 3 seconds to 2 seconds according to the duty ratio. When the duty ratio is 8/16 or more and the duty ratio is 16/16 = 1/1, the duty is changed from 2 seconds to 0 second in accordance with the duty ratio.
[1441]
As described above, the duty ratio control of the present invention changes the wait time according to the duty ratio. When the duty ratio is small, the wait time is lengthened, and when the duty ratio is large, the wait time is shortened. That is, in the driving method of changing at least the DUTY ratio, the DUTY ratio before the first change is smaller than the DUTY ratio before the second change, and the Wait time of the first DUTY ratio before the change is equal to the second time. It is characterized in that it is set longer than the Wait time of the duty ratio before change.
[1442]
In the above embodiment, the wait time is controlled or specified based on the duty ratio before the change. However, the difference between the duty ratio before change and the duty ratio after change is small. Therefore, the duty ratio before the change may be read as the duty ratio after the change in the above embodiment.
[1443]
Further, in the above embodiment, the description has been made based on the duty ratio before the change and the duty ratio after the change. When the difference between the duty ratio before the change and the duty ratio after the change is large, it is needless to say that the wait time needs to be increased. When the difference between the duty ratios is large, it is needless to say that it is preferable to change to the duty ratio after the change through the duty ratio in the intermediate state.
[1444]
The duty ratio control method of the present invention is a driving method in which the wait time is lengthened when the difference between the duty ratio before change and the duty ratio after change is large. That is, this is a driving method in which the Wait time is changed according to the difference in the DUTY ratio. This is a driving method in which the Wait time is lengthened when the difference in the DUTY ratio is large.
[1445]
The duty ratio method according to the present invention is a driving method characterized in that when the difference between the duty ratios is large, the duty ratio is changed to the changed duty ratio via the intermediate duty ratio.
[1446]
In the above embodiment, the description has been given assuming that the Wait time for the DUTY ratio is the same for R (red), G (green), and B (blue). However, in the present invention, it goes without saying that the Wait time may be changed for R, G, and B. This is because the visibility is different for RGB. By setting the Wait time in accordance with the visibility, a better image display can be realized.
[1449]
The above embodiment is an embodiment relating to the duty ratio control. It is preferable to set the Wait time also for the reference current control. FIG. 96 shows the embodiment.
[1448]
When the reference current is small, the screen 50 is dark, and when the reference current is large, the screen 50 is bright. That is, when the reference current magnification is small, it can be translated into a halftone display state. When the reference current magnification is high, the image display state is high brightness. Therefore, when the reference current magnification is low, the visibility with respect to the change is high, and the Wait time needs to be lengthened. On the other hand, when the reference current magnification is high, the wait time may be short because the visibility to the change is low. Therefore, as shown in FIG. 96, the Wait time for the reference current magnification may be set.
[1449]
It is desirable that the reference current magnification for the data sum or the like can be changed from outside the panel module. External changes may be written to the memory of the panel module control circuit 839 (see FIGS. 83 and 205 and the description thereof) using a microcomputer or the like.
[1450]
FIG. 224 is an explanatory diagram of a method of changing the reference current magnification. The horizontal axis in FIG. 224 is the address number. The address number is from address 0 to address 511, and has 9 bits. Although the horizontal axis is an address, it may be considered that the horizontal axis corresponds to the data sum / maximum value described in FIG. 197 to FIG. 202 and the like. That is, when data sum = maximum value, data sum / maximum value = 1. It can be considered that this state corresponds to address 511. When data sum × 2 = maximum value, data sum / maximum value = １ ／. This state may be considered to correspond to address 255.
[1451]
The data (reference current magnification) for each address is sequentially rewritten by the data values applied to the address bus and the data bus as shown in FIG.
[1452]
The reference current on the vertical axis changes depending on the memory state. The solid line a indicates a case where the reference current magnification is constantly changed to 1 regardless of the address value. In the dotted line b, when the data sum is large (the entire screen 50 is close to white display), the reference current is not changed from 1, and when the data sum is small (whether the screen 50 is close to black display or not. In the state where the number of pixels is small), the change of the reference current is increased. Therefore, the dynamic range of image display is expanded. In the dashed-dotted line c, the change is made to change constantly when the data sum is large to small.
[1453]
As described above, rewriting the reference current magnification expands the applicability of the driving method of the present invention. In FIG. 224, the data for each address is rewritten so as to form the a, b, and c lines. However, the present invention is not limited to this. ) May be stored and controlled so as to select and switch.
[1454]
FIG. 226 is an explanatory diagram of a method of changing the duty ratio. The horizontal axis in FIG. 226 is the address number. The address number is from address 0 to address 255, and has 8 bits. Although the horizontal axis is an address, it may be considered that the horizontal axis corresponds to the data sum / maximum value described in FIG. 197 to FIG. 202 and the like. That is, when data sum = maximum value, data sum / maximum value = 1. This state may be considered to correspond to address 255. When data sum × 2 = maximum value, data sum / maximum value = １ ／. It can be considered that this state corresponds to address 127. The data (duty ratio) for each address is sequentially rewritten by data values applied to the address bus and the data bus as shown in FIG.
The reference current on the vertical axis changes depending on the memory state. The solid line a indicates a case where the duty ratio is constantly changed to 1 regardless of the address value. In the dotted line b, when the data sum is large (the whole screen 50 is close to white display), the duty ratio is not changed from 0.2, and when the data sum is small (whether the screen 50 is close to black display). In a state where the number of displayed pixels is small), the change in the duty ratio is large. Therefore, the dynamic range of image display is expanded. In the dashed-dotted line c, the change is made to change constantly when the data sum is large to small.
[1455]
As described above, rewriting the duty ratio expands the applicability of the driving method of the present invention. In FIG. 226, the data for each address is rewritten so as to form the lines a, b, and c. However, the present invention is not limited to this. ) May be stored and controlled so as to select and switch. 224 and 226 may be implemented in combination with each other.
[1456]
The present invention calculates (detects) the data sum or APL, and performs duty ratio control and reference current control based on this value. FIG. 98 is a flowchart for obtaining the duty ratio and the reference current magnification.
[1457]
As shown in FIG. 98, a rough APL is calculated for the input image data (a temporary APL is calculated). The value of the reference current and the reference current magnification are determined from the APL. The determined reference current and reference current magnification are converted into electronic volume data and applied to the source driver circuit 14.
[1458]
On the other hand, the image data is input to the gamma processing circuit, and the gamma characteristic is determined. The APL is calculated from the image data processed with the gamma characteristic. The duty ratio is determined from the calculated APL. Next, the duty pattern is determined based on whether the image is a moving image or a still image. The duty pattern is a distribution state of the non-display area 52 and the display area 53. In the case of a moving image, the non-display area 52 is inserted at a time. In the case of a still image, the non-display area 52 is dispersed and inserted. Therefore, in the case of a still image, the non-display area 52 and the display area non-display area 52 are converted into a duty pattern to be inserted in a dispersed manner. In the case of a moving image, the non-display area 52 is converted into a duty pattern to be inserted at a time. The converted pattern is applied as a start pulse ST (see FIG. 6) of the gate driver circuit 12b.
[1458]
In FIGS. 94 and 95, control of the Wait time according to the duty ratio has been described, and in FIGS. 89 to 93, control of the duty ratio in accordance with the data sum has been described. FIG. 103 is a detailed explanatory diagram for further performing the duty ratio control and the Wait time. However, in order to facilitate the explanation, time factors and the like are reduced.
[1460]
In FIG. 103, the top row shows frame (field) numbers. The second row shows the APL level (corresponding to the data sum). The third row shows the corresponding duty ratio calculated from the APL level. The bottom row shows the resulting duty ratio (processing duty ratio) after correcting in consideration of the Wait time. That is, the corresponding duty ratio (third stage) is 8/64 → 9/64 → 9/64 → 10/64 → 9/64 → 10/64 → 11/64 → 11/64 → 12 depending on the APL level of each frame. / 64 → 14/64 →...
[1461]
For the corresponding duty ratio, the processing duty ratio is 8/64 → 8/64 → 9/64 → 9/64 → 9/64 → 10/64 → 10/64 → 11/64 → in consideration of the Wait time. 12/64 → 12/64 →...
[1462]
In FIG. 103, the corresponding duty ratio is corrected by the Wait time. In the processing duty ratio, the numerator is an integer (FIG. 107 is compared with the fact that the numerator has a decimal point). In FIG. 103, the driving is performed so that the change in the duty ratio is smooth and flicker does not easily occur. In FIG. 103, the corresponding duty ratios have changed to 9/64, 10/64, and 9/64 in frames 3, 4, and 5. However, Wait time control is performed, and the processing duty ratios are 9/64 and 9. / 64, 9/64 (correction points are indicated by dotted lines in frame 4). In FIG. 103, the corresponding duty ratios have changed to 12/64, 14/64, and 11/64 in frames 9, 10, and 11, however, the Wait time control is performed, and the processing duty ratio becomes 12/64. , 12/64 and 11/64 (correction points are indicated by dotted lines in the frame 10). By performing the Wait time control as described above, the duty ratio control is provided with hysteresis (time delay or low-pass filter) so that the duty ratio does not change even if the APL level changes rapidly.
[1463]
The duty ratio control as described above does not need to be completed in one frame or one field. The duty ratio control may be performed during a period of several fields (several frames). In this case, the duty ratio is an average value of several fields (several frames). Even when the duty ratio control is performed in several fields (several frames), it is preferable that the period of several fields (several frames) be six fields (six frames) or less. If it is more than this, flicker may occur. The number of fields (several frames) is not an integer but may be 2.5 frames (2.5 fields). That is, the present invention is not limited to a field (frame) unit.
[1464]
FIG. 104 shows an embodiment in the case where the duty ratio control is performed in several fields (several frames). FIG. 104 illustrates the concept when several fields (several frames) are performed. M is a length for performing the duty ratio control. If one field (one frame) has 256 pixel rows, M = 1024 corresponds to four fields (four frames).
That is, FIG. 104 shows an embodiment in which the duty ratio control is performed in four fields (four frames).
[1465]
M indicates a data string held in the shift register 61b of the virtual gate driver circuit 12b (see FIG. 6). The held data string holds data (on / off voltage) indicating whether the voltage applied to the gate signal line 17b is an off voltage or an on voltage. The average value of the held data string indicates the duty ratio.
In FIG. 104, it goes without saying that M = N. In some cases, the duty ratio control may be performed in the relationship of M <N.
[1466]
For example, in the retained data sequence of M = 1024, if there are 256 on-voltage data and 768 off-voltages, the duty ratio is 256/1024 = 1/4. Note that the distribution state of the on-voltage data is held solid when the display image is a moving image, and the distribution state of the on-voltage is dispersed and held when the display image is a still image.
[1467]
That is, a virtual on / off voltage data sequence is sequentially applied to the gate signal line 17b of the EL display panel. The EL display panel is controlled by the duty ratio by sequentially applying the on / off voltage, and the EL display panel is notified with a predetermined brightness.
[1468]
FIG. 105 is a block diagram of a circuit configuration for implementing the duty ratio control of FIG. First, a video signal (image data) is converted into a luminance signal by a Y conversion circuit 1051. Next, APL level (data sum or data sum / maximum value) is obtained by APL operation circuit 1052. Based on the APL level, the duty ratio is calculated for each field (frame), and the result is stored in the stack 1053. The stack circuit 1053 has a first in first out configuration. Note that the duty ratio is corrected by the wait time control and stored in the stack circuit 1053. The duty ratio data stored in the stack 1053 is applied by a parallel / serial conversion (P / S) circuit 1054 as an ST pulse (see FIG. 6) of the shift register 61b, and is applied in accordance with the order of the applied data. Thus, the on / off voltage of the gate signal line 17b is output from the gate driver circuit 12b.
[1469]
In the above embodiment, the duty ratio control is performed in the field or the frame. However, the present invention is not limited to this. For example, one frame = 4 fields, and the duty ratio control may be performed in units of a plurality of fields. By performing the duty ratio control using a plurality of fields, a smooth image display without flicker can be realized.
[1470]
In FIG. 106, 1-1 means the first field of one frame, 1-2 means the second field of one frame, 1-3 means the third field of one frame, and 1-4 means It means the fourth field of one frame. Further, 2-1 means the first field of two frames.
[1471]
When the duty ratio is changed from 128/1024 to 132/1024, 1-1 / 128/1024, 1-2 / 129/1024, 1-3 / 130/1024, 1-4 / 131/1024, 2- In the case of 1, it is changed to 132/1024. Due to the above change, it gradually changes from 128/1024 to 132/1024.
[1472]
When the duty ratio is changed from 128/1024 to 130/1024, 1-1 / 128/1024, 1-2 / 128/1024, 1-3 / 129/1024, 1-4 / 129/1024, 2- In the case of 1, it is changed to 130/1024. Due to the above change, it gradually changes from 128/1024 to 130/1024.
[1473]
When changing the duty ratio from 128/1024 to 136/1024, 1-1 / 128/1024, 1-2 / 130/1024, 1-3 / 132/1024, 1-4 / 134/1024, 2- At 1, it is changed to 136/1024. Due to the above change, it gradually changes from 128/1024 to 136/1024.
[1474]
The numerator of the duty ratio in the field (frame) duty ratio control need not be an integer. For example, as shown in FIG. 107, control may be performed so that the value is below the decimal point. The numerator below the decimal point can be easily realized by controlling the OEV2 terminal. In addition, by using the average duty ratio in a plurality of frames (fields), the denominator of the duty ratio can be generated to the right of the decimal point. Conversely, a decimal part may be generated in the denominator of the duty ratio. In FIG. 107, the numerator is below the decimal point such as 30.8 or 31.2. By setting the denominator and the numerator to large integers equal to or more than a certain value, it is possible to eliminate the need for decimal places.
[1475]
The duty ratio pattern is changed between a moving image and a still image. If the duty ratio pattern is suddenly changed, an image change may be recognized. Also, flicker may occur. This problem is caused by a difference between the duty ratio of a moving image and the duty ratio of a still image. For a moving image, a duty pattern in which the non-display area 52 is inserted at a time is used. For a still image, a duty pattern in which the non-display area 52 is dispersedly inserted is used. The ratio of the area of the non-display area 52 / the screen area 50 is the duty ratio.
However, even if the duty ratio is the same, the visibility of humans is different depending on the dispersion state of the non-display area 52. This is considered to be due to the human responsiveness to moving images.
[1476]
In the intermediate moving image, the distribution state of the non-display area 52 is a distribution state intermediate between the distribution state of the moving image and the distribution state of the still image. The intermediate moving image may be prepared in a plurality of states, and may be selected from the plurality of intermediate moving images corresponding to the moving image state before the change or the still image state.
The plurality of intermediate moving image states are exemplified by, for example, a configuration in which the non-display area is dispersed in a state similar to moving image display, and the non-display area 52 is divided into three. Conversely, a state where the non-display area is dispersed in a large number like a still image is exemplified.
[1377]
Some still images are bright and some are dark. The same goes for videos. Therefore, it is sufficient to determine which intermediate moving image state to transition to according to the state before the change.
In some cases, a transition from a moving image to a still image may be made without passing through the intermediate moving image. The transition from a still image to a moving image may be performed without going through the intermediate moving image. For example, an image having a low luminance on the screen 50 does not cause any discomfort even if the moving image display and the still image display move directly. Further, the display state may be shifted via a plurality of intermediate moving image displays. For example, the transition from the duty state of the moving image display to the duty ratio state of the intermediate moving image display 1, the transition to the duty state of the intermediate moving image display 2, and the transition to the duty state of the still image display may be performed.
[1478]
As shown in FIG. 108, when moving from the moving image display to the still image display, an intermediate moving image state is passed. Further, the display is shifted from the still image display to the moving image display via the intermediate moving image display. The transition time of each state is preferably a wait time.
[1479]
FIG. 110 shows the duty ratio and the number of variances of the non-display area when a moving image is transferred to a still image and an intermediate moving image. In FIG. 110, when the moving image still image level is 0, the image display is at the moving image level, and when it is 1, the image display is in the quasi moving image (intermediate moving image) state. A value of 2 indicates that the image display is in a still image state.
[1480]
The number of shares is the number of divisions of the non-display area 52. 1 indicates that the non-display area 52 is inserted into the screen at a time. Reference numeral 30 indicates that the non-display area 52 is divided into 30 and inserted. Similarly, 50 indicates that the non-display area 52 is divided into 50 and inserted. As described above, the duty ratio indicates the luminance reduction rate of white display. In other words, a duty ratio of 示 す indicates that the display state is の of the highest white luminance.
[1481]
As shown in FIG. 110, when moving from a moving image to a still image, when moving from a still image to a moving image, the moving image still image level passes through an intermediate moving image (quasi-moving image) state.
[1482]
It is preferable to provide a Wait time for the transition from the moving image to the still image as shown in FIG. The Wait time may be determined based on the ratio of the moving image.
The number of different data on the horizontal axis in FIG. 110 indicates the ratio of moving images detected by moving image detection between a certain frame and the next frame. In other words, the horizontal axis represents the ratio of pixels calculated between frames and having different image data. Therefore, the larger the numerical value, the closer to the moving image display. In FIG. 110, the wait time is secured longer as the moving image is displayed.
[1483]
Further, to explain the duty ratio control, a power supply circuit of the organic EL display device of the present invention will be described. FIG. 112 is a configuration diagram of the power supply circuit of the present invention. 1122 is a control circuit. The midpoint potential of the resistors 1125a and 1125b is controlled, and a gate signal of the transistor 1126 is output. The power supply Vpc is applied to the primary side of the transformer 1121, and the current on the primary side is transmitted to the secondary side by the on / off control of the transistor 1126. 1123 is a rectifier diode, and 1124 is a smoothing capacitor.
[1484]
FIG. 201 is a configuration diagram of the power supply circuit of the present invention. 1122 is a control circuit. By controlling the transistor 1775 to be turned on and off, the current flowing through the coil 1771 and the drive waveform are changed, and the charge charged in the capacitor 1774 is controlled.
The midpoint potential of the resistors 1125a and 1125b is controlled, and a gate signal of the transistor 1126 is output. The Vdd voltage (anode voltage) can be changed by changing the resistance value of the resistor. Since the voltage is generated by the coil (transformer) 1771, the change in the anode voltage causes the change in the cathode voltage (Vss). That is, as the anode voltage (Vdd) increases, the cathode voltage (Vss) also shifts.
[1485]
For example, consider the case where the anode voltage (Vdd) is 6 (V) and the cathode voltage (Vss) is -6 (V). When the anode voltage (Vdd) is changed by 3 (V) to 9 (V), the cathode voltage (Vss) shifts from -6 (V) to -3 (V).
This is an effect that the input side and the output side of the transformer 1121 are insulated.
[1486]
The current-driven organic EL display panel has the following characteristics from the viewpoint of potential.
In the pixel configuration of the present invention, the driving transistor 11a is a P-channel transistor as described with reference to FIG. The unit transistor 484 of the source driver 14 that generates a program current is an N-channel transistor. With this configuration, the program current is a sink current (sink current) flowing from the pixel 16 toward the source driver IC (circuit) 14. Therefore, the potential operation is performed with the anode (Vdd) as the origin. That is, since the program for the pixel 16 is a current, any potential of the source driver IC (circuit) 14 may be used as long as a driving voltage margin is secured.
[1487]
The control of the control circuit 1122 is performed by a logic circuit such as a controller. Therefore, the control circuit 1122 and the ground of the logic circuit need to be matched. However, the input side and the output side of the transformer 1121 are separated. The current program type source driver IC (circuit) 14 acts on the output side and operates based on the anode potential (Vdd). Therefore, the ground of the source driver IC (circuit) 14 does not need to be matched with the ground of the control circuit 1122 and the logic circuit.
In this regard, the source driver IC 14 is of the current program type, and the anode voltage (Vss) is generated by using the transformer 1122 (if added, the cathode voltage (Vss) is generated based on the anode voltage (Vdd)). The combination of the fact that the driving transistor 11a of the pixel 16 is a P-channel has a synergistic effect.
[1488]
Further, the organic EL display panel operates with an absolute value of the anode (Vdd) and the cathode (Vss). For example, if Vdd = 6 (V) and Vss = -6 (V), the operation is performed at 6-(-6) = 12 (V). In the power supply circuit using the transformer 1121 of the present invention in FIG. 112, the cathode voltage (Vss) changes with respect to the anode (Vdd). The anode voltage (Vdd) is the reference position of the program current of the current-driven source driver IC (circuit) 14 of the present invention. That is, the operation is performed with the anode voltage (Vdd) as the origin. Conversely, the potential or control of the cathode voltage (Vss) may be rough. For this reason as well, the power supply circuit of the present invention using the transformer of FIG. 112, the organic EL panel having the current-driven pixel 16 configuration, and the source driver IC (circuit) 14 of the current program type exhibit a synergistic effect. I can understand that. It is also important that the cathode voltage shifts due to a change in the anode voltage.
[1489]
In the organic EL panel, the current Idd flowing from the anode Vdd into the driving transistor 11a substantially coincides with the current Iss flowing from the EL element 15 to the cathode Vss. That is, there is a relationship of Idd = Iss. Actually, Idd> Iss, but since this difference is a program current of the source driver IC (circuit) 14, it is negligible and can be ignored. In the configuration of the transformer 1121 shown in FIGS. 112 and 177, the current output from the anode Vdd matches the current drawn from the cathode Vss. Also in this regard, the synergistic effect of the combination of the organic EL panel and the power supply circuit using the transformer 1121 of the present invention is large.
[1490]
When the driving transistor 11a of the pixel 16 is an N-channel transistor, it is needless to say that the same effect can be obtained when the unit transistor 484 of the source driver IC (circuit) 14 is a P-channel transistor.
[1491]
The Vgh voltage and Vgl voltage of the gate driver circuit 12, the power supply voltage of the source driver circuit, and the like are efficiently generated from the cathode voltage (Vss) or (and) the anode voltage (Vdd). Also, the transformer 1121 may have a four-terminal configuration of two input terminals and two output terminals, or as shown in FIG. 112, it is desirable to have two input terminals and three output terminals at the middle point. The transformer 1121 includes a single-turn transformer (coil).
[1492]
The power supply Vpc is applied to the primary side of the transformer 1121, and the current on the primary side is transmitted to the secondary side by the on / off control of the transistor 1126. 1123 is a rectifier diode, and 1124 is a smoothing capacitor.
[1493]
The output voltage of the anode voltage Vdd is adjusted by the resistor 1125b. Vss is a cathode voltage. As shown in FIG. 178, the cathode voltage Vss is configured to select and output two voltages. The selection is performed by the switch 1781. Generation of two voltages (−9 (V) and −6 (V) in FIG. 178) as the cathode voltage can be easily generated by providing an intermediate tap on the output side of the transformer 1121. Further, two windings for -9 (V) and -6 (V) are formed on the output side of the transformer 1121, and one of these windings can be selected to easily generate the winding.
This is also an excellent point of the present invention. 178 is characterized in that the cathode voltage (Vss) is switched. Changing the anode as the origin of the potential complicates the circuit configuration and increases the cost. On the other hand, even if a potential error of about 10% occurs in the cathode voltage (Vss), it does not affect image display (it is insensitive).
Therefore, it is an excellent feature of the present invention that the cathode voltage is set based on the anode voltage and that the cathode voltage (Vss) is changed in accordance with the temperature characteristics of the panel. The transformer 1121 also has many advantages in that the cathode voltage and the anode voltage can be easily changed by changing the ratio between the number of input windings and the number of output windings. In addition, by changing the switching state of the transistor 1776, the anode voltage (Vdd) can be changed. In FIG. 178, -9 (V) is selected by the switch 1781.
[1494]
In FIG. 178, the cathode voltage Vss is selected from two voltages. However, the present invention is not limited to this, and may be two or more. Further, the cathode voltage may be changed continuously using a variable regulator circuit.
[1495]
The selection of the switch 2021 depends on the output result from the temperature sensor 701. When the panel temperature is low, -9 (V) is selected as the Vss voltage. When the panel temperature is higher than a certain value, -6 (V) is selected. This is because the EL element 15 has a specific characteristic, and the terminal voltage of the EL element 15 increases on the low temperature side. In FIG. 178, one voltage is selected from two voltages and is set to Vss (cathode voltage). However, the present invention is not limited to this. The configuration is such that the Vss voltage can be selected from three or more voltages. May be. The above applies to Vdd as well. The present invention is also characterized in that the cathode voltage (Vss) is lowered at a low temperature below a certain level.
[1496]
In FIG. 178, the cathode voltage is switched (changed) by the temperature sensor 701, but the invention is not limited to this. For example, as shown in FIG. 177, a variable resistor (such as a posistor or a thermistor) is formed or arranged in parallel or in series with a resistor 1775 that determines the output voltage, so that the resistance value can be changed as a whole depending on temperature. May be.
[1497]
As shown in FIG. 178, by configuring so that a plurality of voltages can be selected based on the panel temperature, the power consumption of the panel can be reduced. This is because the Vss voltage may be reduced when the temperature is equal to or lower than a certain temperature. Usually, Vss = −6 (V) having a low voltage can be used. The switch 2021 may be configured as shown in FIG. The generation of a plurality of cathode voltages Vss can be easily realized by taking out an intermediate tap from the transformer 1121 in FIG. The same applies to the case of the anode voltage Vdd. As an example, the configuration of FIG. 179 is illustrated. In FIG. 179, a plurality of cathode voltages are generated using the intermediate tap of the transformer 1771.
[1498]
FIG. 180 is an explanatory diagram of the potential setting. In this example, the source driver IC 14 is described on the basis of GND in order to facilitate the description. The power supply of the source driver IC 14 is Vcc. Vcc may be equal to the anode voltage (Vdd). In the present invention, Vcc <Vdd is set from the viewpoint of power consumption. Preferably, the Vcc voltage of the source driver IC (circuit) preferably satisfies the relationship of Vdd-1.5 (V) <= Vcc <= Vdd. For example, if Vdd = 7 (V), Vcc preferably satisfies the condition of Vdd-1.5 = 5.5 (V) or more and 7 (V) or less. The Vcc voltage is the maximum voltage for operating the switch 481 in FIGS. 48 and 166.
[1499]
The off voltage Vgh of the gate driver circuit 12 is equal to or higher than the voltage Vdd. Preferably, the relationship of Vdd + 0.2 (V) <= Vgh <= Vdd + 2.5 (V) is satisfied. For example, if Vdd = 7 (V), Vgh is set to satisfy the condition of 7 + 0.2 = 7.2 (V) or more and 7 + 2.5 = 9.5 (V) or less. The above conditions apply to both the pixel selection side (the transistors 11b and 11c in the pixel configuration of FIG. 1) and the EL selection side (the transistor 11d in the pixel configuration of FIG. 1).
[1500]
The on-voltage Vgl of the switching transistor (which corresponds to the transistors 11b and 11c in the pixel configuration of FIG. 1) that generates a path of the program current with the driving transistor 11a is Vdd-Vdd or lower and Vdd-Vdd-4. It is preferable to satisfy the condition (V) or make the voltage substantially equal to the cathode voltage Vss. Similarly, the ON voltage on the EL selection side (corresponding to the transistor 11d in the pixel configuration in FIG. 1) is the same. That is, if the anode voltage is 7 (V) and the cathode voltage is -6 (V), the on-voltage Vgl is 7-7 (V) = 0 (V) or less, 7-7-4 = -4 (V). It is preferable to set it in the range. Alternatively, it is preferable that the on-voltage Vgl is substantially equal to the cathode voltage, and is set to -6 (V) or its vicinity.
[1501]
When the driving transistor 11a of the pixel 16 is an N-channel transistor, Vgh is an ON voltage. In this case, it goes without saying that the off-voltage may be replaced with the on-voltage.
[1502]
One of the problems of the power supply circuit of the present invention is that Vgh and Vgl voltages are generated from the anode voltage Vdd and / or the cathode voltage Vss. The anode voltage and the like are generated by the transformer 1121, and from this voltage, the DCDC converter Vgh and Vgl voltages are applied.
[1503]
However, Vgh and Vgl are control voltages of the gate driver circuit 12, and if this voltage is not applied, the transistor 11 of the pixel will be in a floating state. In addition, if there is no Vcc voltage, the source driver IC (circuit) 14 is also in a floating state, causing a malfunction. Accordingly, as shown in FIG. 181, it is necessary to apply the Vdd, Vss voltages after applying the Vgh, Vgl, and Vcc voltages to the panel, after the lapse of T1 time, or simultaneously.
[1504]
The present invention has solved this problem with the configuration shown in FIG. In FIG. 182, 1783a is a power supply circuit including a transformer 1121 and the like. A power supply circuit 1783b receives a voltage from the power supply circuit 1783a and generates Vgh, Vgl, Vcc voltages, and the like, and includes a DCDC converter circuit, a regulator circuit, and the like. 1821 is a switch. Thyristors, mechanical relays, electronic relays, transistors, analog switches, etc. are applicable.
[1505]
In FIG. 182 (a), the power supply circuit 1783a first generates an anode voltage (Vdd) and a cathode voltage (Vss). When this occurs, the switch 1821a is open. Therefore, the anode voltage (Vdd) is not applied to the display panel. The anode voltage (Vdd) and the cathode voltage (Vss) generated by the power supply circuit 1783a are applied to the power supply circuit 1783b, and the voltages Vgh, Vgl, and Vcc are generated by the power supply circuit 1783b and applied to the display panel. After applying the voltages Vgh, Vgl, and Vcc to the display panel, the switch 1821a is turned on (closed), and the anode voltage (Vdd) is applied to the display panel.
[1506]
In FIG. 182 (a), only the anode voltage (Vdd) is cut off by the switch 1821a. This is because, unless the anode voltage (Vdd) is applied, no path for applying a current to the EL element 15 occurs, and no path for flowing to the source driver IC (circuit) 14 occurs. Therefore, there is no malfunction or floating operation of the display panel.
[1507]
Of course, as shown in FIG. 182 (b), the voltage applied to the display panel may be controlled by turning on and off both switches 1821a and 1821b. However, the switches 1821a and 1821b must be closed at the same time, or control must be performed so that the switch 1821b is closed after the switch 1821a is closed.
[1508]
The above is the configuration in which the switch 1821 is formed or arranged at the Vdd terminal of the power supply circuit 1783a. FIG. 183 shows a configuration in which the switch 1821 is not formed or arranged. The point that the anode voltage (Vdd) and the voltage Vgh are similar, and that the anode voltage (Vdd) and the voltage Vcc are similar. If the voltage Vgh is applied, the gate driver circuit 12 turns off the gate signal lines 17a and 17b. This utilizes the fact that the voltage Vgh is applied and the transistor 11 (the transistor 11b, the transistor 11c, and the transistor 11d in the configuration of FIG. 1) is turned off. If the transistor 11 is in the off state, no current path flows from the driving transistor 11a to the EL element 15 and no program current path flows from the driving transistor 11a to the source driver IC (circuit) 14. In addition, the display panel does not malfunction or operate abnormally.
[1509]
When the anode voltage (Vdd) and the Vgh voltage are close to each other, almost no current flows through the resistor even if the resistor 1831a is short-circuited. Therefore, power loss hardly occurs. For example, if the anode voltage (Vdd) = 7 (V), Vgh = 8 (V), and the resistance 1831a is 10 (KΩ), (8−7) /10=0.1, the resistance 1831a Is 0.1 (mA).
Vgh is an off voltage. Further, since the voltage is output from the gate driver circuit 12, the current used is small. The present invention utilizes this property. That is, the gate signal line 17 can be held at the off-voltage (Vgh) or a potential near the off-voltage (Vgh) by the resistor 1831a in which the anode voltage (Vdd) terminal and the Vgh terminal are short-circuited. Therefore, a current path flowing from the anode voltage (Vdd) to the EL element 15 does not occur, and no abnormal operation occurs in the display panel. It goes without saying that the shift register 61 (see FIG. 6) of the gate driver circuit 12 is operated to control so that the off voltage (Vgh) is output from all the gate signal lines 17.
[1510]
After that, the power supply circuit 1783b fully operates, and the specified Vgh voltage, Vgl voltage, and Vcc voltage are output from the power supply circuit 1783b.
[1511]
Similarly, when the anode voltage (Vdd) is close to the Vcc voltage, almost no current flows through the resistor even if the resistor 1831b is short-circuited. Therefore, power loss hardly occurs. For example, if the anode voltage (Vdd) = 7 (V), Vcc = 6 (V), and the resistance 1831a is 10 (KΩ), (7−6) /10=0.1, the resistance 1831b Is 0.1 (mA). Vcc is a voltage used in the source driver IC (circuit) 14. The current consumed from Vcc depends on the on / off state of the shift register circuit of the source driver circuit 14 and the switch 481 (see FIGS. 48 and 166). It is used only for control, and is slight.
[1512]
The present invention utilizes this property. That is, by turning off the switch 481 of the source driver circuit 14 (opening) by the resistor 1831b in which the anode voltage (Vdd) terminal and the Vcc terminal are short-circuited, current can be prevented from flowing into the unit transistor 484. . Therefore, a current path from the anode voltage (Vdd) to the source signal line 18 does not occur, and no abnormal operation occurs in the display panel. It goes without saying that the shift register of the source driver circuit 14 is operated to control so that the current paths of the unit transistors 484 are disconnected from all the source signal lines 17.
[1513]
In FIG. 183, the cathode voltage (Vss) terminal and the Vgl terminal may be short-circuited by a resistor (not shown). Due to the short circuit of the resistor, the cathode voltage (Vss) is applied to the Vgl terminal when the cathode voltage (Vss) is generated. Therefore, the gate driver circuit 12 operates normally.
[1514]
In FIG. 183, the Vgh terminal is short-circuited by the resistor 1831 at the anode voltage (Vdd). However, when the driving transistor 11a is an N-channel transistor, the anode voltage (Vdd) and the Vgl terminal or the cathode voltage (Vss) are used. Needless to say, the Vgl terminal and the Vgl terminal are short-circuited.
[1515]
Although a short circuit (connection) between the anode voltage (Vdd) and the Vgh voltage and between the anode voltage (Vdd) and the Vcc voltage is made with a relatively high resistance, the present invention is not limited to this. The resistor 1831 may be replaced with a switch such as a relay or an analog switch. That is, when the anode voltage (Vdd) is generated, the relay is closed. Therefore, the anode voltage (Vdd) is applied to the Vgh terminal and the Vcc terminal. Next, when the Vgh voltage, the Vhl voltage, the Vcc voltage, etc. are generated in the power supply circuit 1783b, the relay is opened, and the anode voltage (Vdd) and the Vgh terminal, and the anode voltage (Vdd) and the Vcc terminal are disconnected.
[1516]
The transformer 1121 is relatively high. For this reason, as shown in FIG. 206, it is mounted on a substrate 83 arranged at a position facing the source driver IC 14. The board 83 is attached to the chassis 2061 to improve heat radiation from the transformer 1121 and the like. Chip components 2063 such as a chip capacitor and a chip resistor are mounted on the substrate 83. An operation button 2062 of a panel module is arranged on the front of the transformer 1121.
[1517]
It is important to take measures against heat generation from the EL display panel. To prevent heat generation, a chassis 2061 made of a metal material is attached to the back surface of the panel (the surface from which light from the display screen 50 does not come out) (see FIG. 206). Irregularities (not shown) are formed on the chassis 2061 in order to improve heat radiation. Further, an adhesive layer is arranged between the chassis 2061 and the sealing lid 85 in the panel. A material having good heat conductivity is used for the adhesive layer. For example, a paste made of a silicon resin or a silicon material is exemplified. These are often used as an adhesive (adhesive) between the regulator IC and the heat sink. Note that the adhesive layer is not limited to the function of bonding, and may have only the function of bringing the chassis and the panel into close contact with each other.
[1518]
The organic EL display panel has an EL element 15 formed (arranged) between an anode Vdd and a cathode Vss. The anode Vdd voltage and the cathode Vss voltage are supplied from the power supply circuit of FIG. When the EL element 15 does not emit light, the current flowing between the anode and the cathode is zero. In the duty ratio control of the present invention, the current of the EL element 15 is controlled by applying the on / off voltage of the gate signal line 17b for each pixel row. Further, the position of the gate signal line 17b to which the ON voltage is applied is scanned. For example, FIG. 97 shows an embodiment in which the non-display area 52 is divided into four parts. 97 (a), (b), (c) and (d) have different sizes of the non-display area 52. However, the non-display area 52 is scanned (moved) from the top to the bottom of the screen 50. Similarly, the display area 53 is also scanned downward from the top of the screen 50. No current flows through the EL element 15 of the pixel 16 corresponding to the non-display area 52. On the other hand, a current flows through the EL element 15 of the pixel 16 corresponding to the display area 53.
[1519]
Here, in order to explain the problem, a display pattern in which the non-display area 52 and the display area 53 are repeated for each pixel row is exemplified. This display state is a monochrome horizontal stripe display. That is, the odd-numbered pixel rows are displayed in white, and the even-numbered pixel rows are displayed in black. This display pattern is called one horizontal stripe.
Assume that the number of pixel rows is 220 and the duty ratio is 110/220. The duty ratio 110/220 is a state in which an on-voltage and an off-voltage are applied to the gate signal line 17b for each pixel row. The position of the gate signal line 17b to which the ON voltage or the OFF voltage is applied is scanned in synchronization with the horizontal synchronization signal. Therefore, focusing on the gate signal line 17b of a certain pixel row, the ON voltage application state and the OFF voltage application state are alternately repeated on the gate signal line 17b in synchronization with the horizontal synchronization signal. Considering the entire screen 50, the ON voltage is applied to the even-numbered pixel rows. During this period, the off-voltage is applied to the odd-numbered pixel rows. After one horizontal scanning period, an ON voltage is applied to the odd-numbered pixel rows. During this period, an off-voltage is applied to the even-numbered pixel rows.
[1520]
In one horizontal stripe display in which odd-numbered pixel rows display white and even-numbered pixel rows display black, when an ON voltage is applied to the odd-numbered pixel rows, current flows from the power supply circuit to the display area.
However, when the on-voltage is applied to the even-numbered pixel row, no current flows from the power supply circuit to the display area because the even-numbered pixel row displays black. Therefore, the power supply circuit repeats the operation of flowing a current and the operation of not flowing a current every one horizontal scanning period. This operation is not preferable for the power supply circuit. This is because a transient phenomenon occurs in the power supply circuit and the power supply efficiency deteriorates.
[1521]
FIG. 100 shows a driving method for solving this problem. In FIG. 100, the duty ratio is not set to 1/2, but a plurality of duty ratio states are generated in the screen 50, and control is performed so that current always flows even in one horizontal stripe display.
[1522]
(A) and (b) of FIG. 100 generate a Duty ratio of 1/2, a Duty ratio of 1/1, and a Duty ratio of 1/3, and realize a duty ratio of 1/2 (on average in one frame period) as a whole. ing. As described above, by combining a plurality of duty ratios in one frame period, even in the case of one horizontal stripe display, the output current from the power supply circuit does not turn on / off. That is, many regular display patterns such as one horizontal stripe are often displayed. On the other hand, if the duty ratio control is performed by the duty ratio pattern in which the width of the non-display area 52 is equal, the load on the power supply circuit is likely to occur. Therefore, it is preferable to drive so that a plurality of duty ratio patterns are generated on the screen 50 at the same time. Further, it is preferable that the duty ratio pattern is not a single duty ratio pattern, but a predetermined duty ratio as an average of one frame or a few frames (fields).
[1523]
In FIG. 100, it goes without saying that the duty ratio pattern is scanned downward from the top of the screen 50 as shown in FIG. Further, in the duty ratio control method of the present invention, the scanning position is moved for each pixel row in synchronization with the horizontal synchronization signal. However, the present invention is not limited to this. For example, the scanning position may be moved by a plurality of pixel rows in synchronization with the horizontal synchronization signal. Further, the scanning direction is not limited to the downward direction from the top of the screen 50. For example, the first field may be scanned downward from the top of the screen 50, and the second field may be scanned upward from the bottom of the screen 50.
[1524]
FIG. 100 shows a driving method in which an ON voltage is applied and an OFF voltage is applied to each of the gate signal lines 17b of one discrete pixel row. However, the present invention is not limited to this. FIG. 101a) shows the driving state of FIG. Driving for realizing the same screen 50 luminance can be realized by the duty ratio pattern shown in FIG. In FIG. 101B, the pixel rows to which the ON voltage or the OFF voltage is applied are made continuous.
[1525]
There are various types of duty ratio patterns for realizing the same screen 50 luminance. As shown in FIG. 102 (a), there is a pattern in which the non-display area 52 is dispersed very much, and as in FIG. 102 (b), there is a pattern in which the non-display area 52 is relatively less dispersed. . The pattern of FIG. 102 (a) becomes the same if the duty ratio of the pattern of FIG. 102 (b) is approximately reduced. Therefore, the brightness of the screen 50 can be the same.
[1526]
The EL display panel has a problem that an image is burned due to deterioration of the EL element 15. In particular, images are easily burned in with a fixed pattern. To address this problem, the present invention includes a sub-image display screen 50b (sub-screen) for displaying a fixed pattern. The display screen 50a (main screen) is a moving image display area such as a television image.
[1527]
In the EL display panel of the present invention shown in FIG. 147, the gate driver circuit 12 is common to the sub screen 50b and the main screen 50a. The sub screen 50a has 20 pixel rows or more. Therefore, as an example, the screen 50 is composed of 220 pixel rows of the main screen 50a and 24 pixel rows of the sub-screen 50b. The number of pixel columns is 176 × RGB (see FIG. 148).
[1528]
The main screen 50a and the sub-screen 50b may be clearly separated as shown in FIG. In FIG. 149, a space BL is provided between the main screen 50a and the sub screen 50b. The space BL is a region where the pixels 16 are not formed.
[1529]
The W / L (W is the channel width of the driving transistor, L is the channel length of the driving transistor) of the driving transistor 17a of the pixel on the main screen (main panel) and the sub screen (sub panel) may be changed. . Basically, the W / L of the sub screen (sub panel) is increased. Further, the size of the pixel 16a of the main screen (main panel) 50a and the size of the pixel 16b of the sub-screen (sub-panel) 50b may be changed. Further, the anode voltage or the cathode voltage of the main screen (main panel) 50a and the anode voltage Vdd or the cathode voltage Vss of the sub screen (sub panel) 50b may be different voltages, and the applied voltage may be changed.
[1530]
When the sub-panel 71a and the main panel 71a are used in an overlapping manner as shown in FIG. 150 (b), between the sealing substrate (sealing thin film layer) 85a and the sealing substrate (sealing thin film layer) 85b. The buffer sheet 1504 is arranged or formed. Examples of the buffer sheet 1504 include a plate or sheet made of a metal such as a magnesium alloy and a plate or sheet made of a resin such as polyester.
[1531]
As shown in FIG. 150, a sub panel 71b for displaying the sub screen 50b may be separately provided. The main panel 71a and the sub panel 71b are connected to the source signal lines 18a and 18b by a flexible board 84. The connection wiring 1503 is formed on the flexible substrate 84. An analog switch group including an analog switch 1501 is arranged at the end of the source signal line 18a. The analog switch 1501 controls whether to supply a current signal from the source driver circuit 14 to the sub panel 71b.
[1532]
To perform on / off control of the analog switch 1501, a switch control line 1502 is formed. Signal supply to the sub-panel is controlled by a logic signal to the switch control line 1502, and an image is displayed.
[1533]
The gate signal line 17 is formed on the WR side as described with reference to FIG. 9 without forming a gate driver circuit or mounting a gate driver IC chip on the sub panel 71b, and the lighting control line 401 described with reference to FIG. May be formed or arranged (see FIG. 151).
[1534]
The analog switch 1501 is preferably a CMOS type in which a P-channel and an N-channel are combined as shown in FIG. An inverter 1521 is arranged in the middle of the switch control line 1502 to control the switch 1501 to be on / off. As shown in FIG. 153, the analog switch 1501b may be formed with only the P channel.
[1535]
When the number of source signal lines 18 is different between the sub panel 71b and the main panel 71a, a configuration as shown in FIG. 154 may be employed. The outputs of the analog switches 1501a and 1501b are short-circuited and connected to the same terminal 1322a. Further, as shown in FIG. 155, the output of the analog switch 1501b may be connected to the Vdd voltage so as not to be turned on. As shown in FIG. 156, an analog switch 1501a (1501a1, 1501a2) may be arranged or formed at the end of the source signal line 18 that does not need to be connected to the sub panel 71b. The analog switch 1501a is configured to apply an off voltage and not to turn on.
[1536]
Burn-in occurs when the image does not change for a certain period or more. In the present invention, when the data sum is small, the DUTY ratio is increased to expand the dynamic range. However, when the data sum is small, burn-in occurs when a still image is continuously displayed. In order to solve this problem, it is only necessary to detect that a still image is displayed for a certain period or more, and reduce the DUTY ratio or reduce the reference current. The present invention is a driving method that changes (decreases) the duty ratio or (and) the reference current when the still image state continues for a certain period.
[1537]
The problem is how to detect whether the still images are continuous. Stillness detection can be realized by taking the difference in image data between frames or fields. However, a frame memory is required to obtain a difference between frames. In the present invention, this problem is solved by performing a difference operation on image data of only sample points of the image data. FIG. 204 and FIG. 205 are explanatory diagrams thereof.
[1538]
In FIG. 204, the image data constituting the screen 50 is sampled at regular intervals, the sum of the sampled image data is calculated (the sum is performed by the SUM circuit 2051), and then compared with the sum of the image data of the frame. If the sum is the same or the size is similar, it is a still image. The determination is made in units of several seconds or tens of seconds. That is, the comparison of the sums (performed by the comparison circuit 2052) is performed for each frame (field) (of course, it may be performed at a plurality of frames or at field intervals). Although the comparison result may be determined as a still image on the way, if the DUTY ratio or the reference current is not changed immediately and continues for a certain period or more, it is determined that the fixed pattern is displayed and the DUTY ratio or the reference current is displayed. To change.
In the embodiment, the sum of the sampled image data is calculated and compared. However, the present invention is not limited to this. Needless to say, a difference may be obtained for each pixel data to detect whether the image is a still image. .
[1539]
An array substrate used for the EL display device, the liquid crystal display device, and the like of the present invention described above, an EL display panel in which an EL element 15 is formed on the array substrate, an EL display device using the EL display panel, an information display device, and an image. An inspection method and an inspection device for a display device will be described. The inspection method is an indispensable technique for improving the yield and reducing the cost in the method of manufacturing an array substrate or a display device.
[1540]
The inspection method or the inspection apparatus of the EL display panel will be described. However, the present invention can be applied to the state where the EL element 15 is not formed (array state). That is, even if the method is described as an inspection method for an EL display panel, the invention can be applied to an inspection method for an array. The difference between the array and the EL panel is only the presence or absence of the EL element 15. Therefore, the EL display panel and the array inspection method are synonymous, and both are included in the technical category of the present invention. Similarly, the inspection method of the EL display device is the same. Further, the array and the display panel are treated as synonymous unless otherwise specified. Further, a display panel and a display device are treated as synonymous unless otherwise specified.
[1541]
First, an explanation will be given focusing on an array substrate adopting the pixel configuration of the current driving method shown in FIG. 1 or a display device using the same. However, the present invention is not limited to this, and it goes without saying that the present invention can be applied to other pixel configurations.
[1542]
In the pixel configuration of FIG. 1, a voltage is applied to the gate signal line 17 as shown in FIG. Note that in FIG. 357, it is assumed that a voltage equal to or higher than Vt is applied to the gate terminal (G) of the driving TFT 11a of the pixel 16. To apply the Vt voltage, an ON voltage (Vgl) may be applied to the gate signal line 17a and the Vs voltage applied to the source signal line 18 may be written to the gate terminal of the TFT 11a as shown in FIG.
[1543]
Here, the term “Vt voltage” is used to mean a current larger than that at which the EL element 15 emits light and this emission can be detected visually or optically. In other words, the TFT 11a is in a state where a relatively large amount of current flows to cause the EL element to emit light. Therefore, the Vt voltage is obtained by controlling the TFT 11a so as to be equal to or higher than the light emission start current of the EL element 15. Here, for the sake of simplicity, a current flowing through the TFT 11a by applying a voltage higher than the Vt voltage is referred to as an on-current.
A gate-off voltage (Vgh) is applied to the gate signal line 17a, and a gate-on voltage (Vgl) is applied to the gate signal line 17b. (The above is the case where the switching TFT 11 is a P-channel. ).
[1544]
Then, as shown in FIG. 358, the switching TFTs 11b and 11c connected to the gate signal line 17a are turned off, and the switching TFT 11d connected to the gate signal line 17b is turned on. On the other hand, a voltage Vdd higher than that of the drain terminal (D) is applied to the source terminal (S) of the driving TFT 11a.
In this state, the current Ie flows from the driving TFT 11a to the EL element 15. Therefore, the EL element 15 is turned on.
[1545]
In order for the driving TFT 11a to flow an ON current, a voltage equal to or higher than the Vt voltage (voltage at which the driving transistor 11a starts to flow current) is applied to the source signal line 18 and an ON voltage is applied to the gate signal line 17a. Accordingly, there is a method of turning on the TFTs 11b and 11c and applying the voltage applied to the source signal line 18 to the gate (G) terminal of the driving TFT 11a. Of course, this method may be employed in the inspection method of the present invention. However, in this method, it is necessary to apply a voltage to the source signal line 18.
[1546]
As another method, there is a method in which the source signal line 18 is opened (no voltage or the like is applied), and an ON voltage is applied to the gate signal lines 17a and 17b to turn on the TFTs 11b and 11d. Then, the potential of the gate (G) terminal of the driving TFT 11 a becomes the anode potential of the EL element 15. If the Vdd voltage is sufficiently high and the cathode potential (Vss) of the EL element 15 is low, the driving TFT 11a flows an on-current. In this state, even when the off voltage of the gate signal line 17a is applied and the TFT 11b is turned off, sufficient charge is held in the capacitor 19 to keep the TFT 11a on. Therefore, the TFT 11a maintains an ON state (a state in which an ON current flows) for a certain period.
[1547]
That is, even when the source signal line 18 is in an open state, an ON voltage may be applied to the gate signal lines 17a and 17b to turn on the TFTs 11b and 11d. If an ON voltage is applied to the gate signal line 17b and the ON voltage position of the gate signal line 17a is scanned while maintaining the ON state of the TFT 11d, the EL element 15 emits light. Note that an on-voltage is applied to the gate signal line 17a to turn on the TFT 11b so that the driving TFT 11a allows an on-current to flow. However, in practice, the gate signal line 17a is maintained in an off state. Also, the driving TFT 11a allows the ON current to flow, and the EL element 15 emits light. This is presumed to be due to the leakage of the TFT 11b. Therefore, the inspection method of the present invention can be realized without scanning the gate signal line 17a and applying no on-voltage to the gate signal line 17a. However, in the following embodiments, a description will be given assuming that scanning or an ON voltage is applied to the gate signal line 17a in order to ensure inspection. Therefore, the present invention is not limited to the operation state of the gate signal line 17a.
[1548]
By performing the driving described above, in the pixel configuration of FIG. 1, at least the operation state (normal or abnormal) of the TFT 11 a, the TFT 11 b, the TFT 11 d, and the EL element 15 is determined by detecting whether the EL element 15 is on or off. Detection or inspection can be performed.
[1549]
In the inspection method and the like of the present invention, the gate driver circuit 12 will be described as the built-in gate driver circuit 12 formed at the same time as the formation of the pixel 16, but is not limited thereto. For example, a configuration in which a semiconductor gate driver IC made of a silicon chip is connected (mounted) to the gate signal line 17 may be employed. Of course, the present invention is not limited to the method in which the gate driver IC is mounted and the gate driver IC 17 is operated to perform the inspection. The method is implemented by probing with the probe 3591 for each gate signal line 17 or each single gate signal line 17. May be.
[1550]
In the present invention, for the sake of simplicity, the description will be made assuming that the source driver circuit 14 is a semiconductor IC chip (externally attached) and the gate driver circuit 12 is built-in (directly formed on the substrate 71).
[1551]
FIG. 359 is an explanatory diagram for explaining an array (including panel state) substrate inspection method of the present invention. In FIG. 359, the built-in gate driver circuit 17a is connected to the gate signal line 17a, and operates by an external clock, control signal, and power supply (not shown). The control signal is supplied from a gate driver control terminal 3594 (signal line (clock, start pulse, shift signal line), power supply). The built-in gate driver circuit 17b is connected to the gate signal line 17b, and operates by an external clock, control signal, and power supply (not shown). The control signal is supplied from a gate driver control terminal 3594 (signal line (clock, start pulse, shift signal line), power supply).
[1552]
In FIG. 359, the source signal line 17 is described as being in an open state, but a predetermined voltage (Vt voltage or more) is applied as described above, and this predetermined voltage is applied to the gate terminal of the TFT 11a. Needless to say, the operation may be performed as follows.
[1553]
As shown in FIG. 359, an anode terminal electrode 3592 is formed or arranged on the base anode line 2631, and a voltage (current may be a current. The voltage or current from the application wiring 3593 is applied to the base anode line 2631. In the present invention, a description will be given assuming that a voltage is applied from the base anode line 2631; however, the present invention is not limited to this.
A voltage (Vss) may be applied to the card electrode. This is because, in order to control the lighting of the EL element 15, a voltage or a current may be applied with reference to one of the anode and the cathode (that is, the voltage is set so that a potential difference is generated between the anode and the cathode of the EL element 15). In the present invention, for the sake of simplicity, description will be given assuming that a voltage (current) is applied to the anode side as shown in FIG.
[1554]
By applying a voltage to the base anode line 2631, a Vdd voltage is applied to the anode wiring 2632 branched from the base anode line 2631. The gate driver circuit 12b scans the ON voltage under the control of the control terminal 3594b, and operates so that the ON voltage is applied to all the gate signal lines 17b. Of course, control may be performed such that an ON voltage is applied to one or a plurality of gate signal lines 17b, an OFF voltage is applied to the other gate signal lines 17b, and the ON voltage application position is scanned. In the present invention, an ON current is supplied from the driving TFT 11a to the EL element 15 to detect that the EL element 15 does not emit light or does not light. Therefore, even if the TFT 11d is turned on and off in synchronization with the operation state of the gate driver circuit 12b and the EL element 15 is turned on and off, if the EL element 15 can be detected to be turned on (conversely, non-lighting is maintained), the inspection is performed. This is because the method can be realized. Further, by turning on and off the TFT 11d, it is possible to inspect or evaluate the quality and performance of the EL display panel by measuring the blinking cycle and lighting state of the EL.
[1555]
As described above, a voltage is applied to the source signal line 18 to control the TFT 11a (for example, to supply an on-current), and a current is directly supplied to the EL element 15 from the source signal line 18 to provide an EL display panel. Needless to say, the quality or performance of the device may be inspected or evaluated.
[1556]
On the other hand, the gate driver 17a basically applies an on-voltage to one or more gate signal lines 17a and scans the position of the gate signal line 17a to which the on-voltage is applied (controlled by the control terminal 3594a). With this operation, the ON voltage is written to the gate terminal of the driving TFT 11a in the display screen 50, and the TFT 11a can flow the ON current. Of course, as described above, the gate driver circuit 12a may be controlled so that all the gate signal lines 17a are turned off. Alternatively, control may be performed so that all the gate signal lines 17a output an on-voltage and an off-voltage is output to all the gate signal lines 17a in the next period. This control can be easily realized by an enable circuit having a circuit configuration added (formed or manufactured) to the gate driver circuit 17.
[1557]
The above items also apply to the gate driver circuit 12b. That is, the inspection is performed by turning on or off all the gate signal lines 17b by the enable circuit.
[1558]
FIG. 360 is a configuration diagram of the inspection device of the present invention. At one end of the base anode line 2631, an anode terminal electrode 3592 is formed or arranged, and a probe 3591c is connected to this terminal electrode 3592 or arranged or electrically connected. Note that the probe 3591 and the like are arranged on the manipulator, and are configured to be movable in the XYZ directions. By this movement, it is positioned at the terminal electrode 3592 or the like.
[1559]
All the source signal lines 18 are electrically short-circuited by the short wiring 3634. Note that the technical idea is to electrically connect the plurality of source signal lines 18. Therefore, the present invention is not limited to short-circuiting the source signal line 18 with the short wiring 3634. For example, electrical connection may be made by pressing a conductive material between source signal lines. Further, the present invention is not limited to the case where all the source signal lines 18 are connected by one short wiring 3634, and the even-numbered source signal lines 18 are short-circuited by the first short wiring 3634. A first terminal electrode 3631 is arranged or formed on 3634, the odd-numbered source signal lines 18 are short-circuited by a second short wiring 3634, and the first terminal electrode 3631 is arranged or formed on the second short wiring 3634. You may comprise so that it may be.
[1560]
At one end of the base cathode line 2671, a cathode terminal electrode 3606 is formed or arranged, and a probe 3591b is connected to this terminal electrode 3606 or arranged or electrically connected. These probes 3591 and the like are arranged on a manipulator, move in the XYZ directions, and are sequentially probed on one substrate on which a plurality of arrays are formed.
[1561]
Ammeters 3604c and 3604b are connected between the anode terminal electrode 3592 and the cathode terminal electrode 3606. In addition, a voltage source 3605a is connected or arranged between the anode terminal electrode 3592 and the cathode terminal electrode 3606. The control circuit 3601 controls the voltage source 3605a to apply a predetermined voltage between the anode terminal electrode 3592 and the cathode terminal electrode 3606. By applying the voltage, the current flowing through the ammeters 3604c and 3604b is measured and input to the control circuit 3601. Basically, the EL element 15 is a current element. Therefore, instead of using the voltage source 3605a to apply a voltage between the anode terminal electrode 3592 and the cathode terminal electrode 3606 so as to have a predetermined value, the voltage source 3604a operates so that a predetermined current flows through the ammeter 3604. The generated voltage is set to a predetermined value.
[1562]
The current flowing through the ammeter 3604c is a current flowing from the Vdd terminal (the source (S) terminal of the TFT 11a) illustrated in FIG. Therefore, the program current Iw also flows through the Vdd terminal. Further, a current Ie flowing through the EL element 15 also flows. The current flowing through the ammeter 3604b is a current flowing from the Vss terminal (the cathode terminal of the EL element 15) of the EL element 15 shown in FIG. Therefore, basically, only the current Ie flowing through the EL element 15 flows.
[1563]
The program current Iw flows only when the corresponding pixel row is selected. Therefore, the current is small compared to the current Ie of the EL element 15 which is held and continues to flow the current for one frame period. Conversely, when the value of the ammeter 3604c and the value of the ammeter 3604b greatly differ, it can be detected that there is an abnormality in the array. Further, by examining / evaluating the value of the ammeter 3604c and the value of the ammeter 3604b, an array and panel inspection can be performed satisfactorily.
At one end of the base cathode line 2671, a cathode terminal electrode 3606 is formed or arranged, and a probe 3591b is connected to this terminal electrode 3606 or arranged or electrically connected. These probes 3591 and the like are arranged on a manipulator, move in the XYZ directions, and are sequentially probed on one substrate on which a plurality of arrays are formed.
[1564]
The probe 3591a is connected to the source signal line short terminal electrode 3631. The ammeter 3604a is connected to the terminal electrode 3631. Further, a voltage source 3605b is connected or arranged. The control circuit 3601 controls the voltage source 3605b to apply a predetermined voltage to the terminal electrode 3631. By applying the voltage, the current flowing through the ammeter 3604a is measured and input to the control circuit 3601.
[1565]
The current flowing through the source signal line 18 is basically a program current. However, since the plurality of source signal lines 18 are short-circuited, voltage driving is performed instead of current driving. The current flows into the ammeter 3604a only when the pixel row is selected. Therefore, the current is small compared to the current Ie of the EL element 15 which is held and continues to flow the current for one frame period. Conversely, when the value of the ammeter 3604a is significantly different, it can be detected that there is an abnormality in the array. By examining / evaluating the value of the ammeter 3604a, array and panel inspection can be performed satisfactorily.
[1566]
When the Vdd terminal is set to be open as shown in FIG. 397, the probe 3591 is prevented from contacting an electrode or the like. Alternatively, as shown in FIG. 397, a switch 641 is formed or arranged on a path to the probe 3591 so that a conductive state and a high impedance state (open) state can be switched.
[1567]
With the configuration shown in FIG. 397, the probe can be brought into contact or non-contact with the base source line 2631 or the like without moving the probe 3591. Therefore, the inspection method of the present invention can be easily realized.
[1568]
In the inspection, as described with reference to FIG. 359, by applying a voltage to the base anode line 2631, a Vdd voltage is applied to the anode wiring 2632 branched from the base anode line 2631. The gate driver circuit 12b scans the position of the gate signal line 17b to which the ON voltage is applied under the control of the control terminal 3594b, and operates so that the ON voltage is applied to all the gate signal lines 17b. Of course, the configuration may be such that the on-voltage is applied to all the gate signal lines 17b at once by using the enable terminal. Further, the inspection may be performed by controlling the enable terminal, turning on / off the TFT 11d in synchronization with the clock, and causing the EL element 15 to blink. Array / panel inspection / evaluation can also be performed based on the current value of the ammeter 3604 flowing during this inspection.
[1569]
On the other hand, the gate driver 17a basically applies an on-voltage to one or more gate signal lines 17a and scans the position of the gate signal line 17a to which the on-voltage is applied (controlled by the control terminal 3594a). With this operation, the ON voltage is written to the gate terminal of the driving TFT 11a in the display screen 50, and the TFT 11a can flow the ON current. Of course, as described above, the gate driver circuit 12a may be controlled so that all the gate signal lines 17a are turned off. Alternatively, control may be performed so that all the gate signal lines 17a output an on-voltage and an off-voltage is output to all the gate signal lines 17a in the next period. This control can be easily realized by an enable circuit having a circuit configuration added (formed or manufactured) to the gate driver circuit 17.
[1570]
The lighting state of the EL element 15 is performed by a camera (optical input means) 3602. The camera has an image sensor, and is configured to sequentially capture the display state of the display screen 50 in synchronization with a control signal of the gate driver circuit 12. From this display state, the pixel 16 in the non-lighting state is detected. Further, the defective pixel 16 to be lit is detected when the applied signal is in the non-lit state.
[1571]
Note that in FIG. 360, inspection or evaluation is performed using a camera, an image sensor, a photomultiplier, or the like. However, the present invention is not limited to this. The present invention optically inspects, evaluates, measures, or detects arrays, panels, and the like. Therefore, the array, panel, or the like may be visually inspected, evaluated, measured, or detected using human eyes.
[1572]
In addition, it is not limited only optically. It directly detects the current flowing through the TFT 11, the EL element 15, or the signal line (17, 18), or detects the electric or magnetic field generated by the flow of the current (measurement or measurement using a Hall element, a coil, or the like). Can be detected). The array, panel, or the like may be inspected, evaluated, measured, or detected by detecting electrons, electric charges, or photons emitted from the TFT 11, the EL element 15, or the signal line (17, 18, etc.). Further, by detecting magnetostriction, an array, a panel, or the like may be inspected, evaluated, measured, or detected.
[1573]
The above embodiment has been described on the assumption that the pixel 16 defect or the like is optically detected. However, in FIG. 357, the inspection can be performed even in a state where the EL element 15 is not formed (array state). This is because the defect of the transistors 11a, 11b, 11c can be detected by detecting the program current Iw (electrical inspection). Therefore, the inspection device of the present invention shown in FIG. 360 can be used not only as an optical inspection device but also as an electrical inspection device.
[1574]
In the inspection method of the present invention described above, the inspection is performed by applying the Vdd voltage to the Vdd terminal (the source terminal of the TFT 11a). Therefore, by applying the Vdd voltage to the base anode line 2631, the Vdd voltage was applied to the anode wiring 2632 branched from the base anode line 2631.
[1575]
However, the EL element 15 is turned on and the inspection is performed not only by this method but also by the configuration shown in FIG. The difference between FIG. 361 and FIG. 357 is that the Vdd terminal is open (infinite impedance). In the test circuit of FIG. 360, the probe 3591c is in a non-contact state. However, the probe 3591b is brought into contact with the terminal electrode 3606, and the potential relationship with the voltage source 3606b is set to a predetermined value (that is, the voltage sources 3605a and 3605b are shared by the ground, and the probes 3591a, 3591b, and 3591c are used in common. The applied potential is configured so that the potential can be set independently.) As described above, the inspection method illustrated in FIG. 361 can be performed using the inspection circuit in FIG.
[1576]
By setting the Vdd terminal to “Open” as shown in FIG. 361, the current path of the driving TFT 11a is eliminated. When the gate driver circuit 12a is controlled and an on-voltage (Vgl) is applied to the gate signal line 17a, the TFTs 11b and 11c are turned on. When the gate driver circuit 12a is controlled and an on-voltage (Vgl) is applied to the gate signal line 17b, the TFT 11d is turned on.
In this state, if a Vs voltage (Vs> Vss) is applied from the voltage source 3605b to the source signal line 18, a current path from the source signal line 18 through which the current Is of the TFT 11c → the TFT 11d → the EL element 15 → the Vss terminal flows is generated. . Accordingly, the EL element 15 can be turned on as shown in FIG. 362 by applying a voltage to the source signal line 18.
[1577]
The gate driver circuit 12b is controlled to apply an ON voltage to all the gate signal lines 17b (the TFT 11d in the display screen 50 is in an ON state). Further, the gate driver circuit 12a is controlled to sequentially apply an on-voltage (Vgl) to the gate signal line 17a (scan state). Then, one pixel row is sequentially selected, and one pixel row is turned on. Then, the lighting pixel row moves from the top to the bottom of the screen. By observing the lighting pixel row with the camera 3602, a pixel defect can be detected. Of course, if there is a pixel that is lit without applying the Vs voltage to the source signal line 18, it can be detected that the pixel 16 is defective.
[1578]
Further, the gate driver circuit 12b is controlled to apply an ON voltage to all the gate signal lines 17b (the TFT 11d in the display screen 50 is in an ON state). Further, it controls the gate driver circuit 12a and applies an on-voltage (Vgl) to all the gate signal lines 17a. Then, the entire screen 50 is turned on. By observing the lighting screen with the camera 3602, a pixel defect can be detected.
[1579]
The application of the Vs voltage to the source signal line 18 can also be realized by mounting the source driver IC 14 on the source signal line 18 and operating the source driver IC 14. In this case, if the source driver IC 14 is a current driving IC, the signal applied to the source signal line 18 is not Vs but current Is. It is important to note that the present invention also includes an inspection method performed by operating the source driver IC (circuit) 14 within the technical scope.
[1580]
Further, in the inspection method of the present invention, the display image is not limited to the white raster, and may be displayed by displaying a cross patch, a vertical stripe, a horizontal stripe, a checker, a gradation pattern, a color bar, a window, and the like. good.
[1581]
In FIG. 362, the Vdd terminal (the source (S) terminal of the driving TFT 11a) is set to be open, and the inspection method of the present invention is performed. However, this is an example.
For example, as shown in FIG. 398, a negative voltage is applied to the Vdd terminal (at least a voltage that turns off the driving TFT 11a regardless of the potential state of the gate signal line 17a. (Which is a voltage that does not apply), a current path of the source signal line 18 → TFT 11c → TFT 11d → EL element 15 → Vss is generated. If the EL element 15 emits light in this state, the inspection can be performed optically. In addition, if the pickup current is directly connected to the path of the current Is by the ammeter and the voltage across the pickup resistor 531 is detected, the current Is can be indirectly measured by the voltmeter 3991 (voltage measurement means). (See FIG. 399). Therefore, an inspection can be performed.
[1582]
Further, in the case of inspecting whether or not a short circuit has occurred between the cathode and the anode (between the pixel electrode and the cathode electrode) of the EL element 15 (that is, the EL film is broken), it is illustrated in FIG. The inspection can be performed by applying a voltage as described above. In FIG. 398 (b), a high voltage (Vs voltage as an example) is applied to the cathode terminal of the EL element 15 (a low voltage may be used when a current path is generated as in FIG. 398 (a)). . In this state, if an ON voltage is applied to the gate signal lines 17a and 17b, a current path of the Vss terminal → the EL element → the TFT 11d → the TFT 11c → the source signal line 18 is generated. Therefore, it is possible to electrically inspect the array (panel). Further, if the pickup Is 531 is connected directly to the path of the current Is by the ammeter and the voltage across both ends of the pickup 531 is detected, the current Is can be indirectly measured by the voltmeter.
[1583]
Further, the Vs voltage and the Vss voltage are expressed as a DC voltage or a DC current, but are not limited thereto. For example, as shown in FIG. 400, a signal generator 4001 (signal generation means) may be connected.
[1584]
The above embodiment is configured as shown in FIG. 401 at the time of inspection. The built-in gate driver circuits 12a and 12b are connected, and by controlling the gate driver circuit 12, an on / off voltage is applied to the gate signal lines 17a and 17b. The inspection pixel rows are sequentially selected according to the applied state, and the inspection is performed. The present invention basically performs an inspection by optically detecting the light emitting state of a pixel. In the case of performing an electrical test, as shown in FIG. 401, the probe 3591 is brought into contact with the connection terminal 2633 of the source signal line 18 or the like, and the current flowing through the probe 3591 is directly or the pickup resistor 531. Is measured by the voltmeter 32671.
[1585]
Note that it goes without saying that the above items are applied to the inspection method of another pixel configuration. Further, it goes without saying that the present invention is applied to other embodiments of the inspection method of the present invention. When the inspection is performed after the EL element 15 is formed, the inspection is performed after the EL film is sealed.
[1586]
Further, both the second inspection method described in FIGS. 361 and 362 and the first inspection method described in FIGS. 357 and 358 can be performed using the inspection circuit in FIG. 360. By performing both the first inspection method and the second inspection method, all the current paths of the TFTs 11a, 11b, 11c, 11d and the EL element 15 of the pixel 16 have been implemented. Therefore, a complete inspection can be realized. Further, other inspection methods of the present invention described below may be implemented alone or in combination.
[1587]
If the gate driver circuit 12a is sequentially scanned one pixel row at a time, it can be turned on one pixel row at a time. By controlling the gate driver circuit 12a and applying an on-voltage to all the gate signal lines 17a, the entire screen 50 can be displayed. Further, the inspection may be performed by alternately lighting one pixel row (even-numbered row and odd-numbered row). The inspection may be performed by sequentially scanning a set of a plurality of pixel rows (two pixel rows, four pixel rows, etc.). Further, the screen may be divided (for example, the screen 50 may be divided into four, and the four divided areas may be sequentially turned on), and the inspection may be sequentially performed.
[1588]
Needless to say, the above items can also be applied to the inspection method of the present invention described in FIGS. 357, 359, 360, and the like. The above items can be applied to other inspection methods of the present invention described below.
[1589]
As shown in FIG. 363, the source signal line 18 is short-circuited by the short wiring 3634. The short wiring 3634 is formed simultaneously with the source signal line 18.
Forming the short wiring 3634 also provides a measure against static electricity. A source signal line terminal electrode 33313 is formed or arranged at one end of the short wiring 3634. As shown in FIG. 360, a probe 3591a is connected to the terminal electrode 33313, and the probe 3591a is connected to a voltage (current) applying wiring 3593. Is connected.
[1590]
On the other hand, a check terminal electrode 3633 is formed at one end of the source signal line 18. The check terminal 3633 is for checking or measuring the potential of each source signal line 18. After the array inspection, the source signal lines 18 are separated by cutting along the AA 'line, thereby completing the array.
[1591]
Note that, in the inspection method of the present invention, the pixel configuration is not limited to FIG. For example, the present invention can be applied even when the pixel configuration is a current mirror configuration. Further, the present invention can be applied even when the pixel configuration is a voltage-driven pixel configuration.
[1592]
Hereinafter, another embodiment of the present invention will be described with reference to the drawings. FIG. 364 is an explanatory diagram for describing the inspection method of the present invention. In the pixel configuration of FIG. 364, the program current Iw is applied to the source signal line 18. The program current Iw is a current of 1 μA to 10 μA. The driving TFT 11a is driven so that a predetermined program current Iw flows. That is, the potential of the gate (G) terminal of the driving TFT 11a changes. The potential of the gate terminal (G) of the TFT 11a for flowing the predetermined current Iw is called Vt.
[1593]
For example, in order for the driving TFT 11a of a certain pixel to pass the Iw current, the gate terminal needs to be lower than the Vdd voltage by Vt2 (the solid line in FIG. 364 (a)). In order for the driving TFT 11a of another pixel to flow the Iw current, the gate terminal needs to be lower than the Vdd voltage by Vt1 (dotted line in FIG. 364 (a)). These Vt are changes in the potential of the source signal line 18 and indicate the characteristics of the TFT 11 a of the pixel 16.
[1594]
The gate drive circuit 12 is controlled to apply an ON voltage to one gate signal line 17a. That is, selection is sequentially performed for each pixel row (an off voltage is applied to the other gate signal lines 17a). The source signal line 18 is set so as to flow an Iw current. An on-voltage is applied to the gate signal line 17a, and the gate terminal of the TFT 11a of the selected pixel 16 has the Vt voltage required to flow the predetermined current Iw.
[1595]
An off-voltage is applied to the gate signal line 17b. The TFT 11d is turned off by application of the off voltage, and the driving TFT 11a and the EL element 15 are separated. Therefore, the inspection method of the present invention can be applied even in an array state where the EL element 15 is not formed.
[1596]
As described above, when the on-voltage position of the gate signal line 17a is sequentially shifted in synchronization with one horizontal scanning period (1H), the potential of the source signal line 18 changes as shown in FIG. 364). The change is output in synchronization with 1H. Note that synchronization with 1H is not limited. This is because the image is not displayed but for inspection. Therefore, 1H means that one pixel row is sequentially selected, and this is for ease of explanation. 1H may be any fixed time (period).
[1597]
FIG. 366 is an inspection circuit for performing the inspection method of FIG. 364. This is basically the same as the inspection circuit of FIG. 360. The difference is that the probe 3591 is connected to the electrode terminal 2633 of each source signal line 18 and the program current Iw is applied to the source signal line 18. The program current Iw can be changed or adjusted by the voltage value of the reference voltage circuit 3661.
[1598]
The program current Iw is set to 1 μA or more and 10 μA or less. Basically, the operation is performed with the maximum current required to drive the panel. Further, in order to examine the black writing state (during black display), the measurement may be performed at a low current of 100 nA or less.
[1599]
The reference voltage Va output from the reference voltage circuit 3661 is applied to the + terminal of the operational amplifier 722. Since the + terminal and the − terminal of the operational amplifier have the same potential, a current Iw = Va / Rm flowing through the source signal line 18 flows through the transistor 3313. Therefore, the constant current Iw flows through all the source signal lines 18.
[1600]
According to the above circuit configuration, since the constant current Iw flows through the source signal line 18, the voltage waveform in FIG. 365 can be measured by sequentially shifting the gate signal line 17a. This voltage waveform is subjected to AD (analog-digital) conversion, and is taken into data collection means and control means such as a personal computer (PC) 3662.
[1601]
Since a minute current flows through the source signal line 18, the impedance is high. In this state, in order to measure the potential change (or the absolute value) of the source signal line 18 well, a high impedance circuit (for example, an input terminal of an input operational amplifier constituted by an FET circuit) is connected to the source signal line 18. I do. In the case of the QCIF + panel, there are 176 × RGB = 528 source signal lines 18. It is difficult to arrange an AD converter on all of the source signal lines 18. Therefore, a multiplexer type analog switch is arranged at the output terminal of the input operational amplifier. An AD converter is arranged at the output of the analog switch, and data from the AD converter is taken into a personal computer (PC: control means) 3662. In FIG. 366, the high impedance circuit, the analog switch, and the like are represented as 3663. Note that a connection state with the terminal electrode 2633 is illustrated in FIG.
[1602]
FIG. 367 is a timing chart of data measurement of a circuit (inspection circuit) for measuring the potential of the source signal line 18. FIG. 367 (a) shows a potential change of the source signal line 18 synchronized with 1H. FIG. 367 (b) illustrates the potential of the gate signal line 17b. That is, the on-voltage position is shifted by one pixel row. In synchronization with the selected pixel row, the TFT 11a of the selected pixel row operates, and the source signal line potential ((a) in FIG. 367) changes.
[1603]
FIG. 367 (c) shows a data fetch signal to the PC3662 (it can also be referred to as an analog switch switching signal). Data is captured by the PC3662 at the rise of the data capture signal.
[1604]
The PC3662 evaluates / determines the value of the fetched data. Based on the result, a defect state, a defect position, a defect mode, a defect state, and the like of the array or panel are detected or inspected.
[1605]
In the pixel configuration shown in FIG. 357, in a state where an ON voltage is applied to the gate signal line 17a and an OFF voltage is applied to the gate signal line 17b (the inspection method in FIG. 366), between the Vdd terminal → the SD of the TFT 11a → the TFT 11c → the source signal A current path to line 18 results.
[1606]
When an SD short (channel short) occurs in the TFT 11a, a Vdd voltage is output to the source signal line 18 ((a) in FIG. 368). Therefore, an SD short (pixel defect) of the TFT 11a can be detected. If the gate signal line 17a is disconnected, the path of the program current Iw does not occur, so that the potential of the source signal line 18 approaches the ground potential (see FIG. 368 (b)). Therefore, a line defect such as disconnection of the gate signal line 17a can be detected (inspection can be performed). In addition, if a voltage other than the specified voltage is output to the source signal line 18 in a state where the off-voltage is applied to all the gate signal lines 17a, it is possible to detect that the TFT 11c or the TFT 11b is defective. Further, by changing whether the Vdd voltage is applied to the Vdd terminal or the Vdd terminal is opened as shown in FIG. 361, the defect can be examined and inspected in detail.
[1607]
As shown in FIG. 369 (a), by measuring the signal line potential of the source signal line 18 of one pixel column (pixel 16 connected to one source signal line 18), the maximum voltage Vtmax and the minimum voltage are measured. Vtmin can be detected. When the difference between the maximum voltage and the minimum voltage is equal to or greater than a predetermined value, it is easy to determine that the array or panel being measured or inspected is defective. Further, the Vt distribution in the array or the panel is measured, and as shown in FIG. 369 (b), the characteristic distribution of the TFT 11a can be obtained. From this characteristic distribution, the standard deviation and average value of Vt can be calculated. When the standard deviation and the average value of Vt are out of the predetermined range, it is easy to determine that the array or panel being measured or inspected is defective.
[1608]
In the inspection method of the present invention, the pixel driver 16 is inspected by controlling the gate driver circuit 12 to apply an on-voltage to at least one gate signal line 17 a and to supply a program current to the source signal line 18. .
[1609]
In the above embodiment, one pixel row is selected and Vt output to the source signal line 18 is measured or inspected. However, the present invention is not limited to this. Even when a plurality of pixel rows are selected at the same time, the potential of the source signal line 18 changes. Even in this case, a pixel defect (gate disconnection, SD short circuit, etc.) as shown in FIG. 368 can be detected. Therefore, in order to perform the inspection at high speed, first, a plurality of gate signal lines 18 are selected, and after detecting a general defect, an ON voltage is applied to the defective portion again for each gate signal line 17a. Then, the defect position or defect state may be specified.
[1610]
In the inspection method of the present invention, it is not necessary to probe all the source signal lines 18 at one time. For example, as shown in FIG. 371, probing may be performed for each one. That is, the inspection method of the present invention may be implemented by opening the even-numbered source signal lines 18b and probing the probe 3591 to the terminal electrodes 2633a of the odd-numbered source signal lines 18a. After the pixel 16 connected to the source signal line 18a is inspected, the pixel connected to the source signal line 18b is inspected by probing the terminal electrode 2633b of the even-numbered source signal line 18b.
[1611]
In the above embodiment, the connection terminal 2633 for connecting the source driver IC 14 is probed. However, when the connection terminal 2633 is probed, unevenness occurs in the connection terminal 2633, and it becomes difficult to perform the COG connection of the source driver IC 14.
[1612]
In the embodiment of FIG. 372, the connection terminals 2633 are arranged or formed between the display screens 50 with the inspection electrodes 3721. In addition, in order to operate or control the built-in gate driver circuit 12 (such as a shift operation in FIG. 367), the inspection terminal 3721 is also formed or arranged on a control signal line and a power supply terminal of the gate driver circuit 12. . Therefore, by performing the probing, it is possible to control the gate driver circuit 12 and easily control the application position of the ON voltage and the OFF voltage of the gate signal line 17.
[1613]
In FIG. 372, the inspection electrodes 3721 are formed or arranged as the inspection electrodes 3721a and 3721b so that the inspection can be performed by dividing the inspection electrodes into a plurality. The even-numbered source signal line 18b is opened, and the probe 3591 is probed on the terminal electrode 2633a of the odd-numbered source signal line 18a to perform the inspection method of the present invention. After the pixel 16 connected to the source signal line 18a is inspected, the pixel connected to the source signal line 18b is inspected by probing the terminal electrode 2633b of the even-numbered source signal line 18b. When inspecting the odd-numbered source signal lines 18a and the even-numbered source signal lines 18b, a voltage and a signal can be applied to the signal line 3594 so that the gate driver circuit 12 can be controlled. Make up.
[1614]
At the other end of the source signal line 18 where the inspection electrode 3721 is formed, a check terminal electrode 3731 is formed or arranged as shown in FIG. The check terminals 3731 are arranged in a three-stage staggered arrangement. The first stage is a check terminal electrode 3731R connected to the red source signal line 18. The second stage is a check terminal electrode 3731G connected to the red source signal line 18. The third stage is a check terminal electrode 3731B connected to the red source signal line 18.
[1615]
The check terminal electrode 3731 is also for observing or monitoring a potential change of the source signal line 18. By connecting the probe 3591, the evaluation in FIG. 369, the inspection in FIG. 368, and the like can be easily performed.
[1616]
The problem of the inspection method described in FIG. 366 and the like is that the inspection of the TFT 11d in FIG. 357 cannot be completely performed. In particular, the state of the channel (SD) of the TFT 11d cannot be inspected. In order to solve this problem, a TFT 11g may be added (formed or arranged) to the pixel 16 as shown in FIG. The source (S) terminal of the TFT 11g is connected to the adjacent source signal line 18b, and the drain (D) terminal is connected to the anode terminal of the EL element 15. The gate (G) terminal is connected to the gate signal line 17g.
[1617]
The TFT 11g is turned on by applying an on-voltage to the gate signal line 17g. Further, a Vs voltage is applied to the source signal line 18b. Then, a current path Is flowing through the path of the source signal line 18b → the TFT 11g → the TFT 11d → the TFT 11c → the source signal line 18a is formed. Therefore, the inspection of the TFT 11d can be easily performed. Note that the TFT 11g can be turned off by applying an off voltage to the gate signal line 17g. Therefore, an off voltage is applied to the gate signal line 17g except during the inspection.
[1618]
Further, by setting the Vs voltage to a negative voltage, a reverse bias voltage (Vs <Vss) can be applied to the EL element 15 from the source signal line 18b. Of course, when applying a reverse bias voltage, an ON voltage is applied to the gate signal line 17g.
[1619]
In FIG. 366 and the like, the gate driver circuit 12 is a built-in gate driver circuit (not externally provided as a semiconductor chip), but the present invention is not limited to this. As shown in FIG. 384, the gate driver IC 12 may be formed of a semiconductor chip and connected to the connection terminal 3721 (using the COG method or the like). In this case, there is no gate driver circuit 12 for applying an on / off voltage to the gate signal line 17. Therefore, as shown in FIG. 384, the probe 3591 is pressed against the connection terminal 3721 (or the inspection electrode 3721), and an ON voltage or an OFF voltage is applied to each gate signal line 17.
[1620]
In FIG. 363, a voltage is applied to the source signal line 18 via the probe 3591; however, the present invention is not limited to this. After the source driver IC 14 is mounted on the substrate 71, the source driver IC 14 may be operated to apply the voltage Vs to the source signal line 18. FIG. 385 shows the embodiment. As described above, a precharge circuit is formed (configured or arranged) in the source driver IC 14 of the present invention. The test of the present invention is performed using this precharge circuit (see FIG. 70 and the like).
[1621]
In the configuration of FIG. 385, a precharge voltage adjustment circuit is arranged outside the source driver IC. FIG. 385 is simply conceptually illustrated. The resistor 531 forms the Vs voltage from the Vp voltage. This Vs voltage is applied to each source signal line 18 by controlling the switch 641. The other points are the same as those of the inspection method of the present invention described above, and the description is omitted.
[1622]
In the above embodiment, the inspection method in the pixel configuration of FIG. 357 has been described. However, the present invention is not limited to this, and the inspection method of the present invention can be implemented in other pixel configurations.
[1623]
FIG. 386 shows a pixel configuration of a current mirror type (see also FIG. 38 and the description thereof). In the inspection of the pixel configuration in FIG. 386, first, a Vs voltage equal to or higher than the Vt voltage of the TFT 11b is applied to the source signal line 18. Also, the on voltage of the gate signal lines 17a and 17b is applied to turn on the TFTs 11c and 11d, and the Vs voltage is written to the gate terminal of the TFT 11b (FIG. 388 (a)). Next, an off voltage is applied to the gate signal line 17b to turn off the TFT 11d. Then, as shown in FIG. 387, a current path of the Vdd terminal → the TFT 11b → the EL element 15 → the Vss terminal is generated, and the EL element 15 is turned on. Therefore, the lighting inspection of the EL element 15 can be performed. Further, as shown in FIG. 388 (b), a path of the current Is from the Vdd terminal → the TFT 11a → the TFT 11c → the source signal line 18 is generated. Therefore, inspection of the TFTs 11a, 11b, 11c, 11d, and the EL element 15 can be performed.
[1624]
FIG. 389 shows a pixel configuration driven by voltage. The voltage applied to the source signal line 18 is written by the TFT 11b to the gate terminal of the driving TFT 11a, and a current corresponding to this voltage is applied to the EL element 15. The difference from the conventional voltage-driven 2TFT pixel configuration is that a reset TFT 11e is added (formed or arranged) (see also FIG. 44 and its description).
[1625]
As shown in FIG. 389, the TFT 11b is turned on by applying an on-voltage to the gate signal line 17a, and the TFT 11e is turned off by applying an off-voltage to the gate signal line 17b. Therefore, as shown in FIG. 390 (a), the voltage Vs is written to the gate terminal of the driving TFT 11a. Next, as shown in FIG. 390 (b), when the application of the Vs voltage to the source signal line 18 is stopped, the circuit is connected to the constant current circuit, and the ON voltage is applied to the gate signal line 17b, the Vdd terminal → the TFT 11a → A path of the current Is of the TFT 11e → the TFT 11b → the source signal line 18 is generated. Therefore, inspection of the TFT 11a, TFT 11b, TFT 11e, and EL element 15 can be performed.
[1626]
In the embodiment shown in FIG. 390, the Vss terminal is kept open (high impedance state) in order to prevent a current flowing through the EL element 15. Alternatively, the voltage of the Vss terminal is set high so as not to flow to the EL element 15. Alternatively, when the EL element 15 is not formed in the array state, the inspection method of the present invention can be performed because the state between the drain (D) terminal and the Vss terminal of the driving TFT 11a is in a high impedance state. The above matter is the same in other inspection methods of the present invention.
[1627]
As shown in FIG. 391, a better inspection can be realized with the pixel configuration of FIG. As shown in FIG. 391, the TFTs 11b and 11e are turned on by applying an on-voltage to the gate signal lines 17a and 17e, and the TFT 11d is turned off by applying an off-voltage to the gate signal line 17b. Therefore, as shown in FIGS. 392 (a) and (b), even if the EL element 15 is formed, the current path to the EL element 15 can be cut off by the TFT 11d. Therefore, a path of the current Is from the Vdd terminal → the TFT 11 a → the TFT 11 e → the TFT 11 b → the source signal line 18 is generated. Therefore, inspection of the TFT 11a, TFT 11b, TFT 11e, and EL element 15 can be performed.
[1628]
Further, the Vdd terminal is set to Open, and the Vs voltage is applied to the source signal line 18. By applying an on-voltage to the gate signal lines 17a, 17b and 17e, the TFTs 11b, 11d and 11e are turned on. Therefore, a path of the current Is, which includes the source signal line 18, the TFT 11b, the TFT 11e, the TFT 11d, the EL element 15, and the Vss terminal, is generated. Therefore, if the pixel is normal, the EL element 15 is turned on. Therefore, the inspection of the TFT 11a, the TFT 11b, the TFT 11d, the TFT 11e, and the EL element 15 can be performed.
[1629]
The inspection method shown in FIG. 393 can also be implemented. The TFT 11b is turned on by applying an on-voltage to the gate signal line 17a, and the TFT 11e and TFT 11d are turned off by applying an off-voltage to the gate signal lines 17b and 17e. Therefore, as shown in FIG. 393 (a), the Vs voltage is written to the gate terminal of the driving TFT 11a. Next, as shown in FIG. 393 (b), when an ON voltage is applied to the gate signal line 17b and an OFF voltage is applied to the gate signal lines 17a and 17e, the Vdd terminal → the TFT 11a → the TFT 11d → the EL element 15 → the Vss terminal. A path for the current Ie is generated. Therefore, the inspection of the TFT 11a, the TFT 11b, the TFT 11d, the TFT 11e, and the EL element 15 can be performed.
[1630]
As shown in FIG. 394 in addition to FIG. 386, if a TFT 11f is added, the driving TFT 11b can be inspected in the pixel configuration of the current mirror. The TFT 11f has a source (S) terminal connected to the anode terminal of the EL element 15 and a drain (D) terminal connected to one terminal of the capacitor 19. The gate terminal of the TFT 11f is connected to the gate signal line 17c.
[1631]
As shown in FIG. 394, an ON voltage is applied to the gate signal lines 17a and 17b, and an OFF voltage is applied to the gate signal line 17c. The TFT 11c and the TFT 11d are turned on, and the TFT 11f is turned off. In this state, a Vs voltage is applied from the source signal line 18 to the gate (G) terminal of the driving TFT 11b. On the moon, as shown in FIG. 395, an on-voltage is applied to the gate signal line 17c to turn on the TFT 11f. Then, a path of the current Is from the Vdd terminal → the TFT 11b → the TFT 11f → the TFT 11d → the TFT 11c → the source signal line 18 is generated. Accordingly, inspection of the TFTs 11a, 11b, 11d, 11e, and 11f can be performed.
[1632]
Also, in this state, as shown in FIG. 396, if the Vdd terminal is opened and a Vs voltage is applied to the source signal line 18, the source signal line 18 → TFT11c → TFT11d → TFT11f → EL element 15 → Vss terminal. A path for the current Is is generated. Lighting inspection of the EL element can be realized. Therefore, inspection of the TFTs 11a, 11b, 11d, 11e, 11f, and the EL element 15 can be performed.
[1633]
Next, an embodiment of the display device of the present invention that implements the driving method of the present invention will be described. FIG. 157 is a plan view of a mobile phone as an example of the information terminal device. An antenna 1571, a numeric keypad 1572, and the like are attached to the housing 1573. Reference numeral 1572 and the like are display color switching keys or power on / off and frame rate switching keys.
[1634]
When the key 1572 is pressed once, the display color is set to the 8-color mode, when the same key 1572 is pressed, the display color is set to the 4096-color mode, and when the key 1572 is pressed further, the display color is set to the 260,000-color mode. May be. The key is a toggle switch that changes the display color mode each time the key is pressed. Note that a change key for the display color may be separately provided. In this case, the number of keys 1572 is three (or more).
[1635]
The key 1572 may be another mechanical switch such as a slide switch in addition to a push switch, or may be switched by voice recognition or the like. For example, voice input of 4096 colors to the receiver, for example, voice input of "high-quality display", "4096 color mode" or "low display color mode" to the receiver is displayed on the display screen 50 of the display panel. The display color is configured to change. This can be easily achieved by employing current speech recognition technology.
[1636]
Further, the display color may be switched by an electrical switch or a touch panel selected by touching a menu displayed on the display unit 50 of the display panel. The switching may be performed by the number of times the switch is pressed, or may be switched by rotation or direction like a click ball.
[1637]
Although 1572 is a display color switching key, it may be a key for switching a frame rate. Further, a key for switching between a moving image and a still image may be used. A plurality of requirements such as a moving image, a still image, and a frame rate may be simultaneously switched. Further, the frame rate may be changed gradually (continuously) as the holding is continued. This case can be realized by making the resistor R of the capacitor C and the resistor R constituting the oscillator a variable resistor or an electronic volume. The capacitor can be realized by a trimmer capacitor. Alternatively, a plurality of capacitors may be formed on a semiconductor chip, and one or more capacitors may be selected and connected in parallel in a circuit.
[1638]
Further, embodiments employing the EL display panel, the EL display device, or the driving method of the present invention will be described with reference to the drawings.
[1639]
FIG. 158 is a sectional view of the viewfinder according to the embodiment of the present invention. However, it is schematically illustrated for ease of explanation. In addition, some parts are enlarged or reduced, and some parts are omitted. For example, in FIG. 158, the eyepiece cover is omitted. The above also applies to other drawings.
[1640]
The back surface of the body 1573 is dark or black. This is to prevent stray light emitted from the EL display panel (display device) 1574 from being irregularly reflected on the inner surface of the body 1573, thereby preventing a reduction in display contrast. A phase plate (such as a λ / 4 plate) 108 and a polarizing plate 109 are arranged on the light emission side of the display panel. This is also described in FIGS.
[1641]
A magnifying lens 1582 is attached to the eyepiece ring 1581. The observer adjusts the insertion position of the eyepiece ring 1581 in the body 1573 so that the display screen 50 of the display panel 1574 is in focus.
[1642]
If a positive lens 1583 is arranged on the light emission side of the display panel 1574 as needed, the principal ray incident on the magnifying lens 1582 can be converged. Therefore, the lens diameter of the magnifying lens 1582 can be reduced, and the size of the viewfinder can be reduced.
[1643]
FIG. 159 is a perspective view of the video camera. The video camera includes a photographing (imaging) lens portion 1592 and a video camera body 1573, and the photographing lens portion 1592 and the viewfinder portion 1573 are back-to-back. An eyepiece cover is attached to the viewfinder (see also FIG. 158) 1573. An observer (user) observes the screen 50 of the display panel 1574 from the eyepiece cover.
[1644]
On the other hand, the EL display panel of the present invention is also used as a display monitor. The angle of the display unit 50 can be freely adjusted at a fulcrum 1591. When the display unit 50 is not used, it is stored in the storage unit 1593.
[1645]
The switch 1594 is a switch or a control switch for performing the following functions. A switch 1594 is a display mode switch. The switch 1594 is preferably attached to a mobile phone or the like. The display mode switch 1594 will be described.
[1646]
As one of the driving methods of the present invention, there is a method in which an N-fold current is caused to flow through the EL element 15 to light up only 1 / M of 1F. By changing the lighting period, the brightness can be digitally changed. For example, assuming that N = 4, a current that is four times as large flows through the EL element 15. If the lighting period is set to 1 / M and M = 1, 2, 3, or 4, the brightness can be switched from 1 to 4 times. In addition, you may comprise so that M = 1,1.5,2,3,4,5,6, etc. can be changed.
[1647]
The above switching operation is configured to display the display screen 50 very brightly when the power of the mobile phone, the monitor, or the like is turned on, and to reduce the display brightness after a certain period of time to save power. Used for It can also be used as a function to set the brightness desired by the user. For example, outdoors, the screen is made very bright. This is because the surroundings are bright outdoors and the screen is completely invisible. However, if the display is continued at a high luminance, the EL element 15 rapidly deteriorates. For this reason, in the case of making the brightness very bright, it is configured to return to the normal brightness in a short time. Furthermore, in the case of displaying at high luminance, the display luminance is configured to be increased by the user pressing a button.
[1648]
Therefore, it is preferable that the user be able to switch using the button 1594, change the setting automatically in the setting mode, or detect the brightness of the external light and switch automatically. Further, it is preferable that the display brightness is set to be 50%, 60%, 80% and the like so that the user can set the display brightness.
[1649]
It is preferable that the display screen 50 has a Gaussian distribution display. The Gaussian distribution display is a method in which the luminance at the center is bright and the periphery is relatively dark. Visually, if the center is bright, it is felt bright even if the periphery is dark. According to the subjective evaluation, if the peripheral part maintains 70% of the luminance as compared with the central part, it is visually inferior.
There is almost no problem even if the luminance is reduced to 50%. In the self-luminous display panel of the present invention, the N-fold pulse driving (a method in which an N-fold current is applied to the EL element 15 to turn on only for a period of 1 / M of 1F) from the top to the bottom of the screen is used. A Gaussian distribution is generated in the direction.
[1650]
Specifically, the value of M is increased at the upper and lower portions of the screen, and the value of M is decreased at the center. This is realized by modulating the operation speed of the shift register of the gate driver circuit 12. The brightness modulation on the left and right sides of the screen is generated by multiplying the data in the table by the video data. With the above operation, when the peripheral luminance (view angle 0.9) is set to 50%, the power consumption can be reduced by about 20% as compared with the case of 100% luminance. When the peripheral luminance (angle of view 0.9) is set to 70%, it is possible to reduce power consumption by about 15% as compared with the case of 100% luminance.
[1651]
Note that a switch or the like is preferably provided so that the Gaussian distribution display can be turned on and off. This is because, for example, when Gaussian display is performed outdoors, the periphery of the screen becomes completely invisible. Therefore, it is preferable that the user be able to switch with a button, change automatically in the setting mode, or detect the brightness of external light and switch automatically. In addition, it is preferable that the peripheral luminance is set to be 50%, 60%, or 80% so that the user can set the peripheral luminance.
[1652]
In a liquid crystal display panel, a fixed Gaussian distribution is generated by a backlight. Therefore, the Gaussian distribution cannot be turned on / off. The ability to turn on and off the Gaussian distribution is an effect unique to a self-luminous display device.
[1653]
Further, when the frame rate is predetermined, flicker may occur due to interference with the lighting state of a fluorescent light or the like in a room. In other words, when the EL display element 15 is operating at a frame rate of 60 Hz when the fluorescent lamp is lit with an alternating current of 60 Hz, subtle interference occurs and the screen seems to blink slowly. There is. To avoid this, the frame rate may be changed. The present invention has a function of changing the frame rate. Further, in the N-fold pulse driving (a method in which an N-fold current is supplied to the EL element 15 and lighting is performed only for 1 / M of 1F), the value of N or M can be changed.
[1654]
The above functions can be realized by the switch 1594. The switch 1594 switches and implements the functions described above by holding down the switch a plurality of times in accordance with the menu on the display screen 50.
[1655]
It should be noted that the above items are not limited to mobile phones only, but can be used for televisions, monitors, and the like. Further, it is preferable to display an icon on the display screen so that the user can immediately recognize the display state. The above items are the same for the following items.
[1656]
The EL display device and the like of this embodiment can be applied not only to a video camera but also to an electronic camera and a still camera as shown in FIG. The display device is used as the monitor 50 attached to the camera body 1601. A switch 1594 is attached to the camera body 1601 in addition to the shutter 1603.
[1657]
The above is the case where the display area of the display panel is relatively small. However, when the display area is as large as 30 inches or more, the display screen 50 is easily bent. As a countermeasure, in the present invention, an outer frame 1611 is attached to the display panel as shown in FIG. 161, and the display panel is attached with a fixing member 1614 so that the outer frame 1611 can be suspended. It is attached to a wall or the like using the fixing member 1614.
[1658]
However, as the screen size of the display panel increases, the weight also increases. Therefore, the leg attachment portion 1613 is arranged below the display panel, and the weight of the display panel can be held by the plurality of legs 1612.
[1659]
The leg 1612 can move left and right as shown in A, and the leg 1612 can be contracted as shown in B. Therefore, the display device can be easily installed even in a narrow place.
[1660]
In the television of FIG. 161, the surface of the screen is covered with a protective film (or a protective plate). This is one purpose of preventing the object from hitting and damaging the surface of the display panel. An AIR coat is formed on the surface of the protective film, and by embossing the surface, reflection of an external situation (external light) on the display panel is suppressed.
[1661]
A certain space is arranged by dispersing beads or the like between the protective film and the display panel. In addition, fine projections are formed on the back surface of the protection film, and the projections maintain a space between the display panel and the protection film. By maintaining the space in this way, transmission of the impact from the protective film to the display panel is suppressed.
[1662]
It is also effective to dispose or inject an optical binder such as a liquid resin such as alcohol or ethylene glycol or a solid resin such as epoxy between the protective film and the display panel. This is because interface reflection can be prevented and the optical binder functions as a buffer.
[1663]
Examples of the protective film include a polycarbonate film (plate), a polypropylene film (plate), an acrylic film (plate), a polyester film (plate), and a PVA film (plate). Needless to say, other engineering resin films (such as ABS) can be used. Further, it may be made of an inorganic material such as tempered glass. The same effect can be obtained by coating the surface of the display panel with an epoxy resin, a phenol resin, or an acrylic resin to a thickness of 0.5 mm or more and 2.0 mm or less instead of disposing the protective film. It is also effective to emboss the resin surface.
[1664]
It is also effective to coat the surface of the protective film or the coating material with fluorine. This is because dirt on the surface can be easily wiped off with a detergent or the like. Further, the protective film may be formed thick and may also be used as a front light.
[1665]
Environments using an EL display panel or the like include outdoor and indoor environments. Since the illuminance around the room is low, the luminance of the display screen 50 may be 100 (nt) or less. Since sunlight is irradiated outdoors, 400 (nt) or more is required. Further, in the EL display panel, since the cathode electrode 106 is formed of a metal thin film such as Al, a phenomenon that an external scene or a user is reflected on the cathode electrode 106 occurs, and the display screen 50 becomes difficult to see. In order to prevent glare, a circular polarizing plate 144 (polarizing plate + λ / 4 plate) or a polarizing plate (polarizing film) may be disposed on the light emission side of the display screen 50. However, when a circularly polarizing plate or the like is provided, more than half of the light emitted from the display panel is absorbed by the polarizing plate, and the display screen 50 becomes dark. The reflection depends on the use environment. In many cases, the display screen 50 is easy to see if the display screen 50 is bright without using the circularly polarizing plate 144.
[1666]
FIG. 402 and the like show a configuration for solving this problem. Although the drawings are based on the image of the mobile phone described with reference to FIG. 157, the present invention is not limited to this, and the viewfinder in FIG. 158, the video equipment in FIGS. 159 and 160, the television in FIG. Can also be applied.
[1667]
The configuration in FIGS. 402 and 404 is that a circularly polarizing plate (a polarizing plate is also highly effective) 4021 that can be attached to and detached from the display screen 50 is added. When the circularly polarizing plate 4021 is arranged on the display screen 50 of the EL display panel 1574 (on the light emission side), reflection is suppressed. When the circularly polarizing plate is removed from the display screen 50 (light emission side) of the EL display panel 1574, the display screen 50 becomes twice as bright.
[1668]
In the display device shown in FIG. 402 (FIG. 157), the main screen 50 is constituted by the EL display device 1574 of the invention. A liquid crystal display device (liquid crystal display panel) 4033 as a sub display device is arranged or formed back to back with the EL display device 1574. In addition, a backlight 4031 having a white LED is provided on a back surface of the liquid crystal display device 4033. In FIG. 144, components that are not necessary for the description are not shown in order to facilitate the description. However, a folding configuration may be used. Needless to say, a keyboard or the like may be additionally provided.
[1669]
The user observes only one of the display screen of the sub liquid crystal display device 4033 and the display screen 50 of the EL display device 1574 at a time. In the configuration of FIG. 403A, the circularly polarizing plate 4021 is configured such that a λ / 4 plate (film) is disposed on the EL display device 1574 side and a polarizing plate is disposed on the outside.
[1670]
The circularly polarizing plate 4021 is configured to be able to rotate 360 degrees around two fulcrums 1591 (1591a and 1591b). The fulcrum 1591a and the fulcrum 1591b are connected by a support member 4032. That is, the circularly polarizing plate 4021 can be arranged on the display screen 50 side of the EL display device 1574 as shown in FIG. Further, a circularly polarizing plate 4021 can be provided on the liquid crystal display device 4033 side as shown in FIG. Note that FIG. 403 (b) illustrates a state during the transition from the state of FIG. 403 (a) to the state of FIG. 403 (c).
[1671]
The user of the apparatus in FIG. 402 can observe the screen 50 of the EL display device 1574 in two states. One is a state where a circularly polarizing plate 4021 is arranged on the display screen 50 of the EL display device 1574 as shown in FIG. There is no reflection and a good image display can be observed. The other is the state shown in FIG. 403 (b) or FIG. 403 (c). There is no circular polarizing plate 4021 on the EL display device 1574, and the bright screen 50 can be observed. The user can freely change the state of FIG. 403 (a) and the state of FIG. 403 (c) by moving the circularly polarizing plate 4021.
Other points (items related to the EL display device, etc.) have been described (or described) in FIG. 157 and the like, and thus description thereof will be omitted.
[1672]
FIG. 403 shows a configuration in which the circularly polarizing plate 4021 attached to the support member 4032 is moved to dispose the circularly polarizing plate 4021 on the EL display device 1574. FIG. 404 shows a configuration in which the circularly polarizing plate 4021 is inserted (removed) to be disposed on the EL display device 1574.
[1673]
In FIG. 403, a transparent cover 4041 is provided on the light emission side of the EL display device 1574. The transparent cover 4041 is made of an acrylic resin, and has an AIR coat for preventing reflection on the surface thereof (this structure is a two-layer or three-layer structure described earlier, and thus the description is omitted). Further, a hard coat made of a UV resin having a hardness of 6H or more is formed or configured to prevent the surface from being mechanically scratched.
[1674]
An insertion portion (space) 4042 is arranged between the transparent cover 146 and the EL display device 1574. By inserting the circularly polarizing plate 4021 into the insertion portion 4042 as necessary, reflection can be prevented. The other points are the same as those in FIGS.
[1675]
Since the light emitted from the EL element 15 of the EL display device 1574 has no directivity, this light is emitted to an external space via the substrate 71 on which the EL element is formed. Therefore, when light is emitted from a substrate having a high refractive index (refractive index is about 1.5) to a space (refractive index is 1.0), 2/3 of the light has a critical angle based on Snell's law or more, The light is not emitted to the space (that is, ／ of the light generated by the EL element 15 cannot be emitted from the substrate 71). The light confined in the substrate 71 is irregularly reflected in the substrate 71 to form halation, which lowers the display contrast of the EL display device. Further, this is not preferable because it causes heat generation.
[1676]
In FIG. 405 and the like, light from the EL element 15 diffusely reflected on the substrate 71 or the like is used as button illumination light or the like. Note that the illumination of the buttons and the like is not limited to the light from the EL display device 1574, and illumination light such as a white LED may be separately provided, and the light from the EL display device 1574 may be used in an auxiliary manner. Note that it is preferable that the user be able to switch between using white LED illumination light or using only illumination light from the EL display device 1574 with a button or the like.
[1677]
In FIG. 405, an EL display device 1574 is attached to a light guide plate 4054. Alternatively, a substrate functioning as the light guide plate 4054 and the EL display device 1574 are integrally formed. For example, instead of separately providing the light guide plate 4054, the sealing substrate 85 of the EL display device 1574 may function as a light guide plate. The light guide plate 4054 is supposed to be a transparent substrate, but is not limited thereto, and may be a plate made of aluminum or the like. Further, the light guide portion does not need to be formed of resin, and may be air (that is, a configuration in which only the aluminum reflection portion 4052 is provided). When the light guide plate 4054 is a sealing substrate (lid) 85, the substrate 1574 in FIG.
[1678]
A reflective film (reflective portion) 4052 is formed, configured or arranged around the light guide plate 4054 (the area where light effective for image display does not pass, or the area where light effective for illumination such as buttons does not pass). I have. The reflection film may be a thin film formed by vapor deposition of aluminum, silver, or the like, or a reflection plate of aluminum, silver, or the like may be attached or disposed with an adhesive or the like. In addition, the material is not limited to reflecting light, but may be a material (light diffusing material) or a structure that diffuses light. Examples of the light diffusing material include a configuration in which fine powder of titanium oxide is applied, and Ovar glass. These may be applied or a sheet made of a light diffusing material may be attached. Alternatively, a light guide plate 4054 in which a light diffusing material is filled or diffused may be used. Further, a light guide plate 4054 in which a light reflecting material is filled or diffused may be employed.
[1679]
Light 4053a emitted from the EL element 15 (not shown) becomes display light of the EL display device 1574 and contributes as the display screen 50. On the other hand, the light 4053c having a critical angle or more is transmitted through the light guide plate 4054. Note that it is preferable to form the reflection film 4052 also on the back surface of the IC 12 (14). This is to prevent a malfunction caused by the stray light 4053c entering the IC.
As shown in FIG. 10, since the cathode electrode 106 made of a metal thin film is formed on the front surface of the display area, the light 4053c is not generated (there is weak light due to diffuse reflection). Therefore, the cathode electrode 106 is formed of a thin aluminum thin film so that the cathode electrode 106 is in a translucent state, and in order to further reduce the resistance value of the cathode electrode 106, a transparent electrode made of ITO or IZO is formed on the aluminum cathode electrode 106. It is configured by laminating thin films. Alternatively, a fine opening is formed in the cathode electrode 106. However, in practice, when the substrate 71 and the sealing substrate (lid) 85 are arranged in close contact with each other, and the sealing substrate 85 is attached to the substrate 71, wraparound light 4053c is generated.
[1680]
The light 4053c is reflected by the reflection film 4052 and guides the light inside the light guide plate 4054. Light 4053c is emitted from opening 4051 in which button 1572 (see FIGS. 57 and 402) is arranged. The emitted light becomes illumination light for the button 1572 and the like. As described above, the present invention transmits light that is not used as an image display by the EL display device 1574, and uses the transmitted light as illumination light for another illumination member.
[1681]
FIG. 406 shows a configuration in which a light diffusion unit (light diffusion member) 4061 is arranged near an illumination target (the button 1572 in FIG. 406). The vicinity corresponds to the back surface of the illumination target, the reflection surface 4052 or the surface of the light guide plate 4054 in FIG. The light 4053c incident on the light diffusion portion 4061 is scattered, and the scattered light 4053b efficiently enters the opening 4051 to illuminate. Note that in FIG. 406, the light diffusing portion 4061 is formed or arranged. However, the present invention is not limited to this, and an uneven portion or an inclined portion is formed or configured on the reflective film (reflective surface) 4052, and the uneven portion or the inclined portion is formed. It goes without saying that the light 4053c entering the opening may be incident on the opening 4051 by changing the traveling direction.
[1682]
In FIG. 406 and the like, light 4053c is used as illumination light for the button 1572 and the like. This light can also be used as illumination light for the liquid crystal display panel 4033 and the like. The liquid crystal display panel is not a self-luminous device, but requires a backlight 4031 for image display as shown in FIG. That is, light 4053c is used as a backlight of the liquid crystal display panel 4033. Note that the present invention is not limited to illuminating the liquid crystal display panel 4033 with only the light 4053c, and a backlight 4031 may be provided separately and the light 4053c may be used as an auxiliary. Whether the backlight 4031 is turned on or not can be switched by the user.
[1683]
In FIG. 407, a liquid crystal display panel 4033 as a sub-display device provided on the back surface of the EL display device 1574 is illuminated using light 4053c emitted from an EL element 15 (not shown).
[1684]
In FIG. 405, the EL display device 1574 and the light guide plate 4054 are configured as an integral unit, but the present invention is not limited to this. As shown in FIG. 408, the EL display device 1574 and the light guide plate 4054a (or the sealing lid 85) are integrally formed, and a separate light guide plate 4054b is provided. Connection with an adhesive or the like.
[1885]
In FIG. 407, light 4053c generated from the EL element 15 is used for illumination of the liquid crystal display panel 4033 for image display. However, the present invention is not limited to this. For example, as shown in FIG. 409, an EL backlight 4092 may be formed or arranged on the EL display panel 1574 as a backlight (for illumination) of the liquid crystal display panel 4033. The EL backlight 4092 is formed on the substrate 71 simultaneously with the EL element 15 for displaying an image. For example, when the EL element 15 material is a low molecular EL material, the EL element 15 of the image display area 4093 is formed simultaneously with the EL element 15 of the EL backlight 4092 by mask evaporation. The EL backlight 4092 does not require the pixels 16 to be formed in a matrix. Further, the EL element 15 need not be an active matrix type (of course, the EL elements 15 may be formed in a matrix or may be an active matrix type). In the present invention, the EL backlight 4092 is formed in a stripe shape and is a simple type.
[1686]
The EL backlight 4092 does not need to emit white light. It may be a single color. In the case of a single color, the display image on the liquid crystal display panel 4033 is a single color display. However, when the EL backlight 4033 has a plurality of colors, the display color of the liquid crystal display panel 4033 can be variously changed, which is preferable.
[1687]
As shown in FIG. 409, a light-shielding film 4091 (light-shielding means, light-absorbing means) is formed or arranged on one of the light-emitting sides to make the light emitted from the EL backlight 4092 invisible to the user. Is preferred. By forming an opening in a part of the light-blocking film 4091, the opening can be used as an indicator (display) of whether or not the EL backlight 4092 is turned on. This display device can be formed into a character shape or a circular shape by processing the light shielding film 4091.
[1688]
In the embodiment of FIG. 409, the EL backlight 4092 and the image display area 4093 are formed at the same time. However, the present invention is not limited to this, and they may be formed separately. Alternatively, the EL backlight 4092 and the EL display panel 1574 may be separately manufactured and attached.
[1689]
In order to take measures against heat dissipation of the EL display device, the configurations shown in FIGS. 424 and 426 are adopted. As shown in FIG. 427, the housing 1573 is provided with an air hole (air passage) 4271 between the EL display devices. It may be formed or arranged.
[1690]
It goes without saying that the display panel in the embodiment of the present invention is also effective in combination with a three-side free configuration. In particular, the three-side-free configuration is effective when the pixel is manufactured using amorphous silicon technology. Further, in a panel formed by the amorphous silicon technology, it is not possible to perform process control of variation in characteristics of transistor elements. Therefore, it is preferable to perform N-fold pulse driving, reset driving, dummy pixel driving, and the like of the present invention. That is, the transistor 11 and the like in the present invention are not limited to those using the polysilicon technology, but may be those using amorphous silicon. That is, in the display panel of the present invention, the transistor 11 forming the pixel 16 may be a transistor formed using amorphous silicon technology. It goes without saying that the gate driver circuit 12 and the source driver circuit 14 may also be formed or configured using amorphous silicon technology.
[1691]
Note that the N-fold pulse driving of the present invention (FIGS. 13, 16, 19, 20, 22, 24, 30, etc.) and the like use the low-temperature polysilicon technology to form the transistor 11 and provide a higher performance than the display panel. This is effective for a display panel in which the transistor 11 is formed by the amorphous silicon technology. This is because the characteristics of adjacent transistors in the amorphous silicon transistor 11 are almost the same. Therefore, even when driven by the added current, the drive current of each transistor is almost the target value (in particular, the N-fold pulse drive in FIGS. 22, 24, and 30 is the pixel configuration of the transistor formed of amorphous silicon. Is effective in).
[1692]
The driving method and the driving circuit of the present invention described in this specification such as the duty ratio control driving, the reference current control, and the N-fold pulse driving are not limited to the driving method and the driving circuit of the organic EL display panel. It goes without saying that the present invention can be applied to other displays such as a field emission display (FED) as shown in FIG.
[1693]
In the FED of FIG. 173, electron emission projections 1733 (which correspond to the pixel electrode 105 in FIG. 10) for emitting electrons in a matrix are formed on the substrate 71. A holding circuit 1734 for holding image data from a video signal circuit 1732 (corresponding to the source driver circuit 14 in FIG. 1) is formed in each pixel (corresponding to a capacitor in FIG. 1). In addition, a control electrode 1731 is arranged on the front surface of the electron emission projection 1733. A voltage signal is applied to the control electrode 1731 by an on / off control circuit 1735 (corresponding to the gate driver circuit 12 in FIG. 1).
[1694]
If the peripheral circuit is configured as illustrated in FIG. 174 with the pixel configuration illustrated in FIG. 173, the duty ratio control drive or the N-fold pulse drive can be performed. An image data signal is applied from the video signal circuit 1732 to the source signal line 18. The pixel 16 selection signal is applied from the on / off control circuit 1735a to the selection signal line 2173, the pixels 16 are sequentially selected, and image data is written. Further, an on / off signal is applied to the on / off signal line 1742 from the on / off control circuit 1735b, and the FED of the pixel is on / off controlled (duty ratio control).
[1695]
The technical concept described in the embodiment of the present invention can be applied to a video camera, a projector, a three-dimensional television, a projection television, and the like. Further, the present invention can be applied to a viewfinder, a monitor of a mobile phone, a PHS, a portable information terminal and its monitor, a digital camera and its monitor.
[1696]
Further, the present invention can be applied to an electrophotographic system, a head-mounted display, a direct-view monitor display, a notebook personal computer, a video camera, and an electronic still camera. In addition, the present invention can be applied to a monitor of an automatic teller machine, a payphone, a videophone, a personal computer, a wristwatch, and a display device thereof.
[1697]
Further, it goes without saying that the present invention can be applied or applied to a display monitor of a home electric appliance, a pocket game device and its monitor, a backlight for a display panel, or a lighting device for home or business use. It is preferable that the lighting device is configured to be able to change the color temperature. The color temperature can be changed by forming RGB pixels in a stripe shape or a dot matrix shape and adjusting the current flowing through these pixels. Further, the present invention can be applied to a display device for an advertisement or a poster, an RGB signal device, an alarm indicator, and the like.
[1698]
An organic EL display panel is also effective as a light source for a scanner. An image is read by irradiating an object with light using an RGB dot matrix as a light source. Of course, it is needless to say that a single color may be used. Further, the present invention is not limited to the active matrix, but may be a simple matrix. If the color temperature can be adjusted, the image reading accuracy can be improved.
[1699]
The organic EL display device is also effective for a backlight of a liquid crystal display device. The color temperature can be changed by forming RGB pixels of an EL display device (backlight) in a stripe shape or a dot matrix shape and adjusting the current flowing therethrough, and the brightness can be easily adjusted. In addition, since the light source is a surface light source, a Gaussian distribution in which the central part of the screen is bright and the peripheral part is dark can be easily configured. Further, it is also effective as a backlight of a field sequential type liquid crystal display panel that alternately scans R, G, and B lights. Further, even if the backlight blinks, it can be used as a backlight of a liquid crystal display panel for displaying a moving image or the like by inserting black.
[1700]
【The invention's effect】
In the source driver circuit of the present invention, the transistors constituting the cant mirror circuit are formed so as to be adjacent to each other, so that the variation in the output current due to the shift in the threshold value is small. Therefore, it is possible to suppress the occurrence of uneven brightness of the EL display panel, and the practical effect is large.
[1701]
Further, the display panel, the display device, and the like of the present invention exhibit characteristic effects according to the respective configurations such as high image quality, good moving image display performance, low power consumption, low cost, and high luminance.
[1702]
Note that when the present invention is used, a low-power-consumption information display device or the like can be formed, so that power is not consumed. In addition, since it can be reduced in size and weight, resources are not consumed. Further, even a high-definition display panel can sufficiently cope with the problem. Therefore, it is friendly to the global environment and the space environment.
[Brief description of the drawings]
FIG. 1 is a diagram illustrating a pixel configuration of a display panel according to the present invention.
FIG. 2 is a pixel configuration diagram of a display panel of the present invention.
FIG. 3 is an explanatory diagram of an operation of the display panel of the present invention.
FIG. 4 is an explanatory diagram of an operation of the display panel of the present invention.
FIG. 5 is an explanatory diagram of a driving method of a display device of the present invention.
FIG. 6 is a configuration diagram of a display device of the present invention.
FIG. 7 is an explanatory diagram of a method for manufacturing a display panel of the present invention.
FIG. 8 is a configuration diagram of a display device of the present invention.
FIG. 9 is a configuration diagram of a display device of the present invention.
FIG. 10 is a sectional view of a display panel of the present invention.
FIG. 11 is a sectional view of a display panel of the present invention.
FIG. 12 is an explanatory diagram of a display panel of the present invention.
FIG. 13 is an explanatory diagram of a driving method of a display device of the present invention.
FIG. 14 is an explanatory diagram of a driving method of a display device of the present invention.
FIG. 15 is an explanatory diagram of a method for driving a display device of the present invention.
FIG. 16 is an explanatory diagram of a driving method of a display device of the present invention.
FIG. 17 is an explanatory diagram of a driving method of a display device of the present invention.
FIG. 18 is an explanatory diagram of a driving method of a display device of the present invention.
FIG. 19 is an explanatory diagram of a driving method of a display device of the present invention.
FIG. 20 is an explanatory diagram of a driving method of a display device of the present invention.
FIG. 21 is an explanatory diagram of a driving method of a display device of the present invention.
FIG. 22 is an explanatory diagram of a driving method of a display device of the present invention.
FIG. 23 is an explanatory diagram of a driving method of a display device of the present invention.
FIG. 24 is an explanatory diagram of a driving method of a display device of the present invention.
FIG. 25 is an explanatory diagram of a driving method of a display device of the present invention.
FIG. 26 is an explanatory diagram of a driving method of a display device of the present invention.
FIG. 27 is an explanatory diagram of a driving method of a display device of the present invention.
FIG. 28 is an explanatory diagram of a driving method of a display device of the present invention.
FIG. 29 is an explanatory diagram of a driving method of a display device of the present invention.
FIG. 30 is an explanatory diagram of a driving method of a display device of the present invention.
FIG. 31 is an explanatory diagram of a driving method of a display device of the present invention.
FIG. 32 is an explanatory diagram of a driving method of a display device of the present invention.
FIG. 33 is an explanatory diagram of a driving method of a display device of the present invention.
FIG. 34 is a configuration diagram of a display device of the present invention.
FIG. 35 is an explanatory diagram of a driving method of a display device of the present invention.
FIG. 36 is an explanatory diagram of a driving method of a display device of the present invention.
FIG. 37 is a configuration diagram of a display device of the present invention.
FIG. 38 is a diagram illustrating a pixel configuration of a display panel of the present invention.
FIG. 39 is an explanatory diagram of a driving method of a display device of the present invention.
FIG. 40 is a configuration diagram of a display device of the present invention.
FIG. 41 is a configuration diagram of a display device of the present invention.
FIG. 42 is a diagram showing a pixel configuration of a display panel of the present invention.
FIG. 43 is a diagram illustrating a pixel configuration of a display panel of the present invention.
FIG. 44 is an explanatory diagram of a driving method of a display device of the present invention.
FIG. 45 is an explanatory diagram of a method for driving a display device of the present invention.
FIG. 46 is an explanatory diagram of a driving method of a display device of the present invention.
FIG. 47 is an explanatory diagram of a drive circuit of the present invention.
FIG. 48 is an explanatory diagram of a drive circuit of the present invention.
FIG. 49 is an explanatory diagram of a drive circuit of the present invention.
FIG. 50 is an explanatory diagram of a drive circuit of the present invention.
FIG. 51 is an explanatory diagram of a drive circuit of the present invention.
FIG. 52 is an explanatory diagram of a drive circuit of the present invention.
FIG. 53 is an explanatory diagram of a drive circuit of the present invention.
FIG. 54 is an explanatory diagram of a drive circuit of the present invention.
FIG. 55 is an explanatory diagram of a drive circuit of the present invention.
FIG. 56 is an explanatory diagram of a drive circuit of the present invention.
FIG. 57 is an explanatory diagram of a drive circuit of the present invention.
FIG. 58 is an explanatory diagram of a drive circuit of the present invention.
FIG. 59 is an explanatory diagram of a drive circuit of the present invention.
FIG. 60 is an explanatory diagram of a drive circuit of the present invention.
FIG. 61 is an explanatory diagram of a drive circuit of the present invention.
FIG. 62 is an explanatory diagram of a drive circuit of the present invention.
FIG. 63 is an explanatory diagram of a drive circuit of the present invention.
FIG. 64 is an explanatory diagram of a drive circuit of the present invention.
FIG. 65 is an explanatory diagram of a drive circuit of the present invention.
FIG. 66 is an explanatory diagram of a drive circuit of the present invention.
FIG. 67 is an explanatory diagram of a drive circuit of the present invention.
FIG. 68 is an explanatory diagram of a drive circuit of the present invention.
FIG. 69 is an explanatory diagram of a drive circuit of the present invention.
FIG. 70 is an explanatory diagram of a drive circuit of the present invention.
FIG. 71 is an explanatory diagram of a drive circuit of the present invention.
FIG. 72 is an explanatory diagram of a drive circuit of the present invention.
FIG. 73 is an explanatory diagram of a drive circuit of the present invention.
FIG. 74 is an explanatory diagram of a drive circuit of the present invention.
FIG. 75 is an explanatory diagram of a driving method of a display device of the present invention.
FIG. 76 is an explanatory diagram of a method for driving a display device of the present invention.
FIG. 77 is an explanatory diagram of a drive circuit of the present invention.
FIG. 78 is an explanatory diagram of a driving method of a display device of the present invention.
FIG. 79 is an explanatory diagram of a method for driving a display device of the present invention.
FIG. 80 is an explanatory diagram of a driving method of a display device of the present invention.
FIG. 81 is an explanatory diagram of a driving method of a display device of the present invention.
FIG. 82 is an explanatory diagram of a driving method of a display device of the present invention.
FIG. 83 is an explanatory diagram of a drive circuit of a display device of the present invention.
FIG. 84 is an explanatory diagram of a drive circuit of a display device of the present invention.
FIG. 85 is an explanatory diagram of a drive circuit of a display device of the present invention.
FIG. 86 is an explanatory diagram of a drive circuit of a display device of the present invention.
FIG. 87 is an explanatory diagram of a drive circuit of a display device of the present invention.
FIG. 88 is an explanatory diagram of a drive circuit of a display device of the present invention.
FIG. 89 is an explanatory diagram of a drive circuit of a display device of the present invention.
FIG. 90 is an explanatory diagram of a drive circuit of a display device of the present invention.
FIG. 91 is an explanatory diagram of a drive circuit of a display device of the present invention.
FIG. 92 is an explanatory diagram of a drive circuit of a display device of the present invention.
FIG. 93 is an explanatory diagram of a drive circuit of a display device of the present invention.
FIG. 94 is an explanatory diagram of a drive circuit of a display device of the present invention.
FIG. 95 is an explanatory diagram of a drive circuit of a display device of the present invention.
FIG. 96 is an explanatory diagram of a drive circuit of a display device of the present invention.
FIG. 97 is an explanatory diagram of a drive circuit of a display device of the present invention.
FIG. 98 is an explanatory diagram of a drive circuit of a display device of the present invention.
FIG. 99 is an explanatory diagram of a drive circuit of a display device of the present invention.
FIG. 100 is an explanatory diagram of a method for driving a display panel of the present invention.
FIG. 101 is an explanatory diagram of a method for driving a display panel of the present invention.
FIG. 102 is an explanatory diagram of a method for driving a display panel of the present invention.
FIG. 103 is an explanatory diagram of a method for driving a display panel of the present invention.
FIG. 104 is an explanatory diagram of a method for driving a display panel of the present invention.
FIG. 105 is an explanatory diagram of a method for driving a display panel of the present invention.
FIG. 106 is an explanatory diagram of a method for driving a display panel of the present invention.
FIG. 107 is an explanatory diagram of a method for driving a display panel of the present invention.
FIG. 108 is an explanatory diagram of a method for driving a display panel of the present invention.
FIG. 109 is an explanatory diagram of a method for driving a display panel of the present invention.
FIG. 110 is an explanatory diagram of a method for driving a display panel of the present invention.
FIG. 111 is an explanatory diagram of a method for driving a display panel of the present invention.
FIG. 112 is an explanatory diagram of a drive circuit of a display device of the present invention.
FIG. 113 is a pixel configuration diagram of a display panel of the present invention.
FIG. 114 is a pixel configuration diagram of a display panel of the present invention.
FIG. 115 is a diagram illustrating a pixel configuration of a display panel of the present invention.
FIG. 116 is a pixel configuration diagram of a display panel of the present invention.
FIG. 117 is a diagram illustrating a pixel configuration of a display panel of the present invention.
FIG. 118 is an explanatory diagram of a drive circuit of a display device of the present invention.
FIG. 119 is an explanatory diagram of a drive circuit of a display device of the present invention.
FIG. 120 is an explanatory diagram of a drive circuit of a display device of the present invention.
FIG. 121 is an explanatory diagram of a drive circuit of a display device of the present invention.
FIG. 122 is an explanatory diagram of a drive circuit of a display device of the present invention.
FIG. 123 is an explanatory diagram of a drive circuit of a display device of the present invention.
FIG. 124 is an explanatory diagram of a drive circuit of a display device of the present invention.
FIG. 125 is an explanatory diagram of a display device of the present invention.
FIG. 126 is an explanatory diagram of a display device of the present invention.
FIG. 127 is an explanatory diagram of a method for driving a display panel of the present invention.
FIG. 128 is an explanatory diagram of a display panel driving method of the present invention.
FIG. 129 is an explanatory diagram of a display panel driving method of the present invention.
FIG. 130 is an explanatory diagram of a method for driving a display panel of the present invention.
FIG. 131 is an explanatory diagram of a display panel driving method of the present invention.
FIG. 132 is an explanatory diagram of a display device of the present invention.
FIG. 133 is an explanatory diagram of a display device of the present invention.
FIG. 134 is an explanatory diagram of a method for driving a display panel of the present invention.
FIG. 135 is an explanatory diagram of the display panel driving method of the present invention.
FIG. 136 is an explanatory diagram of a method for driving a display panel of the present invention.
FIG. 137 is an explanatory diagram of a method for driving a display panel of the present invention.
FIG. 138 is an explanatory diagram of a method for driving a display panel of the present invention.
FIG. 139 is an explanatory diagram of a display panel driving method of the present invention.
FIG. 140 is an explanatory diagram of a display panel driving method of the present invention.
FIG. 141 is an explanatory diagram of a method for driving a display panel of the present invention.
FIG. 142 is an explanatory diagram of a method for driving a display panel of the present invention.
FIG. 143 is an explanatory diagram of a method for driving a display panel of the present invention.
FIG. 144 is an explanatory diagram of a method for driving a display panel of the present invention.
FIG. 145 is an explanatory diagram of a method for driving a display panel of the present invention.
FIG. 146 is an explanatory diagram of a method for driving a display panel of the present invention.
FIG. 147 is an explanatory diagram of a display device of the present invention.
FIG. 148 is an explanatory diagram of a display device of the present invention.
FIG. 149 is an explanatory diagram of a display device of the present invention.
FIG. 150 is an explanatory diagram of a display device of the present invention.
FIG. 151 is an explanatory diagram of a display device of the present invention.
FIG. 152 is an explanatory diagram of a display device of the present invention.
FIG. 153 is an explanatory diagram of a display device of the present invention.
FIG. 154 is an explanatory diagram of a display device of the present invention.
FIG. 155 is an explanatory diagram of a display device of the present invention.
FIG. 156 is an explanatory diagram of a display device of the present invention.
FIG. 157 is an explanatory diagram of a display device of the present invention.
FIG. 158 is an explanatory diagram of a display device of the present invention.
FIG. 159 is an explanatory diagram of a display device of the present invention.
FIG. 160 is an explanatory diagram of a display device of the present invention.
FIG. 161 is an explanatory diagram of a display device of the present invention.
FIG. 162 is an explanatory diagram of a display device of the present invention.
FIG. 163 is an explanatory diagram of a source driver IC (circuit) of the present invention.
FIG. 164 is an explanatory diagram of a source driver IC (circuit) of the present invention.
FIG. 165 is an explanatory diagram of a source driver IC (circuit) of the present invention.
FIG. 166 is an explanatory diagram of a source driver IC (circuit) of the present invention.
FIG. 167 is an explanatory diagram of a source driver IC (circuit) of the present invention.
FIG. 168 is an explanatory diagram of a source driver IC (circuit) of the present invention.
FIG. 169 is an explanatory diagram of a source driver IC (circuit) of the present invention.
FIG. 170 is an explanatory diagram of a source driver IC (circuit) of the present invention.
FIG. 171 is an explanatory diagram of a source driver IC (circuit) of the present invention.
FIG. 172 is an explanatory diagram of a source driver IC (circuit) of the present invention.
FIG. 173 is an explanatory diagram of a display device of the present invention.
FIG. 174 is an explanatory diagram of a display device of the present invention.
FIG. 175 is an explanatory diagram of a source driver IC (circuit) of the present invention.
FIG. 176 is an explanatory diagram of a source driver IC (circuit) of the present invention.
FIG. 177 is an explanatory diagram of a power supply circuit of the present invention.
FIG. 178 is an explanatory diagram of a power supply circuit of the present invention.
FIG. 179 is an explanatory diagram of a power supply circuit of the present invention.
FIG. 180 is an explanatory diagram of a power supply circuit of the present invention.
FIG. 181 is an explanatory diagram of a power supply circuit of the present invention.
FIG. 182 is an explanatory diagram of a power supply circuit of the present invention.
FIG. 183 is an explanatory diagram of a power supply circuit of the present invention.
FIG. 184 is an explanatory diagram of a source driver IC (circuit) of the present invention.
FIG. 185 is an explanatory diagram of a source driver IC (circuit) of the present invention.
FIG. 186 is an explanatory diagram of a source driver IC (circuit) of the present invention.
FIG. 187 is an explanatory diagram of a source driver IC (circuit) of the present invention.
FIG. 188 is an explanatory diagram of a source driver IC (circuit) of the present invention.
FIG. 189 is an explanatory diagram of a source driver IC (circuit) of the present invention.
FIG. 190 is an explanatory diagram of a source driver IC (circuit) of the present invention.
FIG. 191 is an explanatory diagram of a source driver IC (circuit) of the present invention.
FIG. 192 is an explanatory diagram of a source driver IC (circuit) of the present invention.
FIG. 193 is an explanatory diagram of a source driver IC (circuit) of the present invention.
FIG. 194 is an explanatory diagram of a display device of the present invention.
FIG. 195 is an explanatory diagram of a display device of the present invention.
FIG. 196 is an explanatory diagram of a display device of the present invention.
FIG. 197 is an explanatory diagram of a display device of the present invention.
FIG. 198 is an explanatory diagram of a display device of the present invention.
FIG. 199 is an explanatory diagram of a display device of the present invention.
FIG. 200 is an explanatory diagram of a display device of the present invention.
FIG. 201 is an explanatory diagram of a display device of the present invention.
FIG. 202 is an explanatory diagram of a display device of the present invention.
FIG. 203 is an explanatory diagram of a display device of the present invention.
FIG. 204 is an explanatory diagram of a display device of the present invention.
FIG. 205 is an explanatory diagram of a display device of the present invention.
FIG. 206 is an explanatory diagram of a display device of the present invention.
FIG. 207 is an explanatory diagram of a display device of the present invention.
FIG. 208 is an explanatory diagram of a display device of the present invention.
FIG. 209 is an explanatory diagram of a display device of the present invention.
FIG. 210 is an explanatory diagram of a display device of the present invention.
FIG. 211 is an explanatory diagram of a display device of the present invention.
FIG. 212 is an explanatory diagram of a display device of the present invention.
FIG. 213 is an explanatory diagram of a source driver IC (circuit) of the present invention.
FIG. 214 is an explanatory diagram of a source driver IC (circuit) of the present invention.
FIG. 215 is an explanatory diagram of a source driver IC (circuit) of the present invention.
FIG. 216 is an explanatory diagram of a source driver IC (circuit) of the present invention.
FIG. 217 is an explanatory diagram of a source driver IC (circuit) of the present invention.
FIG. 218 is an explanatory diagram of a source driver IC (circuit) of the present invention.
FIG. 219 is an explanatory diagram of a source driver IC (circuit) of the present invention.
FIG. 220 is an explanatory diagram of a source driver IC (circuit) of the present invention.
FIG. 221 is an explanatory diagram of a source driver IC (circuit) of the present invention.
FIG. 222 is an explanatory diagram of a source driver IC (circuit) of the present invention.
FIG. 223 is an explanatory diagram of a display device of the present invention.
FIG. 224 is an explanatory diagram of a display device of the present invention.
FIG. 225 is an explanatory diagram of a display device of the present invention.
FIG. 226 is an explanatory diagram of a display device of the present invention.
FIG. 227 is an explanatory diagram of a display device of the present invention.
FIG. 228 is an explanatory diagram of a display device of the present invention.
FIG. 229 is an explanatory diagram of a source driver IC (circuit) of the present invention.
FIG. 230 is an explanatory diagram of a source driver IC (circuit) of the present invention.
FIG. 231 is an explanatory diagram of a source driver IC (circuit) of the present invention.
FIG. 232 is an explanatory diagram of a source driver IC (circuit) of the present invention.
FIG. 233 is an explanatory diagram of a source driver IC (circuit) of the present invention.
FIG. 234 is an explanatory diagram of a source driver IC (circuit) of the present invention.
FIG. 235 is an explanatory diagram of a drive circuit of the present invention.
FIG. 236 is an explanatory diagram of a source driver IC (circuit) of the present invention.
FIG. 237 is an explanatory diagram of a source driver IC (circuit) of the present invention.
FIG. 238 is an explanatory diagram of a source driver IC (circuit) of the present invention.
FIG. 239 is an explanatory diagram of a driving method according to the present invention.
FIG. 240 is an explanatory diagram of a driving method according to the present invention.
FIG. 241 is an explanatory diagram of a driving method according to the present invention.
FIG. 242 is an explanatory diagram of a driving method according to the present invention.
FIG. 243 is an explanatory diagram of a driving method according to the present invention.
FIG. 244 is an explanatory diagram of a driving method according to the present invention.
FIG. 245 is an explanatory diagram of a source driver IC (circuit) of the present invention.
FIG. 246 is an explanatory diagram of a source driver IC (circuit) of the present invention.
FIG. 247 is an explanatory diagram of a source driver IC (circuit) of the present invention.
FIG. 248 is an explanatory diagram of a source driver IC (circuit) of the present invention.
FIG. 249 is an explanatory diagram of a source driver IC (circuit) of the present invention.
FIG. 250 is an explanatory diagram of a source driver IC (circuit) of the present invention.
FIG. 251 is an explanatory diagram of a source driver IC (circuit) of the present invention.
FIG. 252 is an explanatory diagram of a source driver IC (circuit) of the present invention.
FIG. 253 is an explanatory diagram of a source driver IC (circuit) of the present invention.
FIG. 254 is an explanatory diagram of a source driver IC (circuit) of the present invention.
FIG. 255 is an explanatory diagram of a source driver IC (circuit) of the present invention.
FIG. 256 is an explanatory diagram of a source driver IC (circuit) of the present invention.
FIG. 257 is an explanatory diagram of a source driver IC (circuit) of the present invention.
FIG. 258 is an explanatory diagram of a source driver IC (circuit) of the present invention.
FIG. 259 is an explanatory diagram of a display panel of the present invention.
FIG. 260 is an explanatory diagram of a display panel of the present invention.
FIG. 261 is an explanatory diagram of a display panel of the present invention.
FIG. 262 is an explanatory diagram of a display panel of the present invention.
FIG. 263 is an explanatory diagram of a display panel of the present invention.
FIG. 264 is an explanatory diagram of a display panel of the present invention.
FIG. 265 is an explanatory diagram of a display panel of the present invention.
FIG. 266 is an explanatory diagram of a display panel of the present invention.
FIG. 267 is an explanatory diagram of a display panel of the present invention.
FIG. 268 is an explanatory diagram of a display panel of the present invention.
FIG. 269 is an explanatory diagram of a display panel of the present invention.
FIG. 270 is an explanatory diagram of a display panel of the present invention.
FIG. 271 is an explanatory diagram of a display panel of the present invention.
FIG. 272 is an explanatory diagram of a display panel of the present invention.
FIG. 273 is an explanatory diagram of a display panel of the present invention.
FIG. 274 is an explanatory diagram of a display panel of the present invention.
FIG. 275 is an explanatory diagram of a display panel of the present invention.
FIG. 276 is an explanatory diagram of a display panel of the present invention.
FIG. 277 is an explanatory diagram of a display panel of the present invention.
FIG. 278 is an explanatory diagram of a method for driving a display panel of the present invention.
FIG. 279 is an explanatory diagram of a display panel driving method of the present invention.
FIG. 280 is an explanatory diagram of a method for driving a display panel of the present invention.
FIG. 281 is an explanatory diagram of a method for driving a display panel of the present invention.
FIG. 282 is an explanatory diagram of a method for driving a display panel of the present invention.
FIG. 283 is an explanatory diagram of a display panel driving method of the present invention.
FIG. 284 is an explanatory diagram of a method for driving a display panel of the present invention.
FIG. 285 is an explanatory diagram of a display panel driving method of the present invention.
FIG. 286 is an explanatory diagram of a display panel driving method of the present invention.
FIG. 287 is an explanatory diagram of a method for driving a display panel of the present invention.
FIG. 288 is an explanatory diagram of a method for driving a display panel of the present invention.
FIG. 289 is an explanatory diagram of a method for driving a display panel of the present invention.
FIG. 290 is an explanatory diagram of a method for driving a display panel of the present invention.
FIG. 291 is an explanatory diagram of a method for driving a display panel of the present invention.
FIG. 292 is an explanatory diagram of a method for driving a display panel of the present invention.
FIG. 293 is an explanatory diagram of a method for driving a display panel of the present invention.
FIG. 294 is an explanatory diagram of a display panel driving method of the present invention.
FIG. 295 is an explanatory diagram of a method for driving a display panel of the present invention.
FIG. 296 is an explanatory diagram of a method for driving a display panel of the present invention.
FIG. 297 is an explanatory diagram of a method for driving a display panel of the present invention.
FIG. 298 is an explanatory diagram of a method for driving a display panel of the present invention.
FIG. 299 is an explanatory diagram of a source driver IC (circuit) of the present invention.
FIG. 300 is an explanatory diagram of a source driver IC (circuit) of the present invention.
FIG. 301 is an explanatory diagram of a source driver IC (circuit) of the present invention.
FIG. 302 is an explanatory diagram of a source driver IC (circuit) of the present invention.
FIG. 303 is an explanatory diagram of a source driver IC (circuit) of the present invention.
FIG. 304 is an explanatory diagram of a source driver IC (circuit) of the present invention.
FIG. 305 is an explanatory diagram of a source driver IC (circuit) of the present invention.
FIG. 306 is an explanatory diagram of a source driver IC (circuit) of the present invention.
FIG. 307 is an explanatory diagram of a source driver IC (circuit) of the present invention.
FIG. 308 is an explanatory diagram of a source driver IC (circuit) of the present invention.
FIG. 309 is an explanatory diagram of a source driver IC (circuit) of the present invention.
FIG. 310 is an explanatory diagram of a method for driving a display panel of the present invention.
FIG. 311 is an explanatory diagram of a method for driving a display panel of the present invention.
FIG. 312 is an explanatory diagram of a method for driving a display panel of the present invention.
FIG. 313 is an explanatory diagram of a source driver IC (circuit) of the present invention.
FIG. 314 is an explanatory diagram of a source driver IC (circuit) of the present invention.
FIG. 315 is an explanatory diagram of a source driver IC (circuit) of the present invention.
FIG. 316 is an explanatory diagram of a source driver IC (circuit) of the present invention.
FIG. 317 is an explanatory diagram of a source driver IC (circuit) of the present invention.
FIG. 318 is an explanatory diagram of a source driver IC (circuit) of the present invention.
FIG. 319 is an explanatory diagram of a source driver IC (circuit) of the present invention.
FIG. 320 is an explanatory diagram of a source driver IC (circuit) of the present invention.
FIG. 321 is an explanatory diagram of a source driver IC (circuit) of the present invention.
FIG. 322 is an explanatory diagram of a source driver IC (circuit) of the present invention.
FIG. 323 is an explanatory diagram of a source driver IC (circuit) of the present invention.
FIG. 324 is an explanatory diagram of a method for driving a display panel of the present invention.
FIG. 325 is an explanatory diagram of a display panel driving method of the present invention.
FIG. 326 is an explanatory diagram of a display panel driving method of the present invention.
FIG. 327 is an explanatory diagram of a source driver IC (circuit) of the present invention.
FIG. 328 is an explanatory diagram of a source driver IC (circuit) of the present invention.
FIG. 329 is an explanatory diagram of a source driver IC (circuit) of the present invention.
FIG. 330 is an explanatory diagram of a source driver IC (circuit) of the present invention.
FIG. 331 is an explanatory diagram of a source driver IC (circuit) of the present invention.
FIG. 332 is an explanatory diagram of a source driver IC (circuit) of the present invention.
FIG. 333 is an explanatory diagram of a source driver IC (circuit) of the present invention.
FIG. 334 is an explanatory diagram of a source driver IC (circuit) of the present invention.
FIG. 335 is an explanatory diagram of a source driver IC (circuit) of the present invention.
FIG. 336 is an explanatory diagram of a source driver IC (circuit) of the present invention.
FIG. 337 is an explanatory diagram of a source driver IC (circuit) of the present invention.
FIG. 338 is an explanatory diagram of a source driver IC (circuit) of the present invention.
FIG. 339 is an explanatory diagram of a source driver IC (circuit) of the present invention.
FIG. 340 is an explanatory diagram of a method for driving a display panel of the present invention.
FIG. 341 is an explanatory diagram of a method for driving a display panel of the present invention.
FIG. 342 is an explanatory diagram of a display panel driving method of the present invention.
FIG. 343 is an explanatory diagram of a display panel driving method of the present invention.
FIG. 344 is an explanatory diagram of a method for driving a display panel of the present invention.
FIG. 345 is an explanatory diagram of a method for driving a display panel of the present invention.
FIG. 346 is an explanatory diagram of a method for driving a display panel of the present invention.
FIG. 347 is an explanatory diagram of a method for driving a display panel of the present invention.
FIG. 348 is an explanatory diagram of a method for driving a display panel of the present invention.
FIG. 349 is an explanatory diagram of a method for driving a display panel of the present invention.
FIG. 350 is an explanatory diagram of a method for driving a display panel of the present invention.
FIG. 351 is an explanatory diagram of a method for driving a display panel of the present invention.
FIG. 352 is an explanatory diagram of a method for driving a display panel of the present invention.
FIG. 353 is an explanatory diagram of a display panel driving method of the present invention.
FIG. 354 is an explanatory diagram of a method for driving a display panel of the present invention.
FIG. 355 is an explanatory diagram of a method for driving a display panel of the present invention.
FIG. 356 is an explanatory diagram of the method for driving the display panel of the present invention.
FIG. 357 is an explanatory diagram of the inspection method of the present invention.
FIG. 358 is an explanatory diagram of the inspection method of the present invention.
FIG. 359 is an explanatory diagram of the inspection method of the present invention.
FIG. 360 is an explanatory diagram of the inspection method of the present invention.
FIG. 361 is an explanatory diagram of the inspection method of the present invention.
FIG. 362 is an explanatory diagram of the inspection method of the present invention.
FIG. 363 is an explanatory diagram of the inspection method of the present invention.
FIG. 364 is an explanatory diagram of the inspection method of the present invention.
FIG. 365 is an explanatory diagram of the inspection method of the present invention.
FIG. 366 is an explanatory diagram of the inspection method of the present invention.
FIG. 367 is an explanatory diagram of the inspection method of the present invention.
FIG. 368 is an explanatory diagram of the inspection method of the present invention.
FIG. 369 is an explanatory diagram of the inspection method of the present invention.
FIG. 370 is an explanatory diagram of the inspection method of the present invention.
FIG. 371 is an explanatory diagram of the inspection method of the present invention.
FIG. 372 is an explanatory diagram of the inspection method of the present invention.
FIG. 373 is an explanatory diagram of the inspection method of the present invention.
FIG. 374 is an explanatory diagram of the inspection method of the present invention.
FIG. 375 is an explanatory diagram of a display panel of the present invention.
FIG. 376 is an explanatory diagram of a display panel of the present invention.
FIG. 377 is an explanatory diagram of a display panel of the present invention.
FIG. 378 is an explanatory diagram of a display panel of the present invention.
FIG. 379 is an explanatory diagram of a display panel of the present invention.
FIG. 380 is an explanatory diagram of a display panel of the present invention.
FIG. 381 is an explanatory diagram of a display panel of the present invention.
FIG. 382 is an explanatory diagram of a display panel of the present invention.
FIG. 383 is an explanatory diagram of a display panel of the present invention.
FIG. 384 is an explanatory diagram of the inspection method of the present invention.
FIG. 385 is an explanatory diagram of the inspection method of the present invention.
FIG. 386 is an explanatory diagram of the inspection method of the present invention.
FIG. 387 is an explanatory diagram of the inspection method of the present invention.
FIG. 388 is an explanatory diagram of the inspection method of the present invention.
FIG. 389 is an explanatory diagram of the inspection method of the present invention.
FIG. 390 is an explanatory diagram of the inspection method of the present invention.
FIG. 391 is an explanatory diagram of the inspection method of the present invention.
FIG. 392 is an explanatory diagram of the inspection method of the present invention.
FIG. 393 is an explanatory diagram of the inspection method of the present invention.
FIG. 394 is an explanatory diagram of the inspection method of the present invention.
FIG. 395 is an explanatory diagram of the inspection method of the present invention.
FIG. 396 is an explanatory diagram of the inspection method of the present invention.
FIG. 397 is an explanatory diagram of the inspection method of the present invention.
FIG. 398 is an explanatory diagram of the inspection method of the present invention.
FIG. 399 is an explanatory view of the inspection method of the present invention.
FIG. 400 is an explanatory diagram of the inspection method of the present invention.
FIG. 401 is an explanatory diagram of the inspection method of the present invention.
FIG. 402 is an explanatory diagram of a display device of the present invention.
FIG. 403 is an explanatory diagram of a display device of the present invention.
FIG. 404 is an explanatory diagram of a display device of the present invention.
FIG. 405 is an explanatory diagram of a display device of the present invention.
FIG. 406 is an explanatory diagram of a display device of the present invention.
FIG. 407 is an explanatory diagram of a display device of the present invention.
FIG. 408 is an explanatory diagram of a display device of the present invention.
FIG. 409 is an explanatory diagram of a display device of the present invention.
FIG. 410 is an explanatory diagram of a display device of the present invention.
FIG. 411 is an explanatory diagram of a display device of the present invention.
FIG. 412 is an explanatory diagram of a display device of the present invention.
FIG. 413 is an explanatory diagram of a display device of the present invention.
FIG. 414 is an explanatory diagram of a display device of the present invention.
FIG. 415 is an explanatory diagram of a display device of the present invention.
FIG. 416 is an explanatory diagram of a display device of the present invention.
FIG. 417 is an explanatory diagram of a display device of the present invention.
FIG. 418 is an explanatory diagram of a display device of the present invention.
FIG. 419 is an explanatory diagram of a display device of the present invention.
FIG. 420 is an explanatory diagram of a display device of the present invention.
FIG. 421 is an explanatory diagram of a display device of the present invention.
FIG. 422 is an explanatory diagram of a display device of the present invention.
FIG. 423 is an explanatory diagram of a display device of the present invention.
FIG. 424 is an explanatory diagram of a display device of the present invention.
FIG. 425 is an explanatory diagram of a display device of the present invention.
FIG. 426 is an explanatory diagram of a display device of the present invention.
FIG. 427 is an explanatory diagram of a display device of the present invention.
FIG. 428 is an explanatory diagram of a display device of the present invention.
FIG. 429 is an explanatory diagram of a display device of the present invention.
FIG. 430 is an explanatory diagram of a display device of the present invention.
[Explanation of symbols]
11 Transistor (thin film transistor)
12 Gate driver IC (circuit)
14 Source driver IC (circuit)
15 EL (element) (light-emitting element)
16 pixels
17 Gate signal line
18 Source signal line
19 Storage capacity (additional capacitor, additional capacity)
50 Display screen
51 Write pixel (row)
52 Non-display pixels (non-display area, non-lighting area)
53 display pixels (display area, lighting area)
61 shift register
62 Inverter
63 output buffer
71 Array substrate (display panel)
72 Laser irradiation range (laser spot)
73 Positioning marker
74 Glass substrate (array substrate)
81 Control IC (circuit)
82 Power supply IC (circuit)
83 Printed circuit board
84 Flexible board
85 Sealing lid
86 Cathode wiring
87 Anode wiring (Vdd)
88 Data signal line
89 Gate control signal line
101 Embankment (rib)
102 Interlayer insulating film
104 Contact connection
105 pixel electrode
106 Cathode electrode
107 desiccant
108 λ / 4 plate
109 Polarizing plate
111 Thin film sealing film
271 Dummy pixel (row)
341 Output stage circuit
371 OR circuit
401 Lighting control line
451 Electronic volume circuit
452 SD (source-drain) short of transistor
471, 472, 473 Current source (transistor)
481 switch (on / off means)
484 current source (unit transistor)
483 Internal Wiring
491 Electronic volume
521 transistor group
531 resistance
532 decoder circuit
533 level shifter circuit
541 Raising circuit
551 D / A converter
552 operational amplifier
561 analog switch
562 inverter
581 gate wiring
631 sleep switch (reference current on / off means)
651 counter
652 NOR
653 AND
654 current output circuit
655 switch
671 Match circuit
681 I / O pad
691 Reference current circuit
692 Current control circuit
701 Temperature detection means
702 Temperature control circuit
711 Unit gate output circuit
1121 Coil (Transformer)
1122 control circuit
1123 Diode
1124 Capacitor
1125 resistance
1126 transistor
1131 Switching circuit (analog switch)
1251 Output switching circuit
1252 switch
1501 Analog switch
1502 Switch control line
1503 Connection wiring
1504 Buffer sheet (board)
1521 Inverter
1522 connection terminal
1571 antenna
1572 key
1573 case
1574 Display panel
1581 Eyepiece ring
1582 magnifying lens
1583 convex lens
1591 fulcrum (rotating part)
1592 shooting lens
1593 storage
1594 switch
1601 body
1602 Imaging unit
1603 Shutter switch
1611 Mounting frame
1612 legs
1613 Mounting base
1614 Fixed part
1731 Control electrode
1732 Video signal circuit
1733 electron emission protrusion
1734 holding circuit
1735 ON / OFF control circuit
1741 Select signal line
1742 ON / OFF signal line
1781 switch
1783 Power supply circuit
1821 switch
1831 Resistance
1901 Reference current circuit
2041 Sampling points
2051 SUM circuit
2052 Comparison circuit
2061 chassis
2062 Operation buttons
2063 Chip parts
2171 Dummy transistor
2181 Subtransistor
2351 Precharge control circuit
2361 Latch circuit
2362 Selector circuit
2363 precharge circuit
2591 level shifter circuit
2611 Cascade current connection line
2621i Current input terminal
2621o Current output terminal
2631 Base anode wire
2632 Anode wiring
2633 connection terminal
2641 Connection anode wire
2642 Common anode line
2651 contact hole
2661 Insulating film, interlayer film, insulating means
2671 Base cathode wire
2672 Input signal line
2681 Connection resin
2691 Light absorbing film
2692 resin beads
2693 sealing resin
2701 circuit forming part
2731 Gate voltage line
2772 Power supply IC control signal
2773 Gate driver circuit control signal
2951 Capacity control line (capacitor ground)
2953 Capacity control common line
3001 Selection switch (selection means, switching means)
3311 Reference voltage circuit (reference voltage generation means)
3313 transistor
3314 transistor
3321 Zener diode (reference voltage generating means)
3331 wiring
3332 buffer circuit
3333 Adjustment reference voltage output wiring
3341 Adjustment reference voltage output terminal
3351 Adjustment reference voltage input wiring
3352 Reference voltage switch (switching means, selecting means)
3353 adjustment reference voltage input terminal
3391 Magnification variable switch
3392 transistor
3431 Output buffer circuit
3433 booster circuit
3591 probe (connection means)
3592 Anode terminal electrode
3593 Voltage (current) application wiring (supply wiring, transmission means)
3594 gate driver (scan driver) control terminal (signal line, power supply line)
3601 control circuit (controller, control means)
3602 camera (optical input means, optical detection means)
3604 Ammeter (current detection means, current measurement means)
3605 Voltage source (voltage generating means, signal generating means)
3631 Source signal line terminal electrode
3633 Check terminal electrode
3634 short wiring
3661 Reference voltage circuit (voltage generation circuit, voltage generation means)
3662 Personal computer (PC) (data input means, control means, data collection means)
3663 Input circuit (data input means, voltage input means)
3721 test electrode
3731 Check terminal electrode
3751 Protection diode
3752 Internal wiring
3761 short circuit
3781 short circuit
3821 slit
3831 laser light
3991 voltmeter (voltage measuring means)
4001 Signal generator (signal generating means)
4021 Circularly polarizing plate (circularly polarizing film, polarizing plate)
4031 Backlight
4032 support member
4033 LCD panel
4041 Transparent cover (light-transmitting film, light-transmitting plate)
4042 insertion section
4051 opening
4052 Reflective film (reflective part, reflective means)
4053 light (trajectory of light)
4054 Light guide part (light guide slope)
4061 Light diffusion part (light diffusion material, light scattering part)
4081 Optical coupling layer (optical coupling material, optical coupling material)
4091 Light shielding film (reflection film)
4092 EL backlight (light generation means, surface light source)
4093 Image display area (effective display area)
4101 Light absorbing film
4102 Light absorbing bank
4111 Transistor formation area (ineffective area)
4121 beads
4123 Adhesive layer (adhesive)
4124 Embankment material
4131 Power supply wiring
4141 Voltage supply wiring
4151 convex
4191 Heatsink (heatsink)
4231 Metal plate (metal sheet, heat radiation sheet, heat radiation plate)
4251 Cathode electrode
4252 beads
4253 conductive material
4254 fixing material
4271 Air hole (air passage)
4291 Polymer EL material

Claims (1)

A gate signal line,
A source signal line,
A source driver circuit for outputting a program current,
A gate driver circuit;
EL elements arranged in a matrix,
A driving transistor for supplying a current flowing to the EL element;
A first transistor disposed in a current path of the EL element;
A second transistor forming a path for transmitting the program current to the driving transistor,
The source driver circuit outputs the program current to the source signal line,
The gate driver circuit is connected to the gate signal line,
A gate terminal of the second transistor is connected to the gate signal line;
A source terminal of the second transistor is connected to the source signal line;
A drain terminal of the second transistor is connected to a drain terminal of the driving transistor;
An EL display device, wherein the gate driver circuit selects a plurality of the gate signal lines and supplies the program current to the driving transistors of a plurality of pixels.

Images