JP2003535468A - 異なる深さのトレンチアイソレーションのための、ウェルの濡れ電流を制御する方法 - Google Patents

異なる深さのトレンチアイソレーションのための、ウェルの濡れ電流を制御する方法

Info

Publication number
JP2003535468A
JP2003535468A JP2002500431A JP2002500431A JP2003535468A JP 2003535468 A JP2003535468 A JP 2003535468A JP 2002500431 A JP2002500431 A JP 2002500431A JP 2002500431 A JP2002500431 A JP 2002500431A JP 2003535468 A JP2003535468 A JP 2003535468A
Authority
JP
Japan
Prior art keywords
trench
isolation material
depth
thickness
ion implantation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2002500431A
Other languages
English (en)
Japanese (ja)
Inventor
フルフォード,エイチ・ジム
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of JP2003535468A publication Critical patent/JP2003535468A/ja
Withdrawn legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76237Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Element Separation (AREA)
JP2002500431A 2000-05-25 2001-04-16 異なる深さのトレンチアイソレーションのための、ウェルの濡れ電流を制御する方法 Withdrawn JP2003535468A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US57876000A 2000-05-25 2000-05-25
US09/578,760 2000-05-25
PCT/US2001/012360 WO2001093311A2 (fr) 2000-05-25 2001-04-16 Procede permettant de controler les fuites de puits pour des isolations de tranches de differentes profondeurs

Publications (1)

Publication Number Publication Date
JP2003535468A true JP2003535468A (ja) 2003-11-25

Family

ID=24314194

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002500431A Withdrawn JP2003535468A (ja) 2000-05-25 2001-04-16 異なる深さのトレンチアイソレーションのための、ウェルの濡れ電流を制御する方法

Country Status (6)

Country Link
EP (1) EP1295329A2 (fr)
JP (1) JP2003535468A (fr)
KR (1) KR20030005391A (fr)
CN (1) CN1437765A (fr)
AU (1) AU2001255414A1 (fr)
WO (1) WO2001093311A2 (fr)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3621400B2 (ja) * 2003-03-03 2005-02-16 松下電器産業株式会社 固体撮像装置およびその製造方法
CN100350588C (zh) * 2003-09-25 2007-11-21 茂德科技股份有限公司 浅槽隔离区与动态随机存取存储器的结构及其制造方法
CN101414554B (zh) * 2007-10-17 2010-04-14 中芯国际集成电路制造(上海)有限公司 离子注入方法
CN101728291B (zh) * 2008-10-14 2012-03-28 中芯国际集成电路制造(上海)有限公司 浅沟槽内绝缘材料高度的确定方法
US11854688B2 (en) * 2020-02-19 2023-12-26 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR0165320B1 (ko) * 1995-12-27 1999-02-01 김광호 반도체 산화 공정의 소크타임 설정 방법
US5861338A (en) * 1997-01-21 1999-01-19 Advanced Micro Devices, Inc. Channel stop implant profile shaping scheme for field isolation
US5937287A (en) * 1997-07-22 1999-08-10 Micron Technology, Inc. Fabrication of semiconductor structures by ion implantation
US6055460A (en) * 1997-08-06 2000-04-25 Advanced Micro Devices, Inc. Semiconductor process compensation utilizing non-uniform ion implantation methodology
US5972728A (en) * 1997-12-05 1999-10-26 Advanced Micro Devices, Inc. Ion implantation feedback monitor using reverse process simulation tool
JPH11274418A (ja) * 1998-03-25 1999-10-08 Nec Corp 半導体装置

Also Published As

Publication number Publication date
AU2001255414A1 (en) 2001-12-11
CN1437765A (zh) 2003-08-20
WO2001093311A3 (fr) 2002-04-11
KR20030005391A (ko) 2003-01-17
EP1295329A2 (fr) 2003-03-26
WO2001093311A2 (fr) 2001-12-06

Similar Documents

Publication Publication Date Title
US6409879B1 (en) System for controlling transistor spacer width
US6859746B1 (en) Methods of using adaptive sampling techniques based upon categorization of process variations, and system for performing same
US8354320B1 (en) Methods of controlling fin height of FinFET devices by performing a directional deposition process
US7504838B1 (en) Methods of determining characteristics of doped regions on device wafers, and system for accomplishing same
JP2003531491A (ja) 半導体加工のための自動プロセスモニタおよび分析システム
US8796048B1 (en) Monitoring and measurement of thin film layers
US8216896B2 (en) Method of forming STI regions in electronic devices
US20150123212A1 (en) Planar metrology pad adjacent a set of fins of a fin field effect transistor device
WO2002025725A2 (fr) Dispositif a semi-conducteur et son procede de fabrication
US6365422B1 (en) Automated variation of stepper exposure dose based upon across wafer variations in device characteristics, and system for accomplishing same
US9018048B2 (en) Process for manufactuirng super-barrier rectifiers
US8580133B2 (en) Methods of controlling the etching of silicon nitride relative to silicon dioxide
JP2003535468A (ja) 異なる深さのトレンチアイソレーションのための、ウェルの濡れ電流を制御する方法
US20040152251A1 (en) Method of forming a floating gate in a flash memory device
US9818657B2 (en) Dry etching method and method of manufacturing semiconductor device
US6707562B1 (en) Method of using scatterometry measurements to control photoresist etch process
US6875680B1 (en) Methods of manufacturing transistors using dummy gate patterns
WO2002063395A1 (fr) Regulation de la dose d'exposition d'un dispositif de sauts fondee sur des variations dans une plaquette dans l'epaisseur de photoresine
CN104282564A (zh) 半导体器件和鳍式场效应晶体管的形成方法
US6110801A (en) Method of fabricating trench isolation for IC manufacture
US6589875B1 (en) Method of selectively processing wafer edge regions to increase wafer uniformity, and system for accomplishing same
US6569692B1 (en) Automated method of controlling photoresist develop time to control critical dimensions, and system for accomplishing same
US6947805B1 (en) Dynamic metrology sampling techniques for identified lots, and system for performing same
US6706631B1 (en) Method of controlling sheet resistance of metal silicide regions by controlling the salicide strip time
US6617258B1 (en) Method of forming a gate insulation layer for a semiconductor device by controlling the duration of an etch process, and system for accomplishing same

Legal Events

Date Code Title Description
A300 Application deemed to be withdrawn because no request for examination was validly filed

Free format text: JAPANESE INTERMEDIATE CODE: A300

Effective date: 20080701