EP1295329A2 - Procede permettant de controler les fuites de puits pour des isolations de tranches de differentes profondeurs - Google Patents

Procede permettant de controler les fuites de puits pour des isolations de tranches de differentes profondeurs

Info

Publication number
EP1295329A2
EP1295329A2 EP01928571A EP01928571A EP1295329A2 EP 1295329 A2 EP1295329 A2 EP 1295329A2 EP 01928571 A EP01928571 A EP 01928571A EP 01928571 A EP01928571 A EP 01928571A EP 1295329 A2 EP1295329 A2 EP 1295329A2
Authority
EP
European Patent Office
Prior art keywords
trench
isolation material
thickness
depth
ion implantation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP01928571A
Other languages
German (de)
English (en)
Inventor
H. Jim Fulford
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of EP1295329A2 publication Critical patent/EP1295329A2/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76237—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior

Definitions

  • TECHNICAL FIELD This invention is generally directed to the field of semiconductor processing, and, more particularly, to a method of controlling well leakage in semiconductor devices having trench isolations of differing depths.
  • Modern integrated circuit devices are comprised of millions of semiconductor devices, e.g., transistors, formed above a semiconducting substrate, such as silicon. These devices are very densely packed, i.e., there is little space between them. These devices, or groups of devices, must be electrically isolated from other devices for the devices to perform their intended functions. Moreover, if the devices are not properly isolated, a variety of malfunctions may occur, e.g., short circuit paths may be established, etc.
  • shallow trench isolations are typically formed by etching a trench in the semiconductor substrate and, thereafter, filling the trench with an isolation material, e.g., an insulator, such as silicon dioxide, silicon oxynitride, silicon nitride, or other like materials.
  • an isolation material e.g., an insulator, such as silicon dioxide, silicon oxynitride, silicon nitride, or other like materials.
  • an ion implantation process is typically performed to implant dopant atoms through the trench isolations and into the substrate beneath the trench isolations.
  • the purpose of this implant process is to help insure that the semiconductor device is properly isolated. In short, this implant helps to prevent the unwanted migration of electrons beyond certain defined boundaries.
  • the type of dopant atoms used, as well as the various energy levels used in the ion implantation process, will vary depending upon the device under construction.
  • the channel-stop implant may be comprised of a P-type dopant material, such as boron.
  • the channel-stop implant may be comprised of an N-type dopant material, such as arsenic or phosphorous.
  • the implantation process is performed in such a manner that the peak concentration of the channel-stop implant is at or slightly below the bottom of the trench isolation.
  • subsequent heat treatment processes may cause the dopant atoms to migrate to some degree.
  • the parameters of the implant process used to form the channel-stop implant is based upon an assumed trench depth and/or thickness of the isolation material through which the channel-stop implant will be performed. However, a variety of manufacturing variations may adversely impact the formation of acceptable, or at least more effective, channel-stop implants.
  • the trench depth, as formed may be greater or less than anticipated, due to operator error, variations within the etching tool used to form the trench, etc.
  • the thickness of the isolation material formed in the trench through which the channel-stop implant process will be performed may be thicker or thinner than anticipated due to errors in polishing or in forming the isolation material, etc.
  • the variations, if not accounted for, may lead to the formation of less effective channel-stop implants, and, thus, less effective isolation of semiconductor devices.
  • the trench is formed deeper than anticipated and/or the thickness of the isolation material in the trench is greater than anticipated, performing a channel-stop implant process based upon assumed design parameters for the trench depth and thickness of the isolation material will result in an implant that does not penetrate into the substrate as deeply as would otherwise be desired.
  • the trench is formed too shallow and/or the thickness of the isolation material is less than anticipated, the resulting channel-stop implant may be formed deeper in the substrate than would otherwise be desired.
  • proper formation of channel-stop implants becomes even more important in modern semiconductor fabrication where the width of the trench isolation is reduced as integrated circuit devices become more densely packed.
  • the present invention is directed to a method of forming a semiconductor device that minimizes or reduces some or all of the aforementioned problems.
  • the present invention is directed to a method of controlling well leakage for trench isolations of differing depths.
  • the method comprises fonning a trench in a semiconducting substrate and forming an isolation material in the trench.
  • the method further comprises determining at least one of the depth of the trench and the thickness of the trench isolation material and detennining an energy level for an ion implantation process to be performed through the isolation material based upon at least one of the determined depth of the trench and the determined thickness of the isolation material.
  • Figure 1 is a cross-sectional view of an illustrative prior art semiconductor device formed above a semiconducting substrate
  • Figure 2 is an enlarged cross-sectional view of one illustrative embodiment of a trench isolation structure
  • Figure 3 is a flowchart depicting one illustrative embodiment of the present invention.
  • Figure 4 depicts an illustrative embodiment of a system that may be used with the present invention..
  • the various regions and structures of a semiconductor device are depicted in the drawings as having very precise, sharp configurations and profiles, those skilled in the art recognize that, in reality, these regions and structures are not as precise as indicated in the drawings. Additionally, the relative sizes of the various features depicted in the drawings may be exaggerated or reduced as compared to the size of those feature sizes on fabricated devices. Nevertheless, the attached drawings are included to describe and explain illustrative examples of the present invention. In general, the present invention is directed to a method of controlling well leakage for trench isolations of differing depths.
  • an illustrative semiconductor device 12 is formed above a surface 11 of a semiconducting substrate 10.
  • the device 12 is formed within an active area 13 in the substrate 10 that is defined by the trench isolation 21.
  • the illustrative semiconductor device 12 depicted in Figure 1 is an NMOS transistor comprised of a gate insulation layer 16, a gate electrode 14, sidewall spacers 20 and source/drain regions 18.
  • the various components of the illustrative transistor depicted in Figure 1 may be formed by a variety of techniques, and they may be comprised of a variety of different materials. Thus, neither the particular technique used to form the illustrative semiconductor device 12, nor the materials or construction of the device 12, should not be considered a limitation of the present invention.
  • trench isolations 21 are formed in the substrate 10.
  • Figure 2 is an enlarged cross-sectional view of an illustrative trench isolation 21.
  • a trench 22 is formed in the substrate 10 by an etching process, such as an anisotropic etching process.
  • the trench 22 has a bottom 28 that defines the depth of the trench 22.
  • the width, depth and shape of the trench 22 may vary depending upon the device under construction. Thus, the particular configuration, width and depth of the trench 22 depicted herein should not be considered a limitation of the present invention unless it is specifically set forth in the appended claims.
  • an isolation material 24 is formed in the trench 22. This may be accomplished by a variety of techniques, e.g., depositing or growing a layer of material across the entire surface 11 of the substrate 10 and in the trench 22.
  • the trench isolation material 24 may be comprised of a variety of materials that are suitable to perform the function of isolating the semiconductor device, e.g., an oxide, an oxynitride, a nitride, silicon dioxide, silicon oxynitride, silicon nitride, etc.
  • a chemical mechanical polishing operation may be performed to planarize a surface 23 of the trench isolation material 24 such that it is substantially planar with the surface 11 of the substrate 10.
  • a planarization operation may be performed such that the surface 23 of the isolation material 24 is approximately planar with the surface of another process layer (not shown) that was previously formed above the surface of the substrate 10.
  • the isolation material 24 has a top surface 23 that is approximately planar with the surface 11 of the substrate 10.
  • the top surface 23 of the isolation material 24 may extend above the surface 11 of the substrate 10 when the fonnation of the trench isolation 21 is complete.
  • an ion implantation process is used to form schematically depicted channel-stop implants 26, as shown in Figure 2.
  • a masking layer 31, e.g., photoresist, is formed on the substrate 10 and patterned to expose the trench isolation 21 to the ion implantation process 30.
  • the dopant atoms used to form the channel-stop implant 26 will vary, depending upon the type of device under construction, boron, phosphorous, arsenic, etc.
  • the depth of the implant and, in particular, the depth of the peak concentration of the channel-stop implant will vary, depending upon the depth of the trench 22 and the thickness of the isolation material 24 through which the ion implantation process will be performed to form the channel-stop implant.
  • variations in the trench depth and/or the thickness of the isolation material 24 are determined, and that information is used to vary the energy level of the ion implantation process used to fonn the channel-stop implants 26.
  • the information regarding the depth of the trench 22 and/or the thickness of the isolation material 24 may be fed-forward and used to vary the energy level of the ion implantation process used to form the channel-stop implants 26. This may be done on a lot-by-lot basis or on a wafer-by-wafer basis.
  • the energy level for the ion implantation process may be increased relative to what it would have otherwise been had the depth of the trench 22 and/or the thickness of the isolation material 24 been as anticipated. Conversely, if it is determined that the trench 22 is shallower than anticipated, or that the isolation material 24 is thinner than anticipated, the energy level of the ion implantation process may be reduced.
  • Figure 3 depicts one illustrative embodiment of the present invention in flowchart form.
  • the method of the present invention comprises forming a trench 22 in a semiconducting substrate, as indicated at block 32, and forming an isolation material 24 in the trench 22, as indicated at block 34.
  • the method further comprises determining at least one of the depth of the trench 22 and the thickness of the isolation material
  • the step of forming the trench 22, as indicated at block 32 may be performed by a variety of processes, e.g., an anisotropic etching process. Moreover, the resulting trench 22 may take any shape, and it may have very low or high aspect ratios.
  • Forming the trench isolation material 24, as indicated at block 34 may also.be accomplished by a variety of techniques, e.g., deposition, thermal growth, etc.
  • the trench isolation material 24 may be comprised of a variety of materials, e.g., an oxide, an oxynitride, etc.
  • determining the depth of the trench 22 may be accomplished by measuring the depth of the trench 22 using a metrology tool, such as an alpha step system tool. With respect to the illustrative embodiment of the trench 22 depicted in Figure 2, the depth of the trench 22 would be considered to be the approximate distance between the surface 11 of the substrate 10 and the bottom surface 28 of the trench 22.
  • the thickness of the isolation material 24 may also be determined, as indicated at block 36, using a metrology tool, such as an ellipsometer, a.Thermawave tool. The thickness of interest with respect to the isolation material 24
  • the thickness dimension of interest would be the dimension from the surface 23 of the isolation material 24 to the bottom surface 28 of the trench 22. Measuring the depth of the trench 22 and/or the thickness of the isolation material 24 may be done on a representative basis, i.e., sufficient measurements may be made to satisfy the user as to the accuracy of the measurements. The measurements may be used for subsequent processing of wafers on a lot-by-lot basis or on a wafer-by-wafer basis.
  • Determining an implant energy for the channel-stop ion implantation process may be accomplished by a variety of techniques. For example, a database may be developed that correlates the determined depth of the trench 22 and/or the determined thickness of the isolation material 24 to a corresponding energy level for the channel-stop implantation process. Alternatively, the energy level could be calculated based upon the determined depth off the trench 22 and/or the thickness of the isolation material 24. Other methodologies are also possible. Thereafter, the method continues with performing the ion implantation process through the isolation material 24 at the determined energy level. In one embodiment of the present invention, the energy level of the channel-stop implantation process varies or is adjusted, depending upon the depth of the trench 22 and/or the thickness of the isolation material 24.
  • a system 50 for processing wafers 52 is comprised of a metrology tool 44, an automatic process controller 48, and an ion implantation tool 46.
  • the metrology tool 44 is used to measure the depth of the trench 22 and/or the thickness of the isolation material 24.
  • the metrology tool 44 may be any type of device capable of performing the desired measurements.
  • the automatic process controller 48 interfaces with the metrology tool 44 and the ion implantation tool 46.
  • the controller 48 may be used to determine or control the energy level of the ion implantation process performed in the ion implantation tool 46, depending upon the depth of the trench 22 and/or the thickness of the isolation material 24, as determined by the metrology tool 44. That is, the depth of the trench 22 and/or the thickness of the isolation material 24 is fed-forward to the controller 48, and the energy level of the channel-stop implant process performed in the ion implant tool 46 is controlled based upon at least one of those parameters.
  • the controller 48 may be a stand-alone device, it may be part of a system, or it may be part of the ion implant tool 46 or another process tool, such as a chemical mechanical polishing tool.
  • the metrology tool 44 may be a stand-alone device or system, or it may be incorporated into the ion implant tool 46, another processing tool, e.g., a chemical mechanical polishing tool, an etch tool, etc., or a system containing both.
  • the automatic process controller 48 is a computer programmed with software to implement the functions described. However, as will be appreciated by those of ordinary skill in the art, a hardware controller (not shown) designed to implement the particular functions may also be used. Portions of the invention and corresponding detailed description are presented in terms of software, or algorithms and symbolic representations of operations on data bits within a computer memory. These descriptions and representations are the ones by which those of ordinary skill in the art effectively convey the substance of their work to others of ordinary skill in the art. An algorithm, as the tenn is used here, and as it is used generally, is conceived to be a self-consistent sequence, of steps leading to a desired result. The steps are those requiring physical manipulations of physical quantities.
  • these quantities take the form of optical, electrical, or magnetic signals capable of being stored, transferred, combined, compared, and otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like. It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities.
  • terms such as “processing” or “computing” or “calculating” or “determining” or “displaying” or the like refer to the actions and processes of a computer system, or similar electronic computing device, that manipulates and transforms data represented as physical, electronic quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage, transmission or display devices.
  • An exemplary software system capable of being adapted to perform the functions of the automatic process controller 48, as described, is the ObjectSpace Catalyst system offered by ObjectSpace, Inc.
  • the ObjectSpace Catalyst system uses Semiconductor Equipment and Materials International (SEMI) Computer Integrated Manufacturing (CIM) Framework compliant system technologies, and is based on the Advanced Process Control (APC) Framework.
  • SEMI Semiconductor Equipment and Materials International
  • CIM Computer Integrated Manufacturing
  • API Advanced Process Control
  • CIM SEMI E81-0699 - Provisional Specification for CIM Framework Domain Architecture
  • APC SEMI E93-0999 - Provisional Specification for CIM Framework Advanced Process Control Component

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Element Separation (AREA)

Abstract

La présente invention concerne un procédé qui consiste à former une tranchée (22) dans un substrat (10) semiconducteur, et à former un matériau (24) d'isolation dans cette tranchée. Ce procédé consiste aussi à déterminer au moins la profondeur de cette tranchée (22) ou l'épaisseur de ce matériau (24) d'isolation de tranchée, et à déterminer un niveau d'énergie pour un processus d'implantation ionique à réaliser à travers ce matériau (24) d'isolation, fondé au moins sur cette profondeur déterminées de tranchée (22) ou sur cette épaisseur déterminée de ce matériau (24) d'isolation.
EP01928571A 2000-05-25 2001-04-16 Procede permettant de controler les fuites de puits pour des isolations de tranches de differentes profondeurs Withdrawn EP1295329A2 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US57876000A 2000-05-25 2000-05-25
US578760 2000-05-25
PCT/US2001/012360 WO2001093311A2 (fr) 2000-05-25 2001-04-16 Procede permettant de controler les fuites de puits pour des isolations de tranches de differentes profondeurs

Publications (1)

Publication Number Publication Date
EP1295329A2 true EP1295329A2 (fr) 2003-03-26

Family

ID=24314194

Family Applications (1)

Application Number Title Priority Date Filing Date
EP01928571A Withdrawn EP1295329A2 (fr) 2000-05-25 2001-04-16 Procede permettant de controler les fuites de puits pour des isolations de tranches de differentes profondeurs

Country Status (6)

Country Link
EP (1) EP1295329A2 (fr)
JP (1) JP2003535468A (fr)
KR (1) KR20030005391A (fr)
CN (1) CN1437765A (fr)
AU (1) AU2001255414A1 (fr)
WO (1) WO2001093311A2 (fr)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3621400B2 (ja) * 2003-03-03 2005-02-16 松下電器産業株式会社 固体撮像装置およびその製造方法
CN100350588C (zh) * 2003-09-25 2007-11-21 茂德科技股份有限公司 浅槽隔离区与动态随机存取存储器的结构及其制造方法
CN101414554B (zh) * 2007-10-17 2010-04-14 中芯国际集成电路制造(上海)有限公司 离子注入方法
CN101728291B (zh) * 2008-10-14 2012-03-28 中芯国际集成电路制造(上海)有限公司 浅沟槽内绝缘材料高度的确定方法
US11854688B2 (en) * 2020-02-19 2023-12-26 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR0165320B1 (ko) * 1995-12-27 1999-02-01 김광호 반도체 산화 공정의 소크타임 설정 방법
US5861338A (en) * 1997-01-21 1999-01-19 Advanced Micro Devices, Inc. Channel stop implant profile shaping scheme for field isolation
US5937287A (en) * 1997-07-22 1999-08-10 Micron Technology, Inc. Fabrication of semiconductor structures by ion implantation
US6055460A (en) * 1997-08-06 2000-04-25 Advanced Micro Devices, Inc. Semiconductor process compensation utilizing non-uniform ion implantation methodology
US5972728A (en) * 1997-12-05 1999-10-26 Advanced Micro Devices, Inc. Ion implantation feedback monitor using reverse process simulation tool
JPH11274418A (ja) * 1998-03-25 1999-10-08 Nec Corp 半導体装置

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO0193311A2 *

Also Published As

Publication number Publication date
AU2001255414A1 (en) 2001-12-11
JP2003535468A (ja) 2003-11-25
CN1437765A (zh) 2003-08-20
WO2001093311A3 (fr) 2002-04-11
KR20030005391A (ko) 2003-01-17
WO2001093311A2 (fr) 2001-12-06

Similar Documents

Publication Publication Date Title
US6746308B1 (en) Dynamic lot allocation based upon wafer state characteristics, and system for accomplishing same
US6409879B1 (en) System for controlling transistor spacer width
US6432798B1 (en) Extension of shallow trench isolation by ion implantation
US7504838B1 (en) Methods of determining characteristics of doped regions on device wafers, and system for accomplishing same
US6365422B1 (en) Automated variation of stepper exposure dose based upon across wafer variations in device characteristics, and system for accomplishing same
US20040241917A1 (en) Method of forming a substrate contact for an SOI semiconductor device
US8580133B2 (en) Methods of controlling the etching of silicon nitride relative to silicon dioxide
EP1295329A2 (fr) Procede permettant de controler les fuites de puits pour des isolations de tranches de differentes profondeurs
US6754553B2 (en) Implant monitoring using multiple implanting and annealing steps
US20160148851A1 (en) Dry etching method and method of manufacturing semiconductor device
US8673696B2 (en) SOI semiconductor device comprising a substrate diode with reduced metal silicide leakage
US8530247B2 (en) Control of implant pattern critical dimensions using STI step height offset
US7494872B2 (en) Field effect transistor having a doped gate electrode with reduced gate depletion and method of forming the transistor
US6589875B1 (en) Method of selectively processing wafer edge regions to increase wafer uniformity, and system for accomplishing same
US6617258B1 (en) Method of forming a gate insulation layer for a semiconductor device by controlling the duration of an etch process, and system for accomplishing same
US9704765B2 (en) Method of controlling etch-pattern density and device made using such method
US20040152222A1 (en) Method of assessing lateral dopant and/or charge carrier profiles
US7033873B1 (en) Methods of controlling gate electrode doping, and systems for accomplishing same
US6706631B1 (en) Method of controlling sheet resistance of metal silicide regions by controlling the salicide strip time
US6947805B1 (en) Dynamic metrology sampling techniques for identified lots, and system for performing same
CN112017987B (zh) 半导体测试结构
US6778876B1 (en) Methods of processing substrates based upon substrate orientation
Morris et al. Technical and economic considerations for retrograde well and channel implants
EP1649506A1 (fr) Transistor a effet de champ muni d'une electrode gachette dopee presentant une depletion de gachette reduite et procede de formation dudit transistor
CN117012716A (zh) 控制晶圆栅氧化层厚度的方法及系统

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 20021125

AK Designated contracting states

Kind code of ref document: A2

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE TR

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE TR

AX Request for extension of the european patent

Extension state: AL LT LV MK RO SI

RIN1 Information on inventor provided before grant (corrected)

Inventor name: FULFORD, H. JIM

RBV Designated contracting states (corrected)

Designated state(s): DE GB

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION HAS BEEN WITHDRAWN

18W Application withdrawn

Effective date: 20040923