JP2003535468A - Method of controlling well wetting current for different depth trench isolation - Google Patents

Abstract

A method comprising: forming a trench (22) in a semiconductor substrate (10); and forming an isolation material (24) in the trench (22). The method further comprises determining at least one of the depth of the trench (22) and the thickness of the trench isolation material (24) and the determined depth of the trench (22) and the isolation material (24). Determining the energy level of the ion implantation process to be performed through the isolation material (24) based on at least one of the determined thicknesses.

Description

Detailed Description of the Invention

[0001]

【Technical field】

This invention is generally directed to the field of semiconductor processing, and more specifically,
A method for controlling well leakage current in semiconductor devices having trench isolations of different depths is directed.

[0002]

[Background technology]

Current integrated circuit devices include millions of semiconductor elements such as transistors formed on a semiconductor substrate such as silicon. These devices are very densely packed and there is little space between them. These elements or groups of elements must be electrically isolated from other elements in order for the element to perform its intended function. Moreover, if these elements are not properly isolated, various malfunctions can occur, for example, short circuit paths are established.

In order to ensure proper isolation of the device or devices, current semiconductor processes involve forming shallow trench isolations (STIs) in various areas of the substrate. These shallow trench isolations are typically performed by etching the trench in the semiconductor substrate and then filling the trench with an isolation material such as silicon dioxide, silicon oxynitride, silicon nitride, or other similar material. Form.

After the trench isolation is formed, an ion implantation process is typically performed to implant dopant atoms throughout the trench isolation and into the substrate below the trench isolation. Channel-stop
The purpose of this implantation process, sometimes referred to as stop) implantation, is to ensure that the semiconductor devices are properly isolated. That is, this injection helps prevent unwanted movement of electrons across some defined boundary. The type of dopant atoms used and the various energy levels used in the ion implantation process will vary depending on the device being constructed. For example, for an NMOS device, the channel-stop implant would include a P-type dopant material such as boron. PMOS
For devices, the channel-stop implant will include N-type dopant material such as arsenic or phosphorus.

The implantation process is intended to be performed such that the peak concentration of the channel-stop implant is at or slightly below the bottom of the trench isolation. Of course, the subsequent heat treatment may cause some movement of the dopant atoms. The parameters of the implantation process used to form the channel-stop implant are based on the assumed trench depth and / or the thickness of the isolation material through which the channel-stop implant is made. However, variations in manufacturing can adversely affect the formation of acceptable or at least more effective channel-stop implants.

[0006] For example, the depth of the formed trench may be deeper or shallower than expected due to operator error and variations in the etching tools used to form the trench. Further, the thickness of the isolation material formed in the trench through which the channel stop implant process is performed may be thicker or thinner than expected due to errors in polishing or forming the isolation material.

If this variation is not taken into account, this leads to less effective channel-stop implants and thus less effective isolation of semiconductor devices. For example, if the trench is formed deeper than expected and / or the isolation material thickness in the trench is thicker than expected, a channel-stop implant process may be performed based on hypothetical design parameters for trench depth and isolation material thickness. When done, the result is an implant that does not penetrate deeply into the substrate as would otherwise be desired. Conversely, if the trench is too shallow and / or the isolation material is thinner than expected, the resulting channel-stop implant will be formed deeper in the substrate than would otherwise be desired. Moreover, proper formation of channel-stop implants becomes even more important in current semiconductor manufacturing, where the width of trench isolation is decreasing as integrated circuit devices are more densely packed.

The present invention is directed to a method of forming a semiconductor device that minimizes or reduces some or all of the aforementioned problems.

[0009]

DISCLOSURE OF THE INVENTION

The present invention is directed to a method of controlling well leakage current for different depth trench isolations. In one embodiment, the method includes forming a trench in the semiconductor substrate and forming an isolation material in the trench. The method further includes determining at least one of a depth of the trench and a thickness of the isolation material, and through the isolation material based on at least one of the determined depth of the trench and the determined thickness of the isolation material. Determining the energy level of the ion implantation process to be performed.

The present invention will be understood by reference to the following description in conjunction with the accompanying drawings, in which like reference numerals indicate corresponding parts.

While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and will be described in detail. However, the description of specific embodiments is not intended to limit the invention to the particular shapes disclosed,
On the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.

[0012]

Modes for Carrying Out the Invention

Exemplary embodiments of the invention are described below. In the interest of clarity, not all features of an actual implementation are described in this specification. In developing such a working example, many execution-specific decisions must be made to achieve the developer's specific goals, such as compliance with system- and business-related constraints that change from execution to execution. It will also be understood that this is not the case. Further, it will be appreciated that such development efforts may be complex and time consuming, but nevertheless be a routine undertaking for those of ordinary skill in the art having the benefit of this disclosure. .

The invention will now be described with reference to FIGS. 1 to 4. Although various regions and structures of a semiconductor device are depicted in the drawings as having very precise and sharp configurations and profiles, those skilled in the art will not actually see these regions and structures as precise as shown in the drawings. I am aware of that. Moreover, the relative sizes of the various features depicted in the figures may be exaggerated or reduced in comparison to the size of those feature sizes on the manufactured device. Nevertheless, the attached drawings are included to describe and describe illustrative examples of the present invention.

In general, the invention is directed to a method of controlling well leakage current for trench isolation of different depths. As will be readily apparent to one of ordinary skill in the art upon a full reading of this application, the invention may be implemented, for example, in NMOS, PMOS, CMOS
The present invention can be applied to various techniques such as, and is easily applicable to various devices including, but not limited to, a logical device and a storage device.

As shown in FIG. 1, an exemplary semiconductor device 12 includes a surface 1 of a semiconductor substrate 10.
1 is formed on. The device 12 is formed in an active region 13 of the substrate 10 defined by a trench isolation 21. The exemplary semiconductor device 12 shown in FIG. 1 is an NMOS transistor and includes a gate insulating layer 16, a gate electrode 14, sidewall spacers 20 and source / drain regions 18. Various components of the exemplary transistor depicted in FIG. 1 may be formed by a variety of techniques and may include a variety of different materials. Therefore, neither the particular technique used to form the exemplary semiconductor device 12 nor the material and construction of the device 12 should be considered limiting of the invention.

First, a trench isolation 21 is formed in the substrate 10. Figure 2
FIG. 3 is an enlarged cross-sectional view of an exemplary trench isolation 21. In particular, the trench 22 may be formed on the substrate 10 by an etching process such as an anisotropic etching process.
Formed within. The trench 22 has a bottom portion 28 that defines the depth of the trench 22. The width, depth and shape of the trench 22 will vary depending on the device being constructed.
Therefore, the particular configurations, widths, and depths of the trenches 22 depicted herein should not be considered limiting of the present invention, unless specifically stated in the claims.

Thereafter, the isolation material 24 is formed in the trench 22. This is a variety of technologies,
This can be achieved, for example, by depositing or growing a layer of material over the surface 11 of the substrate 10 and within the trench 22. Trench isolation material 24 may include a variety of materials suitable for performing the function of isolating semiconductor devices, such as oxides, oxynitrides, nitrides, silicon dioxide, silicon oxynitride, silicon nitride, and the like. Thereafter, a chemical mechanical polishing operation is performed to perform the surface 2 of the trench isolation material 24.
3 may be planarized so that it is substantially flush with the surface 11 of the substrate 10. Alternatively, the planarization operation may be performed so that the surface 23 of the isolation material 24 is substantially flush with the surface of another previously processed layer (not shown) previously formed on the surface of the substrate 10. . In the illustrated embodiment, the isolation material 24 has a top surface 23, which is substantially flush with the surface 11 of the substrate 10. Of course, as will be appreciated by those skilled in the art, the top surface 23 of the isolation material 24 may extend above the surface 11 of the substrate 10 when the trench isolation 21 formation is complete.

After the isolation material 24 is formed in the trench 22, as indicated by arrow 30,
An ion implantation process is used to form the channel-stop implant 26 schematically depicted as shown in FIG. A masking layer 31, such as photoresist, is formed and patterned on the substrate 10 to expose the trench isolation 21 to the ion implantation process 30. The dopant atoms used to form the channel-stop implant 26 depend on the type of device being built, such as boron, phosphorus, arsenic, and so on.

As mentioned above, the implant depth, and in particular the peak concentration depth of the channel-stop implant, depends on the depth of the trench 22 and the isolation through which the ion implant process is performed to form the channel-stop implant. It depends on the thickness of the material 24. However, to ensure that the channel-stop implant 26 is more accurately located, variations in trench depth and / or thickness of the isolation material 24 are quantified and that information is used to form the channel-stop implant 26. To change the energy level of the ion implantation process used to do so. In fact, feeding forward information regarding the depth of the trench 22 and / or the thickness of the isolation material 24 and using it to vary the energy level of the ion implantation process used to form the channel-stop implant 26. You can also This may be done lot by lot or wafer by wafer.

For example, if the trench 22 is determined to be deeper than expected or the isolation material 2
If 4 is determined to be thicker than expected, the energy level for the ion implantation process should be as it should be when the depth of trench 22 and / or the thickness of isolation material 24 was as expected. Will be increased. Conversely, if it is determined that trench 22 is shallower than expected or isolation material 24 is thinner than expected, the energy level for the ion implantation process will be reduced.

FIG. 3 illustrates in flow chart form an exemplary embodiment of the present invention. As shown here, the method of the present invention forms a trench 22 in a semiconductor substrate, as shown at block 32, and forms an isolation material 24 in the trench 22, as shown at block 34. And a step of performing. The method further comprises quantifying at least one of the depth of the trench 22 and the thickness of the isolation material 24, as indicated by block 36, and at least the quantified depth of the trench 22 and the thickness of the isolation material 24. Determining the implant energy of the ion implantation process to be performed through the isolation material based on one.

As mentioned previously, the step of forming the trench 22, shown at block 32, may be performed by a variety of processes, such as an anisotropic etching process. Further, the resulting trench 22 may take any shape and may have a very low or high aspect ratio. The step of forming trench isolation material 24, shown at block 34, can also be accomplished by a variety of techniques, such as deposition, thermal growth, and the like. Further, the trench isolation material 24 may include various materials such as oxides and oxynitrides.

With respect to the step of quantifying the depth of trench 22 indicated by block 36, this may also be accomplished by quantifying the depth of trench 22 using a metrology tool such as the Alphastep system tool. You can With respect to the exemplary embodiment of trench 22 shown in FIG. 2, the depth of trench 22 would be considered to be the approximate distance between surface 11 of substrate 10 and bottom surface 28 of trench 22. The thickness of the separation material 24 may also be measured using a metrology tool such as an ellipsometer or Thermawave tool, as indicated by block 36. The intended thickness of the isolation material 24 will be the amount of isolation material through which the channel-stop implant process is performed to form the channel-stop implant 26. In the exemplary embodiment shown in FIG. 2, the thickness dimension of interest will be from the surface 23 of the isolation material 24 to the bottom surface 28 of the trench 22. The step of quantifying the depth of the trench 22 and / or the thickness of the isolation material 24 can be done on a representative basis. That is, sufficient measurements may be taken to satisfy the user regarding the accuracy of the measurements. This measurement can be used lot by lot or wafer by wafer for subsequent wafer processing.

The step of determining the implant energy for the channel-stop ion implant process can be accomplished by a variety of techniques, as indicated by block 38. For example, a quantified depth of trench 22 and / or isolation material 24.
A database may be developed that correlates the quantified thickness of the with the energy level for the channel-stop implant process. Alternatively, the energy level can be calculated based on the quantified depth of the trench 22 and / or the thickness of the isolation material 24. Other methods are possible. After this, the method continues with the ion implantation process at the energy level determined through the isolation material 24.

In one embodiment of the invention, the energy level of the channel-stop implant process is varied or tuned by the depth of trench 22 and / or the thickness of isolation material 24. An exemplary system that may be used in accordance with the present invention is shown in FIG.
Shown in. System 5 for processing a wafer 52, as shown therein
0 includes metrology tool 44, automatic process controller 48 and ion implantation tool 46. The metrology tool 44 may be used to measure the depth of the trench 22 and / or the isolation material 24.
Is used to measure the thickness of the. The measuring tool 44 may be any type of device as long as it can perform a desired measurement.

In one embodiment, automatic process controller 48 interfaces with metrology tool 44 and ion implantation tool 46. Using the controller 48 to determine or control the energy level of the ion implantation process performed in the ion implantation tool 46 by the depth of the trench 22 and / or the thickness of the isolation material 24 quantified by the metrology tool 44. You can That is, the depth of the trench 22 and / or the thickness of the isolation material 24 are fed forward to the controller 48 and the energy level of the channel-stop implant process performed in the ion implant tool 46 is at least one of those parameters. It is controlled based on. The controller 48 may be a stand-alone device, part of the system, or part of another process tool such as an ion implantation tool 46 or a chemical mechanical polishing tool. Further, metrology tool 44 may be a stand-alone device or system, or may be incorporated into a system that includes ion implantation tool 46, another processing tool such as a chemical mechanical polishing tool, an etching tool, or both. Good.

In this illustrative example, automatic process controller 48 is a computer programmed with software to perform the functions described. However,
As will be appreciated by those skilled in the art, a hardware controller (not shown) designed to perform a particular function may be used. Portions of the invention and corresponding detailed description are presented in terms of software or algorithms and symbolic representations of operations on data bits within a computer memory. These descriptions and presentations are the ones by which those of ordinary skill in the art effectively convey the substance of their work to others of ordinary skill in the art. The term algorithm, as used herein and more commonly, is considered a sequence of self-consistent steps leading to a desired result. The steps require physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of optical, electrical or magnetic signals that can be stored, transferred, combined, compared or otherwise manipulated. It has been found convenient to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, etc., primarily because of their idiomaticity.

However, it should be borne in mind that all of these terms and similar terms are associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. is there. Unless specifically stated otherwise or apparent from discussion, terms such as "processing" or "computing" or "decision" or "display" or similar terms are used in computer system registers. And data presented in memory as physical and electrical quantities,
The operation of a computer system or similar electronic computing device to manipulate and transform into computer system registers or memory or other such information storage devices, transmissions or other similar data presented as physical quantities in a display device and It refers to a process.

An exemplary software system applicable for performing the functions of the automatic process controller 48 as described is an object space catalyst provided by ObjectSpace, Inc. It is a system (ObjectSpace Catalyst system). The object space catalyst system is based on the International Semiconductor Equipment and Materials Association.
International; SEMI Computer Integrated Manufacturing
It uses system technology compliant with the Manufacturing (CIM) framework and is based on the Advanced Process Control (APC) framework. CIM (SEMI E81-0699 Provisional Specification for CIM Framework Domain Architecture) and APC (SEMI E93-0999 CI
M framework advanced process control component provisional specification) is SE
Available publicly from MI.

By using the present invention, effective trench isolation can be created while taking into account variations in trench depth and / or isolation material thickness. As a result, more effective trench isolations can be manufactured and used in current semiconductor devices.

The particular embodiments disclosed above are exemplary only, as the invention comprises:
Because it can be modified and practiced in different but equivalent ways, which will be apparent to those skilled in the art having the benefit of this teaching. Furthermore, no limitations are intended to the details of construction or design herein shown, other than as described in the claims below. It is therefore evident that the particular embodiments disclosed above may be altered or improved and all such variations are considered within the scope and spirit of the invention. Accordingly, the protection sought herein is as set forth in the claims.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of an exemplary prior art semiconductor device formed on a semiconductor substrate.

FIG. 2 is an enlarged cross-sectional view of an exemplary embodiment of a trench isolation structure.

FIG. 3 is a flow chart showing an exemplary embodiment of the present invention.

FIG. 4 is a diagram illustrating an exemplary embodiment of a system that may be used with the present invention.

─────────────────────────────────────────────────── ─── Continued front page    (81) Designated countries EP (AT, BE, CH, CY, DE, DK, ES, FI, FR, GB, GR, IE, I T, LU, MC, NL, PT, SE, TR), OA (BF , BJ, CF, CG, CI, CM, GA, GN, GW, ML, MR, NE, SN, TD, TG), AP (GH, G M, KE, LS, MW, MZ, SD, SL, SZ, TZ , UG, ZW), EA (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM), AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BY, B Z, CA, CH, CN, CR, CU, CZ, DE, DK , DM, DZ, EE, ES, FI, GB, GD, GE, GH, GM, HR, HU, ID, IL, IN, IS, J P, KE, KG, KP, KR, KZ, LC, LK, LR , LS, LT, LU, LV, MA, MD, MG, MK, MN, MW, MX, MZ, NO, NZ, PL, PT, R O, RU, SD, SE, SG, SI, SK, SL, TJ , TM, TR, TT, TZ, UA, UG, UZ, VN, YU, ZA, ZW (72) Inventor Fulford, H. Jim             Oh, United States, 78748 Texas             Austin, Woodshire Dry             Bu, 9808 F-term (reference) 5F032 AA35 AA44 AA46 AC01 BA02                       BA03 CA17 CA20 DA01 DA25                       DA33 DA44

Claims (9)

[Claims] 1. Forming a trench (22) in a semiconductor substrate (10), the trench having a depth, and forming an isolation material (24) in the trench (22). Further comprising, the isolation material (24) has a thickness, quantifying at least one of a depth of the trench (22) and a thickness of the isolation material (24), and the quantified trench (). 22. The method further comprising determining an energy level of an ion implantation process to be performed through the separation material (24) based on at least one of the depth of 22) and the thickness of the separation material (24). 2. The method of claim 1, wherein forming the trench (22) in the semiconductor substrate (10) comprises etching the trench (22) in the semiconductor substrate. 3. The step of forming a trench isolation material (24) in the trench (22) includes a trench isolation material (24) including at least one of oxide, oxynitride and nitride. The method of claim 1 including the step of forming in). 4. The step of quantifying at least one of the depth of the trench (22) and the thickness of the isolation material (24) comprises the depth of the trench (22) and the thickness of the isolation material (24). The method of claim 1, comprising measuring at least one. 5. Energy level of an ion implantation process to be performed through the isolation material (24) based on at least one of the quantified depth of the trench (22) and the thickness of the isolation material (24). Determining the energy of the ion implantation process to be performed through the isolation material (24) based on at least one of the quantified depth of the trench (22) and the thickness of the isolation material (24). The method of claim 1 including the step of calculating a level. 6. Energy level of an ion implantation process to be performed through said isolation material (24) based on at least one of said quantified depth of said trench (22) and said thickness of said isolation material (24). Determining the energy level of the ion implantation process to be performed through the isolation material (24), the quantified depth of the trench (22) and the isolation material (2).
4. The method of claim 1 including the step of 4) correlating with at least one of the thicknesses. 7. A control for controlling at least one of said quantified depth of said trench and said thickness of said isolation material to control the implantation energy of an ion implantation tool used to perform an ion implantation process through the isolation material. The method of claim 1, further comprising reporting to a container. 8. The method of claim 1, further comprising performing the ion implantation process using the determined energy level. 9. A metrology tool (44) for quantifying at least one of a depth of a trench (22) and a thickness of an isolation material (24) formed in the trench.
And a separation material (24) based on at least one of a quantified depth and thickness.
A system including a controller (48) for determining an energy level of an ion implantation process to be performed through an ion implantation tool (46) for performing the ion implantation process at the determined energy level.