WO2001093311A3 - Method of controlling well leakage for trench isolations of differing depths - Google Patents

Method of controlling well leakage for trench isolations of differing depths Download PDF

Info

Publication number
WO2001093311A3
WO2001093311A3 PCT/US2001/012360 US0112360W WO0193311A3 WO 2001093311 A3 WO2001093311 A3 WO 2001093311A3 US 0112360 W US0112360 W US 0112360W WO 0193311 A3 WO0193311 A3 WO 0193311A3
Authority
WO
WIPO (PCT)
Prior art keywords
trench
trench isolations
controlling well
differing depths
well leakage
Prior art date
Application number
PCT/US2001/012360
Other languages
French (fr)
Other versions
WO2001093311A2 (en
Inventor
H Jim Fulford
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Priority to JP2002500431A priority Critical patent/JP2003535468A/en
Priority to EP01928571A priority patent/EP1295329A2/en
Priority to AU2001255414A priority patent/AU2001255414A1/en
Publication of WO2001093311A2 publication Critical patent/WO2001093311A2/en
Publication of WO2001093311A3 publication Critical patent/WO2001093311A3/en

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76237Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Element Separation (AREA)

Abstract

A method comprising forming a trench (22) in a semiconducting substrate (10) and forming an isolation material (24) in said trench (22). The method further comprises determining at least one of the depth of said trench (22) and the thickness of said trench isolation material (24) and determining an energy level for an ion implantation process to be performed through said isolation material (24) based upon at least one of said determined depth of said trench (22) and said determined thickness of said isolation material (24).
PCT/US2001/012360 2000-05-25 2001-04-16 Method of controlling well leakage for trench isolations of differing depths WO2001093311A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2002500431A JP2003535468A (en) 2000-05-25 2001-04-16 Method of controlling well wetting current for different depth trench isolation
EP01928571A EP1295329A2 (en) 2000-05-25 2001-04-16 Method of controlling well leakage for trench isolations of differing depths
AU2001255414A AU2001255414A1 (en) 2000-05-25 2001-04-16 Method of controlling well leakage for trench isolations of differing depths

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US57876000A 2000-05-25 2000-05-25
US09/578,760 2000-05-25

Publications (2)

Publication Number Publication Date
WO2001093311A2 WO2001093311A2 (en) 2001-12-06
WO2001093311A3 true WO2001093311A3 (en) 2002-04-11

Family

ID=24314194

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/012360 WO2001093311A2 (en) 2000-05-25 2001-04-16 Method of controlling well leakage for trench isolations of differing depths

Country Status (6)

Country Link
EP (1) EP1295329A2 (en)
JP (1) JP2003535468A (en)
KR (1) KR20030005391A (en)
CN (1) CN1437765A (en)
AU (1) AU2001255414A1 (en)
WO (1) WO2001093311A2 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3621400B2 (en) * 2003-03-03 2005-02-16 松下電器産業株式会社 Solid-state imaging device and manufacturing method thereof
CN100350588C (en) * 2003-09-25 2007-11-21 茂德科技股份有限公司 Structure of shallow ridge isolation area and dynamic DASD and its mfg method
CN101414554B (en) * 2007-10-17 2010-04-14 中芯国际集成电路制造(上海)有限公司 Ion implantation method
CN101728291B (en) * 2008-10-14 2012-03-28 中芯国际集成电路制造(上海)有限公司 Method for determining height of insulating material in shallow trench
US11854688B2 (en) * 2020-02-19 2023-12-26 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2308733A (en) * 1995-12-27 1997-07-02 Samsung Electronics Co Ltd Growing an oxide film of a semiconductor device
US5861338A (en) * 1997-01-21 1999-01-19 Advanced Micro Devices, Inc. Channel stop implant profile shaping scheme for field isolation
WO1999008306A1 (en) * 1997-08-06 1999-02-18 Advanced Micro Devices, Inc. Semiconductor process compensation utilizing non-uniform ion implantation methodology
US5937287A (en) * 1997-07-22 1999-08-10 Micron Technology, Inc. Fabrication of semiconductor structures by ion implantation
EP0948044A1 (en) * 1998-03-25 1999-10-06 Nec Corporation Trench isolated wells in a semiconductor device
US5972728A (en) * 1997-12-05 1999-10-26 Advanced Micro Devices, Inc. Ion implantation feedback monitor using reverse process simulation tool

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2308733A (en) * 1995-12-27 1997-07-02 Samsung Electronics Co Ltd Growing an oxide film of a semiconductor device
US5861338A (en) * 1997-01-21 1999-01-19 Advanced Micro Devices, Inc. Channel stop implant profile shaping scheme for field isolation
US5937287A (en) * 1997-07-22 1999-08-10 Micron Technology, Inc. Fabrication of semiconductor structures by ion implantation
WO1999008306A1 (en) * 1997-08-06 1999-02-18 Advanced Micro Devices, Inc. Semiconductor process compensation utilizing non-uniform ion implantation methodology
US5972728A (en) * 1997-12-05 1999-10-26 Advanced Micro Devices, Inc. Ion implantation feedback monitor using reverse process simulation tool
EP0948044A1 (en) * 1998-03-25 1999-10-06 Nec Corporation Trench isolated wells in a semiconductor device

Also Published As

Publication number Publication date
KR20030005391A (en) 2003-01-17
WO2001093311A2 (en) 2001-12-06
AU2001255414A1 (en) 2001-12-11
JP2003535468A (en) 2003-11-25
CN1437765A (en) 2003-08-20
EP1295329A2 (en) 2003-03-26

Similar Documents

Publication Publication Date Title
AU2002357717A1 (en) Method for limiting divot formation in post shallow trench isolation processes
WO2002001607A3 (en) Method of producing trench capacitor buried strap
TW375773B (en) Method for forming shallow junctions in semiconductor wafer
WO2002006568A3 (en) Slicing of single-crystal films using ion implantation
EP0316165A3 (en) A method of trench isolation
WO2006028731A3 (en) Multiple-depth sti trenches in integrated circuit fabrication
SG102548A1 (en) A method to form shallow trench isolation structures with improved isolation fill and surface planarity
TW339468B (en) A semiconductor device having a shallow trench isolation structure and a method for fabricating the same
WO2001093311A3 (en) Method of controlling well leakage for trench isolations of differing depths
ATE460745T1 (en) METHOD FOR TRANSFERRING A THIN, ELECTRICALLY ACTIVE LAYER
EP0905758A3 (en) Methods for performing planarization and recess etches and apparatus therefor
WO2004079744A3 (en) Magnetic memory cell junction and method for forming a magnetic memory cell junction
MY124533A (en) Semiconductor device and method of manufacturing same
TW366559B (en) Manufacturing method of shallow trench isolation structure
TW356579B (en) Planar trenches
WO2001088977A3 (en) Method and device for array threshold voltage control by trapped charge in trench isolation
WO2002041393A3 (en) Method of forming shallow trench isolation in silicon
WO2003063218A3 (en) Method for forming shallow junctions by ion implantation in silicon wafers
TW370693B (en) Method for forming a contact to a substrate
SG88829A1 (en) A method to reduce trench cone formation in the fabrication of shallow trench isolations
TW335532B (en) An isolation method for memory cell and periphery circuit substrate
WO2004028960A3 (en) Method for forming a microstructure from a monocrystalline substrate
TW375772B (en) Field implant method
KR100352930B1 (en) Method for manufacturing semiconductor device
WO2004025725A3 (en) Method for producing a memory cell field comprising memory transistors that are located in trenches

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CR CU CZ DE DK DM DZ EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NO NZ PL PT RO RU SD SE SG SI SK SL TJ TM TR TT TZ UA UG UZ VN YU ZA ZW

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR BF BJ CF CG CI CM GA GN GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
AK Designated states

Kind code of ref document: A3

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CR CU CZ DE DK DM DZ EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NO NZ PL PT RO RU SD SE SG SI SK SL TJ TM TR TT TZ UA UG UZ VN YU ZA ZW

AL Designated countries for regional patents

Kind code of ref document: A3

Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR BF BJ CF CG CI CM GA GN GW ML MR NE SN TD TG

WWE Wipo information: entry into national phase

Ref document number: 1020027015882

Country of ref document: KR

WWE Wipo information: entry into national phase

Ref document number: 2001928571

Country of ref document: EP

Ref document number: 018100252

Country of ref document: CN

WWP Wipo information: published in national office

Ref document number: 1020027015882

Country of ref document: KR

WWP Wipo information: published in national office

Ref document number: 2001928571

Country of ref document: EP

WWW Wipo information: withdrawn in national office

Ref document number: 2001928571

Country of ref document: EP