JP2003524969A5 - - Google Patents

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JP2003524969A5
JP2003524969A5 JP2001560843A JP2001560843A JP2003524969A5 JP 2003524969 A5 JP2003524969 A5 JP 2003524969A5 JP 2001560843 A JP2001560843 A JP 2001560843A JP 2001560843 A JP2001560843 A JP 2001560843A JP 2003524969 A5 JP2003524969 A5 JP 2003524969A5
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logic
interface
memory
programmable logic
reconfigurable
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JP2001560843A
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JP2003524969A (ja
JP4510353B2 (ja
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Priority claimed from US09/505,059 external-priority patent/US6438737B1/en
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JP2001560843A 2000-02-15 2001-02-14 コンピュータのための再構成可能なロジック Expired - Fee Related JP4510353B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/505,059 2000-02-15
US09/505,059 US6438737B1 (en) 2000-02-15 2000-02-15 Reconfigurable logic for a computer
PCT/US2001/004733 WO2001061525A2 (en) 2000-02-15 2001-02-14 Reconfigurable logic for a computer

Publications (3)

Publication Number Publication Date
JP2003524969A JP2003524969A (ja) 2003-08-19
JP2003524969A5 true JP2003524969A5 (cg-RX-API-DMAC10.html) 2007-04-12
JP4510353B2 JP4510353B2 (ja) 2010-07-21

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JP2001560843A Expired - Fee Related JP4510353B2 (ja) 2000-02-15 2001-02-14 コンピュータのための再構成可能なロジック

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US (1) US6438737B1 (cg-RX-API-DMAC10.html)
EP (2) EP1257928B1 (cg-RX-API-DMAC10.html)
JP (1) JP4510353B2 (cg-RX-API-DMAC10.html)
AT (1) ATE313829T1 (cg-RX-API-DMAC10.html)
AU (1) AU2001237005A1 (cg-RX-API-DMAC10.html)
DE (1) DE60116060T2 (cg-RX-API-DMAC10.html)
HK (1) HK1048871B (cg-RX-API-DMAC10.html)
WO (1) WO2001061525A2 (cg-RX-API-DMAC10.html)

Families Citing this family (95)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7356620B2 (en) * 2003-06-10 2008-04-08 Altera Corporation Apparatus and methods for communicating with programmable logic devices
DE19946752A1 (de) * 1999-09-29 2001-04-12 Infineon Technologies Ag Rekonfigurierbares Gate-Array
US20030033450A1 (en) * 2000-07-20 2003-02-13 John Appleby-Alis System, method, and article of manufacture for remote updating of hardware
GB2406416A (en) * 2000-10-31 2005-03-30 Advanced Risc Mach Ltd Describing an integrated circuit configuration
EP1211598A1 (en) * 2000-11-29 2002-06-05 Texas Instruments Incorporated Data processing apparatus, system and method
US6578186B1 (en) * 2000-12-22 2003-06-10 Juniper Networks Reset control for systems using programmable logic
US7752419B1 (en) 2001-03-22 2010-07-06 Qst Holdings, Llc Method and system for managing hardware resources to implement system functions using an adaptive computing architecture
US7249242B2 (en) 2002-10-28 2007-07-24 Nvidia Corporation Input pipeline registers for a node in an adaptive computing engine
US7400668B2 (en) 2001-03-22 2008-07-15 Qst Holdings, Llc Method and system for implementing a system acquisition function for use with a communication device
US7489779B2 (en) 2001-03-22 2009-02-10 Qstholdings, Llc Hardware implementation of the secure hash standard
US6836839B2 (en) 2001-03-22 2004-12-28 Quicksilver Technology, Inc. Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements
US7962716B2 (en) 2001-03-22 2011-06-14 Qst Holdings, Inc. Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements
US7653710B2 (en) 2002-06-25 2010-01-26 Qst Holdings, Llc. Hardware task manager
US20020143518A1 (en) * 2001-03-28 2002-10-03 Abrahamson Carl K. Dynamically adaptable digital architecture system
US7155602B2 (en) * 2001-04-30 2006-12-26 Src Computers, Inc. Interface for integrating reconfigurable processors into a general purpose computing system
US7840777B2 (en) * 2001-05-04 2010-11-23 Ascenium Corporation Method and apparatus for directing a computational array to execute a plurality of successive computational array instructions at runtime
US6577678B2 (en) 2001-05-08 2003-06-10 Quicksilver Technology Method and system for reconfigurable channel coding
TW548550B (en) * 2001-05-16 2003-08-21 Ibm Method and system for efficient access to remote I/O functions in embedded control environments
US20020174266A1 (en) * 2001-05-18 2002-11-21 Krishna Palem Parameterized application programming interface for reconfigurable computing systems
AU2002347560A1 (en) * 2001-06-20 2003-01-02 Pact Xpp Technologies Ag Data processing method
TW577020B (en) * 2001-07-12 2004-02-21 Ip Flex Inc Integrated circuit device
US20030056091A1 (en) * 2001-09-14 2003-03-20 Greenberg Craig B. Method of scheduling in a reconfigurable hardware architecture with multiple hardware configurations
US7046635B2 (en) 2001-11-28 2006-05-16 Quicksilver Technology, Inc. System for authorizing functionality in adaptable hardware devices
US8412915B2 (en) 2001-11-30 2013-04-02 Altera Corporation Apparatus, system and method for configuration of adaptive integrated circuitry having heterogeneous computational elements
US6986021B2 (en) 2001-11-30 2006-01-10 Quick Silver Technology, Inc. Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements
US7602740B2 (en) 2001-12-10 2009-10-13 Qst Holdings, Inc. System for adapting device standards after manufacture
US7215701B2 (en) 2001-12-12 2007-05-08 Sharad Sambhwani Low I/O bandwidth method and system for implementing detection and identification of scrambling codes
US7403981B2 (en) 2002-01-04 2008-07-22 Quicksilver Technology, Inc. Apparatus and method for adaptive multimedia reception and transmission in communication environments
US7171659B2 (en) * 2002-03-19 2007-01-30 Sun Microsystems, Inc. System and method for configurable software provisioning
US7493375B2 (en) 2002-04-29 2009-02-17 Qst Holding, Llc Storage and delivery of device features
US7328414B1 (en) 2003-05-13 2008-02-05 Qst Holdings, Llc Method and system for creating and programming an adaptive computing engine
US7660984B1 (en) 2003-05-13 2010-02-09 Quicksilver Technology Method and system for achieving individualized protected space in an operating system
US7073158B2 (en) * 2002-05-17 2006-07-04 Pixel Velocity, Inc. Automated system for designing and developing field programmable gate arrays
US7451410B2 (en) * 2002-05-17 2008-11-11 Pixel Velocity Inc. Stackable motherboard and related sensor systems
US7024654B2 (en) * 2002-06-11 2006-04-04 Anadigm, Inc. System and method for configuring analog elements in a configurable hardware device
JP3904493B2 (ja) * 2002-07-24 2007-04-11 株式会社ルネサステクノロジ 半導体装置
US8108656B2 (en) 2002-08-29 2012-01-31 Qst Holdings, Llc Task definition for specifying resource requirements
JP2005537563A (ja) * 2002-08-30 2005-12-08 コーニンクレッカ　フィリップス　エレクトロニクス　エヌ　ヴィ バージョンプログラム可能回路モジュール
US20050272197A1 (en) * 2002-09-13 2005-12-08 Hiroshi Tanaka Semiconductor device
US7937591B1 (en) 2002-10-25 2011-05-03 Qst Holdings, Llc Method and system for providing a device which can be adapted on an ongoing basis
US7478031B2 (en) 2002-11-07 2009-01-13 Qst Holdings, Llc Method, system and program for developing and scheduling adaptive integrated circuity and corresponding control or configuration information
US8276135B2 (en) 2002-11-07 2012-09-25 Qst Holdings Llc Profiling of software and circuit designs utilizing data operation analyses
US7225301B2 (en) 2002-11-22 2007-05-29 Quicksilver Technologies External memory controller node
WO2004079564A2 (de) * 2003-03-05 2004-09-16 Bridgeco Ag Prozessor mit verschiedenartigen steuerwerken für gemeinsam genutzte ressourcen
US7873811B1 (en) 2003-03-10 2011-01-18 The United States Of America As Represented By The United States Department Of Energy Polymorphous computing fabric
WO2005001689A1 (ja) * 2003-06-25 2005-01-06 Nec Corporation 電子計算機、半導体集積回路、制御方法、プログラムの生成方法、及びプログラム
US7609297B2 (en) 2003-06-25 2009-10-27 Qst Holdings, Inc. Configurable hardware based digital imaging apparatus
JP4572835B2 (ja) * 2003-08-29 2010-11-04 富士ゼロックス株式会社 データ処理装置
JP2005122514A (ja) * 2003-10-17 2005-05-12 Rikogaku Shinkokai プログラム共通制御のソフトウェア及びハードウェアで成る装置
US7200703B2 (en) * 2004-06-08 2007-04-03 Valmiki Ramanujan K Configurable components for embedded system design
WO2005125014A1 (ja) * 2004-06-15 2005-12-29 Nec Corporation プログラマブル半導体装置
DE602005010639D1 (de) * 2004-09-03 2008-12-11 Derek Ward Verbesserungen an numerischen Steuerungen und verwandten elektronischen Geräten
JP2006236106A (ja) * 2005-02-25 2006-09-07 Canon Inc データ処理装置及びデータ処理方法
WO2006109623A1 (ja) * 2005-04-05 2006-10-19 Matsushita Electric Industrial Co., Ltd. コンピュータシステム、コンフィギュレーション情報を表すデータ構造、並びにマッピング装置および方法
US7590768B2 (en) * 2005-09-23 2009-09-15 Joseph Gormley Control and interconnection system
US7596636B2 (en) * 2005-09-23 2009-09-29 Joseph Gormley Systems and methods for implementing a vehicle control and interconnection system
US7688820B2 (en) * 2005-10-03 2010-03-30 Divitas Networks, Inc. Classification for media stream packets in a media gateway
FR2895106A1 (fr) 2005-12-20 2007-06-22 Thomson Licensing Sas Procede de telechargement d'un fichier de configuration dans un circuit programmable, et appareil comportant ledit composant.
JP2007207136A (ja) * 2006-02-06 2007-08-16 Nec Corp データ処理装置、データ処理方法、及びデータ処理プログラム
JP4646840B2 (ja) * 2006-03-22 2011-03-09 富士通セミコンダクター株式会社 回路構成を動的に切り替える並列処理装置
US20080317241A1 (en) * 2006-06-14 2008-12-25 Derek Wang Code-based echo cancellation
US20090016333A1 (en) * 2006-06-14 2009-01-15 Derek Wang Content-based adaptive jitter handling
US20080036864A1 (en) * 2006-08-09 2008-02-14 Mccubbrey David System and method for capturing and transmitting image data streams
US7555469B2 (en) * 2006-11-16 2009-06-30 L-3 Communications Integrated Systems L.P. Reconfigurable neural network systems and methods utilizing FPGAs having packet routers
US20080151049A1 (en) * 2006-12-14 2008-06-26 Mccubbrey David L Gaming surveillance system and method of extracting metadata from multiple synchronized cameras
US8694328B1 (en) 2006-12-14 2014-04-08 Joseph Gormley Vehicle customization and personalization activities
US20080162856A1 (en) * 2006-12-29 2008-07-03 Motorola, Inc. Method for dynamic memory allocation on reconfigurable logic
WO2008103850A2 (en) * 2007-02-21 2008-08-28 Pixel Velocity, Inc. Scalable system for wide area surveillance
US20090086023A1 (en) * 2007-07-18 2009-04-02 Mccubbrey David L Sensor system including a configuration of the sensor as a virtual sensor device
US20090024839A1 (en) * 2007-07-21 2009-01-22 Arssov Paul Plamen Variable instruction set microprocessor
US9336051B2 (en) * 2007-10-19 2016-05-10 National Instruments Corporation Programmable controller with multiple processors using a scanning architecture
JP5373620B2 (ja) * 2007-11-09 2013-12-18 パナソニック株式会社 データ転送制御装置、データ転送装置、データ転送制御方法及び再構成回路を用いた半導体集積回路
US8612729B2 (en) * 2007-12-17 2013-12-17 Advanced Micro Devices, Inc. Known good code for on-chip device management
US7831813B2 (en) * 2007-12-17 2010-11-09 Globalfoundries Inc. Uses of known good code for implementing processor architectural modifications
JP4740982B2 (ja) * 2008-06-18 2011-08-03 東芝テック株式会社 プログラマブル論理回路
JP2010044578A (ja) * 2008-08-12 2010-02-25 Toshiba Corp マルチコアプロセッサ
JP5431003B2 (ja) * 2009-04-03 2014-03-05 スパンション エルエルシー リコンフィギュラブル回路及びリコンフィギュラブル回路システム
US20110115909A1 (en) * 2009-11-13 2011-05-19 Sternberg Stanley R Method for tracking an object through an environment across multiple cameras
EP2526494B1 (en) 2010-01-21 2020-01-15 SVIRAL, Inc. A method and apparatus for a general-purpose, multiple-core system for implementing stream-based computations
US8789065B2 (en) 2012-06-08 2014-07-22 Throughputer, Inc. System and method for input data load adaptive parallel processing
US8869123B2 (en) 2011-06-24 2014-10-21 Robert Keith Mykland System and method for applying a sequence of operations code to program configurable logic circuitry
US10089277B2 (en) 2011-06-24 2018-10-02 Robert Keith Mykland Configurable circuit array
US9158544B2 (en) 2011-06-24 2015-10-13 Robert Keith Mykland System and method for performing a branch object conversion to program configurable logic circuitry
US9448847B2 (en) 2011-07-15 2016-09-20 Throughputer, Inc. Concurrent program execution optimization
US9304770B2 (en) 2011-11-21 2016-04-05 Robert Keith Mykland Method and system adapted for converting software constructs into resources for implementation by a dynamically reconfigurable processor
US9633160B2 (en) 2012-06-11 2017-04-25 Robert Keith Mykland Method of placement and routing in a reconfiguration of a dynamically reconfigurable processor
US8476926B1 (en) * 2012-02-08 2013-07-02 Altera Corporation Method and apparatus for implementing periphery devices on a programmable circuit using partial reconfiguration
CN103577266B (zh) 2012-07-31 2017-06-23 国际商业机器公司 用于对现场可编程门阵列资源进行分配的方法及系统
US9619265B2 (en) * 2013-06-25 2017-04-11 Empire Technology Development Llc Reconfiguration with virtual machine switching
KR102066940B1 (ko) * 2013-11-13 2020-01-16 한화테크윈 주식회사 집적 회로 소자들의 시스템
US9880952B2 (en) 2015-01-15 2018-01-30 Toshiba Memory Corporation Bus access controller, hardware engine, controller, and memory system
US10250572B2 (en) 2016-09-29 2019-04-02 Amazon Technologies, Inc. Logic repository service using encrypted configuration data
US10162921B2 (en) 2016-09-29 2018-12-25 Amazon Technologies, Inc. Logic repository service
US10642492B2 (en) 2016-09-30 2020-05-05 Amazon Technologies, Inc. Controlling access to previously-stored logic in a reconfigurable logic device
US11115293B2 (en) 2016-11-17 2021-09-07 Amazon Technologies, Inc. Networked programmable logic service provider

Family Cites Families (75)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE68920388T2 (de) 1988-09-19 1995-05-11 Fujitsu Ltd Paralleles Rechnersystem mit Verwendung eines SIMD-Verfahrens.
EP0651343B1 (en) 1988-10-05 2004-04-28 Quickturn Design Systems, Inc. Method of using electronically reconfigurable gate array logic and apparatus formed thereby
GB8906145D0 (en) 1989-03-17 1989-05-04 Algotronix Ltd Configurable cellular array
US5338984A (en) 1991-08-29 1994-08-16 National Semiconductor Corp. Local and express diagonal busses in a configurable logic array
US5633830A (en) * 1995-11-08 1997-05-27 Altera Corporation Random access memory block circuitry for programmable logic array integrated circuit devices
US5684980A (en) * 1992-07-29 1997-11-04 Virtual Computer Corporation FPGA virtual computer for executing a sequence of program instructions by successively reconfiguring a group of FPGA in response to those instructions
DE59301609D1 (de) * 1992-08-28 1996-03-21 Siemens Ag Verfahren zum betrieb eines rechnersystems mit mindestens einem mikroprozessor und mindestens einem coprozessor
US5857109A (en) 1992-11-05 1999-01-05 Giga Operations Corporation Programmable logic device for real time video processing
GB9223226D0 (en) 1992-11-05 1992-12-16 Algotronix Ltd Improved configurable cellular array (cal ii)
US5535342A (en) 1992-11-05 1996-07-09 Giga Operations Corporation Pld connector for module having configuration of either first PLD or second PLD and reconfigurable bus for communication of two different bus protocols
US5361373A (en) * 1992-12-11 1994-11-01 Gilson Kent L Integrated circuit computing device comprising a dynamically configurable gate array having a microprocessor and reconfigurable instruction execution means and method therefor
US5537654A (en) 1993-05-20 1996-07-16 At&T Corp. System for PCMCIA peripheral to execute instructions from shared memory where the system reset signal causes switching between modes of operation by alerting the starting address
EP1215584A3 (en) 1994-03-01 2004-04-21 Intel Corporation Highly pipelined bus architecture
US5689195A (en) * 1995-05-17 1997-11-18 Altera Corporation Programmable logic array integrated circuit devices
US5600845A (en) * 1994-07-27 1997-02-04 Metalithic Systems Incorporated Integrated circuit computing device comprising a dynamically configurable gate array having a microprocessor and reconfigurable instruction execution means and method therefor
US5742180A (en) 1995-02-10 1998-04-21 Massachusetts Institute Of Technology Dynamically programmable gate array with multiple contexts
US6052773A (en) * 1995-02-10 2000-04-18 Massachusetts Institute Of Technology DPGA-coupled microprocessors
US5628028A (en) 1995-03-02 1997-05-06 Data Translation, Inc. Reprogrammable PCMCIA card and method and apparatus employing same
US6049223A (en) * 1995-03-22 2000-04-11 Altera Corporation Programmable logic array integrated circuit with general-purpose memory configurable as a random access or FIFO memory
US5745785A (en) * 1995-05-09 1998-04-28 Sofmap Future Design, Inc. System for alternatively transferring data from external memory to memory device and from memory device to internal memory depending upon processing unit's operational
US5692159A (en) 1995-05-19 1997-11-25 Digital Equipment Corporation Configurable digital signal interface using field programmable gate array to reformat data
EP0830736B1 (en) * 1995-06-09 2001-10-24 Vantis Corporation Field programmable gate array (fpga) having an improved configuration memory and look up table
JP3736855B2 (ja) 1995-07-10 2006-01-18 ジーリンクス インコーポレイテッド フィールドプログラマブル・ゲートアレイ及びインテリジェント・メモリを含んでいるシステム
US5784313A (en) 1995-08-18 1998-07-21 Xilinx, Inc. Programmable logic device including configuration data or user data memory slices
US5600263A (en) 1995-08-18 1997-02-04 Xilinx, Inc. Configuration modes for a time multiplexed programmable logic device
US5838954A (en) 1995-08-18 1998-11-17 Xilinx, Inc. Computer-implemented method of optimizing a time multiplexed programmable logic device
US5646545A (en) 1995-08-18 1997-07-08 Xilinx, Inc. Time multiplexed programmable logic device
US5794164A (en) 1995-11-29 1998-08-11 Microsoft Corporation Vehicle computer system
US5737766A (en) 1996-02-14 1998-04-07 Hewlett Packard Company Programmable gate array configuration memory which allows sharing with user memory
US5744980A (en) * 1996-02-16 1998-04-28 Actel Corporation Flexible, high-performance static RAM architecture for field-programmable gate arrays
GB9604496D0 (en) * 1996-03-01 1996-05-01 Xilinx Inc Embedded memory for field programmable gate array
US6023565A (en) * 1996-03-29 2000-02-08 Xilinx, Inc. Method for configuring circuits over a data communications link
US5673198A (en) 1996-03-29 1997-09-30 Xilinx, Inc. Concurrent electronic circuit design and implementation
US5956518A (en) 1996-04-11 1999-09-21 Massachusetts Institute Of Technology Intermediate-grain reconfigurable processing device
US5894565A (en) * 1996-05-20 1999-04-13 Atmel Corporation Field programmable gate array with distributed RAM and increased cell utilization
US6097211A (en) * 1996-07-18 2000-08-01 Altera Corporation Configuration memory integrated circuit
US5838165A (en) * 1996-08-21 1998-11-17 Chatter; Mukesh High performance self modifying on-the-fly alterable logic FPGA, architecture and method
US5933023A (en) * 1996-09-03 1999-08-03 Xilinx, Inc. FPGA architecture having RAM blocks with programmable word length and width and dedicated address and data lines
US5828858A (en) 1996-09-16 1998-10-27 Virginia Tech Intellectual Properties, Inc. Worm-hole run-time reconfigurable processor field programmable gate array (FPGA)
US6102964A (en) * 1996-10-28 2000-08-15 Altera Corporation Fitting for incremental compilation of electronic designs
US5946219A (en) 1996-10-30 1999-08-31 Atmel Corporation Method and system for configuring an array of logic devices
US5892962A (en) 1996-11-12 1999-04-06 Lucent Technologies Inc. FPGA-based processor
US6151688A (en) * 1997-02-21 2000-11-21 Novell, Inc. Resource management in a clustered computer system
US5970439A (en) 1997-03-13 1999-10-19 International Business Machines Corporation Performance monitoring in a data processing system
US6085317A (en) * 1997-08-15 2000-07-04 Altera Corporation Reconfigurable computer architecture using programmable logic devices
JP3106998B2 (ja) * 1997-04-11 2000-11-06 日本電気株式会社 メモリ付加型プログラマブルロジックｌｓｉ
US6134516A (en) * 1997-05-02 2000-10-17 Axis Systems, Inc. Simulation server system and method
US6026230A (en) * 1997-05-02 2000-02-15 Axis Systems, Inc. Memory simulation system and method
JPH1115773A (ja) * 1997-06-24 1999-01-22 Matsushita Electron Corp 半導体集積回路、コンピュータシステム、データ処理装置及びデータ処理方法
JPH1115866A (ja) * 1997-06-25 1999-01-22 Fuji Xerox Co Ltd 回路装置、情報入出力装置、情報処理装置および回路装置の再構成システム
US5970254A (en) 1997-06-27 1999-10-19 Cooke; Laurence H. Integrated processor and programmable data path chip for reconfigurable computing
US5978862A (en) 1997-08-08 1999-11-02 Toshiba America Information Systems, Inc. PCMCIA card dynamically configured in first mode to program FPGA controlling application specific circuit and in second mode to operate as an I/O device
US6311149B1 (en) * 1997-08-18 2001-10-30 National Instruments Corporation Reconfigurable test system
US6216191B1 (en) * 1997-10-15 2001-04-10 Lucent Technologies Inc. Field programmable gate array having a dedicated processor interface
US5915123A (en) * 1997-10-31 1999-06-22 Silicon Spice Method and apparatus for controlling configuration memory contexts of processing elements in a network of multiple context processing elements
US6091263A (en) * 1997-12-12 2000-07-18 Xilinx, Inc. Rapidly reconfigurable FPGA having a multiple region architecture with reconfiguration caches useable as data RAM
US6339819B1 (en) * 1997-12-17 2002-01-15 Src Computers, Inc. Multiprocessor with each processor element accessing operands in loaded input buffer and forwarding results to FIFO output buffer
US6076152A (en) 1997-12-17 2000-06-13 Src Computers, Inc. Multiprocessor computer architecture incorporating a plurality of memory algorithm processors in the memory subsystem
US6127843A (en) * 1997-12-22 2000-10-03 Vantis Corporation Dual port SRAM memory for run time use in FPGA integrated circuits
US6028445A (en) * 1997-12-30 2000-02-22 Xilinx, Inc. Decoder structure and method for FPGA configuration
US6172520B1 (en) * 1997-12-30 2001-01-09 Xilinx, Inc. FPGA system with user-programmable configuration ports and method for reconfiguring the FPGA
US6064676A (en) * 1998-01-14 2000-05-16 Skystream Corporation Remultipelxer cache architecture and memory organization for storing video program bearing transport packets and descriptors
US6230307B1 (en) * 1998-01-26 2001-05-08 Xilinx, Inc. System and method for programming the hardware of field programmable gate arrays (FPGAs) and related reconfiguration resources as if they were software by creating hardware objects
US6026459A (en) 1998-02-03 2000-02-15 Src Computers, Inc. System and method for dynamic priority conflict resolution in a multi-processor computer system having shared memory resources
US6011740A (en) 1998-03-04 2000-01-04 Xilinx, Inc. Structure and method for providing additional configuration memories on an FPGA
JPH11260928A (ja) * 1998-03-13 1999-09-24 Nec Kansai Ltd 半導体論理回路装置
US6175247B1 (en) * 1998-04-14 2001-01-16 Lockheed Martin Corporation Context switchable field programmable gate array with public-private addressable sharing of intermediate data
US6237054B1 (en) * 1998-09-14 2001-05-22 Advanced Micro Devices, Inc. Network interface unit including a microcontroller having multiple configurable logic blocks, with a test/program bus for performing a plurality of selected functions
JP3444216B2 (ja) * 1999-01-28 2003-09-08 日本電気株式会社 プログラマブルデバイス
JP3269526B2 (ja) * 1999-02-09 2002-03-25 日本電気株式会社 プログラマブルロジックｌｓｉ
JP3616518B2 (ja) * 1999-02-10 2005-02-02 日本電気株式会社 プログラマブルデバイス
US6308311B1 (en) * 1999-05-14 2001-10-23 Xilinx, Inc. Method for reconfiguring a field programmable gate array from a host
US6312381B1 (en) * 1999-09-14 2001-11-06 Acuson Corporation Medical diagnostic ultrasound system and method
US6255849B1 (en) * 2000-02-04 2001-07-03 Xilinx, Inc. On-chip self-modification for PLDs
US6986073B2 (en) * 2000-03-01 2006-01-10 Realtek Semiconductor Corp. System and method for a family of digital subscriber line (XDSL) signal processing circuit operating with an internal clock rate that is higher than all communications ports operating with a plurality of port sampling clock rates

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