JP2003519914A - ヘリウムを付加するエッチングを使用する半導体製造方法 - Google Patents
ヘリウムを付加するエッチングを使用する半導体製造方法Info
- Publication number
- JP2003519914A JP2003519914A JP2001550791A JP2001550791A JP2003519914A JP 2003519914 A JP2003519914 A JP 2003519914A JP 2001550791 A JP2001550791 A JP 2001550791A JP 2001550791 A JP2001550791 A JP 2001550791A JP 2003519914 A JP2003519914 A JP 2003519914A
- Authority
- JP
- Japan
- Prior art keywords
- etching
- substrate
- gas
- semiconductor
- inert gas
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000005530 etching Methods 0.000 title claims abstract description 76
- 239000004065 semiconductor Substances 0.000 title claims abstract description 48
- 238000004519 manufacturing process Methods 0.000 title claims description 22
- 239000001307 helium Substances 0.000 title description 5
- 229910052734 helium Inorganic materials 0.000 title description 5
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 title description 5
- 239000007789 gas Substances 0.000 claims abstract description 37
- 239000000758 substrate Substances 0.000 claims abstract description 31
- 239000011261 inert gas Substances 0.000 claims abstract description 28
- 238000000034 method Methods 0.000 claims abstract description 25
- 239000000463 material Substances 0.000 claims description 11
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 5
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 4
- 238000000059 patterning Methods 0.000 claims description 4
- 238000000137 annealing Methods 0.000 claims 1
- 229910052710 silicon Inorganic materials 0.000 claims 1
- 239000010703 silicon Substances 0.000 claims 1
- 239000000126 substance Substances 0.000 claims 1
- 235000012431 wafers Nutrition 0.000 description 12
- 230000015572 biosynthetic process Effects 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 239000006117 anti-reflective coating Substances 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 230000001627 detrimental effect Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- XZWYZXLIPXDOLR-UHFFFAOYSA-N metformin Chemical compound CN(C)C(=N)NC(N)=N XZWYZXLIPXDOLR-UHFFFAOYSA-N 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
- H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Plasma & Fusion (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Drying Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US47589299A | 1999-12-30 | 1999-12-30 | |
| US09/475,892 | 1999-12-30 | ||
| PCT/US2000/035131 WO2001050511A1 (en) | 1999-12-30 | 2000-12-22 | Semiconductor manufacture using helium-assisted etch |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2003519914A true JP2003519914A (ja) | 2003-06-24 |
Family
ID=23889598
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2001550791A Pending JP2003519914A (ja) | 1999-12-30 | 2000-12-22 | ヘリウムを付加するエッチングを使用する半導体製造方法 |
Country Status (4)
| Country | Link |
|---|---|
| EP (1) | EP1166346A1 (ko) |
| JP (1) | JP2003519914A (ko) |
| KR (1) | KR20010112294A (ko) |
| WO (1) | WO2001050511A1 (ko) |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3729869B2 (ja) * | 1990-09-28 | 2005-12-21 | セイコーエプソン株式会社 | 半導体装置の製造方法 |
| US6008139A (en) * | 1996-06-17 | 1999-12-28 | Applied Materials Inc. | Method of etching polycide structures |
-
2000
- 2000-12-22 KR KR1020017011029A patent/KR20010112294A/ko not_active Application Discontinuation
- 2000-12-22 WO PCT/US2000/035131 patent/WO2001050511A1/en not_active Application Discontinuation
- 2000-12-22 EP EP00986720A patent/EP1166346A1/en not_active Withdrawn
- 2000-12-22 JP JP2001550791A patent/JP2003519914A/ja active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| WO2001050511B1 (en) | 2001-11-22 |
| WO2001050511A1 (en) | 2001-07-12 |
| EP1166346A1 (en) | 2002-01-02 |
| KR20010112294A (ko) | 2001-12-20 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR101691717B1 (ko) | 다중 막층을 갖는 스페이서를 형성하기 위한 에칭 방법 | |
| US6107172A (en) | Controlled linewidth reduction during gate pattern formation using an SiON BARC | |
| JPH08306672A (ja) | 垂直側壁を形成する方法 | |
| JP2000036492A (ja) | エッチング方法 | |
| JP2903884B2 (ja) | 半導体装置の製法 | |
| JP4242158B2 (ja) | シリコンと窒素を含む材料をウエットエッチングする方法 | |
| JP4282391B2 (ja) | 半導体装置の製造方法 | |
| JP2003519914A (ja) | ヘリウムを付加するエッチングを使用する半導体製造方法 | |
| JP2003519912A (ja) | エッチング及びアッシングフォトレジスト除去プロセス | |
| JPH03280532A (ja) | 半導体装置の製造方法 | |
| JP2879841B2 (ja) | プレーナ型ダイオードの製造方法 | |
| JP3371179B2 (ja) | 配線形成方法 | |
| WO2001035455A1 (en) | Etch process that resists notching at electrode bottom | |
| US6812148B2 (en) | Preventing gate oxice thinning effect in a recess LOCOS process | |
| EP1348233A1 (en) | Method of dry etching an antireflection coating in semiconductor devices | |
| JP2002525850A (ja) | 集積回路ゲート導電体上に形成されたスペーサをエッチングするための装置および方法 | |
| WO2022001486A1 (zh) | 半导体结构的处理方法及形成方法 | |
| KR20010019642A (ko) | 폴리실리콘 게이트의 식각 방법 | |
| JP2001332510A (ja) | 半導体装置およびその製造方法 | |
| KR0168208B1 (ko) | 다중합체 제거방법 | |
| JP2001237415A (ja) | 半導体装置の製造方法 | |
| KR100701687B1 (ko) | 게이트전극 식각방법 | |
| JPH08274078A (ja) | エッチング方法 | |
| JP2002261077A (ja) | ドライエッチング方法 | |
| JPH0774148A (ja) | ドライエッチング方法 |