WO2001050511B1 - Semiconductor manufacture using helium-assisted etch - Google Patents

Semiconductor manufacture using helium-assisted etch

Info

Publication number
WO2001050511B1
WO2001050511B1 PCT/US2000/035131 US0035131W WO0150511B1 WO 2001050511 B1 WO2001050511 B1 WO 2001050511B1 US 0035131 W US0035131 W US 0035131W WO 0150511 B1 WO0150511 B1 WO 0150511B1
Authority
WO
WIPO (PCT)
Prior art keywords
etch
gas
substrate
plasma
sufficient
Prior art date
Application number
PCT/US2000/035131
Other languages
French (fr)
Other versions
WO2001050511A1 (en
Inventor
Tammy Zheng
Original Assignee
Koninkl Philips Electronics Nv
Philips Semiconductors Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninkl Philips Electronics Nv, Philips Semiconductors Inc filed Critical Koninkl Philips Electronics Nv
Priority to EP00986720A priority Critical patent/EP1166346A1/en
Priority to KR1020017011029A priority patent/KR20010112294A/en
Priority to JP2001550791A priority patent/JP2003519914A/en
Publication of WO2001050511A1 publication Critical patent/WO2001050511A1/en
Publication of WO2001050511B1 publication Critical patent/WO2001050511B1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Plasma & Fusion (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Drying Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

Semiconductor chip manufacturing is enhanced using a highly selective etching process that enables the formation of structure having near 90° side walls within the chip without degrading the selectivity. According to an example embodiment of the present invention, a plasma generated from an etch gas and an inert gas is used to etch a semiconductor chip having substrate formed over a thin oxide. The chip is etched at an etch pressure and plasma power that, when coupled with the etch gas chemistry, are sufficient to achieve high oxide selectivity. The inert gas supplied concurrently with the etch gas is sufficient to maintain an about vertical side wall profile of the substrate as it is etched without degrading the etch gas selectivity.

Claims

AMENDED CLAIMS[received by the International Bureau on 24 July 2001 24.07.01); original claim 1 amended; remaining claims unchanged (1 page)]
1. A method for processing a semiconductor chip having a substrate formed over a thin oxide, the method comprising: supplying an etch gas including a chemistry sufficient to maintain a high selectivity to the thin oxide; while supplying the etch gas, supplying an amount of inert gas that is sufficient to achieve an about vertical side wall profile of the etched substrate wliile maintairiing the high etch selectivity; and using the etch gas and the inert gas but without using chlorine, generating a plasma and etching the semiconductor chip and foπning a structure -from the substrate, thereby not degrading the high etch selectivity and mitigating icrotrenching at a bottom portion of the vertical side wall profile.
2. The method of claim 1 , wherein generating a plasma and etching the semiconductor chip includes using a plasma source power, a plasma bias power, and an etch pressure that are sufficient to maintain a high selectivity to the thin oxide when used with the etch gas chemistry.
3. The method of claim 2, wherein the plasma source power is between about 50- 400 Watts; and wherein the plasma bias power is between about 10-200 watts; and wherein the etch pressure is between about 5-100 mTorr.
4 , The method of claim 1 , wherein the etch gas includes a gas used in a highly selective Si/SiO2 etch process.
5. The method of claim 1, wherein the inert gas flow rate is sufficient to achieve an at least about 85ό side wall profile of the substrate.
6. The method of claim 1, wherein the plasma docs not etch the thin oxide.
7. The method of claim 1, and prior to supplying an etch gas, further comprising; forming a substrate having silicon on the semiconductor chip; patterning a mask material over the substrate; and placing the chip in an etch chamber.
10
PCT/US2000/035131 1999-12-30 2000-12-22 Semiconductor manufacture using helium-assisted etch WO2001050511A1 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
EP00986720A EP1166346A1 (en) 1999-12-30 2000-12-22 Semiconductor manufacture using helium-assisted etch
KR1020017011029A KR20010112294A (en) 1999-12-30 2000-12-22 Semiconductor manufacture using helium-assisted etch
JP2001550791A JP2003519914A (en) 1999-12-30 2000-12-22 Semiconductor manufacturing method using etching to add helium

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US47589299A 1999-12-30 1999-12-30
US09/475,892 1999-12-30

Publications (2)

Publication Number Publication Date
WO2001050511A1 WO2001050511A1 (en) 2001-07-12
WO2001050511B1 true WO2001050511B1 (en) 2001-11-22

Family

ID=23889598

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2000/035131 WO2001050511A1 (en) 1999-12-30 2000-12-22 Semiconductor manufacture using helium-assisted etch

Country Status (4)

Country Link
EP (1) EP1166346A1 (en)
JP (1) JP2003519914A (en)
KR (1) KR20010112294A (en)
WO (1) WO2001050511A1 (en)

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3729869B2 (en) * 1990-09-28 2005-12-21 セイコーエプソン株式会社 Manufacturing method of semiconductor device
US6008139A (en) * 1996-06-17 1999-12-28 Applied Materials Inc. Method of etching polycide structures

Also Published As

Publication number Publication date
EP1166346A1 (en) 2002-01-02
WO2001050511A1 (en) 2001-07-12
KR20010112294A (en) 2001-12-20
JP2003519914A (en) 2003-06-24

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