JP2003503854A - 半導体デバイス - Google Patents

半導体デバイス

Info

Publication number
JP2003503854A
JP2003503854A JP2001506611A JP2001506611A JP2003503854A JP 2003503854 A JP2003503854 A JP 2003503854A JP 2001506611 A JP2001506611 A JP 2001506611A JP 2001506611 A JP2001506611 A JP 2001506611A JP 2003503854 A JP2003503854 A JP 2003503854A
Authority
JP
Japan
Prior art keywords
layer
semiconductor device
insulating
semiconductor
patterned metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001506611A
Other languages
English (en)
Japanese (ja)
Other versions
JP2003503854A5 (https=
Inventor
ヘンリカス ジー アール マアス
デュゼン マリア エッチ ダブリュ エー ファン
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Electronics NV filed Critical Philips Electronics NV
Publication of JP2003503854A publication Critical patent/JP2003503854A/ja
Publication of JP2003503854A5 publication Critical patent/JP2003503854A5/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W44/00—Electrical arrangements for controlling or matching impedance
    • H10W44/601—Capacitive arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W44/00—Electrical arrangements for controlling or matching impedance
    • H10W44/20—Electrical arrangements for controlling or matching impedance at high-frequency [HF] or radio frequency [RF]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/951—Materials of bond pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/951—Materials of bond pads
    • H10W72/952—Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)
JP2001506611A 1999-06-29 2000-06-26 半導体デバイス Pending JP2003503854A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
EP99202104.8 1999-06-29
EP99202104 1999-06-29
PCT/EP2000/005915 WO2001001485A2 (en) 1999-06-29 2000-06-26 A semiconductor device

Publications (2)

Publication Number Publication Date
JP2003503854A true JP2003503854A (ja) 2003-01-28
JP2003503854A5 JP2003503854A5 (https=) 2007-08-16

Family

ID=8240379

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001506611A Pending JP2003503854A (ja) 1999-06-29 2000-06-26 半導体デバイス

Country Status (5)

Country Link
US (1) US6452272B1 (https=)
EP (1) EP1118118A1 (https=)
JP (1) JP2003503854A (https=)
KR (1) KR100654473B1 (https=)
WO (1) WO2001001485A2 (https=)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005285988A (ja) * 2004-03-29 2005-10-13 Sony Corp 固体撮像素子とその製造方法、及び半導体集積回路装置とその製造方法
JP2008113018A (ja) * 2007-12-03 2008-05-15 Sony Corp 固体撮像素子とその製造方法、及び半導体集積回路装置とその製造方法

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10109877A1 (de) * 2001-03-01 2002-09-19 Infineon Technologies Ag Leiterbahnanordnung und Verfahren zur Herstellung einer Leiterbahnanordnung
US6962835B2 (en) * 2003-02-07 2005-11-08 Ziptronix, Inc. Method for room temperature metal direct bonding
US8981427B2 (en) 2008-07-15 2015-03-17 Taiwan Semiconductor Manufacturing Company, Ltd. Polishing of small composite semiconductor materials
US8916425B2 (en) * 2010-07-26 2014-12-23 Semiconductor Energy Laboratory Co., Ltd. Method for forming microcrystalline semiconductor film and method for manufacturing semiconductor device

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1997019462A2 (de) * 1995-11-22 1997-05-29 Siemens Aktiengesellschaft Vertikal integriertes halbleiterbauelement und herstellungsverfahren dafür
JPH09508502A (ja) * 1994-11-22 1997-08-26 フィリップス エレクトロニクス ネムローゼ フェンノートシャップ 半導体素子を有し導体トラックが形成されている基板が接着層により結合されている支持本体を有する半導体装置
JPH10503328A (ja) * 1995-05-10 1998-03-24 フィリップス エレクトロニクス ネムローゼ フェンノートシャップ 電子装置の製造方法
JP2001526842A (ja) * 1998-03-02 2001-12-18 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ 半導体素子及び金属化層を有する基板を接着剤により取付られているガラス支持体を有する半導体装置

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4485553A (en) 1983-06-27 1984-12-04 Teletype Corporation Method for manufacturing an integrated circuit device
JP2821830B2 (ja) 1992-05-14 1998-11-05 セイコーインスツルメンツ株式会社 半導体薄膜素子その応用装置および半導体薄膜素子の製造方法
US5656830A (en) * 1992-12-10 1997-08-12 International Business Machines Corp. Integrated circuit chip composite having a parylene coating
US5654222A (en) * 1995-05-17 1997-08-05 Micron Technology, Inc. Method for forming a capacitor with electrically interconnected construction
US5872393A (en) * 1995-10-30 1999-02-16 Matsushita Electric Industrial Co., Ltd. RF semiconductor device and a method for manufacturing the same
US5914508A (en) * 1995-12-21 1999-06-22 The Whitaker Corporation Two layer hermetic-like coating process for on-wafer encapsulation of GaAs MMIC's
US5913144A (en) * 1996-09-20 1999-06-15 Sharp Microelectronics Technology, Inc. Oxidized diffusion barrier surface for the adherence of copper and method for same
US6255731B1 (en) * 1997-07-30 2001-07-03 Canon Kabushiki Kaisha SOI bonding structure

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09508502A (ja) * 1994-11-22 1997-08-26 フィリップス エレクトロニクス ネムローゼ フェンノートシャップ 半導体素子を有し導体トラックが形成されている基板が接着層により結合されている支持本体を有する半導体装置
JPH10503328A (ja) * 1995-05-10 1998-03-24 フィリップス エレクトロニクス ネムローゼ フェンノートシャップ 電子装置の製造方法
WO1997019462A2 (de) * 1995-11-22 1997-05-29 Siemens Aktiengesellschaft Vertikal integriertes halbleiterbauelement und herstellungsverfahren dafür
JP2001526842A (ja) * 1998-03-02 2001-12-18 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ 半導体素子及び金属化層を有する基板を接着剤により取付られているガラス支持体を有する半導体装置

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005285988A (ja) * 2004-03-29 2005-10-13 Sony Corp 固体撮像素子とその製造方法、及び半導体集積回路装置とその製造方法
JP2008113018A (ja) * 2007-12-03 2008-05-15 Sony Corp 固体撮像素子とその製造方法、及び半導体集積回路装置とその製造方法

Also Published As

Publication number Publication date
WO2001001485A3 (en) 2001-05-03
EP1118118A1 (en) 2001-07-25
KR100654473B1 (ko) 2006-12-05
KR20010072980A (ko) 2001-07-31
US6452272B1 (en) 2002-09-17
WO2001001485A2 (en) 2001-01-04

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