JP2003264287A - Mos transistor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent contact resistance from rising accompanying a decrease in the contact area of a source due to an increase in cell density and to improve the reliability of an element. <P>SOLUTION: A gate is formed of a polysilicon layer in a trench, and an interlayer insulating film covering the surface of the polysilicon layer is also formed in the trench. A conductor film for the source is formed on the whole surface of the source region and the trench so that the source region can be brought into contact with the conductor film even in the trench to increase the whole contact area, and its resistance can be reduced. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a vertical power MOS transistor used as a power semiconductor device,
The present invention relates to the structure of a trench gate type MOSFET.

[0002]

2. Description of the Related Art Various MOSFs are used as power semiconductor devices.
ET is used, and one of them is a trench.
There is a vertical MOSFET in which the gate is formed. Figure 2
FIG. 3 is a front cross-sectional view showing an example of such a MOSFET, which has a source 20 on the front surface side and a drain 21 on the back surface side, and a gate 23 is made of polysilicon filled in a groove, and a channel is formed in a P-type well 22. It is what is formed.

The drain electrode 21 'is formed by forming a metal film on the back surface of the substrate, and the wiring to the source 20 region is formed by the metal wiring layer 25 formed on the front surface side of the substrate. The gate 23 is made of polysilicon in the groove in which the gate oxide film 24 is formed, and is insulated from the wiring layer 25 to the source 20 region via the interlayer insulating film 26.

In the MOSFET having such a structure, after forming a trench (groove), polysilicon is deposited in the trench to form a gate electrode. It is a usual method to form a contact hole in a source region by photo-etching after forming an interlayer insulating film on the surface, deposit metal on the contact hole by sputtering, and form a wiring in a photolithography process.

[0005]

There are several problems in forming the above contact holes. Since the contact hole has a two-dimensional structure, the contact resistance of the source part is inversely proportional to the plane area of the contact part. As the device becomes finer and the pitch of the transistor cells becomes smaller, the opening area for connecting to the source portion of the semiconductor substrate becomes smaller. When a large current is passed, the contact resistance increases, and there arises a problem that a power semiconductor element that requires a large current cannot be obtained.

Another problem is that a sidewall spacer is attached to a polysilicon gate to form a self-aligned contact, and then a metal wiring is sputtered. A photolithography process for that is required, and
Sidewall space is wasted. In this way, the metal wiring film formed by sputtering has a problem that voids are generated due to the non-uniform base.

The present invention can secure a sufficient contact area and reduce the contact resistance of the source portion even if the pitch of the transistor cells is reduced due to miniaturization, and the contact resistance in the metal wiring film is reduced. Provided is a MOS transistor capable of improving reliability by eliminating voids, and a manufacturing method thereof.

[0008]

The present invention solves the above problems by forming an interlayer insulating film in a trench and also forming a part of a wiring metal layer in the trench. is there.

That is, a layer of the second conductivity type is provided at a predetermined depth from the surface of the semiconductor substrate of the first conductivity type to be the drain region, and a source region of the first conductivity type is formed on the surface. And a groove that penetrates the layer of the second conductivity type from the surface to reach the substrate of the first conductivity type, and faces the second conductivity type region through the insulating film in the groove. In a MOS transistor comprising a gate electrode and an interlayer insulating film on the surface side of the gate electrode and a conductor film connected to the source region, the interlayer insulating film is formed inside the groove while covering the gate electrode, and It is characterized in that a part of the conductor film connected to the region is formed in the groove.

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION Structurally, the gate electrode and the interlayer insulating film are completely buried in the trench (groove), and the metal film contacting the source region is also in the groove. Since it is formed, the contact area is greatly expanded.

[0011]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a front sectional view showing an example of a MOS transistor according to the present invention. The source 10 is provided on the front surface side, the drain 11 is provided on the back surface side, the gate 13 is made of polysilicon filled in the groove, and the channel is formed in the P-type well 12, which is the same as the conventional one.

The drain electrode 11 'is formed by forming a metal film on the back surface of the substrate, and the wiring to the source 10 region is formed by the metal wiring layer 15 formed on the front surface side of the substrate. The gate 13 is made of polysilicon in the groove in which the gate oxide film 14 is formed, and is insulated from the wiring layer 15 to the source 10 region through the interlayer insulating film 16 formed in the groove. Thus, the structure in which the interlayer insulating film 16 is housed in the groove and lower than the surface of the substrate, that is, formed inside is adopted.

An embodiment of the method for manufacturing a MOS transistor according to the present invention will be described below. The cell portion of the MOS transistor and the peripheral portion used for wiring and the like are formed on the surface of the substrate in which the N type epitaxial layer is formed on the N type silicon substrate. The feature of the present invention resides in the cell portion. Therefore, only the manufacturing method of that portion will be described. After forming a field oxide film in the peripheral portion, a P-type relatively deep layer is formed in the cell portion by ion implantation. The inside of this P-type layer will later become a P-type well.

A mask for photoetching a trench (groove) is formed on the surface of the silicon substrate on which the P-type layer is thus formed on the surface, and silicon is etched from the surface to form a groove. The depth of this groove is about 2 μm,
This depth is set to penetrate the P-type region and reach the N-type region. The steps up to this point are not much different from the conventional steps except for the depth of the P-type layer.

An oxide film is formed on the surface of the trench and the silicon substrate. This oxide film serves as a gate oxide film and can be formed by an ordinary method. The thickness of the gate oxide film is about 250Å.

Polysilicon doped with P-type impurities is deposited in the trench and the silicon substrate on which the gate oxide film is formed. The thickness of this polysilicon is about 8000Å. As a result, a polysilicon layer is formed on the entire surface of the silicon substrate. It is deposited to leave the portion formed in the groove as a gate electrode.

Next, the polysilicon is etched to leave the polysilicon layer as the gate electrode. At this time, a mask is formed in the peripheral portion to leave polysilicon as a wiring, but the cell portion is entirely etched. This etching is performed to the extent that polysilicon does not remain on the surface of the silicon substrate other than the portion where the groove is formed and the inside of the groove is also partially etched.

The surface of the polysilicon in the groove is oxidized to 200 Å
An oxide film of a certain degree is formed on the surface. At this time, an oxide film is similarly formed on the surface of the polysilicon layer used for wiring in the peripheral portion.

A heat treatment step is required in order to use the oxide film covering the polysilicon in the groove thus formed as an interlayer insulating film. In this heat treatment step, an N-type region to be a source region is formed on the surface of the silicon substrate. At this time, if the interlayer insulating film in the groove is formed inside the groove, the silicon substrate has a surface in a state where the groove is not filled up.

As described above, the metal film to be the wiring of the source region is deposited on the surface of the silicon substrate on which the polysilicon which becomes the gate in the groove and the interlayer insulating film are formed. The metal film is formed of aluminum or the like containing 1% of silicon and has a thickness of about 40,000Å. Thereafter, the pre-process is completed by etching the wiring pattern and forming a passivation film.

The process of the present invention is not limited to the above, and basically any process capable of forming the interlayer insulating film only in the trench (groove) may be used. As a result, the photolithography process can be omitted once, and the distance between the polysilicon gates can be minimized, so that space efficiency can be improved and a cell of a highly integrated MOS transistor can be formed. It becomes possible to manufacture.

[0022]

According to the present invention, since the cell pitch can be reduced, the cell density of the power MOSFET can be increased. Further, since the contact area between the conductor film and the source can be increased, the contact resistance can be reduced, and the ON resistance (resistance during device operation) can be reduced.

Since the difference between the upper surface of the contact hole and the surface of the silicon substrate is also small, the metal film formed by sputtering can be made uniform and voids inside the source metal electrode film can be eliminated to eliminate the element The reliability can be increased.

[Brief description of drawings]

FIG. 1 is a front sectional view showing an embodiment of the present invention.

FIG. 2 is a front sectional view showing a conventional MOSFET.

[Explanation of symbols]

10: Source 11: Drain 13: Gate 14: Gate oxide film 15: Metal wiring layer 16: Interlayer insulation film

Claims (3)

[Claims] 1. A second conductivity type layer is provided at a predetermined depth from the surface of a first conductivity type semiconductor substrate to be a drain region, and a source region of the first conductivity type is provided on the surface. And a groove that penetrates the layer of the second conductivity type from the surface to reach the substrate of the first conductivity type, and the second groove via the insulating film in the groove.
In a MOS transistor having a gate electrode facing a region of conductivity type, and having an inter-layer insulation film on the surface side of the gate electrode and a conductor film connected to the source region, the inter-layer insulation film covers the gate electrode and A MOS transistor, wherein a part of a conductor film formed inside and connected to a source region is formed in a groove thereof. 2. The MOS transistor according to claim 1, wherein an interlayer insulating film is formed inside the groove so as to cover the gate electrode, and a surface of the interlayer insulating film is formed inside the groove. 3. A second-conductivity-type layer is provided at a predetermined depth from the surface of the first-conductivity-type semiconductor substrate to be a drain region, and a first-conductivity-type source region is formed on the surface. And a groove that penetrates the layer of the second conductivity type from the surface to reach the substrate of the first conductivity type, and the second groove via the insulating film in the groove.
In a MOS transistor having a gate electrode facing a region of conductivity type, and having an interlayer insulating film on the surface side of the gate electrode and a conductor film connected to the source region, the interlayer insulating film covers the gate electrode and A MOS transistor characterized in that a part of a conductor film formed inside and connected to a source region is formed in the groove, and the conductor film and the source region are in contact in the groove.