JP2003258255A - Mos transistor and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the on-resistance of a MOS transistor and, at the same time, to improve the qualities of source wiring metallic films. <P>SOLUTION: Interlayer insulating films which insulate polysilicon gates formed in the trenches (groove) of a vertical MOS transistor and metallic films which are caused to deposit as source wiring conductor films from each other are formed in the grooves of the transistor so as to cover the gates. Since the wiring conductor films are formed on an almost flattened surface of a silicon substrate, the occurrence of voids (cavities) can be prevented and the qualities of the source wiring metallic films are improved. In addition, since the number of photolithographic steps requiring mask matching can be reduced, the interval between the gates can be narrowed and the degree of integration of the vertical MOS transistor can be increased. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a vertical power MOS transistor used as a power semiconductor device,
The present invention relates to a structure of a trench gate type MOSFET and a manufacturing method thereof.

[0002]

2. Description of the Related Art Various MOSFs are used as power semiconductor devices.
ET is used, and one of them is a trench.
There is a vertical MOSFET in which the gate is formed. Figure 6
Is a front sectional view showing an example of such a MOSFET, which has a source 60 on the front side and a drain 61 on the back side, and
The gate 63 is composed of polysilicon filled in 67, and P
A channel is formed in the mold well 62.

The drain electrode 61 'is formed by forming a metal film on the back surface of the semiconductor substrate, and the wiring to the source 60 region is formed by the metal wiring layer 65 formed on the front surface side of the substrate. Gate
63 is made of polysilicon in the groove 67 in which the gate oxide film 64 is formed, and is insulated from the wiring layer 65 to the source 60 region through the interlayer insulating film 66.

In the MOSFET having such a structure, after forming a trench (groove), polysilicon is deposited in the trench to form a gate electrode. The usual method is to deposit an interlayer insulating film on the surface, form a contact hole in the source region by photo-etching, deposit metal on the contact hole by sputtering, and form a wiring in a photolithography process.

[0005]

There are several problems in forming the above contact holes. one is,
The method is to form a tapered contact hole by wet and dry etching steps, and then sputter a metal wiring film on the contact hole. For this reason, a photolithography process is required, a margin for mask alignment is small, and a space for tapering is required, which limits the miniaturization.

In addition, a sidewall spacer is attached to the polysilicon gate to form a self-aligned contact,
After that, the metal wiring is sputtered. A photolithography process is needed for this purpose, and the space for the side wall is wasted. In this manner, the metal wiring film formed by sputtering has a problem that voids (holes) 68 are generated due to the non-uniform base.

The present invention provides a MOS transistor and a method for manufacturing the same, which can increase the density of cells such as power MOSFETs, reduce ON resistance, and eliminate voids in a metal wiring film to improve reliability. To do.

[0008]

The present invention solves the above problems by forming an interlayer insulating film in a groove and forming a wiring metal layer on a flattened surface.

That is, a layer of the second conductivity type is provided at a predetermined depth from the surface of the semiconductor substrate of the first conductivity type to be the drain region, and a source region of the first conductivity type is formed on the surface. And a groove that penetrates the second conductivity type layer from the surface to reach the first conductivity type semiconductor substrate, and faces the second conductivity type region through the insulating film in the groove. In a MOS transistor having a gate electrode for forming a gate electrode, and having an interlayer insulating film on the surface side of the gate electrode and a conductor film connected to the source region, the interlayer insulating film covers the gate electrode and is formed inside the groove. It has characteristics.

In a method of manufacturing a MOS transistor in which a vertical MOS transistor having a gate electrode formed in a groove is formed on a semiconductor substrate, a first drain region is formed.
A second conductivity type layer is formed at a position of a predetermined depth from the surface of the second conductivity type semiconductor substrate, and a layer to be a first conductivity type source region is formed on the surface,
Forming a groove penetrating the first conductivity type semiconductor substrate and reaching the first conductivity type semiconductor substrate, and forming a gate electrode facing the second conductivity type region through the insulating film in the groove. An interlayer insulating film covering the gate electrode is formed inside the groove on the surface side of the electrode, and a conductor film connected to the source region is formed on the surface of the semiconductor substrate including the groove.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION Structurally, an interlayer insulating film is completely buried in a groove, and a photolithography process for the interlayer insulating film is unnecessary in terms of process. That is,
Plasma C after oxidizing the polysilicon surface of the gate
The TEOS oxide film is deposited by VD and then the TEO
An interlayer insulating film is formed by a process of etching back the S oxide film to a position where the silicon surface other than the trench is exposed.

[0012]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a front sectional view showing an example of a MOS transistor according to the present invention. The semiconductor substrate has a source 10 on the front surface side, a drain 11 on the back surface side, a gate 13 is made of polysilicon filled in a groove, and a channel is formed in a P-type well 12, which is the same as in the conventional case.

The drain electrode 11 'is formed by forming a metal film on the back surface of the semiconductor substrate, and the wiring to the source 10 region is formed by the metal wiring layer 15 formed on the front surface side of the substrate. Gate
13 is made of polysilicon in the groove in which the gate oxide film 14 is formed, and is insulated from the wiring layer 15 to the source 10 region through the interlayer insulating film 16 formed in the groove. As described above, the structure in which the interlayer insulating film 16 is housed in the groove and does not protrude from the surface of the substrate is adopted.

An embodiment of the method for manufacturing a MOS transistor according to the present invention will be described below. The cell portion of the MOS transistor and the peripheral portion used for wiring and the like are formed on the surface of the substrate in which the N type epitaxial layer is formed on the N type silicon substrate. The feature of the present invention resides in the cell portion. Therefore, only the manufacturing method of that portion will be described. After forming a field oxide film in the peripheral portion, a P-type relatively deep layer is formed in the cell portion by ion implantation. The inside of this P-type layer will later become a P-type well.

A mask for photoetching a trench is formed on the surface of the silicon substrate having the P-type layer formed on the surface as described above, and silicon is etched from the surface to form a groove (FIG. 2). (A)). The depth of this groove (groove) is about 2 mμ. The depth of this groove is such that it penetrates the P-type region and reaches the N-type region. The steps up to this point are not much different from the conventional steps except for the depth of the P-type layer.

An oxide film is formed on the trench and the surface of the silicon substrate (FIG. 2 (B)). This oxide film serves as a gate oxide film and can be formed by an ordinary method. The thickness of the gate oxide film is about 250Å.

Polysilicon doped with P-type impurities is deposited in the silicon substrate on which the gate oxide film is formed and the trench (groove) (FIG. 2C). The thickness of this polysilicon is about 8000Å. As a result, a polysilicon layer is formed on the entire surface of the silicon substrate. It is deposited to leave the portion formed in the groove as a gate electrode.

Next, the polysilicon is etched to leave the polysilicon layer as the gate electrode. At this time, a mask is formed in the peripheral portion to leave polysilicon as a wiring, but the cell portion is entirely etched. This etching is performed until polysilicon does not remain on the surface of the silicon substrate other than the portion where the groove is formed (FIG. 2D).

The surface of the polysilicon in the groove is oxidized to 200 Å
An oxide film of a certain degree is formed on the surface (FIG. 3). At this time, an oxide film is similarly formed on the surface of the polysilicon layer used for wiring in the peripheral portion.

In order to use the oxide film covering the polysilicon in the groove thus formed as an interlayer insulating film, a heat treatment step is required. In this heat treatment step, an N-type region to be a source region is formed on the surface of the silicon substrate (FIG. 4). At this time, if the interlayer insulating film in the groove is set so as to almost completely fill the trench, the silicon substrate will have a substantially flat surface as a whole.

As described above, the metal film to be the wiring of the source region is deposited on the surface of the silicon substrate which is filled with the polysilicon serving as the gate and the interlayer insulating film in the groove (FIG. 6). The metal film is formed of aluminum or the like containing 1% of silicon and has a thickness of about 40,000Å. Thereafter, the pre-process is completed by etching the wiring pattern and forming a passivation film.

The process of the present invention is not limited to the above, and basically any process capable of forming the interlayer insulating film only in the groove may be used. As a result, the photolithography process can be omitted once, and the distance between the polysilicon gates can be minimized, so that space efficiency can be improved and a cell of a highly integrated MOS transistor can be formed. It becomes possible to manufacture.

Further, by providing the deep source region with the diffusion region, it is not necessary to use the barrier metal in the connection portion (contact) with the metal wiring even if the metal spike occurs. It is also possible to prevent the problem of increase in contact resistance caused by using a barrier metal such as TiN.

[0024]

According to the present invention, since the cell pitch can be reduced, the cell density of the power MOSFET can be increased, and the channel resistance per unit area can be reduced. It is possible to reduce the resistance of the.

Since the upper surface of the contact hole is at the same height as the surface of the silicon substrate, the metal film formed by sputtering can be made uniform and voids inside the source metal electrode film can be eliminated to eliminate the element The reliability can be increased.

[Brief description of drawings]

FIG. 1 is a front sectional view showing an embodiment of the present invention.

FIG. 2 is a front sectional view showing a process of the present invention.

FIG. 3 is a front sectional view showing a process of the present invention.

FIG. 4 is a front sectional view showing a process of the present invention.

FIG. 5 is a front sectional view showing a process of the present invention.

FIG. 6 is a front sectional view showing a conventional MOSFET.

[Explanation of symbols]

10: Source 11: Drain 13: Gate 14: Gate oxide film 15: Metal wiring layer 16: Interlayer insulation film

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H01L 29/78 658G

Claims (4)

[Claims] 1. A second conductivity type layer is provided at a predetermined depth from the surface of a first conductivity type semiconductor substrate to be a drain region, and a source region of the first conductivity type is provided on the surface. A groove reaching the first conductivity type semiconductor substrate from the surface through the second conductivity type layer, the groove facing the second conductivity type region via an insulating film. In a MOS transistor having a gate electrode for forming a gate electrode, and an interlayer insulating film on the surface side of the gate electrode and a conductor film connected to the source region, an interlayer insulating film covering the gate electrode is formed inside the groove. Characteristic MOS transistor. 2. The MOS transistor according to claim 1, wherein an interlayer insulating film is formed inside the groove so as to cover the gate electrode, and the surface of the interlayer insulating film is made substantially equal to the surface of the semiconductor substrate. 3. A method of manufacturing a vertical MOS transistor in which a gate electrode is formed in a groove in a semiconductor substrate, wherein a predetermined depth is formed from a surface of a first conductivity type semiconductor substrate to be a drain region. A second conductivity type layer is formed at the position of, and a layer to be a source region of the first conductivity type is formed on the surface, and the first conductivity type is penetrated from the surface to the second conductivity type layer. Forming a groove reaching the semiconductor substrate of the second type, a gate electrode facing the second conductivity type region is formed in the groove via an insulating film, and the gate electrode is formed inside the groove on the surface side of the gate electrode. A method of manufacturing a MOS transistor, which comprises forming an interlayer insulating film to cover and forming a conductor film connected to the source region on the surface of the semiconductor substrate including the groove. 4. The method of manufacturing a MOS transistor according to claim 3, wherein a polysilicon layer is formed as the gate electrode.