JP2005033023A - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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JP2005033023A
JP2005033023A JP2003271231A JP2003271231A JP2005033023A JP 2005033023 A JP2005033023 A JP 2005033023A JP 2003271231 A JP2003271231 A JP 2003271231A JP 2003271231 A JP2003271231 A JP 2003271231A JP 2005033023 A JP2005033023 A JP 2005033023A
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spacer
insulating film
wiring
forming
semiconductor device
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Michihiro Sugano
道博 菅野
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Sony Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor device for enhancing the embedding of an insulation film between wires spaced with a narrow interval and forming the insulating film without high reliability without causing voids to the insulating film when the insulating film is embedded between the wires. <P>SOLUTION: The manufacturing method of the semiconductor device includes the steps of forming spacers 17 to the sides of the wires 14 after forming the wires 14 on a substrate 11; forming the insulating film 21 to be embedded between the wires 14 on the substrate 11 and covering the wires 14 and the spacers 17; and removing each upper side face of the spacers 17 in order to increase the curvature of each upper side face of the spacers 17 before, forming the pacers 17, and thereafter forming the insulating film 21. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明は、半導体装置の製造方法および半導体装置に関し、詳しくは半導体装置の絶縁膜の形成に係わる半導体装置の製造方法およびその製造方法により形成される半導体装置に関する。   The present invention relates to a semiconductor device manufacturing method and a semiconductor device, and more particularly to a semiconductor device manufacturing method related to formation of an insulating film of a semiconductor device and a semiconductor device formed by the manufacturing method.

従来、半導体装置における金属配線形成工程前の層間絶縁膜の形成技術およびその層間絶縁膜の平坦化技術は、ホウ素やヒ素を入れて流動化させるホウ素リンシリケートガラス（ＢＰＳＧ）を用いたリフロー技術や、全面エッチバック技術の組み合わせなどが主流であった（例えば、特許文献１参照。）が、世代が進むにつれて高温処理によるトランジスタ特性や信頼性への影響が無視できなくなってきたことや、リソグラフィーの焦点深度（ＤＯＦ）マージン確保のためにはグローバル段差を極力抑える必要性が生じてきたことなどにより、低温でグローバル段差を小さくできるプロセス技術に変わってきた。   Conventionally, a technique for forming an interlayer insulating film before a metal wiring forming process in a semiconductor device and a technique for planarizing the interlayer insulating film include a reflow technique using boron phosphorus silicate glass (BPSG) in which boron and arsenic are introduced and fluidized, However, the combination of full-scale etch-back techniques has been the mainstream (see, for example, Patent Document 1). However, as generations have progressed, the influence of high-temperature processing on transistor characteristics and reliability has become ignorable. In order to secure a depth of focus (DOF) margin, it has become necessary to suppress the global level difference as much as possible, and the process technology has been changed to reduce the global level difference at a low temperature.

熱的にはトランジスタに影響を及ぼさない温度限界から、０．１μｍ世代のトランジスタでは熱処理温度を６００℃以下に抑える必要があり、局所（ローカル）段差のギャップフィル（Gap-fill）特性との兼ね合いからオゾン−ノンドープトシリケートガラス（Ｏ3ＮＳＧ）膜や高密度プラズマ−ノンドープトシリケートガラス（ＨＤＰＮＳＧ）膜が埋め込みの絶縁膜として使われている。これらの膜のグローバル段差を低減する方法の主流としては化学的機械研磨（以下、ＣＭＰという）があげられる。 Because of the temperature limit that does not affect the transistor thermally, it is necessary to keep the heat treatment temperature below 600 ° C in the 0.1 μm generation transistor, which is a balance with the gap fill characteristics of local steps. Ozone-non-doped silicate glass (O 3 NSG) film and high-density plasma-non-doped silicate glass (HDPNSG) film are used as buried insulating films. A main method for reducing the global level difference of these films is chemical mechanical polishing (hereinafter referred to as CMP).

特開平１０−１８９５１８号公報（段落番号０００２および段落番号００１３−００２２、図１および３）JP-A-10-189518 (paragraph number 0002 and paragraph number 0013-0022, FIGS. 1 and 3)

しかしながら、これら低温で埋め込み可能な膜種であっても、０．１μｍ世代のロジック部ゲート−ゲート間距離の設計値は０．２μｍ以下と小さくなり、さらに図４に示すように、ゲート配線１１４の側壁にスペーサ膜１１７が形成されるので、スペーサ１１７間の実質的なアスペクト比は１を大きく超えることになる。このため、埋め込み絶縁膜１２１によるこの部分の段差被覆が難しくなる。また、スペーサ膜１１７の側壁１１７ｓの傾斜が垂直になり、絶縁膜１２１の埋め込み性が悪化し、ゲート配線１１４、１１４間にボイド１３１を生じるようになる。さらに、図示はしないが、ソース・ドレイン領域となる拡散層上およびゲート上にサリサイド（Salicide）を形成する前のウエットエッチング処理やスペーサ膜厚のばらつきなどで、下地プロセスばらつきが悪化する方向になって埋め込み領域がオーバーハング状態となるとさらに埋め込みが厳しくなることがわかっている。   However, even for these types of films that can be embedded at low temperatures, the design value of the logic part gate-gate distance of the 0.1 μm generation is as small as 0.2 μm or less. Further, as shown in FIG. Since the spacer film 117 is formed on the side wall, the substantial aspect ratio between the spacers 117 greatly exceeds 1. For this reason, it becomes difficult to cover this portion with the buried insulating film 121. In addition, the inclination of the side wall 117 s of the spacer film 117 becomes vertical, the embedding property of the insulating film 121 is deteriorated, and a void 131 is generated between the gate wirings 114 and 114. Further, although not shown in the drawing, the underlying process variation tends to deteriorate due to the wet etching process before the formation of the salicide (Salicide) on the diffusion layer serving as the source / drain regions and the variation of the spacer film thickness. It has been found that the embedding becomes more severe when the embedding region is overhanged.

また、ＨＤＰＮＳＧを用いて層間絶縁膜を形成する場合は、成膜プロセスがプラズマ中のため、プラズマダメージによるトランジスタ特性や信頼性への影響が、プラズマの影響が受けやすいアンテナ比の高いトランジスタにおいて顕著になる問題がある。それに比べてオゾンＮＳＧはプラズマダメージの影響がないので、ダメージフリーであることにおいて優位である。   In addition, when an interlayer insulating film is formed using HDPNSG, since the film forming process is in plasma, the influence of plasma damage on transistor characteristics and reliability is remarkable in a transistor having a high antenna ratio that is easily affected by plasma. There is a problem to become. In comparison, ozone NSG is not affected by plasma damage, and is superior in being free from damage.

したがって、埋め込みの膜そのものの能力向上だけでなく、下地プロセスのばらつき抑制や埋め込みのしやすい形状にするようなプロセスインテグレーレションによる改善が必要になっている。   Therefore, it is necessary not only to improve the capability of the embedded film itself, but also to improve the process integration so as to suppress the variation of the underlying process and make the shape easy to be embedded.

本発明の半導体装置の製造方法は、基板上に配線を形成した後に前記配線の側部にスペーサを形成する工程と、前記基板上に前記配線間を埋め込むとともに前記配線および前記スペーサを被覆する絶縁膜を形成する工程とを備えた半導体装置に製造方法において、前記スペーサを形成した後で前記絶縁膜を形成する前に、前記スペーサの上部側面の曲率を大きくするように前記スペーサ上部の側部を除去する工程を備えていることを最も主要な特徴とする。   According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming a spacer on a side of the wiring after forming the wiring on the substrate; and insulating covering the wiring and the spacer while embedding the wiring on the substrate. In the manufacturing method of the semiconductor device including the step of forming a film, the side portion of the upper portion of the spacer is formed so as to increase the curvature of the upper side surface of the spacer before forming the insulating film after forming the spacer. The most important feature is that it includes a step of removing.

上記半導体装置の製造方法では、スペーサを形成した後で絶縁膜を形成する前に、スペーサの上部側面の曲率を大きくするようにスペーサの上部側面を除去することから、スペーサ側壁の急峻な傾斜面が緩く形成されることになり、絶縁膜の埋め込みが容易になる。よって、スペーサ間の絶縁膜の埋め込みに際し、ボイドの発生が防止される。   In the manufacturing method of the semiconductor device, since the upper side surface of the spacer is removed so as to increase the curvature of the upper side surface of the spacer before forming the insulating film after forming the spacer, the steep inclined surface of the spacer side wall is removed. Therefore, the insulating film is easily embedded. Therefore, generation of voids is prevented when the insulating film is embedded between the spacers.

本発明の半導体装置は、基板上に形成された配線と、前記配線の側部に形成されたスペーサと、前記配線間を埋め込むとともに前記配線および前記スペーサを被覆するように前記基板上に形成された絶縁膜とを備えた半導体装置において、前記スペーサは、前記スペーサの上部側面の曲率を大きくするように前記スペーサの上部側面が除去されたものからなり、前記配線側部に形成されたスペーサ間の前記絶縁膜が埋め込まれる領域はアスペクトが１以下となるように形成されているものであることを最も主要な特徴とする。   The semiconductor device according to the present invention is formed on the substrate so as to embed a space between the wirings and cover the wirings and the spacers while wirings formed on the substrate, spacers formed on side portions of the wirings, and the wirings. In the semiconductor device including the insulating film, the spacer is formed by removing the upper side surface of the spacer so as to increase the curvature of the upper side surface of the spacer, and between the spacers formed on the wiring side portion. The region in which the insulating film is buried is formed so that the aspect is 1 or less.

上記半導体装置では、スペーサは、スペーサの上部側面の曲率を大きくするようにスペーサの上部側面が除去されたものからなることから、スペーサ側面の急峻な傾斜面が緩く形成されることになり、絶縁膜の埋め込みが容易になる。さらに、配線側部に形成されたスペーサ間の絶縁膜が埋め込まれる領域はアスペクトが１以下となるように形成されていることから、絶縁膜の埋め込みの容易性が高められる。よって、スペーサ間の絶縁膜の埋め込みに際し、ボイドの発生が防止される。   In the semiconductor device, since the spacer is formed by removing the upper side surface of the spacer so as to increase the curvature of the upper side surface of the spacer, a steep inclined surface on the side surface of the spacer is formed loosely, and insulation is performed. The film can be easily embedded. Furthermore, since the region where the insulating film between the spacers formed on the wiring side portion is embedded is formed so that the aspect is 1 or less, the ease of embedding the insulating film is enhanced. Therefore, generation of voids is prevented when the insulating film is embedded between the spacers.

本発明の半導体装置の製造方法によれば、スペーサを形成した後で絶縁膜を形成する前に、スペーサの上部側面の曲率を大きくするようにスペーサの上部側面を除去することから、スペーサ側壁の急峻な傾斜面が緩く形成されることになり、絶縁膜の埋め込みが容易になる。よって、従来の絶縁膜材料による狭いスペーサ間の埋め込みに際し、ボイドの発生が防止される。このように、ボイドを発生することなく、絶縁膜を配線間に良好に埋め込むことが可能になることで、コンタクト−コンタクト間のショートがなくなり、コンタクトのショート起因によるデバイスの歩留まり低下をなくすことができる。またドライエッチング工程を追加するだけですみ、プロセスが簡単である。さらに、従来から適用されているデバイスのスペーサ構造を利用することができ、従来のプロセスから要求されるスペーサ構造との整合性がよいという利点がある。   According to the method of manufacturing a semiconductor device of the present invention, the upper side surface of the spacer is removed so as to increase the curvature of the upper side surface of the spacer before forming the insulating film after forming the spacer. A steep inclined surface is formed loosely, and the insulating film can be easily embedded. Therefore, generation of voids is prevented when the narrow spacers are filled with the conventional insulating film material. In this way, it is possible to satisfactorily embed the insulating film between the wirings without generating voids, so that there is no contact-contact short circuit, and the device yield reduction due to the contact short circuit can be eliminated. it can. Moreover, it is only necessary to add a dry etching process, and the process is simple. Furthermore, the spacer structure of the device applied conventionally can be used, and there is an advantage that the matching with the spacer structure required from the conventional process is good.

本発明の半導体装置によれば、スペーサは、スペーサの上部側面の曲率を大きくするようにスペーサの上部側面が除去されたものからなることから、スペーサ側面の急峻な傾斜面が緩く形成されることになり、絶縁膜の埋め込みが容易になる。さらに、配線側部に形成されたスペーサ間の絶縁膜が埋め込まれる領域はアスペクトが１以下となるように形成されていることから、絶縁膜の埋め込みの容易性が高められる。よって、スペーサ間の絶縁膜の埋め込みに際し、ボイドの発生を防止することができるので、信頼性の高い絶縁膜構造をもつ半導体装置とすることができるという利点がある。   According to the semiconductor device of the present invention, since the spacer is formed by removing the upper side surface of the spacer so as to increase the curvature of the upper side surface of the spacer, the steep inclined surface of the spacer side surface is formed loosely. This makes it easier to fill the insulating film. Furthermore, since the region where the insulating film between the spacers formed on the wiring side portion is embedded is formed so that the aspect is 1 or less, the ease of embedding the insulating film is enhanced. Accordingly, since voids can be prevented when the insulating film is embedded between the spacers, there is an advantage that a semiconductor device having a highly reliable insulating film structure can be obtained.

本発明の半導体装置の製造方法に係る第１実施の形態を、図１の製造工程断面図によって説明する。   A first embodiment of the method for manufacturing a semiconductor device according to the present invention will be described with reference to the manufacturing process sectional view of FIG.

図１（１）に示すように、通常のＭＯＳトランジスタの形成技術によって、基板（半導体基板）１１に対してアクティブ領域を分離する素子分離領域およびフィールド領域となるフィールド絶縁膜１２を形成する。上記半導体基板には通常のシリコン基板を用いた。次いで、上記基板１１上にゲート絶縁膜１３を形成する。次いで、ゲート電極およびゲート配線を形成するための導電膜を形成した後、リソグラフィー技術およびエッチング技術を用いて導電膜をゲート電極およびゲート配線（以下、ゲート電極およびゲート配線を配線１４という）に加工する。上記導電膜は、例えばポリシリコンにて形成される。このポリシリコン膜の膜厚は、例えば２００ｎｍとし、フィールド絶縁膜１２上の配線１４（１４a）とこの配線１４ａに隣接する配線１４（１４ｂ）との間隔は、例えば設計値で２００ｎｍとする。ポリシリコン膜厚は、後に形成されるサリサイドのブリッジング（Bridging）や、ゲート絶縁膜１３に与える影響から決められている。配線１４間の間隔は配線１４の加工限界から決まる。なお、配線１４の間隔は実際には設計値よりもやや広く形成される。   As shown in FIG. 1A, an element isolation region for isolating an active region from a substrate (semiconductor substrate) 11 and a field insulating film 12 to be a field region are formed by a normal MOS transistor forming technique. A normal silicon substrate was used as the semiconductor substrate. Next, a gate insulating film 13 is formed on the substrate 11. Next, after forming a conductive film for forming a gate electrode and a gate wiring, the conductive film is processed into a gate electrode and a gate wiring (hereinafter, the gate electrode and the gate wiring are referred to as a wiring 14) using a lithography technique and an etching technique. To do. The conductive film is made of, for example, polysilicon. The thickness of this polysilicon film is, for example, 200 nm, and the distance between the wiring 14 (14a) on the field insulating film 12 and the wiring 14 (14b) adjacent to this wiring 14a is, for example, 200 nm as a design value. The thickness of the polysilicon film is determined from the effect of salicide bridging, which will be formed later, and the gate insulating film 13. The interval between the wirings 14 is determined by the processing limit of the wirings 14. The interval between the wirings 14 is actually formed slightly wider than the design value.

次に、アクティブ領域の半導体基板１１に低濃度拡散層からなるエクステンション領域１５、１６を例えば配線１４をマスクにしたイオン注入により形成する。したがって、エクステンション領域１５、１６は、配線１４の側方におけるアクティブ領域の半導体基板１１に形成される。またＭＯＳＦＥＴの短チャネル効果を抑制するための斜めイオン注入を行う。   Next, extension regions 15 and 16 made of a low concentration diffusion layer are formed on the semiconductor substrate 11 in the active region by, for example, ion implantation using the wiring 14 as a mask. Therefore, the extension regions 15 and 16 are formed in the semiconductor substrate 11 in the active region on the side of the wiring 14. In addition, oblique ion implantation is performed to suppress the short channel effect of the MOSFET.

その後、図１（２）に示すように、配線１４の側部にスペーサ１７を形成する。スペーサ１７は、配線１４を被覆するように、スペーサを形成するための絶縁膜を形成した後、エッチバックによりその絶縁膜をエッチングして配線１４の側壁にのみ残すことにより形成される。ここでは、スペーサ１７を形成する絶縁膜に窒化シリコン膜を用い、その膜厚は一例として１００ｎｍとした。その結果、スペーサ１７は、配線１４の配設方向に沿った厚さｗはおよそ８０ｎｍになった。このとき、スペーサ１７の上部側面１７ｓｕは小さな曲率の曲面となっており、スペーサ１７の下部側面１７ｓｄは半導体基板１１表面に対して垂直な状態に形成された。また、スペーサ１７の下部側面１７ｓｄ（垂直面）におけるスペーサ１７間のアスペクト比は１以下であり、この状態では絶縁膜を埋め込んだ際にボイドを発生するような形状となっていた。   Thereafter, as shown in FIG. 1B, spacers 17 are formed on the side portions of the wiring 14. The spacer 17 is formed by forming an insulating film for forming the spacer so as to cover the wiring 14, and then etching the insulating film by etching back to leave only the side wall of the wiring 14. Here, a silicon nitride film is used as the insulating film for forming the spacer 17, and the film thickness is set to 100 nm as an example. As a result, the thickness 17 of the spacer 17 along the arrangement direction of the wiring 14 was about 80 nm. At this time, the upper side surface 17su of the spacer 17 has a curved surface with a small curvature, and the lower side surface 17sd of the spacer 17 is formed in a state perpendicular to the surface of the semiconductor substrate 11. In addition, the aspect ratio between the spacers 17 on the lower side surface 17sd (vertical surface) of the spacer 17 is 1 or less, and in this state, a void is generated when the insulating film is embedded.

次に、配線１４およびスペーサ１７をマスクにしたイオン注入法によって、アクティブ領域の半導体基板１１に上記低濃度拡散層よりも濃度の濃い（高濃度拡散層からなる）ソース・ドレイン領域１８、１９を形成する。このソース・ドレイン領域１８、１９は、配線１４側方のアクティブ領域の半導体基板１１にスペーサ１７の厚さ分、すなわちエクステンション領域１５、１６を介して形成される。ここでスペーサ１７は、ソース・ドレイン領域１８、１９のゲート電極となる配線１４（１４ｇ）側にエクステンション領域１５、１６というオフセットをつけることでＭＯＳＦＥＴのホットキャリア耐性向上を図るとともに、前記斜めイオン注入によって行われたＭＯＳＦＥＴの短チャネル効果抑制領域を残す役割を成す。   Next, the source / drain regions 18 and 19 having a higher concentration than the low concentration diffusion layer (consisting of the high concentration diffusion layer) are formed on the semiconductor substrate 11 in the active region by ion implantation using the wiring 14 and the spacer 17 as a mask. Form. The source / drain regions 18 and 19 are formed on the semiconductor substrate 11 in the active region on the side of the wiring 14 by the thickness of the spacer 17, that is, the extension regions 15 and 16. Here, the spacer 17 improves the hot carrier resistance of the MOSFET by offsetting the extension regions 15 and 16 on the side of the wiring 14 (14g) serving as the gate electrode of the source / drain regions 18 and 19, and the oblique ion implantation. It serves to leave a short channel effect suppression region of the MOSFET performed by the above.

次いで、図１（３）に示すように、サリサイド形成を行う。サリサイド形成は、スパッタリングにより、配線１４が形成されている側の全面に高融点金属膜を被覆形成した後、急速加熱処理（以下、ＲＴＡという、ＲＴＡはRapid Thermal Annealingの略）によって、シリコンの露出している部分において高融点金属膜とシリコンとをシリサイド反応させて、自己整合的にサリサイド層２０を形成する技術である。このサリサイド形成では、アクティブ領域の半導体基板１１（ソース・ドレイン領域１８、１９）上と配線１４上に同時に形成される。なお、絶縁膜であるフィールド絶縁膜１２上、スペーサ１７表面ではシリサイド化反応は起こらない。その後、シリサイド化反応に寄与しない余剰な高融点金属膜を除去する。   Next, as shown in FIG. 1 (3), salicide formation is performed. In the salicide formation, a refractory metal film is coated over the entire surface on which the wiring 14 is formed by sputtering, and then exposed to silicon by rapid heating (hereinafter referred to as RTA, RTA is abbreviated to Rapid Thermal Annealing). This is a technique for forming a salicide layer 20 in a self-aligned manner by subjecting a refractory metal film and silicon to a silicidation reaction in a portion where the film is formed. In this salicide formation, the active region is formed simultaneously on the semiconductor substrate 11 (source / drain regions 18 and 19) and the wiring 14 in the active region. Note that silicidation reaction does not occur on the surface of the spacer 17 on the field insulating film 12 which is an insulating film. Thereafter, an excessive refractory metal film that does not contribute to the silicidation reaction is removed.

次に、図１（４）に示すように、上記スペーサ１７の上部側面１７ｓｕの曲率を大きくするようにスペーサ１７の上部側面の曲率が小さな部分〔前記図１の（２）のスペーサの上部側面１７ｓｕ参照〕を例えばエッチングにより除去するとともに、このエッチングによりスペーサ１７の下部側面１７ｓｄから垂直面を無くしてスペーサ１７の側面全体を９０度未満の傾斜面、例えば８８度程度の傾斜面とする。これによって、スペーサ１７の側面間のアスペクト比を１未満とする。このように、スペーサ１７の側面をエッチングすることにより、スペーサ１７によるテーパー形状が顕著になるようにする。   Next, as shown in FIG. 1 (4), a portion having a small curvature on the upper side surface of the spacer 17 so as to increase the curvature of the upper side surface 17su of the spacer 17 [the upper side surface of the spacer in FIG. 17su] is removed by, for example, etching, and this etching eliminates the vertical surface from the lower side surface 17sd of the spacer 17 so that the entire side surface of the spacer 17 has an inclined surface of less than 90 degrees, for example, an inclined surface of about 88 degrees. As a result, the aspect ratio between the side surfaces of the spacer 17 is less than 1. As described above, the side surface of the spacer 17 is etched so that the taper shape by the spacer 17 becomes remarkable.

上記スペーサ１７の側面の除去加工は、具体的には、平行平板型ドライエッチング装置を用い、エッチングガスには、一例としてトリフルオロメタン（ＣＨＦ3）と酸素（Ｏ2）とを用い、それぞれのガスの流量は標準状態において、ＣＨＦ3が４５ｃｍ3／ｍｉｎ、Ｏ2が５ｃｍ3／ｍｉｎに設定され、エッチング雰囲気の圧力は５．３ｋＰａ、基板温度は２０℃に設定され、スペーサ１７の膜厚換算で３ｎｍ程度のエッチングを行うことにより成される。上記スペーサ１７のエッチングは一例であって、上記エッチング装置およびエッチング条件に限定されるものではなく、スペーサ１７を上記所望の形状にエッチングする条件であり、下地との選択比が高い条件であれば如何なる装置、条件であってもよい。 Specifically, the side surface of the spacer 17 is removed by using a parallel plate type dry etching apparatus. As an etching gas, for example, trifluoromethane (CHF 3 ) and oxygen (O 2 ) are used. In the standard state, the flow rate of CHF 3 is set to 45 cm 3 / min, O 2 is set to 5 cm 3 / min, the pressure of the etching atmosphere is set to 5.3 kPa, the substrate temperature is set to 20 ° C., and the film thickness of the spacer 17 is converted. This is done by performing etching of about 3 nm. The etching of the spacer 17 is an example, and is not limited to the etching apparatus and etching conditions, but is a condition for etching the spacer 17 into the desired shape as long as the selection ratio with the base is high. Any device and conditions may be used.

また、上記スペーサ１７の側壁を上記説明したごとくエッチング加工することによりテーパー形状にするだけでなく、エッチング量を大目にすることで、スペーサ１７の高さを低くして配線１４間のアスペクト比を小さくすることもできる。   Further, the side wall of the spacer 17 is not only tapered by etching as described above, but also by increasing the etching amount, the height of the spacer 17 is reduced and the aspect ratio between the wirings 14 is reduced. Can be reduced.

次いで、上記配線１４、スペーサ１７等を埋め込むように、半導体基板１１上に絶縁膜２１を形成する。その際、配線１４間はスペーサ１７を介して絶縁膜（層間絶縁膜）２１によって完全に埋め込む。この絶縁膜２１は６００℃以下の成膜温度で成膜可能なオゾン−ノンドープトガラス（Ｏ3−ＮＳＧ）を用いることができる。前述した通り、Ｏ3−ＮＳＧの成膜はプラズマＣＶＤによる成膜と異なってダメージフリーの優位性があるが、埋め込み領域の形状が少しでもオーバーハング状態に形成されていると完全な埋め込みが原理的にできなくなる特徴を有する。しかさいながら、本実施の形態では、スペーサ１７の側面は基板表面に対して９０度未満の傾斜面に形成されていることから、また、スペーサ１７間のアスペクト比が１未満となっていることから、Ｏ3−ＮＳＧの成膜においても配線１４間にボイドを発生することなく、完全なる埋め込みができる。 Next, an insulating film 21 is formed on the semiconductor substrate 11 so as to bury the wirings 14, the spacers 17, and the like. At that time, the space between the wirings 14 is completely filled with an insulating film (interlayer insulating film) 21 via a spacer 17. The insulating film 21 can be made of ozone-non-doped glass (O 3 -NSG) that can be formed at a film forming temperature of 600 ° C. or less. As described above, the film formation of O 3 -NSG has the advantage of being damage-free unlike the film formation by plasma CVD, but if the shape of the buried region is formed in an overhang state even a little, the principle of complete filling is the principle It has a characteristic that cannot be achieved. However, in the present embodiment, the side surface of the spacer 17 is formed as an inclined surface of less than 90 degrees with respect to the substrate surface, and the aspect ratio between the spacers 17 is less than 1. Therefore, even when the O 3 —NSG film is formed, complete embedding can be performed without generating voids between the wirings 14.

上記製造方法によれば、スペーサ１７を形成した後で絶縁膜２１を形成する前に、スペーサ１７の上部側面１７ｓｕの曲率を大きくするようにスペーサ１７上部の側部を除去することから、スペーサ１７の側壁の急峻な傾斜面が緩く形成されることになり、絶縁膜２１の埋め込みが容易になる。よって、スペーサ１７間の絶縁膜２１の埋め込みに際し、ボイドの発生が防止される。   According to the manufacturing method described above, the side portion of the upper portion of the spacer 17 is removed so as to increase the curvature of the upper side surface 17su of the spacer 17 before the insulating film 21 is formed after the spacer 17 is formed. The steeply inclined surface of the side wall is formed loosely, and the embedding of the insulating film 21 becomes easy. Therefore, generation of voids is prevented when the insulating film 21 is embedded between the spacers 17.

また、上記スペーサ１７を形成し、スペーサ１７の側面の形状を９０度未満の傾斜面に加工した後、配線１４間の領域を埋め込む上記絶縁膜２１を形成する前に、配線１４間の領域を埋め込むことなく配線１４およびスペーサ１７を被覆する絶縁膜（図示せず）を形成した場合には、配線１４間におけるスペーサ１７および被覆絶縁膜（図示せず）を介した領域のアスペクト比が１未満であればよい。   In addition, after forming the spacer 17 and processing the shape of the side surface of the spacer 17 into an inclined surface of less than 90 degrees, before forming the insulating film 21 that fills the region between the wirings 14, the region between the wirings 14 is formed. When an insulating film (not shown) that covers the wiring 14 and the spacer 17 without being embedded is formed, the aspect ratio of the region between the wiring 14 via the spacer 17 and the covering insulating film (not shown) is less than 1. If it is.

次に、本発明の半導体装置の製造方法に係る第２実施の形態を、図２の製造工程断面図によって説明する。この第２実施の形態では前記第１実施の形態で説明したのと同様なる構成部品には、前記第１実施の形態と同一の符号を付与して説明する。   Next, a second embodiment of the method for manufacturing a semiconductor device according to the present invention will be described with reference to the manufacturing process sectional view of FIG. In the second embodiment, the same components as those described in the first embodiment will be described with the same reference numerals as those in the first embodiment.

前記第１実施の形態と同様にして、図２（１）に示すように、通常のＭＯＳトランジスタの形成技術によって、基板（半導体基板）１１に対してアクティブ領域を分離する素子分離領域およびフィールド領域となるフィールド絶縁膜１２を形成する。上記半導体基板には通常のシリコン基板を用いた。次いで、上記アクティブ領域の基板１１上にゲート絶縁膜１３を形成する。次いで、ゲート電極およびゲート配線を形成するための導電膜を形成した後、リソグラフィー技術およびエッチング技術を用いて導電膜をゲート電極およびゲート配線（以下、ゲート電極およびゲート配線を配線１４という）に加工する。上記導電膜は、例えばポリシリコンにて形成される。このポリシリコン膜の膜厚は、例えば２００ｎｍとし、フィールド絶縁膜１２上の配線１４（１４a）とこの配線１４ａに隣接する配線１４（１４ｂ）との間隔は、例えば２００ｎｍとする。ポリシリコン膜厚は、後に形成されるサリサイドのブリッジング（Bridging）や、ゲート絶縁膜１３に与える影響から決められている。配線１４間の間隔は配線１４の加工限界から決まる。なお、配線１４の間隔は実際には設計値よりもやや広く形成される。   As in the first embodiment, as shown in FIG. 2A, an element isolation region and a field region for isolating an active region from a substrate (semiconductor substrate) 11 by a normal MOS transistor forming technique. A field insulating film 12 is formed. A normal silicon substrate was used as the semiconductor substrate. Next, a gate insulating film 13 is formed on the substrate 11 in the active region. Next, after forming a conductive film for forming a gate electrode and a gate wiring, the conductive film is processed into a gate electrode and a gate wiring (hereinafter, the gate electrode and the gate wiring are referred to as a wiring 14) using a lithography technique and an etching technique. To do. The conductive film is made of, for example, polysilicon. The thickness of this polysilicon film is, for example, 200 nm, and the distance between the wiring 14 (14a) on the field insulating film 12 and the wiring 14 (14b) adjacent to this wiring 14a is, for example, 200 nm. The thickness of the polysilicon film is determined from the effect of salicide bridging, which will be formed later, and the gate insulating film 13. The interval between the wirings 14 is determined by the processing limit of the wirings 14. The interval between the wirings 14 is actually formed slightly wider than the design value.

次に、アクティブ領域の半導体基板１１に低濃度拡散層からなるエクステンション領域１５、１６を例えば配線１４をマスクにしたイオン注入により形成する。したがって、エクステンション領域１５、１６は、配線１４の側方におけるアクティブ領域の半導体基板１１に形成される。またＭＯＳＦＥＴの短チャネル効果を抑制するための斜めイオン注入を行う。   Next, extension regions 15 and 16 made of a low concentration diffusion layer are formed on the semiconductor substrate 11 in the active region by, for example, ion implantation using the wiring 14 as a mask. Therefore, the extension regions 15 and 16 are formed in the semiconductor substrate 11 in the active region on the side of the wiring 14. In addition, oblique ion implantation is performed to suppress the short channel effect of the MOSFET.

その後、図２（２）に示すように、配線１４の側部にスペーサ１７を形成する。スペーサ１７は、配線１４を被覆するように、スペーサを形成するための絶縁膜を形成した後、エッチバックによりその絶縁膜をエッチングして配線１４の側壁にのみ残すことにより形成される。ここでは、スペーサ１７を形成する絶縁膜に窒化シリコン膜１７１と酸化シリコン膜１７２の２層の絶縁膜を用い、その膜厚は一例として、窒化シリコン膜１７１は２０ｎｍ、酸化シリコン膜１７２は８０ｎｍとした。エッチバックにより形成されたスペーサ１７の上部側面１７ｓｕは小さな曲率の曲面となっており、スペーサ１７の下部側面１７ｓｄは半導体基板１１表面に対して垂直な状態に形成された。このように、スペーサ１７を形成する絶縁膜を２層構造にすることで、第１実施の形態のように窒化シリコン膜単層の場合と比較して、エッチバック時のフィールド酸化膜との選択比が取り易くなった。つまり、窒化シリコン膜１７１をストッパーとして酸化シリコン膜１７２をエッチングし、窒化シリコン膜１７１を薄くすることで窒化シリコン膜１７１のエッチング時にはフィールド絶縁膜１２のフィールド酸化膜をできるだけ削らないようにしている。   Thereafter, as shown in FIG. 2B, spacers 17 are formed on the side portions of the wirings 14. The spacer 17 is formed by forming an insulating film for forming the spacer so as to cover the wiring 14, and then etching the insulating film by etching back to leave only the side wall of the wiring 14. Here, a two-layer insulating film of a silicon nitride film 171 and a silicon oxide film 172 is used as an insulating film for forming the spacer 17, and the film thicknesses thereof are, for example, 20 nm for the silicon nitride film 171 and 80 nm for the silicon oxide film 172. did. The upper side surface 17su of the spacer 17 formed by etch back has a curved surface with a small curvature, and the lower side surface 17sd of the spacer 17 is formed in a state perpendicular to the surface of the semiconductor substrate 11. As described above, the insulating film for forming the spacer 17 has a two-layer structure, so that the selection of the field oxide film at the time of etch back is made as compared with the case of the silicon nitride film single layer as in the first embodiment. The ratio is easy to take. That is, the silicon oxide film 172 is etched using the silicon nitride film 171 as a stopper, and the silicon nitride film 171 is thinned so that the field oxide film of the field insulating film 12 is not etched as much as possible when the silicon nitride film 171 is etched.

また、酸化シリコン膜／窒化シリコン膜／酸化シリコン膜のように窒化シリコン膜を酸化シリコン膜で挟む構造とすることもできる。この場合には、例えば、上層の酸化シリコン膜を７０ｎｍ、中間層の窒化シリコン膜を２０ｎｍ、下層の酸化シリコン膜を１０ｎｍの厚さに形成する。これは先に説明した２層構造のスペーサと比較すると窒化シリコン膜が配線１４（ゲート電極）に直接に触れることがないため、界面準位の発生を抑えることができ、トランジスタ特性や信頼性的に優位な構造となる。また、窒化シリコン膜のストレスを酸化シリコン膜で緩和させることにもなり、ゲート電極への窒化シリコン膜の応力によるストレスを低減することもできる。   Alternatively, a structure in which a silicon nitride film is sandwiched between silicon oxide films, such as a silicon oxide film / a silicon nitride film / a silicon oxide film, may be employed. In this case, for example, the upper silicon oxide film is formed to a thickness of 70 nm, the intermediate silicon nitride film is formed to a thickness of 20 nm, and the lower silicon oxide film is formed to a thickness of 10 nm. This is because the silicon nitride film does not directly touch the wiring 14 (gate electrode) as compared with the spacer having the two-layer structure described above, so that generation of interface states can be suppressed, and transistor characteristics and reliability are improved. It becomes a structure superior to. Further, the stress of the silicon nitride film is relieved by the silicon oxide film, and the stress due to the stress of the silicon nitride film on the gate electrode can be reduced.

その後は、前記第１実施の形態で説明したのと同様に、ソース・ドレイン領域形成以降の工程を行う。すなわち、配線１４およびスペーサ１７をマスクにしたイオン注入法によって、アクティブ領域の半導体基板１１に上記低濃度拡散層よりも濃度の濃い（高濃度拡散層からなる）ソース・ドレイン領域１８、１９を形成する。このソース・ドレイン領域１８、１９は、配線１４側方のアクティブ領域の半導体基板１１にスペーサ１７の厚さ分、すなわちエクステンション領域１５、１６を介して形成される。ここでスペーサ１７は、ソース・ドレイン領域１８、１９のゲート電極となる配線１４（１４ｇ）側にエクステンション領域１５、１６というオフセットをつけることでＭＯＳＦＥＴのホットキャリア耐性向上を図るとともに、前記斜めイオン注入によって行われたＭＯＳＦＥＴの短チャネル効果抑制領域を残す役割を成す。   Thereafter, the steps after the formation of the source / drain regions are performed in the same manner as described in the first embodiment. That is, the source / drain regions 18 and 19 having a higher concentration than the low concentration diffusion layer (consisting of the high concentration diffusion layer) are formed in the semiconductor substrate 11 in the active region by ion implantation using the wiring 14 and the spacer 17 as a mask. To do. The source / drain regions 18 and 19 are formed on the semiconductor substrate 11 in the active region on the side of the wiring 14 by the thickness of the spacer 17, that is, the extension regions 15 and 16. Here, the spacer 17 improves the hot carrier resistance of the MOSFET by offsetting the extension regions 15 and 16 on the side of the wiring 14 (14g) serving as the gate electrode of the source / drain regions 18 and 19, and the oblique ion implantation. It serves to leave a short channel effect suppression region of the MOSFET performed by the above.

次いで、図２（３）に示すように、サリサイド形成を行う。サリサイド形成は、スパッタリングにより配線１４が形成されている側の全面に高融点金属膜を被覆形成した後、急速加熱処理（以下、ＲＴＡという、ＲＴＡはRapid Thermal Annealingの略）によって、シリコンの露出している部分において高融点金属膜とシリコンとをシリサイド反応させて、自己整合的にサリサイド層２０を形成する技術である。このサリサイド形成では、アクティブ領域の半導体基板１１（ソース・ドレイン領域１８、１９）上と配線１４上に同時に形成される。その後、シリサイド化反応に寄与しない余剰な高融点金属膜を除去する。   Next, as shown in FIG. 2 (3), salicide formation is performed. In the salicide formation, a refractory metal film is coated over the entire surface where the wiring 14 is formed by sputtering, and then silicon is exposed by rapid heating treatment (hereinafter referred to as RTA, RTA is an abbreviation for Rapid Thermal Annealing). In this part, the salicide layer 20 is formed in a self-aligned manner by subjecting the refractory metal film and silicon to a silicidation reaction. In this salicide formation, the active region is formed simultaneously on the semiconductor substrate 11 (source / drain regions 18 and 19) and the wiring 14 in the active region. Thereafter, an excessive refractory metal film that does not contribute to the silicidation reaction is removed.

次に、図２（４）に示すように、上記スペーサ１７の上部側面１７ｓｕの曲率を大きくするようにスペーサ１７の上部側面の曲率が小さな部分〔前記図１の（２）のスペーサの上部側面１７ｓｕ参照〕を例えばエッチングにより除去するとともに、このエッチングによりスペーサ１７の下部側面１７ｓｄから垂直面を無くしてスペーサの側面１７ｓ全体を９０度未満の傾斜面、例えば８８度程度の傾斜面とするとともに、スペーサの側面１７ｓ間のアスペクト比を１未満とする。このように、スペーサ１７の側面をエッチングすることにより、スペーサ１７によるテーパー形状が顕著になるようにする。   Next, as shown in FIG. 2 (4), a portion having a small curvature on the upper side surface of the spacer 17 so as to increase the curvature of the upper side surface 17su of the spacer 17 [the upper side surface of the spacer in FIG. 17su] is removed by etching, for example, and the etching eliminates the vertical surface from the lower side surface 17sd of the spacer 17 so that the entire side surface 17s of the spacer has an inclined surface of less than 90 degrees, for example, an inclined surface of about 88 degrees. The aspect ratio between the side surfaces 17s of the spacer is less than 1. As described above, the side surface of the spacer 17 is etched so that the taper shape by the spacer 17 becomes remarkable.

上記スペーサ１７の側面の除去加工は、スペーサ１７を上記所望の形状にエッチングする条件であり、下地との選択比が高い条件であれば如何なる装置、条件であってもよい。また、上記スペーサ１７の側壁を上記説明したごとくエッチング加工することによりテーパー形状にするだけでなく、エッチング量を大目にすることで、スペーサ１７の高さを低くして配線１４間のアスペクト比を小さくすることもできる。   The removal processing of the side surface of the spacer 17 is a condition for etching the spacer 17 into the desired shape, and any apparatus and conditions may be used as long as the selection ratio with the base is high. Further, the side wall of the spacer 17 is not only tapered by etching as described above, but also by increasing the etching amount, the height of the spacer 17 is reduced and the aspect ratio between the wirings 14 is reduced. Can be reduced.

次いで、上記配線１４、スペーサ１７等を埋め込むように、半導体基板１１上に絶縁膜２１を形成する。その際、配線１４間はスペーサ１７を介して絶縁膜（層間絶縁膜）２１によって完全に埋め込む。この絶縁膜２１は６００℃以下の成膜温度で成膜可能なオゾン−ノンドープトガラス（Ｏ3−ＮＳＧ）を用いることができる。前述した通り、Ｏ3−ＮＳＧの成膜はプラズマＣＶＤによる成膜と異なってダメージフリーの優位性があるが、埋め込み領域の形状が少しでもオーバーハング状態に形成されていると完全な埋め込みが原理的にできなくなる特徴を有する。しかさいながら、本実施の形態では、スペーサ１７の側面は基板表面に対して９０度未満の傾斜面に形成されていることから、また、スペーサ１７間のアスペクト比が１未満となっていることから、Ｏ3−ＮＳＧの成膜においても配線１４間にボイドを発生することなく、完全なる埋め込みができる。 Next, an insulating film 21 is formed on the semiconductor substrate 11 so as to bury the wirings 14, the spacers 17, and the like. At that time, the space between the wirings 14 is completely filled with an insulating film (interlayer insulating film) 21 via a spacer 17. The insulating film 21 can be made of ozone-non-doped glass (O 3 -NSG) that can be formed at a film forming temperature of 600 ° C. or less. As described above, the film formation of O 3 -NSG has the advantage of being damage-free unlike the film formation by plasma CVD, but if the shape of the buried region is formed in an overhang state even a little, the principle of complete filling is the principle It has a characteristic that cannot be achieved. However, in the present embodiment, the side surface of the spacer 17 is formed as an inclined surface of less than 90 degrees with respect to the substrate surface, and the aspect ratio between the spacers 17 is less than 1. Therefore, even when the O 3 —NSG film is formed, complete embedding can be performed without generating voids between the wirings 14.

上記製造方法によれば、スペーサ１７を形成した後で絶縁膜２１を形成する前に、スペーサ１７の上部側面１７ｓｕの曲率を大きくするようにスペーサ１７上部の側部を除去することから、スペーサ１７の側壁の急峻な傾斜面が緩く形成されることになり、絶縁膜２１の埋め込みが容易になる。よって、スペーサ１７間の絶縁膜２１の埋め込みに際し、ボイドの発生が防止される。   According to the manufacturing method described above, the side portion of the upper portion of the spacer 17 is removed so as to increase the curvature of the upper side surface 17su of the spacer 17 before the insulating film 21 is formed after the spacer 17 is formed. The steeply inclined surface of the side wall is formed loosely, and the embedding of the insulating film 21 becomes easy. Therefore, generation of voids is prevented when the insulating film 21 is embedded between the spacers 17.

また、上記スペーサ１７を形成し、スペーサ１７の側面の形状を９０度未満の傾斜面に加工した後、配線１４間の領域を埋め込む上記絶縁膜２１を形成する前に、配線１４間の領域を埋め込むことなく配線１４およびスペーサ１７を被覆する絶縁膜（図示せず）を形成した場合には、配線１４間におけるスペーサ１７および被覆絶縁膜（図示せず）を介した領域のアスペクト比が１未満であればよい。   In addition, after forming the spacer 17 and processing the shape of the side surface of the spacer 17 into an inclined surface of less than 90 degrees, before forming the insulating film 21 that fills the region between the wirings 14, the region between the wirings 14 is formed. When an insulating film (not shown) that covers the wiring 14 and the spacer 17 without being embedded is formed, the aspect ratio of the region between the wiring 14 via the spacer 17 and the covering insulating film (not shown) is less than 1. If it is.

実際のデバイス作製に適用する場合には、上記説明した第１実施の形態もしくは第２実施の形態を適宜選択して実施することになる。現状では、第２実施の形態のほうが第１実施の形態よりも実際のデバイス形成にあったプロセスにも対応した絶縁膜の埋め込みが可能になる。   When applied to actual device fabrication, the above-described first embodiment or second embodiment is appropriately selected and implemented. At present, the second embodiment can embed an insulating film corresponding to a process suitable for actual device formation as compared with the first embodiment.

次に、本発明の半導体装置の製造方法に係る第３実施の形態を図３の製造工程断面図によって説明する。この第３実施の形態では前記第１実施の形態で説明したのと同様なる構成部品には、前記第１実施の形態と同一の符号を付与して説明する。   Next, a third embodiment of the method for manufacturing a semiconductor device according to the present invention will be described with reference to the manufacturing process sectional view of FIG. In the third embodiment, the same components as those described in the first embodiment are given the same reference numerals as those in the first embodiment.

第３実施の形態は、スペーサ１７の側面のエッチング加工を行う前に、イオン注入によりダメージ層を形成することを特徴としている。その他の工程は、前記第１、第２実施の形態で説明したのと同様である。したがって、ここでは、ダメージ層の形成方法について、以下に説明する。なお、スペーサ１７は、前記第２実施の形態の構成を用いたが前記第１実施の形態の構成であってもよい。   The third embodiment is characterized in that a damaged layer is formed by ion implantation before the side surface of the spacer 17 is etched. Other steps are the same as those described in the first and second embodiments. Therefore, here, a method for forming a damaged layer will be described below. In addition, although the structure of the said 2nd Embodiment was used for the spacer 17, the structure of the said 1st Embodiment may be sufficient.

図３（１）に示すように、配線１４の側部にスペーサ１７を形成し、サリサイドプロセスを行った後、全面にイオン注入を行ってスペーサ１７の表面にダメージ層（図示せず）を形成する。このイオン注入では、シリコンまたはゲルマニウムなどのＮ型、Ｐ型どちらにもならない比較的重いイオンを１×１０15以上の高いドーズ量でスペーサ１７表面のおよそ２０ｎｍぐらいの深さの領域に注入する。このように注入するには、例えばイオン注入の注入エネルギーを２０ｋｅＶ程度とすればよい。上記ダメージ層の形成によって、スペーサ１７の上部側面の曲率が小さな部分のエッチングレートが高くなり、それによって他の部分とのエッチング選択比が高まるので、スペーサ１７の上部側面の曲率が小さな部分を制御性よくエッチングすることが可能となり、プロセス的なマージンを広げることができる。 As shown in FIG. 3A, a spacer 17 is formed on the side of the wiring 14 and after a salicide process is performed, ion implantation is performed on the entire surface to form a damage layer (not shown) on the surface of the spacer 17. To do. In this ion implantation, relatively heavy ions such as silicon or germanium, which are neither N-type nor P-type, are implanted into a region having a depth of about 20 nm on the surface of the spacer 17 with a high dose of 1 × 10 15 or more. For such implantation, for example, the implantation energy of ion implantation may be about 20 keV. By forming the damage layer, the etching rate of the portion having a small curvature on the upper side surface of the spacer 17 is increased, thereby increasing the etching selectivity with respect to the other portion. Therefore, the portion having a small curvature on the upper side surface of the spacer 17 is controlled. Etching can be performed with good performance, and the process margin can be widened.

その後、図３（２）に示すように、前記第１、第２実施の形態で説明したのと同様にして、上記スペーサ１７の上部側面１７ｓｕの曲率を大きくするようにスペーサ１７の上部側面の曲率が小さな部分〔前記図３の（１）のスペーサの上部側面１７ｓｕ参照〕を例えばエッチングにより除去するとともに、このエッチングによりスペーサ１７の下部側面１７ｓｄから垂直面を無くしてスペーサ１７の側面全体を９０度未満の傾斜面とする。これによって、スペーサ１７の側面間のアスペクト比を１未満とする。このように、スペーサ１７の側面をエッチングすることにより、スペーサ１７によるテーパー形状が顕著になるようにする。 Thereafter, as shown in FIG. 3B, the upper side surface of the spacer 17 is increased so as to increase the curvature of the upper side surface 17su of the spacer 17 in the same manner as described in the first and second embodiments. A portion having a small curvature (see the upper side surface 17su of the spacer in FIG. 3A) is removed by, for example, etching, and the vertical surface is eliminated from the lower side surface 17sd of the spacer 17 by this etching, so that the entire side surface of the spacer 17 is 90%. The inclined surface is less than 1 degree. As a result, the aspect ratio between the side surfaces of the spacer 17 is less than 1. As described above, the side surface of the spacer 17 is etched so that the taper shape by the spacer 17 becomes remarkable.

その後、前記第１、第２実施の形態と同様にして、配線１４間にスペーサ１７を介して絶縁膜２１を埋め込むように形成する。   Thereafter, in the same manner as in the first and second embodiments, the insulating film 21 is embedded between the wirings 14 via the spacers 17.

上記各実施の形態で説明したスペーサ１７のエッチングは、ドライエッチングの他にスパッタエッチングもしくはウエットエッチングで行うことができる。   The etching of the spacer 17 described in the above embodiments can be performed by sputter etching or wet etching in addition to dry etching.

スパッタエッチングで行う場合には、スパッタエッチング装置を用い、プロセスガスにアルゴン（Ａｒ）を用い、スパッタ出力を３００Ｗ、エッチング雰囲気の圧力を５．３ｋＰａ、基板温度を２５℃として、スペーサ１７の膜厚換算で３ｎｍ程度エッチングを行う。このように、アルゴン（Ａｒ）によるスパッタエッチングによって、スペーサ１７の上部側面を削り取る。このスパッタエッチングでは、ドライエッチングよりも異方性が高くなり、パワーによっては強力なエッチングが可能となる。   When performing sputter etching, a sputter etching apparatus is used, argon (Ar) is used as a process gas, a sputter output is 300 W, an etching atmosphere pressure is 5.3 kPa, a substrate temperature is 25 ° C., and the film thickness of the spacer 17 is increased. Etching is performed by about 3 nm in terms of conversion. Thus, the upper side surface of the spacer 17 is scraped off by sputter etching with argon (Ar). In this sputter etching, anisotropy is higher than in dry etching, and strong etching is possible depending on the power.

ウエットエッチングで行う場合には、ウエットエッチング装置を用い、エッチング液に希フッ酸（ＨＦ：Ｈ2Ｏ＝１：２００の０．５％希フッ酸）を用い、エッチング液温度を２５℃として３ｎｍ／ｍｉｎ程度の遅いエッチング速度でスペーサ１７の膜厚換算で３ｎｍ程度エッチングを行ってもよい。なお、上記エッチング液はスペーサ１７が酸化シリコン膜で形成されている場合である。また、スペーサ１７が窒化シリコン膜の場合には熱リン酸をエッチング液に用いることができる。 In the case of wet etching, a wet etching apparatus is used, dilute hydrofluoric acid (HF: H 2 O = 1: 200, 0.5% dilute hydrofluoric acid) is used as an etchant, and the etchant temperature is 25 ° C. and 3 nm. Etching may be performed by about 3 nm in terms of the thickness of the spacer 17 at a slow etching rate of about / min. The etching solution is used when the spacer 17 is formed of a silicon oxide film. Further, when the spacer 17 is a silicon nitride film, hot phosphoric acid can be used as an etching solution.

上記各エッチング技術によって、スペーサ１７の側面の傾斜を９０度未満にしている。この傾斜面は、例えば８８度程度でも絶縁膜２１の埋め込みがボイドを発生することなく良好に行えることが本発明者の実験により確認されている。   By the above etching techniques, the inclination of the side surface of the spacer 17 is made less than 90 degrees. It has been confirmed by experiments of the present inventors that this inclined surface can be satisfactorily embedded in the insulating film 21 without generating voids even at about 88 degrees, for example.

また、上記説明したように、イオン注入によるダメージ層を形成することにより、ウエットエッチングのような等方性のエッチングでありながらスペーサ１７の上部側面のみエッチングレートを早めてエッチングを行うことができる。この場合、先のスパッタエッチングやドライエッチングのようなプラズマもしくはスパッタ雰囲気に下地がさらされることがないため、ゲート酸化膜へのダメージが無い点で有利となる。   Further, as described above, by forming a damaged layer by ion implantation, it is possible to perform etching only at the upper side surface of the spacer 17 while increasing the etching rate while performing isotropic etching such as wet etching. In this case, since the substrate is not exposed to plasma or sputtering atmosphere as in the previous sputter etching or dry etching, it is advantageous in that there is no damage to the gate oxide film.

上記説明した製造方法により、前記図１（４）および前記図２（４）に示したように、基板１１上に形成された配線１４と、この配線１４の側部に形成されたスペーサ１７と、配線１４間を埋め込むとともに配線１４およびスペーサ１７を被覆するように基板１１上に形成された絶縁膜２１とを備えた半導体装置において、スペーサ１７は、このスペーサ１７の上部側面１７ｓｕの曲率を大きくするようにスペーサ１７の上部側部１７ｓｕが除去されたものからなり、配線１４側部に形成されたスペーサ１７間の絶縁膜２１が埋め込まれる領域はアスペクトが１以下となるように形成されている半導体装置を構成することができる。   With the manufacturing method described above, as shown in FIG. 1 (4) and FIG. 2 (4), the wiring 14 formed on the substrate 11 and the spacers 17 formed on the sides of the wiring 14 In the semiconductor device including the insulating film 21 formed on the substrate 11 so as to embed between the wirings 14 and cover the wirings 14 and the spacers 17, the spacers 17 increase the curvature of the upper side surface 17 su of the spacers 17. Thus, the upper side portion 17su of the spacer 17 is removed, and the region where the insulating film 21 between the spacers 17 formed on the side portion of the wiring 14 is buried is formed so that the aspect is 1 or less. A semiconductor device can be configured.

このような半導体装置では、スペーサ１７は、スペーサ１７の上部側面１７ｓｕの曲率を大きくするようにスペーサ１７上部の側部が除去されたものからなることから、スペーサ１７側面の急峻な傾斜面が緩く形成されることになり、絶縁膜２１の埋め込みが容易になる。さらに、配線１４側部に形成されたスペーサ１７間の絶縁膜２１が埋め込まれる領域はアスペクトが１以下となるように形成されていることから、絶縁膜２１の埋め込みの容易性が高められる。よって、スペーサ１７間の絶縁膜２１の埋め込みに際し、ボイドの発生が防止されるので、信頼性の高い半導体装置となる。   In such a semiconductor device, since the spacer 17 is formed by removing the side portion of the upper portion of the spacer 17 so as to increase the curvature of the upper side surface 17su of the spacer 17, the steep inclined surface on the side surface of the spacer 17 is loose. As a result, the insulating film 21 can be easily embedded. Furthermore, since the region where the insulating film 21 between the spacers 17 formed on the side of the wiring 14 is embedded is formed so that the aspect is 1 or less, the ease of embedding the insulating film 21 is improved. Therefore, when the insulating film 21 between the spacers 17 is embedded, the generation of voids is prevented, so that a highly reliable semiconductor device is obtained.

本発明の半導体装置の製造方法および半導体装置は、配線間の絶縁膜の埋め込みを伴う半導体装置に適用でき、例えば半導体メモリ素子、半導体ロジック素子等の半導体装置に適用できる。   The method for manufacturing a semiconductor device and the semiconductor device of the present invention can be applied to a semiconductor device that involves embedding an insulating film between wirings, and can be applied to a semiconductor device such as a semiconductor memory element or a semiconductor logic element.

本発明の半導体装置の製造方法に係る第１実施の形態を示す製造工程断面図である。It is manufacturing process sectional drawing which shows 1st Embodiment which concerns on the manufacturing method of the semiconductor device of this invention. 本発明の半導体装置の製造方法に係る第２実施の形態を示す製造工程断面図である。It is manufacturing process sectional drawing which shows 2nd Embodiment which concerns on the manufacturing method of the semiconductor device of this invention. 本発明の半導体装置の製造方法に係る第３実施の形態を示す製造工程断面図である。It is manufacturing process sectional drawing which shows 3rd Embodiment which concerns on the manufacturing method of the semiconductor device of this invention. 従来の半導体装置の製造方法に係る課題を示す製断面図である。It is sectional drawing which shows the subject which concerns on the manufacturing method of the conventional semiconductor device.

符号の説明Explanation of symbols

１１…基板、１４…配線、１７…スペーサ、１７ｓｕ…スペーサの上部側面、２１…絶縁膜   DESCRIPTION OF SYMBOLS 11 ... Board | substrate, 14 ... Wiring, 17 ... Spacer, 17su ... Upper side surface of spacer, 21 ... Insulating film

Claims (6)

基板上に配線を形成した後に前記配線の側部にスペーサを形成する工程と、前記基板上に前記配線間を埋め込むとともに前記配線および前記スペーサを被覆する絶縁膜を形成する工程とを備えた半導体装置に製造方法において、
前記スペーサを形成した後で前記絶縁膜を形成する前に、前記スペーサの上部側面の曲率を大きくするように前記スペーサの上部側面を除去する工程
を備えたことを特徴とする半導体装置の製造方法。 Forming a spacer on a side of the wiring after forming the wiring on the substrate; and forming an insulating film covering the wiring and the spacer while embedding between the wirings on the substrate In the manufacturing method for the device,
A method of manufacturing a semiconductor device comprising: removing the upper side surface of the spacer so as to increase the curvature of the upper side surface of the spacer before forming the insulating film after forming the spacer. . 前記配線間における前記絶縁膜が埋め込まれる領域のアスペクト比を１以下とする
ことを特徴とする請求項１記載の半導体装置の製造方法。 The method of manufacturing a semiconductor device according to claim 1, wherein an aspect ratio of a region where the insulating film is embedded between the wirings is set to 1 or less. 前記スペーサ側面の傾斜は９０度未満とする
ことを特徴とする請求項１記載の半導体装置の製造方法。 The method of manufacturing a semiconductor device according to claim 1, wherein an inclination of the side surface of the spacer is less than 90 degrees. 前記スペーサの上部側面を除去する工程は、
前記スペーサの上部側面にダメージ層を形成する工程と、
前記スペーサの上部側面に形成された前記ダメージ層を選択的に除去する工程と
を備えたことを特徴とする請求項１記載の半導体装置の製造方法。 Removing the upper side surface of the spacer,
Forming a damage layer on the upper side surface of the spacer;
The method for manufacturing a semiconductor device according to claim 1, further comprising: selectively removing the damage layer formed on the upper side surface of the spacer. 前記ダメージ層を形成する工程は、
前記スペーサ上部の側部のみにイオン注入する、
ことを特徴とする請求項４記載の半導体装置の製造方法。 The step of forming the damage layer includes
Ion implantation is performed only on the side of the upper part of the spacer.
The method of manufacturing a semiconductor device according to claim 4. 基板上に形成された配線と、
前記配線の側部に形成されたスペーサと、
前記配線間を埋め込むとともに前記配線および前記スペーサを被覆するように前記基板上に形成された絶縁膜とを備えた半導体装置において、
前記スペーサは、前記スペーサの上部側面の曲率を大きくするように前記スペーサの上部側面が除去されたものからなり、
前記配線側部に形成されたスペーサ間の前記絶縁膜が埋め込まれる領域はアスペクトが１以下となるように形成されている
ことを特徴とする半導体装置。


Wiring formed on the substrate;
A spacer formed on a side of the wiring;
In a semiconductor device comprising an insulating film formed on the substrate so as to embed between the wirings and cover the wirings and the spacers,
The spacer is formed by removing the upper side surface of the spacer so as to increase the curvature of the upper side surface of the spacer,
A region in which the insulating film between the spacers formed on the wiring side portion is embedded is formed so that an aspect is 1 or less.


JP2003271231A 2003-07-07 2003-07-07 Semiconductor device and manufacturing method thereof Pending JP2005033023A (en)

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