JP2008159745A - Mos transistor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve reliability of a device by ensuring a sufficient contact surface of a source and by preventing generation of voids in a source electrode. <P>SOLUTION: A gate electrode of polysilicon is formed in a trench. An interlayer insulating layer whose top surface is protruded is also formed in the trench. Further, a source electrode is so formed that it covers the surface of a semiconductor substrate and a part of it enters into the trench. Since the contact surface between the source region and the source electrode is increased, the on-state resistance can be reduced. Also, since the top surface of the interlayer insulating film is protruded, voids are hardly generated in the source electrode. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to the structure of a trench gate type MOSFET used as a power semiconductor device.

  Various types of MOSFETs are used as power semiconductor devices. One example is a vertical MOSFET in which a trench (groove) is formed in a semiconductor substrate and a gate electrode is embedded in the trench. Recently, with the progress of microfabrication technology, the cell pitch has been reduced, and a technology for achieving high integration with a structure as shown in FIG. 4 (see, for example, Patent Document 1) has also been proposed. The MOS transistor of FIG. 4 has a source electrode 28 on the front side and a drain electrode (not shown) on the back side, and a filled polysilicon gate 36 is formed in the trench 34. When a forward bias is applied, the P type transistor is formed. A channel is formed inside the well 32.

  2 will be described in more detail. The drain electrode (not shown) is formed by forming a metal film on the back surface of the substrate, and the source electrode 38 is formed by a metal wiring layer formed on the front surface side of the substrate. The gate electrode 36 is made of polysilicon filled in the trench 34, and is insulated from each semiconductor region (31, 32, 33) by a gate oxide film 35 formed on the inner wall of the trench 34. The source electrode 38 is insulated by an interlayer insulating film 37 formed inside the trench 34. Note that the interlayer insulating film 37 is formed at a position lower than the surface of the semiconductor substrate in the trench 34, whereby a part of the source electrode 38 enters the trench 34.

In the case of the structure as shown in FIG. 4, since the interlayer insulating film 37 is formed only in the trench 34, the polysilicon gate electrode 36 can be made as small as possible, and a highly integrated MOS transistor cell can be manufactured. it can. Furthermore, in the structure of FIG. 4, not only the surface of the semiconductor substrate but also a part of the source electrode 38 and the source region 33 are in contact with each other inside the trench 34, and the contact area between the source electrode 38 and the source region 33 is increased. This has the advantage that the on-resistance can be reduced.
JP 2003-264287 A

  However, when the interlayer insulating film 47 is dropped deep inside the trench 44 as shown in FIG. 5 to increase the contact area between the source electrode 48 and the source region 43, large irregularities are generated on the surface side of the semiconductor substrate. Further, the surface of the interlayer insulating film 47 generally has a shape recessed in the direction opposite to the surface direction of the semiconductor substrate, and the difference in height between the surface of the semiconductor substrate and the surface recessed portion of the interlayer insulating film 47 is further increased. growing. As a result, when the source electrode 48 is formed, there is a problem that a void (vacancy) 49 is generated in the source electrode 48 above the interlayer insulating film 47.

  The present invention provides a MOS transistor capable of reducing on-resistance by ensuring a sufficient contact area between a source electrode and a source region and at the same time improving reliability by preventing the generation of voids. .

  The present invention solves the above problem by embedding an interlayer insulating film at a position lower than the surface of the semiconductor substrate inside the trench, and forming the surface of the interlayer insulating film so as to protrude toward the surface of the semiconductor substrate. It is a solution.

  That is, a first conductivity type first region to be a drain region, a second conductivity type second region formed to a predetermined depth from the surface of the first region, and a surface of the second region A semiconductor substrate having a third region of the first conductivity type serving as a source region is provided with a trench that penetrates the second region from the surface of the third region to reach the first region, and an insulating film is provided in the trench. In a MOS transistor having a gate electrode facing the second region through the interlayer insulating film formed on the surface side of the gate electrode and a source electrode connected to the source region, the surface direction of the semiconductor substrate inside the trench A protruding interlayer insulating film is formed, and a part of the source electrode is formed so as to penetrate into the trench.

  According to the present invention, since the cell pitch can be reduced, the power MOSFET can be highly integrated. In addition, since the contact area between the source electrode and the source region can be increased, the contact resistance can be reduced, and the on-resistance can be reduced.

  By forming the interlayer insulating film inside the trench into a convex shape protruding in the surface direction of the semiconductor substrate, the difference in height between the surface of the semiconductor substrate and the surface of the interlayer insulating film can be reduced. As a result, generation of voids can be prevented, and the reliability of the element can be improved.

  In the MOS transistor of the present invention, the gate electrode and the interlayer insulating film are embedded in the trench, the interlayer insulating film has a convex shape protruding toward the surface of the semiconductor substrate, and a part of the source electrode is in the trench. It is also characterized by being formed inside.

  Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a front sectional view showing a first embodiment of a MOS transistor according to the present invention. A source region 13 is provided on the front surface side of the semiconductor substrate, a drain region 11 is provided on the back surface side, and a gate electrode 16 is made of polysilicon filled in the trench 14. A channel is formed inside the P-type well 12 when a forward bias is applied. The point to be formed is the same as the conventional one. In order to prevent stress concentration in the opening of the trench 14 in a diffusion process or the like, the opening of the trench 14 is formed in a shape in which the surface of the semiconductor substrate and the side surface of the trench are smoothly coupled at the corners.

  The drain electrode (not shown) is configured by forming a metal film on the back surface of the substrate, and the wiring to the source region 13 is configured by the source electrode 18 formed on the substrate surface side.

  The gate electrode 16 is insulated from each region of the drain region 11, the P-type well 12, and the source region 13 by a gate oxide film 15 formed on the inner wall of the trench 14. The upper surface of the gate electrode 16 is covered with an interlayer insulating film 17, and the gate electrode 16 and the source electrode 18 are insulated by the interlayer insulating film 17. The interlayer insulating film 17 is formed inside the trench 14, and the upper surface of the interlayer insulating film 17 is formed in a convex shape that gently rises in the surface direction of the semiconductor substrate.

  Further, in the trench 14, the interlayer insulating film 17 is formed at a position lower than the surface of the semiconductor substrate, and a part of the source electrode 18 is formed so as to penetrate into the trench 14.

  In the MOS transistor according to the present invention having the above structure, the surface of the semiconductor substrate and the surface of the interlayer insulating film 17 are formed because the shape of the interlayer insulating film 17 is a convex shape protruding in the surface direction of the semiconductor substrate. And the height difference can be reduced. As a result, voids are unlikely to occur in the source electrode 18 above the interlayer insulating film 17.

  Further, the source region 13 near the upper end inside the trench 14 is exposed in the trench 14 without being covered with the interlayer insulating film 17. When a part of the source electrode 18 penetrates into the trench 14, a sufficient area for the source region 13 and the source electrode 18 to contact can be secured. As a result, the contact resistance can be lowered, and the on-resistance can be reduced.

  FIG. 2 is a perspective view showing the shape of the trench gate of the first embodiment of the MOS transistor according to the present invention. In the case of a power MOS transistor, it is important to ensure a sufficient contact area between the source region and the source electrode. By forming the trenches 14 in a stripe shape as shown in FIG. 2, the contact area between the source region and the source electrode can be efficiently secured, and the on-resistance can be reduced while maintaining a high degree of integration. In the case of a power MOS transistor, it is more preferable to form the trench gates in a stripe shape as shown in FIG.

  FIG. 3 is a front sectional view showing a second embodiment of the MOS transistor according to the present invention. The difference from the first embodiment is that the surface of the interlayer insulating film 27 embedded in the trench 28 is not gentle but is formed in an acute convex shape. Since other parts are the same as those of the first embodiment, description thereof is omitted. Depending on the means used for manufacturing and the processing conditions, an acute convex interlayer insulating film 27 as shown in FIG. 2 is formed. Even in this case, the protrusion of the interlayer insulating film 27 relaxes the drop of the source electrode 28 into the central portion of the trench 14, thereby preventing the generation of voids.

1 is a front sectional view showing a first embodiment of a MOS transistor according to the present invention. The perspective view which shows the shape of the trench gate of 1st Example of the MOS transistor by this invention. FIG. 6 is a front sectional view showing a second embodiment of the MOS transistor according to the present invention. Front sectional view showing a conventional MOS transistor. FIG. 6 is a front sectional view showing generation of voids in a conventional MOS transistor.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11, 21 ... Drain region, 12, 22 ... P-type well, 13, 23 ... Source region, 14, 24 ... Trench, 15, 25 ... Gate oxide film, 16, 26 ... Gate electrode, 17, 27 ... Interlayer insulating film , 18, 28 ... source electrode

Claims (4)

A first conductivity type first region to be a drain region, a second conductivity type second region formed on the first region, and a source region on the surface of the second region. To a semiconductor substrate having a third region of one conductivity type,
Comprising a trench extending from the surface of the third region through the second region to the first region;
A gate electrode facing the second region via an insulating film in the trench;
In a MOS transistor comprising a source electrode connected to an interlayer insulating film and the source region on the surface side of the gate electrode,
The interlayer insulating film has a convex shape raised in the semiconductor substrate surface direction, covers the gate electrode surface in the trench,
A MOS transistor, wherein a part of the source electrode is formed so as to penetrate into the trench.   The MOS transistor according to claim 1, wherein the source electrode and the source region are in contact with each other in the trench.   3. The transistor according to claim 1, wherein the semiconductor substrate surface and the side surface of the trench are coupled with each other at a corner of the trench opening with a smooth shape.   The MOS transistor according to claim 1, wherein the trench is formed in a stripe shape on a semiconductor substrate.

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