JP2003264260A - 半導体チップ搭載基板、半導体装置、半導体モジュール及び半導体装置実装基板 - Google Patents

半導体チップ搭載基板、半導体装置、半導体モジュール及び半導体装置実装基板

Info

Publication number
JP2003264260A
JP2003264260A JP2002062893A JP2002062893A JP2003264260A JP 2003264260 A JP2003264260 A JP 2003264260A JP 2002062893 A JP2002062893 A JP 2002062893A JP 2002062893 A JP2002062893 A JP 2002062893A JP 2003264260 A JP2003264260 A JP 2003264260A
Authority
JP
Japan
Prior art keywords
terminal
semiconductor chip
semiconductor
connection
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2002062893A
Other languages
English (en)
Japanese (ja)
Other versions
JP2003264260A5 (https=
Inventor
Shinya Watanabe
慎也 渡辺
Isao Ozawa
勲 小澤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP2002062893A priority Critical patent/JP2003264260A/ja
Priority to US10/382,020 priority patent/US6791193B2/en
Publication of JP2003264260A publication Critical patent/JP2003264260A/ja
Priority to US10/911,363 priority patent/US20050006747A1/en
Publication of JP2003264260A5 publication Critical patent/JP2003264260A5/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H10W70/635—Through-vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/401—Package configurations characterised by multiple insulating or insulated package substrates, interposers or RDLs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H10W70/654—Top-view layouts
    • H10W70/655—Fan-out layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Dram (AREA)
JP2002062893A 2002-03-08 2002-03-08 半導体チップ搭載基板、半導体装置、半導体モジュール及び半導体装置実装基板 Pending JP2003264260A (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2002062893A JP2003264260A (ja) 2002-03-08 2002-03-08 半導体チップ搭載基板、半導体装置、半導体モジュール及び半導体装置実装基板
US10/382,020 US6791193B2 (en) 2002-03-08 2003-03-05 Chip mounting substrate, first level assembly, and second level assembly
US10/911,363 US20050006747A1 (en) 2002-03-08 2004-08-03 Chip mounting substrate, first level assembly, and second level assembly

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002062893A JP2003264260A (ja) 2002-03-08 2002-03-08 半導体チップ搭載基板、半導体装置、半導体モジュール及び半導体装置実装基板

Publications (2)

Publication Number Publication Date
JP2003264260A true JP2003264260A (ja) 2003-09-19
JP2003264260A5 JP2003264260A5 (https=) 2004-12-24

Family

ID=29196435

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002062893A Pending JP2003264260A (ja) 2002-03-08 2002-03-08 半導体チップ搭載基板、半導体装置、半導体モジュール及び半導体装置実装基板

Country Status (2)

Country Link
US (2) US6791193B2 (https=)
JP (1) JP2003264260A (https=)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009522791A (ja) * 2005-12-29 2009-06-11 ビットマイクロ ネットワークス、インク． 記憶装置用の複数チップモジュールおよびパッケージの積層方法
JP2025507887A (ja) * 2022-03-01 2025-03-21 グラフコアー リミテッド モジュール

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TWI300971B (en) * 2002-04-12 2008-09-11 Hitachi Ltd Semiconductor device
TW569416B (en) * 2002-12-19 2004-01-01 Via Tech Inc High density multi-chip module structure and manufacturing method thereof
US20050170609A1 (en) * 2003-12-15 2005-08-04 Alie Susan A. Conductive bond for through-wafer interconnect
US7608534B2 (en) 2004-06-02 2009-10-27 Analog Devices, Inc. Interconnection of through-wafer vias using bridge structures
CN101124674B (zh) * 2005-04-18 2010-06-16 株式会社村田制作所 电子元器件组件
DE102006003377B3 (de) * 2006-01-24 2007-05-10 Infineon Technologies Ag Halbleiterbaustein mit einem integrierten Halbleiterchip und einem Chipgehäuse und elektronisches Bauteil
JP4938346B2 (ja) * 2006-04-26 2012-05-23 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
US20080087979A1 (en) * 2006-10-13 2008-04-17 Analog Devices, Inc. Integrated Circuit with Back Side Conductive Paths
WO2008086530A2 (en) * 2007-01-11 2008-07-17 Analog Devices, Inc. Mems sensor with cap electrode
KR101179268B1 (ko) * 2010-08-05 2012-09-03 에스케이하이닉스 주식회사 관통 비아들을 통한 칩선택이 가능한 반도체 패키지
US8803326B2 (en) * 2011-11-15 2014-08-12 Xintec Inc. Chip package
JP2018032141A (ja) 2016-08-23 2018-03-01 東芝メモリ株式会社 半導体装置

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US5216278A (en) * 1990-12-04 1993-06-01 Motorola, Inc. Semiconductor device having a pad array carrier package
US5734201A (en) * 1993-11-09 1998-03-31 Motorola, Inc. Low profile semiconductor device with like-sized chip and mounting substrate
JPH07169872A (ja) * 1993-12-13 1995-07-04 Fujitsu Ltd 半導体装置及びその製造方法
US5506756A (en) * 1994-01-25 1996-04-09 Intel Corporation Tape BGA package die-up/die down
US5741729A (en) * 1994-07-11 1998-04-21 Sun Microsystems, Inc. Ball grid array package for an integrated circuit
US5798564A (en) * 1995-12-21 1998-08-25 Texas Instruments Incorporated Multiple chip module apparatus having dual sided substrate
KR100234694B1 (ko) * 1996-10-29 1999-12-15 김영환 비지에이 패키지의 제조방법
JP2924840B2 (ja) * 1997-02-13 1999-07-26 日本電気株式会社 Ｔａｐｅ−ＢＧＡタイプの半導体装置
US5835355A (en) * 1997-09-22 1998-11-10 Lsi Logic Corporation Tape ball grid array package with perforated metal stiffener
KR100260997B1 (ko) * 1998-04-08 2000-07-01 마이클 디. 오브라이언 반도체패키지
US6020629A (en) * 1998-06-05 2000-02-01 Micron Technology, Inc. Stacked semiconductor package and method of fabrication
US6313522B1 (en) 1998-08-28 2001-11-06 Micron Technology, Inc. Semiconductor structure having stacked semiconductor devices
US6381141B2 (en) 1998-10-15 2002-04-30 Micron Technology, Inc. Integrated device and method for routing a signal through the device
JP2001077301A (ja) * 1999-08-24 2001-03-23 Amkor Technology Korea Inc 半導体パッケージ及びその製造方法
JP3798597B2 (ja) 1999-11-30 2006-07-19 富士通株式会社 半導体装置
JP2001203470A (ja) * 2000-01-21 2001-07-27 Toshiba Corp 配線基板、半導体パッケージ、および半導体装置
US6555917B1 (en) * 2001-10-09 2003-04-29 Amkor Technology, Inc. Semiconductor package having stacked semiconductor chips and method of making the same
US6686656B1 (en) * 2003-01-13 2004-02-03 Kingston Technology Corporation Integrated multi-chip chip scale package

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009522791A (ja) * 2005-12-29 2009-06-11 ビットマイクロ ネットワークス、インク． 記憶装置用の複数チップモジュールおよびパッケージの積層方法
JP2014132662A (ja) * 2005-12-29 2014-07-17 Bitmicro Networks Inc 記憶装置用の複数チップモジュールおよびパッケージの積層方法
JP2025507887A (ja) * 2022-03-01 2025-03-21 グラフコアー リミテッド モジュール

Also Published As

Publication number Publication date
US20050006747A1 (en) 2005-01-13
US6791193B2 (en) 2004-09-14
US20040046262A1 (en) 2004-03-11

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