JP2003258142A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To miniaturize a semiconductor device. <P>SOLUTION: There are provided a package substrate 4 having a microstrip line 4g, composed of a signal surface layer wiring 4c and a GND layer 4f, a high-frequency semiconductor chip 2 mounted on a principal surface 4a of the package 4 via flip-chip connection, a coaxial cable 7 having a core wire 7a electrically connected to a signal surface layer wiring 4c, and underfilled resin 6 for protecting the flip-chip connection portion of the semiconductor chip 2, a plurality of ball electrodes 3 each being disposed in a back surface 4b of the package substrate 4, and a coaxial connector 11 provided on a frame member 8 mounted on the package substrate 4. A high-frequency signal from the coaxial cable 7 can be transmitted to the entire surface layer of the package substrate 4. The package is miniaturized, by arranging all of the plurality of the ball electrodes 3 in an array configuration, on the back surface 4b of the package substrate 4. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a technique effective when applied to miniaturization of a semiconductor device for optical communication using a coaxial cable.

[0002]

2. Description of the Related Art There is a coaxial cable as one of high speed signal transmitting means, and an example of a structure using this coaxial cable is described in, for example, Japanese Patent Laid-Open No. 5-167258.

Japanese Unexamined Patent Publication No. 5-167258 discloses a PG
In a semiconductor package (semiconductor device) of A (Pin Grid Array) type, there is described a technique of forming a signal transmission path in the thickness direction between a component mounting surface and a back surface of a multilayer wiring board with a coaxial cable.

As an example of a semiconductor package having a high-frequency optical communication element, for example, Japanese Patent Laid-Open No. 5-167 is known.
No. 258, which discloses that a microstrip line (Au thin film wiring layer) is formed on the surface of an insulating ceramic substrate, an insulating lid having a low dielectric constant is joined by a glass having a low dielectric constant, and Techniques for reducing transmission loss are described.

As an example of an optical communication device using a coaxial cable, "Characteristics of 565 Mb / s optical transmitter using DFB-LD", Shoichi Hanatani, Katsuyoshi Karasawa, Kiichi Yamashita, Minoru Maeda, It is described on September 2, 1986, National Convention on Communications, Optical and Radio Waves, page 2-170.

[0006]

However, Japanese Unexamined Patent Publication No.
In the semiconductor package described in Japanese Patent No. 167258, the core wire of the coaxial cable and the surface wiring of the multilayer wiring board are joined in a state of being abutted on each other at a right angle, and a direction perpendicular to the core wire extending direction between the core wire and the surface wiring. Because of the large difference in the cross-sectional area of the signal, the signal is reflected at the portion where the area of the joint between the core wire and the surface wiring changes.

As a result, deterioration of high frequency characteristics becomes a problem.

Further, the present inventor has, as a structure for realizing a high-frequency semiconductor device to which a coaxial cable is connected, connects an inner lead as an external connection terminal to a package substrate on which a high-frequency semiconductor chip is mounted, A structure was studied in which outer leads connected to the inner leads were projected outward from the package substrate along the plane direction.

However, in the structure in which the outer leads project outward of the package substrate along the plane direction of the package substrate, there is a problem that miniaturization cannot be achieved.

An object of the present invention is to provide a semiconductor device which is downsized.

Another object of the present invention is to provide a thin semiconductor device.

Still another object of the present invention is to provide a semiconductor device whose cost is reduced.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0014]

Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows.

That is, the present invention provides a wiring board having surface wiring and a ground conductor layer, a semiconductor chip mounted on the wiring board, and a coaxial cable in which a core wire is electrically connected to the surface wiring of the wiring board. In addition, a plurality of external connection terminals are arranged in either the main surface or the back surface of the wiring board.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings.

In the following embodiments, when there is a need for convenience, the description will be divided into a plurality of sections or embodiments, but unless otherwise specified, they are not unrelated to each other, One has a relationship such as a modification of some or all of the other, details, and supplementary explanation.

Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, amount, range, etc.) of the elements, it is clearly limited to a specific number when explicitly stated and in principle. The number is not limited to the specific number except the case, and may be a specific number or more or less.

Furthermore, in the following embodiments, the constituent elements (including element steps, etc.) are not necessarily essential unless otherwise specified or in principle considered to be essential. Needless to say

Similarly, in the following embodiments, when referring to shapes, positional relationships, etc. of constituent elements, etc., except when explicitly stated or when it is considered that the principle is not clear, it is substantially the same. In addition, the shape and the like are included. This also applies to the above numerical values and ranges.

In all the drawings for explaining the embodiments, members having the same function are designated by the same reference numerals, and their repeated description will be omitted.

(Embodiment 1) FIG. 1 is a sectional view showing an example of the structure of a high-frequency package according to Embodiment 1 of the present invention, and FIG. 2 is an example of the structure of an optical module incorporating the high-frequency package shown in FIG. 2 is a cross-sectional view showing the structure of the optical module shown in FIG. 2, FIG. 4 is a plan view showing an example of the arrangement of components incorporated in the optical module shown in FIG. 2, and FIG. 5 is shown in FIG. FIG. 6 is a cross-sectional view showing an example of the arrangement of components incorporated in the optical module, FIG. 6 is a cross-sectional view showing the structure of a modified high frequency package, and FIG. 7 is an example of the structure of a microstrip line in the wiring board of the high frequency package shown in FIG. 8 is a partial plan view showing the structure of the microstrip line shown in FIG. 7, and FIG. 9 is a microstrip of a modification of the wiring board of the high-frequency package shown in FIG. Partial plan view showing the structure of the line, Figure 1
0 is a partial sectional view showing the structure of the modified microstrip line shown in FIG. 9, FIG. 11 is a perspective view and a sectional view showing the structure of a modified high frequency package, and FIG. 12 is a cap mounting of the high frequency package shown in FIG. Sectional view showing an example of the structure,
13 is a plan view of the cap mounting structure shown in FIG. 12, FIG.
4 is a sectional view taken along line AA of FIG.
13 is a bottom view of the cap mounting structure shown in FIG. 13, FIG. 16 is a plan view showing an example of the positional relationship between the surface wiring and the cap in the cap mounting structure shown in FIG. 12, and FIG.
FIG. 18 is a bottom view showing the structure of the cap as seen from the direction of the arrow, FIG. 18 is a side view showing the structure of the cap shown in FIG. 17, and FIG. 19 is a sectional view showing the structure of the cap shown in FIG. 20, FIG. 20 is an enlarged partial sectional view taken along the line AA of FIG. 13, FIG. 21 is an enlarged partial sectional view taken along the line BB of FIG. 13, and FIG. 22 is the cap mounting shown in FIG. FIG. 23 is an enlarged partial plan view showing an example of the positional relationship between the surface wiring and the opening of the cap in the structure, FIG. 23 is a cross-sectional view showing the structure of the high frequency package of the modification, and FIG. 24 is a heat dissipation member attached to the cap shown in FIG. FIG. 25, FIG. 26, and FIG. 27 are enlarged partial cross-sectional views showing an example of the structure, and FIG.
29 is a plan view showing the structure of a high frequency package of a modification of the first embodiment, FIG. 29 is a sectional view of the high frequency package shown in FIG. 28, and FIGS. 30, 31 and 32 are modifications of the first embodiment of the present invention. 33 is a plan view showing the structure of an example high-frequency package, FIG. 33 is a plan view showing the structure of a high-frequency package of a modification of the first embodiment, FIG. 34 is a cross-sectional view of the high-frequency package shown in FIG. 33, and FIG. 35 is a plan view showing the structure of the high frequency package of the modified example of FIG.
37 is a cross-sectional view of the high-frequency package shown in FIG. 37, FIG. 37 is a plan view showing the structure of the high-frequency package of the modification of the first embodiment, and FIG. 38 is a cross-sectional view of the high-frequency package shown in FIG.

The semiconductor device according to the first embodiment shown in FIG. 1 is a semiconductor package mounted with an optical communication IC (Integrated Circuit), and is, for example, a high frequency package 1 capable of high-speed transmission of 40 Gbps. In addition,
The high frequency package 1 is mounted on the optical module (semiconductor module device) 14 shown in FIGS. 2 and 3, and has a coaxial cable 7 for transmitting signals on the high frequency side.

The structure of the high frequency package 1 includes a signal surface wiring (surface wiring) 4c and a signal surface wiring 4c.
A package substrate (wiring substrate) 4 which is a chip carrier having a microstrip line 4g including a GND layer (ground conductor layer) 4f formed inside via an insulating layer 4e, and a main surface 4a of the package substrate 4. A high-frequency semiconductor chip 2 that is electrically connected and mounted by flip-chip connection via a plurality of solder bump electrodes 5, a coaxial cable 7 in which a core wire 7a is electrically connected to a signal surface wiring 4c, and a semiconductor An underfill resin 6 that is poured between the main surface 2a of the chip 2 and the main surface 4a of the package substrate 4 to protect the flip chip connection portion, and is placed in the back surface 4b opposite to the main surface 4a of the package substrate 4. Ball electrode 3 which is a plurality of external connection terminals.

That is, in the high frequency package 1, a high frequency (for example, 40 Gbps) signal from the coaxial cable 7 is directly transmitted to the semiconductor chip 2 through the solder bump electrode 5 via the signal surface wiring 4c of the package substrate 4. The package substrate 4 has a structure capable of transmitting high-frequency signals only through the microstrip lines on the entire surface layer of the package substrate 4.

Therefore, by transmitting the high frequency signal only through the microstrip line on the surface layer of the package substrate 4 without passing through the wiring such as the via, it becomes possible to transmit the high frequency signal without loss of frequency characteristics. .

The surface wirings such as the signal surface wirings 4c and the GND surface wirings 4h are wirings formed of, for example, copper and arranged in the uppermost layer on the main surface 4a side of the package substrate 4. It may be exposed on the surface of the main surface 4a, or may be coated with a non-conductive thin film or the like.

Further, when high-speed transmission of 40 Gbps or the like is performed, it is preferable that the signal surface wiring 4c of the microstrip line 4g be as short as possible. Therefore, among the plurality of solder bump electrodes 5 connected to the semiconductor chip 2 of the package substrate 4, the solder bump electrode 5 arranged closer to the coaxial cable 7 (coaxial connector 11) from the center of the semiconductor chip 2 is the signal surface wiring 4c. Connected with.

Preferably, of the plurality of solder bump electrodes 5, any one of the solder bump electrodes 5 arranged on the outermost periphery is connected to the signal surface wiring 4c.

As a result, it is possible to realize high-speed signal transmission in which the loss of the frequency characteristic of the high frequency is minimized, and it is possible to reduce the noise on the microstrip line 4g, so that the deterioration of the high frequency characteristic can be suppressed. .

Further, in the high frequency package 1, a plurality of ball electrodes (bump electrodes) 3 provided as external connection terminals are arranged in an array on the back surface 4b of the package substrate 4. Therefore, the high frequency package 1 is It is a ball grid array type semiconductor package.

As a result, the size of the package can be reduced as compared with the outer lead projecting type high frequency package in which the outer leads project outward from the package substrate 4.

The microstrip line 4g transmits a high frequency signal as an electromagnetic wave in the insulating layer 4e between the signal surface wiring 4c and the internal GND layer 4f, but in the surface layer of the package substrate 4, As shown in FIG. 7, the GND surface layer wiring (grounding surface wiring) 4h arranged on both sides of the signal surface layer wiring 4c via the insulating portion also forms a microstrip line 4g.

In the high frequency package 1, a frame member 8 is attached to the package substrate 4 along the outer periphery thereof, and the frame member 8 is provided with a coaxial connector (relay member) 11 which is fitted with the coaxial cable 7. It is provided with the beads 12. Therefore, the coaxial connector 1
1 is fitted with a coaxial cable 7, and the coaxial cable 7
The core wire 7a is soldered 31 to the signal surface wiring 4c of the package substrate 4 (may be connected by a conductive resin or the like).

The diameter of the coaxial connector 11 is, for example, about 10 mm.

The package substrate 4 is a substrate formed of, for example, glass-filled ceramic,
The thickness thereof is, for example, about 1 mm, and in addition to the GND layer 4f, the solder bump electrodes 5 for flip chip connection and the ball electrodes 3 corresponding to the terminals for external connection are connected to the inside thereof. Internal signal wiring 4d which is a signal line
Are formed.

Further, the high frequency package 1 having such a structure is incorporated in an optical module (semiconductor module device) 14 as shown in FIG. 2 and mounted on the module substrate (relay member) 13.

Here, the structure of the optical module 14 will be described.

The optical module 14 shown in FIGS. 2 to 5 is a module for high-speed optical communication, and is a module product mounted in, for example, a mobile phone.

As shown in FIG. 2, the optical module 14 according to the first embodiment has a size of, for example, L (100 to 100).
200 mm) × M (60 to 150 mm), and the height (T) is 10 to 25 mm as shown in FIG. 3, but the size and height of the optical module 14 are not limited to these numerical values. Absent.

The high frequency package 1 according to the first embodiment is
Mounted on the module substrate 13 of the optical module 14,
The entire module board 13 is covered with a module case 15. A plurality of fins 16 are formed side by side on the surface of the module case 15, and the fins 16 receive wind 18 to improve the heat dissipation of the optical module 14.

The external terminal of the optical module 14 is the module connector 17 attached to the module substrate 13, and a part of it is exposed on the back side of the module case 15.

As shown in FIGS. 4 and 5, the optical module 14
Then, the high frequency optical signal input from the input is converted into the photoelectric converter 2
0 is converted into an electric signal, and this electric signal is further transmitted to the high frequency semiconductor chip 2 on the input side via the amplifier element 19 and the microstrip line 4 of the package substrate 4.
After passing through g, the signal changes to a low frequency signal and the internal signal wiring 4d, the solder bump electrodes 5, the module substrate 13 and the module connector 17 of the package substrate 4 shown in FIG.
And is sent to the outside of the optical module 14.

On the other hand, the signal input from the module connector 17 side is sent as an output through the opposite path.

In FIG. 4, the high frequency semiconductor chip 2 is shown.
2 shows the case where two are provided on the input side and the output side, but it is also possible to incorporate the input side and the output side in one semiconductor chip 2.

Further, in FIG. 4, in the arrows showing the flow of the input and output signals, the arrow shown by the solid line shows the transmission of the optical signal by the optical fiber, and the arrow shown by the dotted line shows the coaxial cable 7 or Microstrip line 4g
2 shows the transmission of an electric signal by.

Next, FIG. 6 shows a modification of the high frequency package 1, in which the core wire 7a of the coaxial cable 7 is directly connected to the signal surface wiring 4c of the package substrate 4 by soldering or the like.

That is, the coaxial cable 7 is directly attached to the package substrate 4 by soldering or the like without using the coaxial connector 11.

In this case, a step 4k for arranging the coaxial cable 7 is provided at the end of the package substrate 4, a surface wiring 4h for GND is provided on the surface of the step 4k, and the coaxial cable 7 is placed at the step 4k. And the coaxial cable 7
The shield (GND) 7b that covers the core wire 7a and the GND surface wiring 4h having the step 4k are electrically connected by soldering or the like.

By directly attaching the coaxial cable 7 to the package substrate 4 in this way, the coaxial connector 11 which is expensive and has a relatively large diameter is not used, so that the high-frequency package 1 can be thinned. At the same time, cost reduction can be achieved.

Next, a preferable shape of the GND layer 4f which is the inner layer of the package substrate 4 will be described with reference to FIGS.

First, FIG. 7 and FIG. 8 show the microstrip line structure 21 by the microstrip line 4g.
In, the GND layer 4f inside the substrate is the package substrate 4
Of the coaxial cable 22 and the microstrip line structure 21 by the coaxial cable 7.
This is the case where the structure is such that and are connected.

In this case, high-speed input / output signals to / from the outside of the package pass through the coaxial cable 7, the signal surface wiring 4c of the package substrate 4 and the semiconductor chip 2. At this time, the core wire 7a of the coaxial cable 7 is connected to the signal surface wiring 4c of the package substrate 4, and the GN of the coaxial cable 7 is connected.
The D shield 7 b is connected to the GND surface wiring 4 h of the package substrate 4.

A frame member 8 for supporting the coaxial cable 7 may be fixed on the package substrate 4, and further, the frame member 8 and the shield 7b of the coaxial cable 7 or the GND surface layer of the package substrate 4 may be attached. The wiring 4h may be connected. Note that, as shown in FIG. 8, the GND surface layer wiring 4h and the inner GND layer 4f are connected by a via wiring 4i.

Therefore, in order to reduce the L (inductance) of GND, the signal surface layer wiring 4c on the package substrate 4 is provided with the microstrip line structure 21 in all regions.
In order to achieve this, the GND layer 4f is exposed at the end of the substrate and connected to the shield 7b of the coaxial cable 7 or the GND of the frame member 8, or the GND surface layer wiring 4h and the inner GND layer 4f are connected. It is necessary to form the via wiring 4i at the end portion of the substrate, and cut and expose the via wiring 4i at the time of cutting the substrate so as to be connected to the GND of the coaxial cable 7 or the frame member 8.

However, these techniques require high accuracy in the positioning of the surface layer / inner layer wiring of the package substrate 4, and lead to the sagging of the wiring when a sticky material such as Cu is used for the wiring. And there is concern that it will be difficult to manufacture.

On the other hand, the structure shown in FIGS. 9 and 10 has the outermost via wiring 4 among the plurality of via wirings 4i.
i in the area between the coaxial cable 7 and the signal surface wiring 4c
And a surface layer wiring 4h for GND are formed on the same plane (main surface 4a) to form a coplanar line 23a, and the coaxial cable 7 and the microstrip line 4g of the package substrate 4 are connected via the coplanar line 23a. It is connected.

That is, the area outside the outermost via wiring 4i near the end of the package substrate 4 is the coplanar structure 23, and the coaxial structure 22, the coplanar structure 23 and the microstrip line structure 21 are connected. Has been done.

As a result, the inductance of GND can be reduced.

Furthermore, in order to match the characteristic impedance in the region of the coplanar structure 23, the distance between the signal surface layer wiring 4c and the GND surface layer wiring 4h is reduced as shown in FIG. The via wiring 4i and the inner GND layer 4f
The positional deviation accuracy between and is the same as the conventional one (for example, 50
Since it does not require a new technology, it is possible to prevent cost increase.

Therefore, by connecting the coaxial structure 22, the coplanar structure 23 and the microstrip line structure 21, it is possible to reduce the loss of high frequency signals and bring the characteristic impedance of the high speed signal path close to the target value.

Further, the signal surface wiring for the surface 4c and the GN are provided.
By reducing the distance to the D surface wiring 4h,
The characteristic impedance can be brought closer to the target value.

As a result, deterioration of high-speed signal characteristics can be suppressed, and the electrical characteristics of the high frequency package 1 can be improved without increasing the cost.

Next, the high frequency package 1 of the modification shown in FIG. 11 will be described.

The high frequency package 1 shown in FIG. 11 uses the coaxial cable 7 and a thin coaxial connector 24 which is a plate-shaped member as a relay member for the microstrip line 4g of the package substrate 4.

The thin coaxial connector 24 has a microstrip line 24c including a signal surface wiring (surface wiring) 24a and a GND line (ground wiring) 24b formed on both sides of the signal wiring via an insulating portion. Therefore, in the high frequency package 1, the signal surface wiring 24a of the microstrip line 4g of the package substrate 4 and the core wire 7a of the coaxial cable 7 are electrically connected via the signal surface wiring 24a of the microstrip line 24c of the thin coaxial connector 24. Connected to each other.

That is, the signal surface wiring 24a and the GND lines 24b are provided on both surfaces of the upper surface of a thin ceramic plate having a step 24d, and the GND wiring is provided on the lower surface.
Only the line 24b is provided, and the upper and lower GND lines 24b are connected by a surface or inner layer via.

Then, the coaxial cable 7 is mounted on the lower stage,
Place the core wire 7a at the tip on the signal surface wiring 24a in the upper stage,
The shield 7b of the coaxial cable 7 is connected to the upper and lower GND wires 24b of the ceramic plate by soldering, and the core wire 7a of the coaxial cable 7 and the upper signal surface wiring 24a are similarly connected by soldering or the like.

After that, the surface wiring of the ceramic plate and the surface wiring of the package substrate 4 are opposed to each other, and the wirings are connected to each other with solder or conductive resin. Alternatively, gold (A
u) -Gold (Au) pressure bonding connection may be performed, or the ceramic plate and the package substrate 4 may be closely fixed.

As described above, by using the thin coaxial connector 24 which is a plate-shaped member as the relay member, the high frequency package 1 can be thinned.

Furthermore, handling of the coaxial cable 7 is facilitated, and connector repair is possible. The thin coaxial connector 24 may be attached to both ends of the coaxial cable 7, or one end of the thin coaxial connector 24 may be the thin coaxial connector 24 and the other end may be the same as in FIG.
It is also possible to use the coaxial connector 11 as shown in, and it is possible to attach connectors of different shapes to the coaxial cable 7. Alternatively, one end may be the thin coaxial connector 24 and the other end may expose the cable end.

The coaxial cable 7 to which the thin coaxial connector 24 is attached can be supplied only by the coaxial cable 7, and is supplied as the high frequency package 1 to which the thin coaxial connector 24 is attached as shown in FIG. You may.

Next, the high frequency package 1 of the modification shown in FIG. 12 will be described.

First, in the high-frequency package 1 shown in FIG. 12, among the ball electrodes 3 of the plurality of external connection terminals, the one shown in FIG.
As shown in 5, support balls 3 are provided at the four outermost corners.
a is provided.

Since the coaxial connector 11 is heavy, when the high frequency package 1 is mounted on a mounting substrate such as the module substrate 13, the ball electrodes 3 are crushed and an electrical short circuit occurs between the adjacent ball electrodes 3. Since the support balls 3a are provided at the four corners of the outermost circumference, the support balls 3a at the corners support the package substrate 4 to support the package substrate 4 when the ball electrode 3 is melted. It is possible to prevent an electrical short circuit due to the crushing of No. 3.

The support balls 3a are made of, for example, high melting point solder, resin or ceramic.

Further, the high frequency package 1 shown in FIG.
In the above, a cap 9 as a heat dissipation member is attached to a back surface 2b of the semiconductor chip 2 opposite to the main surface 2a via a heat conductive adhesive 10.

That is, since the high-frequency semiconductor chip 2 may generate a high amount of heat when it is driven, its back surface 2b.
By attaching the heat dissipation cap 9 or the heat diffusion plate or the heat dissipation fin to the semiconductor chip 2, the heat dissipation of the semiconductor chip 2 can be improved and the heat dissipation of the high frequency package 1 can be improved to prevent the deterioration of the electrical characteristics.

Here, the arrangement position of the cap 9 with respect to the package substrate 4 will be described. As shown in FIGS. 12 to 14, the cap 9 is attached to the back surface 2b of the semiconductor chip 2 via the heat conductive adhesive 10 or the like so as to cover the semiconductor chip 2, and at that time, FIG. Signal surface wiring 4c and GND surface wiring 4
It is preferable to be arranged also on the surface wiring such as h (microstrip line 4g).

That is, it is preferable that the cap 9 covers the microstrip line 4g in order to prevent noise due to external electromagnetic waves from being applied to the surface microstrip line 4g.

Therefore, it is preferable that the semiconductor chip 2 and the surface wiring are covered to some extent so as to prevent the entry of electromagnetic waves from the outside. However, the cap 9 and the surface layer wirings such as the signal surface layer wiring 4c and the GND surface layer wiring 4h must be insulated from each other.

Therefore, in the package substrate 4 of the first embodiment, as shown in FIG. 17, an opening portion (meat relief portion) 9a is formed in the leg portion 9b on the surface wiring of the cap 9, and the cap 9 is formed. Has a cap shape so that the leg portions 9b and the surface wiring are not in contact with each other.

20 and 22 show the cap 9
3 shows the detailed positional relationship between the opening 9a of the leg portion 9b and the signal surface layer wiring 4c and the GND surface layer wiring 4h of the package substrate 4. That is, the leg portion 9b of the cap 9 is opened as an opening 9a up to the outside of both sides of the GND surface layer wiring 4h so as not to contact the signal surface layer wiring 4c and the GND surface layer wiring 4h.

Further, as shown in FIG. 20, an insulating thin film (non-conductive layer) made of resin or the like is formed at a portion other than the connection region of the signal surface layer wiring 4c, which is the surface layer wiring of the package substrate 4, with the coaxial cable 7. Thin film) Solder resist 4j
(The same applies to the GND surface layer wiring 4h). The solder resist 4j has an insulating function as well as a solder flow stopping function for the solder connection 31 of the coaxial cable 7.

Therefore, since the opening 9a which is the meat relief portion of the cap 9 and the solder resist 4j which is an insulating thin film are formed on the surface layer wiring, the surface layer wiring and the cap 9 may come into contact with each other. Can be prevented.

It should be noted that the cap 9 has a structure shown in FIGS.
As shown in FIG. 8, cutouts 9c are formed in the corners and sides so as not to contact the surface wirings.

Since the cap 9 also needs a shielding effect, as shown in FIG. 19, the entire surface of the base material 9d made of a copper alloy or the like is covered with a chrome-based conductive film 9e, and further outside thereof. Is covered with the non-conductive film 9f so as to prevent an electrical short circuit with other parts.

As shown in FIGS. 21 and 22, such a cap 9 has a signal surface wiring 4c and a GND surface wiring 4h formed on the main surface 4a of the package substrate 4.
It is attached to the same layer as. The layer of the base electrode of the solder bump electrode 5 is the same layer.

Also, the opening 9a of the leg 9b of the cap 9 is formed.
21, the legs 9b are connected to the GND layer 4f inside the package substrate 4 via the conductive material 25 and the via wiring 4i in order to enhance the shielding effect, as shown in FIG. Therefore, the cap 9 itself is electrically connected to the GND layer 4f and the GND surface wiring 4h inside the package substrate 4.

As a result, the periphery of the solder bump electrode 5 for the high frequency signal is surrounded by the GND potential, and the shielding effect of the cap 9 can be enhanced.

Further, the solder bump electrodes 5 for high frequency signals, that is, the solder bump electrodes 5 connected to the signal surface wiring 4c.
As shown in FIG. 22, it is preferable that the solder bump electrodes 5 are arranged substantially at the center of the sides of the outermost solder bump electrode 5 row, and the solder bump electrodes 5 and the signal surface wiring 4c are interposed therebetween. It is preferable that the coaxial connector 11 to be connected by means of is also arranged substantially at the center of the side.

As a result, the microstrip line 4
g can be minimized, high-speed signal transmission can be realized with the loss of high-frequency characteristics minimized, and
It is also possible to reduce noise on the microstrip line 4g.

Next, the high frequency package 1 of the modification shown in FIG. 23 has a structure in which the cap 9 is attached to the high frequency package 1 using the thin coaxial connector 24 shown in FIG. 11, and the high frequency package shown in FIG. According to 1, it is possible to improve both thinning of the high frequency package 1 and heat dissipation.

Further, in the high frequency package 1 of the modified example shown in FIG. 24, the heat dissipation block (heat dissipation member) 26 is provided on the surface of the cap 9 attached to the back surface 2b of the semiconductor chip 2 with the heat conductive adhesive 10 interposed therebetween. The heat radiation of the high frequency package 1 can be further improved.

The high frequency package 1 of the modification shown in FIG. 25 has a structure in which a second semiconductor chip 27 is mounted on the package substrate 4 in addition to the semiconductor chip 2, and covers both chips. A cap 9 is attached.

Here, a signal is input from the semiconductor chip 2 connected to the coaxial cable 7 via the surface microstrip line 4g to the second semiconductor chip 27 via the internal signal wiring 4d of the package substrate 4. Further, a signal is transmitted from the solder bump electrode 5 of the second semiconductor chip 27 to the ball electrode 3 which is an external connection terminal via the internal signal wiring 4d.

The high frequency packages 1 of the modified examples shown in FIGS. 26 and 27 both have the frame member 8 and the balancer 28 attached thereto. Balancer 28
Has a function of adjusting the center of gravity of the package so that the high-frequency package 1 does not tilt when the high-frequency package 1 is mounted on a substrate.

In FIG. 26, the balancer 28 is fixed to the frame member 8 via the screw member 29. In FIG. 27, a groove is formed in the balancer 28 and the groove is fitted into the frame member 8. The balancer 28 is attached to the frame member 8.

Therefore, in the high frequency package 1 of FIGS. 26 and 27, the package center of gravity is adjusted by the balancer 28 so that the high frequency package 1 does not tilt when mounted on the substrate.

Next, the package substrate 4 and the semiconductor chip 2
The arrangement position of will be described.

In the high frequency package 1, the semiconductor chip 2
Is preferably arranged on the package substrate 4 as close to the coaxial cable 7 as possible.

That is, when transmitting a high-frequency signal from the coaxial cable 7 to the semiconductor chip 2 via the microstrip line 4g on the surface of the package substrate 4, if the microstrip line 4g has a long path, noise will be generated and the high frequency will be increased. Since the characteristic deteriorates, it is preferable to dispose the semiconductor chip 2 closer to the coaxial cable 7 than the central portion of the package substrate 4 in order to prevent this, and the semiconductor chip 2 is disposed as close to the coaxial cable 7 as possible.

Thus, the microstrip line 4g
Can be shortened, and it is possible to suppress deterioration of high frequency characteristics due to noise.

The high frequency package 1 shown in FIG. 13 is a case where one semiconductor chip 2 is mounted on the package substrate 4, and the semiconductor chip 2 is arranged closer to the coaxial connector 11 than the central portion of the package substrate 4. By fitting the coaxial cable 7 into the coaxial connector 11, the semiconductor chip 2 is arranged closer to the coaxial cable 7 than the central portion.

28 and 29 show the case where the high-frequency semiconductor chip 2 and the low-frequency second semiconductor chip 27 are mounted on the package substrate 4, and the high-frequency semiconductor chip 2 is located at the center of the package substrate 4. From the coaxial connector 11
It is arranged closer to the coaxial connector 11 than the second low frequency semiconductor chip 27, and two coaxial connectors 11 are attached to one semiconductor chip 2 in a corresponding manner. There is something.

FIG. 30 shows a modification of the structure of FIG. 28, in which the arrangement combination of the two coaxial connectors 11 is changed.

31 and 32 show the case where one semiconductor chip 2 is mounted on the package substrate 4, and FIG. 31 shows the case where two coaxial connectors 11 are provided on the same side. The semiconductor chip 2 is arranged closer to the coaxial connector 11 than the central portion.

Also, in FIG. 32, the semiconductor chip 2 is arranged closer to the coaxial connector 11 than the central portion, but the two coaxial connectors 11 are symmetrically arranged facing each other on two opposite sides.

The high frequency package 1 shown in FIGS. 33 and 34 is
One semiconductor chip 2 is arranged closer to the coaxial connector 11 than the central portion, and the coaxial connector 11 is provided on the closest side corresponding to this. Further, a plurality of chip capacitors 30 are mounted around the semiconductor chip 2 on the main surface 4a of the package substrate 4.

That is, since the semiconductor chip 2 is arranged closer to the coaxial connector 11 than the central portion, a plurality of chip capacitors 30 and the like can be mounted in an empty space on the opposite side of the semiconductor chip 2.

On the other hand, in the high frequency package 1 shown in FIGS. 35 and 36, one semiconductor chip 2 is arranged closer to the coaxial connector 11 than the central portion, and the chip corresponding region on the back surface 4b of the package substrate 4 is arranged. In the high frequency package 1 shown in FIGS. 37 and 38, one semiconductor chip 2 is arranged closer to the coaxial connector 11 than the central portion, and the package capacitors are mounted on the package. A plurality of chip capacitors 30 are mounted in a recess 4l which is a cavity formed in the chip corresponding region of the back surface 4b of the substrate 4.

Any of the high frequency packages 1 shown in FIGS. 28 to 38 can be downsized, thinned and reduced in cost.

(Second Embodiment) FIG. 39 is a sectional view showing the structure of a semiconductor device (high-frequency package) according to the second embodiment of the present invention, and FIGS. 40 and 41 are modification examples of the second embodiment of the present invention. 43 is a cross-sectional view showing the structure of the high-frequency package of FIG. 42, FIG.
41 is a partial cross-sectional view showing an example of the connection state of the auxiliary board and the coaxial cable in the assembly of the high-frequency package shown in FIG. 41, and FIG. 44 is a partial cross-sectional view showing an example of the testing state in the assembly of the high-frequency package shown in FIG. 41. 45 is a partial cross-sectional view showing an example of the structure of the high-frequency package shown in FIG. 41 after completion of assembly.

The semiconductor device shown in FIG. 39 of the second embodiment is a high frequency semiconductor package for optical communication having a coaxial cable 7 as in the high frequency package 1 of the first embodiment. The coaxial cable 7 as shown in FIG. 1 is not attached via the coaxial connector 11 or the coaxial cable 7 is directly attached to the package substrate 4 which is a chip carrier, but the coaxial cable 7 is shown in FIG. The optical module 14 (semiconductor module device) is connected to the module substrate 13, and the module substrate 13 is connected to the package substrate 4 via the projecting electrodes.

Therefore, the module substrate 13 is used as a relay member when transmitting a high-frequency signal from the coaxial cable 7 to the package substrate 4. The module substrate 13 also has a signal on the surface of the main surface 13a thereof. Surface wiring (surface wiring) 13c and the signal surface wiring 13
A microstrip line 13g composed of c and a GND layer (ground conductor layer) 13f formed inside via an insulating layer 13e is formed.

Therefore, the signal surface wiring 4c of the microstrip line 4g of the package substrate 4 and the coaxial cable 7 are used.
Is connected to the core wire 7a via the signal surface wiring 13c of the microstrip line 13g of the module substrate 13.

That is, since the thin ball electrodes 34 as external connection terminals are formed on the main surface 4a of the package substrate 4 on the flip chip connection side, the main surface 4a of the package substrate 4 and the main surface 13a of the module substrate 13 are formed. Are arranged so as to face each other, so that the signal surface wiring 4 of the package substrate 4 is interposed via the thin ball electrode 34 made of solder or the like.
c and the signal surface wiring 13c of the module substrate 13 can be connected, whereby the microstrip line 4g of the package substrate 4 and the microstrip line 13g of the module substrate 13 are connected via the thin ball electrode 34 of solder. It is connected.

Therefore, the high frequency package 1 of the second embodiment also has a high frequency (for example, 40 Hz) from the coaxial cable 7.
Gbps) signal can be directly input to the semiconductor chip 2 via the signal surface wiring 13c of the module substrate 13 and the thin ball electrode 34, and a high frequency signal can be input to the surface layer of the package substrate 4 via the module substrate 13. Can be transmitted only by the microstrip line.

As a result, as in the high frequency package 1 of the first embodiment, by transmitting the high frequency signal only through the microstrip line on the surface layer of the module substrate 13 and the package substrate 4 without passing through the wiring by the via, A high frequency signal can be transmitted without loss of frequency characteristics.

The signal on the low frequency side is sent to the outside through the internal signal wiring 4d of the package substrate 4, the thin ball electrode 34, and the internal signal wiring 13d of the module substrate 13.

The semiconductor chip 2 is the package substrate 4
Module board 1 with flip-chip connection to
3 is arranged in the opening 13h, and the semiconductor chip 2
A heat radiation block (heat radiation member) 26 is attached to the back surface 2b of the module via the heat conductive adhesive 10. Therefore, the heat radiation block 26 is arranged on the back surface 13b side of the module substrate 13.

Since the high frequency package 1 of the second embodiment has a structure in which the module substrate 13 is interposed between the coaxial cable 7 and the package substrate 4 without directly mounting the coaxial cable 7 on the package substrate 4, the IC A maker can handle a structure in which the semiconductor chip 2 is flip-chip connected to the package substrate 4 as a product.

In this case, the coaxial cable 7 is connected to the module substrate 13 on the user side, and further, the user side connects the package substrate 4 and the module substrate 13 via the thin ball electrode 34 to the high frequency package. Assemble 1.

As described above, in the high frequency package 1 using the module substrate 13 as a relay member, the semiconductor chip 2
Since the package board 4 on which is mounted and the module board 13 to which the coaxial cable 7 is connected are separately assembled and then connected, the respective yields can be separated.

That is, the yield risk can be divided between the assembly of the semiconductor chip 2 and the assembly of the coaxial cable 7, and the yield of the structure after connecting both the assemblies can be improved.

Further, in the high frequency package 1 using the module substrate 13, since the expensive coaxial connector 11 is not used, it is possible to reduce the cost of the high frequency package 1 and to reduce the thickness thereof.

Further, since all the external connection terminals are provided on the main surface 4a of the package substrate 4 on the flip chip connection side, a selection test can be easily performed when selecting the high frequency semiconductor chip 2 of 40 Gbps. be able to.

That is, since all the high frequency and low frequency external connection terminals are provided on one surface (main surface 4a) of the package substrate 4, it is easy to bring the probe needle into contact during the selection test. Therefore, the test can be performed without using a jig having a complicated shape.

As a result, the test time can be shortened.

In the high frequency package 1 of the modified example shown in FIG. 40, a cap 9 is first attached to the back surface 2b of the semiconductor chip 2 via a heat conductive adhesive 10, and the surface of the cap 9 is heated. The heat dissipation block 26 is attached via the conductive adhesive 10.

In this case, the cap 9 is provided with an opening (meat relief) 9a for insulating the cap 9 from the surface wiring such as the signal surface wiring 4c.

Furthermore, the high frequency package 1 shown in FIG.
Since not only the cap 9 but also the heat dissipation block 26 is provided on the cap 9, the heat dissipation of the high frequency package 1 can be further enhanced and deterioration of the high frequency characteristics can be prevented.

Next, in the high frequency package 1 of the modified example shown in FIG. 41, when the relay member connecting the coaxial cable 7 and the signal surface wiring 4c of the package substrate 4 is the auxiliary substrate 32 which is the second package substrate. And this auxiliary board 3
2 includes a signal surface layer wiring (surface layer wiring) 32c on the surface layer of the main surface 32a, and a GND layer (ground conductor layer) 32f formed inside via the signal surface layer wiring 32c and the insulating layer 32e. A microstrip line 32g consisting of is formed.

Therefore, the signal surface wiring 4c of the microstrip line 4g of the package substrate 4 and the coaxial cable 7 are used.
To the core wire 7a of the auxiliary substrate 32 via the signal surface wiring 32c of the microstrip line 32g of the auxiliary substrate 32.

That is, the thin ball electrodes 34 as external connection terminals are formed on the main surface 4a of the package substrate 4 on the flip chip connection side, and the main surface 4a of the package substrate 4 and the main surface 32a of the auxiliary substrate 32 are connected to each other. Are arranged to face each other, the signal surface wiring 4c of the package substrate 4 and the signal surface wiring 32c of the auxiliary substrate 32 can be connected via the thin ball electrode 34 made of solder or the like. The microstrip line 4g of the package substrate 4 and the microstrip line 32g of the auxiliary substrate 32 are connected via the thin ball electrode 34 of solder.

Therefore, also in the high frequency package 1 of the modification shown in FIG. 41, the high frequency (for example, 40 Gbps) signal from the coaxial cable 7 is passed through the signal surface wiring 32c of the auxiliary substrate 32 and through the thin ball electrode 34. Can be directly input to the semiconductor chip 2, and high-frequency signals can be transmitted through the auxiliary substrate 32 only on the microstrip line on the entire surface layer of the package substrate 4.

As a result, like the high frequency package 1 of the first embodiment, by transmitting the high frequency signal only through the microstrip lines on the surface layers of the auxiliary substrate 32 and the package substrate 4 without passing through the wiring by the vias or the like,
A high frequency signal can be transmitted without loss of frequency characteristics.

The signal on the low frequency side passes through the internal signal wiring 4d of the package substrate 4, the thin ball electrode 34, the internal signal wiring 32d of the auxiliary substrate 32, and the pin member (connection terminal). Module board 1 through 33
3 is transmitted.

Also, the semiconductor chip 2 is the package substrate 4
Is placed in the opening 32h of the auxiliary substrate 32 in the state of being flip-chip connected to the semiconductor chip 2, and the cap 9 is attached to the back surface 2b of the semiconductor chip 2 via the heat conductive adhesive 10. A heat dissipation block (heat dissipation member) 26 is attached to the
The heat dissipation block 26 is arranged on the back surface 32b side of the auxiliary substrate 32.

In the high frequency package 1 of the second embodiment, the parts on the coaxial cable 7 side and the parts on the semiconductor chip 2 side are separately sorted, and good parts are connected to each other to form the high frequency package 1. The yield can be improved.

That is, the chip side structure 36 shown in FIG. 42 in which the semiconductor chip 2 with the cap 9 attached is flip-chip connected, and the cable side shown in FIG. 43 in which the coaxial cable 7 is connected to the auxiliary substrate 32 by solder connection 31. The structure 37 and the structure 37 are respectively assembled, and each structure is separately tested.

Thus, since both structures include the microstrip line, a high-frequency test can be performed for each component, and the yields can be separated by connecting non-defective products.
As a result, the chip side structure 36 and the cable side structure 3
Yield risk can be divided into 7 and 7, and the yield of the high frequency package 1 shown in FIG. 41 in which both structures are connected can be improved.

Furthermore, the chip-side structure 36 and the cable-side structure 37 can be distributed as individual parts, or can be obtained as parts.

Since all the external connection terminals are provided on the main surface 4a of the package substrate 4 on the flip chip connection side, a selection test can be easily performed when selecting the high frequency semiconductor chip 2 of 40 Gbps. be able to.

That is, since all the high frequency and low frequency external connection terminals are provided on one surface (main surface 4a) of the package substrate 4, it is easy to bring the probe needle into contact during the selection test. Therefore, the test can be performed without using a jig having a complicated shape.

As a result, the test time can be shortened.

The auxiliary board 32 can also be used as a testing board 35 as shown in FIG. 44, and can also be used as a socket in the selection test of the package board 4.

At that time, ACF (Anisotropic Conductive
The testing is performed by electrically contacting the package substrate 4 and the testing substrate 35 via an interposer 35a such as a film) and transmitting a signal to the outside via a pin member 35b.

As with the auxiliary substrate 32 and the like, the testing substrate 35 includes the signal surface layer wiring 35c, the internal signal wiring 35d, the signal surface layer wiring 35c, and the GND layer 35f and the insulating layer 35e. A microstrip line 35g is formed.

The chip side structure 36 shown in FIG. 42 and FIG.
FIG. 45 shows a structure obtained by separately selecting the cable-side structure 37 shown in FIG. 3 and obtaining a good product for each, and then assembling the chip-side structure 36 and the cable-side structure 37 by connecting them. It is a high frequency package 1 of a modification of the second embodiment.

Further, the heat conductive adhesive 10 is applied to the surface of the cap 9, the heat radiation block 26 is attached via the heat conductive adhesive 10, and the high frequency package 1 is attached to the optical module 14 via the pin member 35b. 41 is mounted on the module board 13 of FIG.

The high frequency package 1 shown in FIG.
First, the cap 9 is attached to the back surface 2b of the semiconductor chip 2 via the heat conductive adhesive 10, and the heat dissipation block 26 is attached to the surface of the cap 9 via the heat conductive adhesive 10. Optical module 14
In this case, the module case 15 shares the role of the heat dissipation block 26, and the cap 9 is formed with an opening (meat relief) 9a for insulating the cap 9 from the surface wiring such as the signal surface wiring 4c. There is.

Therefore, not only in the cap 9 but also in the high-frequency package 1 shown in FIG.
Since the heat dissipation block 26 (module case 15) is provided in the, the heat dissipation of the high frequency package 1 can be further enhanced, and deterioration of the high frequency characteristics can be prevented.

Although the invention made by the present inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the embodiments of the present invention, and does not depart from the scope of the invention. It goes without saying that various changes can be made with.

For example, in the first embodiment, the case where the semiconductor device is a ball grid array type semiconductor package has been described. However, in the semiconductor device, a plurality of external connection terminals are arranged in the plane of the package substrate. For example, an LGA (Land Grid Array) or the like may be used as long as it has a structure.

Further, in the first and second embodiments, the case where the semiconductor chip 2 is flip-chip connected to the package substrate 4 has been described. However, the electrical connection method between the semiconductor chip 2 and the package substrate 4 is The connection is not limited to flip chip connection, and ribbon bonding using a flat metal wire may be used.

[0157]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.
It is as follows.

In a semiconductor device having a wiring board having a microstrip line and a coaxial cable in which a core wire is electrically connected to the surface wiring of the microstrip line, a plurality of external connection terminals are arranged in the plane of the wiring board. Therefore, the size of the semiconductor device can be reduced.

[Brief description of drawings]

FIG. 1 is a sectional view showing an example of a structure of a semiconductor device (high frequency package) according to a first embodiment of the present invention.

2 is an external perspective view showing an example of the structure of an optical module in which the high-frequency package shown in FIG. 1 is incorporated.

3 is a cross-sectional view showing the structure of the optical module shown in FIG.

FIG. 4 is a plan view showing an example of arrangement of parts incorporated in the optical module shown in FIG.

5 is a cross-sectional view showing an example of arrangement of components incorporated in the optical module shown in FIG.

FIG. 6 is a cross-sectional view showing a structure of a semiconductor device (high frequency package) according to a modification of the first embodiment of the present invention.

7 is a partial plan view showing an example of the structure of a microstrip line in the wiring board of the high-frequency package shown in FIG.

8 is a partial cross-sectional view showing the structure of the microstrip line shown in FIG.

9 is a partial plan view showing a structure of a modified microstrip line in the wiring board of the high frequency package shown in FIG. 1. FIG.

10 is a partial cross-sectional view showing the structure of the microstrip line of the modified example shown in FIG.

FIG. 11 is a perspective view and a cross-sectional view showing a structure of a semiconductor device (high-frequency package) according to a modification of the first embodiment of the present invention.

12 is a cross-sectional view showing an example of a cap mounting structure of the high frequency package shown in FIG.

13 is a plan view of the cap mounting structure shown in FIG.

14 is a sectional view showing a structure of a section taken along line AA of FIG.

FIG. 15 is a bottom view of the cap mounting structure shown in FIG.

16 is a plan view showing an example of the positional relationship between the surface wiring and the cap in the cap mounting structure shown in FIG.

17 is a bottom view showing the structure of the cap as viewed from the direction of arrow C in FIG.

FIG. 18 is a side view showing the structure of the cap shown in FIG.

19 is a sectional view showing the structure of the cap shown in FIG. 17 and an enlarged partial sectional view of a corner portion.

20 is an enlarged partial cross-sectional view showing the detailed structure of a cross section taken along line AA of FIG.

21 is an enlarged partial cross-sectional view showing the detailed structure of a cross section taken along line BB of FIG.

22 is an enlarged partial plan view showing an example of the positional relationship between the surface wiring and the opening of the cap in the cap mounting structure shown in FIG.

FIG. 23 is a cross-sectional view showing the structure of a semiconductor device (high frequency package) according to a modification of the first embodiment of the present invention.

24 is an enlarged partial cross-sectional view showing an example of a structure in which a heat dissipation member is attached to the cap shown in FIG.

FIG. 25 is a cross-sectional view showing the structure of a semiconductor device (high frequency package) according to a modification of the first embodiment of the present invention.

FIG. 26 is a cross-sectional view showing the structure of a semiconductor device (high frequency package) according to a modification of the first embodiment of the present invention.

FIG. 27 is a cross-sectional view showing a structure of a semiconductor device (high frequency package) according to a modification of the first embodiment of the present invention.

FIG. 28 is a plan view showing the structure of the semiconductor device (high frequency package) of the modification of the first embodiment of the invention.

FIG. 29 is a cross-sectional view showing the structure of the high frequency package shown in FIG. 28.

FIG. 30 is a plan view showing a structure of a semiconductor device (high-frequency package) according to a modification of the first embodiment of the present invention.

FIG. 31 is a plan view showing a structure of a semiconductor device (high frequency package) according to a modification of the first embodiment of the present invention.

FIG. 32 is a plan view showing a structure of a semiconductor device (high frequency package) according to a modification of the first embodiment of the present invention.

FIG. 33 is a plan view showing a structure of a semiconductor device (high frequency package) according to a modification of the first embodiment of the present invention.

34 is a cross-sectional view showing the structure of the high frequency package shown in FIG. 33.

FIG. 35 is a plan view showing a structure of a semiconductor device (high frequency package) according to a modification of the first embodiment of the present invention.

36 is a cross-sectional view showing the structure of the high-frequency package shown in FIG. 35.

FIG. 37 is a plan view showing a structure of a semiconductor device (high frequency package) according to a modification of the first embodiment of the present invention.

38 is a sectional view showing the structure of the high-frequency package shown in FIG. 37.

FIG. 39 is a sectional view showing a structure of a semiconductor device (high frequency package) according to a second embodiment of the present invention.

FIG. 40 is a cross-sectional view showing the structure of a semiconductor device (high frequency package) according to a modification of the second embodiment of the present invention.

FIG. 41 is a sectional view showing a structure of a semiconductor device (high-frequency package) according to a modification of the second embodiment of the present invention.

42 is a cross-sectional view showing an example of a cap mounted state in the assembly of the high frequency package shown in FIG. 41.

43 is a partial cross-sectional view showing an example of the connection state of the auxiliary board and the coaxial cable in the assembly of the high-frequency package shown in FIG. 41.

44 is a partial cross-sectional view showing an example of a testing state in assembling the high-frequency package shown in FIG. 41.

45 is a partial cross-sectional view showing an example of the structure of the high-frequency package shown in FIG. 41 after the assembly is completed.

[Explanation of symbols]

1 High frequency package (semiconductor device) 2 semiconductor chips 2a Main surface 2b back 3 ball electrodes (external connection terminals) 3a support ball 4 Package board (wiring board) 4a main surface 4b back side 4c Signal surface wiring (surface wiring) 4d internal signal wiring 4e insulating layer 4f GND layer (ground conductor layer) 4g microstrip line 4h GND surface wiring (ground wiring for ground) 4i via wiring 4j Solder resist 4k step 4l recess 5 Solder bump electrode 6 Underfill resin 7 coaxial cable 7a core wire 7b shield 8 frame members 9 Cap (heat dissipation member) 9a Opening (flesh escape) 9b leg 9c Cutout part (meat relief part) 9d base material 9e conductive film 9f non-conductive film 10 Thermally conductive adhesive 11 Coaxial connector (relay member) 12 glass beads 13 Module board (relay member) 13a main surface 13b back side 13c Signal surface wiring (surface wiring) 13d Internal signal wiring 13e insulating layer 13f GND layer (ground conductor layer) 13g microstrip line 13h opening 14 Optical module (semiconductor module device) 15 module case 16 fins 17 module connector 18 wind 19 Amplifier element 20 photoelectric converter 21 Microstrip line structure 22 Coaxial structure 23 Coplanar structure 23a Coplanar track 24 Thin coaxial connector (plate member) 24a Signal surface wiring (surface wiring) 24b GND line (ground wiring) 24c microstrip line 24d step 25 Conductive material 26 Heat dissipation block (heat dissipation member) 27 Second semiconductor chip 28 Balancer 29 screw members 30 chip capacitors 31 Solder connection 32 Auxiliary board (relay member) 32a main surface 32b back side 32c signal surface wiring (surface wiring) 32d internal signal wiring 32e insulating layer 32f GND layer (ground conductor layer) 32g microstrip line 32h opening 33-pin member (connection terminal) 34 Thin ball electrode 35 testing board 35a interposer 35b pin member 35c Signal surface wiring 35d Internal signal wiring 35e insulating layer 35f GND layer 35g microstrip line 36 Chip side structure 37 Cable side structure

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Taku Suga             292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa             Inside the Hitachi, Ltd. production technology laboratory (72) Inventor Hiroyasu Sasaki             292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa             Inside the Hitachi, Ltd. production technology laboratory (72) Inventor Eiko Ando             3 shares at 6-16 Shinmachi, Ome City, Tokyo             Hitachi Device Development Center (72) Inventor Masanori Fukuhara             3 shares at 6-16 Shinmachi, Ome City, Tokyo             Hitachi Device Development Center (72) Inventor Satoru Isomura             3 shares at 6-16 Shinmachi, Ome City, Tokyo             Hitachi Device Development Center F-term (reference) 5J011 CA12 CA21

Claims (22)

[Claims] 1. A wiring board having surface wiring, a ground conductor layer formed inside via the surface wiring and an insulating layer, and a semiconductor chip mounted electrically connected to the wiring board, And a structure having a coaxial structure in which a core wire is electrically connected to the surface wiring, and a plurality of external connection terminals are provided in any one of the main surface of the wiring board and the back surface on the opposite side thereof. A semiconductor device characterized by being arranged. 2. A wiring board having surface wiring, a ground conductor layer formed inside via the surface wiring and an insulating layer, and a semiconductor chip mounted electrically connected to the wiring board. A coaxial cable in which a core wire is electrically connected to the surface layer wiring, and a plurality of external connection terminals are arranged in any one of the main surface of the wiring board and the back surface opposite to the main surface. A semiconductor device characterized by: 3. The semiconductor device according to claim 2, wherein the semiconductor device is a ball grid array having a plurality of bump electrodes as the external connection terminals. 4. The semiconductor device according to claim 2, wherein the semiconductor device is a land grid array having a plurality of land electrodes as the external connection terminals. 5. The semiconductor device according to claim 2, wherein the semiconductor chip is mounted on the wiring board via a plurality of solder bump electrodes, and the coaxial cable is one of the plurality of solder bump electrodes. A semiconductor device characterized in that a solder bump electrode arranged nearer is connected to the surface wiring. 6. The semiconductor device according to claim 2, wherein the semiconductor chip is mounted on the wiring board via a plurality of solder bump electrodes, and the semiconductor chip is mounted on the outermost periphery of the plurality of solder bump electrodes. A semiconductor device, wherein the arranged solder bump electrode is connected to the surface wiring. 7. The semiconductor device according to claim 2, wherein the core wire of the coaxial cable is directly soldered to the signal surface wiring of the surface wiring of the wiring board. 8. The semiconductor device according to claim 2, wherein the semiconductor chip is flip-chip connected onto the wiring board via a solder bump electrode, and a heat dissipation member is attached to a back surface of the semiconductor chip. A semiconductor device characterized in that 9. The semiconductor device according to claim 2, wherein the semiconductor chip is flip-chip connected to the wiring board via solder bump electrodes, and a part of the heat dissipation is arranged on the surface wiring. A member is attached to a back surface of the semiconductor chip, and the heat dissipation member is provided with a meat relief portion for insulating the heat dissipation member and the surface wiring from each other. 10. The semiconductor device according to claim 2, wherein:
A semiconductor device, wherein a frame member is attached to the wiring board along an outer peripheral portion thereof, and the frame member is provided with a coaxial connector to be fitted with the coaxial cable. 11. The semiconductor device according to claim 2, wherein:
The semiconductor device, wherein the wiring board is a package board on which the semiconductor chip is mounted. 12. A wiring board having surface wiring, a ground conductor layer formed inside via the surface wiring and an insulating layer, and a semiconductor chip mounted electrically connected to the wiring board. A semiconductor device comprising: the surface layer wiring and a coaxial cable in which a core wire is electrically connected, and the semiconductor chip is arranged on the main surface of the wiring board so as to be closer to the coaxial cable. 13. A wiring board having surface wiring, a ground conductor layer formed inside via the surface wiring and an insulating layer, and a semiconductor chip electrically connected to and mounted on the wiring board, A coaxial cable in which the surface layer wiring and the core wire are electrically connected, and a plurality of external connection terminals are arranged in any one of the main surface of the wiring board and the back surface on the opposite side thereof. A semiconductor device in which the semiconductor chip is arranged on the main surface of the wiring board so as to be closer to the coaxial cable. 14. A semiconductor device incorporated in a semiconductor module device, comprising: a wiring board having surface wiring and a ground conductor layer formed inside via the surface wiring and an insulating layer; Are electrically connected to each other, the coaxial cable, the surface wiring of the wiring board and the coaxial cable are electrically connected to each other, and the signal surface wiring and insulating layers are formed on both sides of the wiring. And a coaxial cable, the surface layer wiring of the wiring board and the coaxial cable are connected via the signal surface layer wiring of the relay member. 15. The semiconductor device according to claim 14, wherein the relay member is a plate-shaped member having signal surface wirings and ground wirings formed on both sides of the signal wirings via insulating portions, A semiconductor device in which a surface wiring of a wiring board and a core wire of the coaxial cable are connected via a signal surface wiring of the plate member. 16. The semiconductor device according to claim 14, wherein the relay member has a surface wiring and a ground conductor layer formed inside via the insulating layer and the surface wiring, and the semiconductor device is mounted on the relay member. Also, the semiconductor device is a module substrate of the semiconductor module device, wherein the surface wiring of the wiring board of the semiconductor device and the core wire of the coaxial cable are connected via the surface wiring of the module substrate. 17. The semiconductor device according to claim 16, wherein external connection terminals are formed on a main surface of the wiring board on a flip-chip connection side, and surface wiring of the wiring board is provided via the external connection terminals. A semiconductor device in which the surface layer wiring of the module substrate is connected to the module substrate. 18. The semiconductor device according to claim 14, wherein the relay member has a surface wiring and a ground conductor layer formed inside via a surface wiring and an insulating layer, and the module of the semiconductor module device. It is an auxiliary substrate in which a connection terminal connected to the substrate is formed, and the surface wiring of the wiring substrate of the semiconductor device and the core wire of the coaxial cable are electrically connected via the surface wiring of the auxiliary substrate. A semiconductor device characterized by the above. 19. The semiconductor device according to claim 18, wherein external connection terminals are formed on a main surface of the wiring board on a flip chip connection side, and surface wiring of the wiring board is provided via the external connection terminals. And a surface wiring of the auxiliary substrate are connected to each other, the semiconductor device. 20. The semiconductor device according to claim 14, wherein the semiconductor chip is flip-chip connected onto the wiring board via a solder bump electrode, and a heat dissipation member is attached to a back surface of the semiconductor chip. A semiconductor device characterized in that 21. The semiconductor device according to claim 14, wherein the semiconductor chip is flip-chip connected to the wiring board via solder bump electrodes, and a part of the heat dissipation is arranged on the surface wiring. A member is attached to a back surface of the semiconductor chip, and the heat dissipation member is provided with a meat relief portion for insulating the heat dissipation member and the surface wiring from each other. 22. A plurality of via wirings, each of which has a surface layer wiring and a grounding conductor layer formed inside with an insulating layer interposed therebetween, and which connects the grounding surface layer wiring of the surface layer wiring and the grounding conductor layer to each other. A formed wiring board, a semiconductor chip mounted electrically connected to the wiring board, a coaxial cable in which a core wire is directly connected to the signal surface wiring of the surface wiring, a main surface of the wiring board or A plurality of external connection terminals arranged in any one of the opposite back surface, the plurality of via wiring, in the region between the outermost via wiring and the coaxial cable A semiconductor device, wherein the signal surface wiring of the surface wiring and the ground conductor layer are arranged on the same plane, and the ground conductor layer is arranged inside the outermost via wiring.