JP2010141366A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To downsize a semiconductor device by arranging a plurality of terminals for external connection in a surface of a wiring board. <P>SOLUTION: This semiconductor device includes: a package board 4 having an optical communication IC mounted thereon, and including a micro-strip line 4g having surface layer wiring 4c for a signal and a GND layer 4f; a high-frequency semiconductor chip 2 mounted on a principal surface 4a of the package board 4 by flip chip connection; a coaxial cable 7 with a core 7a electrically connected to the surface layer wiring 4c for a signal; an underfill resin 6 for protecting the flip chip connection part of the semiconductor chip 2; a plurality of ball electrodes 3 arranged in the back face 4b of the package board 4; and a coaxial connector 11 arranged on a frame member 8 attached to the package board 4. The semiconductor device includes a structure capable of transmitting a high-frequency signal from the coaxial cable 7 to all the surface layer of the package board 4 only by the micro-strip line, and allows the package to be downsized by arranging the plurality of ball electrodes 3 in an array-like form on the back face 4b of the package board 4. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to a technique effective when applied to miniaturization of an optical communication semiconductor device using a coaxial cable.

  There is a coaxial cable as one of high-speed signal transmission means. As an example of a structure using this coaxial cable, in a PGA (Pin Grid Array) type semiconductor package (semiconductor device), There is a technique in which a signal transmission path in the thickness direction between the back surfaces is constituted by a coaxial cable. Furthermore, as an example of a semiconductor package having a high-frequency optical communication element, a microstrip line (Au thin film wiring layer) is formed on the surface of an insulating ceramic substrate, and an insulating lid with a low dielectric constant is made of glass with a low dielectric constant. There is a technique for reducing transmission loss of a high-frequency signal by joining together (see, for example, Patent Document 1).

  Moreover, it describes about the optical communication apparatus using a coaxial cable (for example, refer nonpatent literature 1).

JP-A-5-167258

Shoichi Hanatani, Katsuyoshi Karasawa, Kiyoshi Yamashita, Keisuke Maeda, published on September 3, 1986, National Convention on Communications, Optical and Radio Waves, "Characteristics of 565 Mb / s optical transmitter using DFB-LD" , Pages 2-170

  In the semiconductor package described in Japanese Patent Application Laid-Open No. 5-167258 (Patent Document 1), the core wire of the coaxial cable and the surface wiring of the multilayer wiring substrate are joined at a right angle, and the core wire and the surface wiring are joined. Since the difference in cross-sectional area in the direction perpendicular to the direction in which the core wire extends is large, the signal is reflected at a location where the area of the joint portion between the core wire and the surface wiring has changed.

  As a result, there is a problem of deteriorating high frequency characteristics.

  Further, the present inventor, as a structure for realizing a high-frequency semiconductor device to which a coaxial cable is connected, connects an inner lead as an external connection terminal to a package substrate on which a high-frequency semiconductor chip is mounted. The structure in which the outer lead connected to the outer surface of the package substrate protrudes outward from the package substrate along the plane direction thereof was examined.

  However, in the structure in which the outer lead protrudes toward the outside of the substrate along the planar direction of the package substrate, there is a problem that the size cannot be reduced.

  An object of the present invention is to provide a technique capable of reducing the size of a semiconductor device.

  Another object of the present invention is to provide a technique capable of reducing the thickness of a semiconductor device.

  Another object of the present invention is to provide a technique capable of reducing the price of a semiconductor device.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.

  That is, the present invention relates to a wiring board having a surface layer wiring, a grounding conductor layer formed inside through the surface layer wiring and the insulating layer, a semiconductor chip electrically connected to the wiring board, and a coaxial Electrically connecting the cable, the surface layer wiring of the wiring board, and the coaxial cable, and having a signal surface layer wiring and a relay member provided with grounding wiring formed on both sides of the wiring via an insulating portion. The surface layer wiring of the substrate and the coaxial cable are connected via the signal surface wiring of the relay member.

  Of the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  In a semiconductor device having a wiring board having a microstrip line and a coaxial cable in which a core wire is electrically connected to a surface layer wiring of the microstrip line, a plurality of external connection terminals are arranged in the plane of the wiring board Thus, the semiconductor device can be reduced in size.

It is sectional drawing which shows an example of the structure of the semiconductor device (high frequency package) of Embodiment 1 of this invention. It is an external appearance perspective view which shows an example of the structure of the optical module in which the high frequency package shown in FIG. 1 is integrated. It is sectional drawing which shows the structure of the optical module shown in FIG. It is a top view which shows an example of arrangement | positioning of the components integrated in the optical module shown in FIG. It is sectional drawing which shows an example of arrangement | positioning of the components integrated in the optical module shown in FIG. It is sectional drawing which shows the structure of the semiconductor device (high frequency package) of the modification of Embodiment 1 of this invention. It is a partial top view which shows an example of the structure of the microstrip line in the wiring board of the high frequency package shown in FIG. It is a fragmentary sectional view which shows the structure of the microstrip line shown in FIG. It is a fragmentary top view which shows the structure of the microstrip line | wire of the modification in the wiring board of the high frequency package shown in FIG. It is a fragmentary sectional view which shows the structure of the microstrip line | wire of the modification shown in FIG. It is the perspective view and sectional drawing which show the structure of the semiconductor device (high frequency package) of the modification of Embodiment 1 of this invention. It is sectional drawing which shows an example of the cap mounting structure of the high frequency package shown in FIG. It is a top view of the cap mounting structure shown in FIG. It is sectional drawing which shows the structure of the cross section cut | disconnected along the AA line of FIG. It is a bottom view of the cap mounting structure shown in FIG. It is a top view which shows an example of the positional relationship of surface layer wiring and a cap in the cap mounting structure shown in FIG. It is a bottom view which shows the structure of the cap seen from C arrow of FIG. It is a side view which shows the structure of the cap shown in FIG. It is sectional drawing which shows the structure of the cap shown in FIG. 17, and the expanded partial sectional view of a corner | angular part. It is an expanded partial sectional view which shows the detailed structure of the cross section cut | disconnected along the AA line of FIG. It is an expanded partial sectional view which shows the detailed structure of the cross section cut | disconnected along the BB line of FIG. FIG. 13 is an enlarged partial plan view showing an example of the positional relationship between the surface wiring and the cap opening in the cap mounting structure shown in FIG. 12. It is sectional drawing which shows the structure of the semiconductor device (high frequency package) of the modification of Embodiment 1 of this invention. It is an expanded partial sectional view which shows an example of the structure which attached the heat radiating member to the cap shown in FIG. It is sectional drawing which shows the structure of the semiconductor device (high frequency package) of the modification of Embodiment 1 of this invention. It is sectional drawing which shows the structure of the semiconductor device (high frequency package) of the modification of Embodiment 1 of this invention. It is sectional drawing which shows the structure of the semiconductor device (high frequency package) of the modification of Embodiment 1 of this invention. It is a top view which shows the structure of the semiconductor device (high frequency package) of the modification of Embodiment 1 of this invention. It is sectional drawing which shows the structure of the high frequency package shown in FIG. It is a top view which shows the structure of the semiconductor device (high frequency package) of the modification of Embodiment 1 of this invention. It is a top view which shows the structure of the semiconductor device (high frequency package) of the modification of Embodiment 1 of this invention. It is a top view which shows the structure of the semiconductor device (high frequency package) of the modification of Embodiment 1 of this invention. It is a top view which shows the structure of the semiconductor device (high frequency package) of the modification of Embodiment 1 of this invention. It is sectional drawing which shows the structure of the high frequency package shown in FIG. It is a top view which shows the structure of the semiconductor device (high frequency package) of the modification of Embodiment 1 of this invention. FIG. 36 is a cross-sectional view showing the structure of the high-frequency package shown in FIG. 35. It is a top view which shows the structure of the semiconductor device (high frequency package) of the modification of Embodiment 1 of this invention. It is sectional drawing which shows the structure of the high frequency package shown in FIG. It is sectional drawing which shows the structure of the semiconductor device (high frequency package) of Embodiment 2 of this invention. It is sectional drawing which shows the structure of the semiconductor device (high frequency package) of the modification of Embodiment 2 of this invention. It is sectional drawing which shows the structure of the semiconductor device (high frequency package) of the modification of Embodiment 2 of this invention. It is sectional drawing which shows an example of the cap mounting state in the assembly of the high frequency package shown in FIG. It is a fragmentary sectional view which shows an example of the connection state of the auxiliary | assistant board | substrate and a coaxial cable in the assembly of the high frequency package shown in FIG. FIG. 42 is a partial cross-sectional view showing an example of a testing state in assembling the high-frequency package shown in FIG. 41. FIG. 42 is a partial cross-sectional view showing an example of the structure after the assembly of the high-frequency package shown in FIG. 41 is completed.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  In the following embodiment, when necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. Is related to some or all of the other modifications, details, supplementary explanations, and the like.

  Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), particularly when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and it may be more or less than the specific number.

  Further, in the following embodiments, the constituent elements (including element steps) are not necessarily essential unless explicitly stated or considered to be clearly essential in principle. Needless to say.

  Similarly, in the following embodiments, when referring to the shape, positional relationship, etc., of components, etc., the shape of the component is substantially the case unless specifically stated or otherwise considered in principle. And the like are included. The same applies to the numerical values and ranges.

  Further, members having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted.

(Embodiment 1)
1 is a sectional view showing an example of the structure of a high-frequency package according to Embodiment 1 of the present invention, FIG. 2 is an external perspective view showing an example of the structure of an optical module in which the high-frequency package shown in FIG. 1 is incorporated, and FIG. 4 is a cross-sectional view showing the structure of the optical module shown in FIG. 2, FIG. 4 is a plan view showing an example of the arrangement of components incorporated in the optical module shown in FIG. 2, and FIG. 5 shows the arrangement of components incorporated in the optical module shown in FIG. FIG. 6 is a sectional view showing a structure of a high-frequency package according to a modification, FIG. 7 is a partial plan view showing an example of the structure of a microstrip line in the wiring board of the high-frequency package shown in FIG. 1, and FIG. FIG. 9 is a partial cross-sectional view showing the structure of the microstrip line shown in FIG. 7, and FIG. 9 is a partial plan view showing the structure of the microstrip line as a modification of the wiring board of the high-frequency package shown in FIG. 10 is a partial cross-sectional view showing the structure of the microstrip line of the modification shown in FIG. 9, FIG. 11 is a perspective view and a cross-sectional view showing the structure of the high-frequency package of the modification, and FIG. 12 is a cap of the high-frequency package shown in FIG. FIG. 13 is a plan view of the cap mounting structure shown in FIG. 12, FIG. 14 is a cross-sectional view taken along line AA in FIG. 13, and FIG. 15 is a cap mounting shown in FIG. FIG. 16 is a plan view showing an example of the positional relationship between the surface layer wiring and the cap in the cap mounting structure shown in FIG. 12, and FIG. 17 is a bottom view showing the structure of the cap as viewed from the arrow C in FIG. 18 is a side view showing the structure of the cap shown in FIG. 17, FIG. 19 is a sectional view showing the structure of the cap shown in FIG. 17, an enlarged partial sectional view of the corner, and FIG. 20 is taken along the line AA in FIG. Enlarged partial cut 21 is an enlarged partial cross-sectional view taken along the line BB in FIG. 13. FIG. 22 is an enlarged partial plan view showing an example of the positional relationship between the surface wiring and the cap opening in the cap mounting structure shown in FIG. FIG. 23 is a cross-sectional view showing the structure of a high-frequency package of a modification, FIG. 24 is an enlarged partial cross-sectional view showing an example of a structure in which a heat dissipation member is attached to the cap shown in FIG. 12, and FIGS. 28 is a cross-sectional view showing the structure of the high-frequency package of the modification, FIG. 28 is a plan view showing the structure of the high-frequency package of the modification of Embodiment 1, and FIG. 29 is a cross-sectional view of the high-frequency package shown in FIG. 31 and 32 are plan views showing the structure of a high-frequency package according to a modification of the first embodiment of the present invention, FIG. 33 is a plan view showing the structure of a high-frequency package according to a modification of the first embodiment, and FIG. 4 is a cross-sectional view of the high-frequency package shown in FIG. 33, FIG. 35 is a plan view showing the structure of a high-frequency package according to a modification of the first embodiment, FIG. 36 is a cross-sectional view of the high-frequency package shown in FIG. FIG. 38 is a cross-sectional view of the high-frequency package shown in FIG. 37. FIG.

  The semiconductor device according to the first embodiment shown in FIG. 1 is a semiconductor package on which an optical communication IC (Integrated Circuit) is mounted. For example, the semiconductor device is a high-frequency package 1 capable of high-speed transmission at 40 Gbps. The high frequency package 1 is mounted on the optical module (semiconductor module device) 14 shown in FIGS. 2 and 3 and has a coaxial cable 7 for signal transmission on the high frequency side.

  The configuration of the high-frequency package 1 is a microstrip comprising a signal surface layer wiring (surface layer wiring) 4c, and a signal layer wiring 4c and a GND layer (grounding conductor layer) 4f formed inside through the insulating layer 4e. A package substrate (wiring substrate) 4 which is a chip carrier having a line 4g, and a high-frequency semiconductor mounted and electrically connected to the main surface 4a of the package substrate 4 by a flip chip connection via a plurality of solder bump electrodes 5 Flip chip connection portion is inserted between the chip 2, the coaxial cable 7 in which the core wire 7a is electrically connected to the signal surface wiring 4c, and the main surface 2a of the semiconductor chip 2 and the main surface 4a of the package substrate 4. A ball that is a plurality of external connection terminals disposed in a back surface 4 b opposite to the main surface 4 a of the package substrate 4. Consisting of the pole 3.

  In other words, the high-frequency package 1 is for directly inputting a high-frequency (for example, 40 Gbps) signal from the coaxial cable 7 to the semiconductor chip 2 through the solder bump electrode 5 via the signal surface wiring 4c of the package substrate 4. The high-frequency signal can be transmitted to all the surface layers of the package substrate 4 only by the microstrip line.

  Therefore, a high frequency signal can be transmitted without losing frequency characteristics by transmitting the high frequency signal only through the microstrip line on the surface layer of the package substrate 4 without using vias or the like.

  The surface layer wirings such as the signal surface layer wiring 4c and the GND surface layer wiring 4h are, for example, wirings formed of copper or the like and arranged in the uppermost layer on the main surface 4a side of the package substrate 4. It may be exposed on the surface of 4a, or may be coated with a nonconductive thin film.

  In addition, when high-speed transmission such as 40 Gbps is performed, it is preferable that the signal surface wiring 4c of the microstrip line 4g be shortest. Therefore, among the plurality of solder bump electrodes 5 connected to the semiconductor chip 2 of the package substrate 4, the solder bump electrode 5 disposed closer to the coaxial cable 7 (coaxial connector 11) from the center of the semiconductor chip 2 is connected to the signal surface wiring 4c. Connected with.

  Preferably, among the plurality of solder bump electrodes 5, any one of the solder bump electrodes 5 arranged on the outermost periphery is connected to the signal surface wiring 4c.

  As a result, high-speed signal transmission can be realized while minimizing the loss of high-frequency frequency characteristics, and noise can be reduced on the microstrip line 4g, so that deterioration of high-frequency characteristics can also be suppressed.

  In the high frequency package 1, a plurality of ball electrodes (bump electrodes) 3 provided as external connection terminals are arranged in an array on the back surface 4 b of the package substrate 4. Therefore, the high frequency package 1 includes a ball grid array. Type semiconductor package.

  As a result, the package can be reduced in size as compared with the outer lead protruding high frequency package in which the outer lead protrudes outward from the package substrate 4.

  The microstrip line 4g transmits a high-frequency signal as an electromagnetic wave in the insulating layer 4e between the signal surface wiring 4c and the internal GND layer 4f. However, in the surface layer of the package substrate 4, FIG. As shown, a microstrip line 4g is formed also with a GND surface layer wiring (grounding surface layer wiring) 4h disposed on both sides of the signal surface layer wiring 4c via an insulating portion.

  In the high-frequency package 1, a frame member 8 is attached to the package substrate 4 along the outer peripheral portion thereof, and a coaxial connector (relay member) 11 that fits with the coaxial cable 7 is attached to the frame member 8 together with the glass beads 12. Is provided. Therefore, the coaxial cable 7 is fitted into the coaxial connector 11, and the core wire 7a of the coaxial cable 7 is soldered 31 to the signal surface wiring 4c of the package substrate 4 (even if it is connected by a conductive resin or the like). Good).

  The diameter of the coaxial connector 11 is, for example, about 10 mm.

  The package substrate 4 is a substrate formed of, for example, glass-containing ceramic, and has a thickness of, for example, about 1 mm. Inside the package substrate 4, in addition to the GND layer 4 f, solder for flip chip connection is provided. An internal signal wiring 4d which is a signal line for connecting the bump electrode 5 and the ball electrode 3 which is an external connection terminal corresponding to the bump electrode 5 is formed.

  The high-frequency package 1 having such a structure is incorporated in an optical module (semiconductor module device) 14 as shown in FIG. 2 and mounted on the module substrate (relay member) 13.

  Here, the structure of the optical module 14 will be described.

  The optical module 14 shown in FIGS. 2 to 5 is a module for high-speed optical communication, for example, a module product mounted on a mobile phone or the like.

  As shown in FIG. 2, the size of the optical module 14 according to the first embodiment is, for example, L (100 to 200 mm) × M (60 to 150 mm), and as shown in FIG. Although (T) is 10 to 25 mm, the size and height of the optical module 14 are not limited to these numerical values.

  The high-frequency package 1 according to the first embodiment is mounted on the module substrate 13 of the optical module 14 and is covered with the module case 15 together with the module substrate 13. A plurality of fins 16 are formed side by side on the surface of the module case 15, and the heat dissipation of the optical module 14 can be improved when the fins 16 receive the wind 18.

  The external terminal of the optical module 14 is a module connector 17 attached to the module substrate 13, and a part thereof is exposed on the back side of the module case 15.

  As shown in FIGS. 4 and 5, in the optical module 14, a high-frequency optical signal input from the input is converted into an electric signal by the photoelectric converter 20, and this electric signal is further input to the input side via the amplifier element 19. 1 enters the high frequency semiconductor chip 2 through the microstrip line 4g of the package substrate 4 and then changes to a low frequency signal so that the internal signal wiring 4d, the solder bump electrode 5, the module substrate 13 and the module substrate 13 shown in FIG. It is sent to the outside of the optical module 14 through the module connector 17.

  On the other hand, a signal input from the module connector 17 side is sent as an output through the reverse path.

  FIG. 4 shows a case where two high-frequency semiconductor chips 2 are provided on the input side and the output side, but the input side and the output side may be incorporated in one semiconductor chip 2. Is possible.

  In FIG. 4, arrows indicated by solid lines in the arrows indicating the flow of input and output signals indicate transmission of optical signals through the optical fiber, and arrows indicated by dotted lines indicate the coaxial cable 7 or the microstrip line. The transmission of the electric signal by 4g is shown.

  Next, FIG. 6 shows a modification of the high-frequency package 1 in which the core wire 7a of the coaxial cable 7 is directly connected to the signal surface wiring 4c of the package substrate 4 by solder or the like.

  That is, the coaxial cable 7 is directly attached to the package substrate 4 with solder or the like without using the coaxial connector 11.

  In this case, the step 4k for arranging the coaxial cable 7 is provided at the end of the package substrate 4, and the surface wiring 4h for GND is provided on the surface of the step 4k, and the coaxial cable 7 is arranged at the step 4k. A shield (GND) 7b covering the core wire 7a of the cable 7 and the GND surface layer wiring 4h at the step 4k are electrically connected by soldering or the like.

  By directly attaching the coaxial cable 7 to the package substrate 4 in this manner, the high-frequency package 1 can be reduced in thickness because the expensive and relatively large coaxial connector 11 is not used. Cost can be reduced.

  Next, a preferable shape of the inner GND layer 4f in the package substrate 4 will be described with reference to FIGS.

  7 and 8 show a case where the GND layer 4f inside the substrate extends to the end of the package substrate 4 in the microstrip line structure 21 using the microstrip line 4g. This is a case where the structure 22 is connected to the microstrip line structure 21.

In this case, input / output high-speed signals to / from the outside of the package pass through the paths of the coaxial cable 7, the signal surface wiring 4 c of the package substrate 4, and the semiconductor chip 2. At this time, the core wire 7 a of the coaxial cable 7 is connected to the signal surface wiring 4 c of the package substrate 4, and the GN of the coaxial cable 7 is connected.
The shield 7 b, which is D, is connected to the GND surface layer wiring 4 h of the package substrate 4.

  Further, a frame member 8 for supporting the coaxial cable 7 may be fixed on the package substrate 4, and the frame member 8 and the shield 7 b of the coaxial cable 7 or the GND surface layer wiring 4 h of the package substrate 4 may be provided. May be connected. As shown in FIG. 8, the GND surface layer wiring 4h and the inner GND layer 4f are connected by a via wiring 4i.

  Therefore, in order to make the signal surface wiring 4c on the package substrate 4 the microstrip line structure 21 in all regions so as to reduce the L (inductance) of the GND, the GND layer 4f is exposed at the end of the substrate. A via wiring 4i is formed at the end of the substrate to be connected to the shield 7b of the coaxial cable 7 or the GND of the frame member 8 or to connect the GND surface layer wiring 4h and the inner GND layer 4f. 4i must be cut and exposed and connected to the GND of the coaxial cable 7 or the frame member 8.

  However, these technologies require high accuracy for positioning the surface layer / inner layer wiring of the package substrate 4, and when using a sticky material such as Cu for the wiring, it may lead to the sagging of the wiring, There is concern over manufacturing difficulties.

  On the other hand, in the structure shown in FIG. 9 and FIG. 10, the signal surface layer wiring 4c and the GND surface layer wiring 4h are arranged in the region between the outermost via wiring 4i and the coaxial cable 7 among the plurality of via wirings 4i. Are arranged on the same plane (main surface 4a), and the coaxial cable 7 and the microstrip line 4g of the package substrate 4 are connected via the coplanar line 23a.

  That is, a region outside the outermost via wiring 4i near the end of the package substrate 4 is the coplanar structure 23, and the coaxial structure 22, the coplanar structure 23, and the microstrip line structure 21 are connected. .

  Thereby, the inductance of GND can be reduced.

Further, for characteristic impedance matching in the area of the coplanar structure 23, the distance between the signal surface wiring 4c and the GND surface wiring 4h is made closer as shown in FIG. The positional deviation accuracy between the via wiring 4i and the inner GND layer 4f is equivalent to the conventional one (for example, 50
In addition, since no new technology is required, an increase in cost can be prevented.

  Therefore, by connecting the coaxial structure 22, the coplanar structure 23, and the microstrip line structure 21, it is possible to reduce the loss of the high-frequency signal and bring the characteristic impedance of the high-speed signal path close to the target value.

  Furthermore, the characteristic impedance can be made closer to the target value by reducing the distance between the signal surface wiring 4c and the GND surface wiring 4h.

  As a result, it is possible to suppress the deterioration of the high-speed signal characteristics, and to improve the electrical characteristics of the high-frequency package 1 without increasing the cost.

  Next, the high frequency package 1 of the modification shown in FIG. 11 will be described.

  The high-frequency package 1 shown in FIG. 11 uses a thin coaxial connector 24 that is a plate-like member as a relay member between the coaxial cable 7 and the microstrip line 4g of the package substrate 4.

  The thin coaxial connector 24 has a microstrip line 24c composed of a signal surface layer wiring (surface layer wiring) 24a and a GND line (ground wiring) 24b formed on both sides of the signal line wiring 24a through insulating portions. In the high frequency package 1, the signal surface wiring 24 a of the microstrip line 4 g of the package substrate 4 and the core wire 7 a of the coaxial cable 7 are electrically connected via the signal surface wiring 24 a of the microstrip line 24 c of the thin coaxial connector 24. Has been.

  That is, a signal surface layer wiring 24a is provided on the upper surface of a thin ceramic plate or the like provided with a step 24d, and GND lines 24b are provided on both sides thereof, and only the GND line 24b is provided on the lower stage, and the upper and lower GND lines are provided. 24b are connected by a surface or an inner layer via.

  Then, the coaxial cable 7 is mounted at the lower stage, the core wire 7a at the tip is placed on the upper signal wiring 24a, and the shield 7b of the coaxial cable 7 and the upper and lower GND lines 24b of the ceramic plate are connected by soldering, etc. Further, the core wire 7a of the coaxial cable 7 and the upper signal surface wiring 24a are similarly connected with solder or the like.

  Thereafter, the surface layer wiring of the ceramic plate and the surface layer wiring of the package substrate 4 are opposed to each other, and the mutual wiring is connected by solder or conductive resin. Alternatively, gold (Au) -gold (Au) crimp connection may be performed, or the ceramic plate and the package substrate 4 may be closely fixed.

  As described above, by using the thin coaxial connector 24 which is a plate member as the relay member, the high-frequency package 1 can be thinned.

  Furthermore, handling of the coaxial cable 7 becomes easy and connector repair becomes possible. Further, the thin coaxial connector 24 may be attached to both ends of the coaxial cable 7, or one end may be the thin coaxial connector 24 and the other end may be the coaxial connector 11 as shown in FIG. It is possible to attach connectors having different shapes to the connector 7. Alternatively, one end may be a thin coaxial connector 24 and the other end may be exposed at the cable end.

  The coaxial cable 7 to which the thin coaxial connector 24 is attached can be supplied only by the coaxial cable 7, or can be supplied as the high frequency package 1 to which the thin coaxial connector 24 is attached as shown in FIG. Good.

  Next, a high-frequency package 1 of a modification shown in FIG. 12 will be described.

First, in the high-frequency package 1 shown in FIG. 12, among the ball electrodes 3 of the plurality of external connection terminals, support balls 3a are provided at the four outermost corners as shown in FIG.

  This is because the weight of the coaxial connector 11 is heavy, so that when the high-frequency package 1 is mounted on a mounting substrate such as the module substrate 13, the ball electrode 3 is crushed and an electrical short occurs between adjacent ball electrodes 3. Since the support balls 3a are provided at the four corners on the outermost periphery, when the ball electrodes 3 are melted, the corner support balls 3a support the package substrate 4 and the ball electrodes 3 are crushed. It is possible to prevent the occurrence of an electrical short due to.

  The support ball 3a is formed of, for example, high melting point solder, resin or ceramic.

  In addition, the high-frequency package 1 shown in FIG. 12 has a cap 9 as a heat radiating member attached to a back surface 2 b opposite to the main surface 2 a of the semiconductor chip 2 via a heat conductive adhesive 10.

  That is, since the high-frequency semiconductor chip 2 may generate high heat when driven, the heat dissipation of the semiconductor chip 2 can be improved by attaching a heat-dissipating cap 9 or a heat diffusion plate or a heat-dissipating fin to the back surface 2b. In addition, the heat dissipation of the high-frequency package 1 can be improved and the deterioration of electrical characteristics can be prevented.

  Here, the arrangement position of the cap 9 with respect to the package substrate 4 will be described. As shown in FIGS. 12 to 14, the cap 9 is attached to the back surface 2 b of the semiconductor chip 2 with a heat conductive adhesive 10 or the like so as to cover the semiconductor chip 2. As shown in FIG. 4, it is preferable that the wiring is disposed also on the surface wiring (microstrip line 4g) such as the signal surface wiring 4c and the GND surface wiring 4h.

  That is, it is preferable that the cap 9 covers the microstrip line 4g so that the surface microstrip line 4g does not receive noise due to external electromagnetic waves or the like.

  Therefore, it is preferable to cover the semiconductor chip 2 and the surface layer wiring to some extent so as to prevent the entry of electromagnetic waves from the outside. However, the cap 9 and the surface layer wirings such as the signal surface layer wiring 4c and the GND surface layer wiring 4h must be insulated.

  In view of this, in the package substrate 4 of the first embodiment, as shown in FIG. 17, an opening (a meat escape portion) 9 a is formed in the leg 9 b on the surface layer wiring of the cap 9, and the leg of the cap 9 The cap shape is such that 9b does not come into contact with the surface wiring.

  20 and 22 show details of the positional relationship between the opening 9a of the leg 9b of the cap 9, and the signal surface wiring 4c and the GND surface wiring 4h of the package substrate 4. FIG. That is, the leg portion 9b of the cap 9 opens as an opening portion 9a up to the outer side of the both sides of the GND surface layer wiring 4h so as not to contact the signal surface layer wiring 4c and the GND surface layer wiring 4h.

  Further, the portions other than the connection area of the signal surface wiring 4c, which is the surface wiring of the package substrate 4, with the coaxial cable 7 are insulating thin films (non-conductive thin films) made of resin or the like as shown in FIG. It is covered with a certain solder resist 4j (the same applies to the GND surface layer wiring 4h). The solder resist 4j has an insulating function and also has a function of preventing a solder flow for the solder connection 31 of the coaxial cable 7.

  Therefore, since the opening 9a that is the flare escape portion of the cap 9 and the solder resist 4j that is an insulating thin film are formed on the surface layer wiring, it is possible to prevent the surface layer wiring and the cap 9 from contacting each other.

  Note that, as shown in FIGS. 17 and 18, the cap 9 is formed with a cutout portion 9 c that is a flesh escape portion that does not come into contact with the surface layer wiring at corners and side portions.

  Further, since the cap 9 also needs a shielding effect, as shown in FIG. 19, the entire surface of the base material 9d made of a copper alloy or the like is covered with a chromium-based conductive film 9e, and only the outer surface thereof is covered. However, it is covered with a non-conductive film 9f so as to prevent an electrical short circuit with other components.

  Such a cap 9 is attached to the same layer as the signal surface wiring 4c and the GND surface wiring 4h formed on the main surface 4a of the package substrate 4 as shown in FIGS. Note that the base electrode layer of the solder bump electrode 5 is the same layer.

  Further, in the portion where the opening portion 9a of the leg portion 9b of the cap 9 is not formed, the leg portion 9b is placed inside the package substrate 4 through the conductive material 25 in order to enhance the shielding effect as shown in FIG. It is connected to the GND layer 4f via the via wiring 4i, and the cap 9 itself is electrically connected to the GND layer 4f inside the package substrate 4 and the GND surface layer wiring 4h.

  As a result, the periphery of the solder bump electrode 5 for the high frequency signal is surrounded by the GND potential, and the shielding effect by the cap 9 can be enhanced.

  Further, as shown in FIG. 22, the solder bump electrode 5 connected to the high-frequency signal solder bump electrode 5, that is, the signal surface layer wiring 4c, is arranged at substantially the center of the side of the outermost solder bump electrode 5 row. The solder bump electrode 5 is preferably used, and the coaxial connector 11 connected to the solder bump electrode 5 via the signal surface wiring 4c is also preferably arranged at a substantially central portion of the side.

  As a result, the microstrip line 4g can be shortened, high-speed signal transmission can be realized with the loss of high frequency characteristics minimized, and noise on the microstrip line 4g can be reduced.

  Next, the high-frequency package 1 of the modification shown in FIG. 23 has a structure in which a cap 9 is attached to the high-frequency package 1 using the thin coaxial connector 24 shown in FIG. 11, and the high-frequency package 1 shown in FIG. For example, both the thinning and heat dissipation of the high-frequency package 1 can be improved.

  Further, in the high-frequency package 1 of the modification shown in FIG. 24, a heat dissipation block (heat dissipation member) 26 is further attached to the surface of the cap 9 attached to the back surface 2 b of the semiconductor chip 2 via the heat conductive adhesive 10. Therefore, the heat dissipation of the high-frequency package 1 can be further improved.

  25 shows a structure in which a second semiconductor chip 27 is further mounted on the package substrate 4 in addition to the semiconductor chip 2, and a cap 9 that covers both chips is provided. It is attached.

  Here, a signal is input from the semiconductor chip 2 connected to the coaxial cable 7 via the surface microstrip line 4g to the second semiconductor chip 27 via the internal signal wiring 4d of the package substrate 4, and A signal is transmitted from the solder bump electrode 5 of the second semiconductor chip 27 to the ball electrode 3 which is an external connection terminal via the internal signal wiring 4d.

  In addition, the high-frequency package 1 of the modified example shown in FIGS. 26 and 27 is one in which a balancer 28 is attached to the frame member 8. The balancer 28 functions to adjust the center of gravity of the package so that the high frequency package 1 does not tilt when the high frequency package 1 is mounted on the board.

  FIG. 26 shows the balancer 28 fixed to the frame member 8 via the screw member 29. FIG. 27 shows a groove formed in the balancer 28 and this groove is fitted to the frame member 8 so that the balancer 28 is fitted. Is attached to the frame member 8.

26 and 27, the center of gravity of the package is adjusted by the balancer 28 so that the high-frequency package 1 does not tilt when the board is mounted.

  Next, arrangement positions of the package substrate 4 and the semiconductor chip 2 will be described.

  In the high frequency package 1, the semiconductor chip 2 is preferably arranged on the package substrate 4 in a region as close to the coaxial cable 7 as possible.

  That is, when a high-frequency signal is transmitted from the coaxial cable 7 to the semiconductor chip 2 via the microstrip line 4g on the surface layer of the package substrate 4, if the path of the microstrip line 4g is long, noise is applied and the high-frequency characteristics are degraded. Therefore, in order to prevent this, it is preferable to dispose the semiconductor chip 2 so as to be offset from the central portion of the package substrate 4 closer to the coaxial cable 7, and as close to the coaxial cable 7 as possible.

  Thereby, the length of the microstrip line 4g can be shortened, and it is possible to prevent the high frequency characteristics from being deteriorated due to noise.

  The high-frequency package 1 shown in FIG. 13 is a case where one semiconductor chip 2 is mounted on a package substrate 4, and the semiconductor chip 2 is disposed closer to the coaxial connector 11 than the central portion of the package substrate 4. By fitting the coaxial cable 7 to the connector 11, the semiconductor chip 2 is arranged closer to the coaxial cable 7 than the central portion.

  28 and 29 show a case where the high-frequency semiconductor chip 2 and the low-frequency second semiconductor chip 27 are mounted on the package substrate 4. The high-frequency semiconductor chip 2 is coaxial from the center of the package substrate 4. It is arranged closer to the connector 11, is located closer to the coaxial connector 11 than the low-frequency second semiconductor chip 27, and two coaxial connectors 11 are attached correspondingly to one semiconductor chip 2. It is what has been.

  FIG. 30 is a modified example of the structure of FIG. 28, in which the arrangement combination of the two coaxial connectors 11 is changed.

  FIGS. 31 and 32 each show a case where one semiconductor chip 2 is mounted on the package substrate 4, and FIG. 31 shows a case where two coaxial connectors 11 are provided on the same side. Is disposed closer to the coaxial connector 11 than the central portion.

  Also in FIG. 32, the semiconductor chip 2 is arranged closer to the coaxial connector 11 than the center portion, but the two coaxial connectors 11 are arranged symmetrically facing two opposite sides.

  In the high-frequency package 1 shown in FIGS. 33 and 34, one semiconductor chip 2 is disposed closer to the coaxial connector 11 than the central portion, and the coaxial connector 11 is provided on the nearest side correspondingly. Further, a plurality of chip capacitors 30 are mounted around the semiconductor chip 2 on the main surface 4 a of the package substrate 4.

  That is, since the semiconductor chip 2 is arranged closer to the coaxial connector 11 than the center portion, a plurality of chip capacitors 30 and the like can be mounted in an empty space on the opposite side of the semiconductor chip 2.

  On the other hand, in the high frequency package 1 shown in FIGS. 35 and 36, one semiconductor chip 2 is disposed closer to the coaxial connector 11 than the central portion, and a plurality of chip-corresponding regions on the back surface 4 b of the package substrate 4 are provided. In the high-frequency package 1 shown in FIGS. 37 and 38, one semiconductor chip 2 is disposed closer to the coaxial connector 11 than the center portion and the package substrate 4 is mounted. A plurality of chip capacitors 30 are mounted in a recess 41 that is a cavity formed in the chip corresponding area of the back surface 4b.

  Any high frequency package 1 shown in FIGS. 28 to 38 can be reduced in size, thickness, and cost.

(Embodiment 2)
39 is a cross-sectional view showing the structure of the semiconductor device (high-frequency package) according to the second embodiment of the present invention. FIGS. 40 and 41 are cross-sectional views showing the structure of a high-frequency package according to a modification of the second embodiment of the present invention. 42 is a cross-sectional view showing an example of a cap mounting state in the assembly of the high-frequency package shown in FIG. 41, and FIG. 43 is a partial cross-sectional view showing an example of the connection state of the auxiliary board and the coaxial cable in the assembly of the high-frequency package shown in FIG. 44 is a partial cross-sectional view showing an example of a testing state in the assembly of the high-frequency package shown in FIG. 41, and FIG. 45 is a partial cross-sectional view showing an example of the structure after the assembly of the high-frequency package shown in FIG.

  The semiconductor device shown in FIG. 39 of the second embodiment is a high-frequency semiconductor package for optical communication having a coaxial cable 7 as in the high-frequency package 1 of the first embodiment. The coaxial cable 7 is not attached via the coaxial connector 11, or the coaxial cable 7 is directly attached to the package substrate 4 which is a chip carrier. Instead, the coaxial cable 7 is an optical module 14 shown in FIG. The module substrate 13 is connected to the module substrate 13 of the (semiconductor module device), and the module substrate 13 is connected to the package substrate 4 via a protruding electrode.

  Therefore, the module substrate 13 is used as a relay member for transmitting a high-frequency signal from the coaxial cable 7 to the package substrate 4, and the signal substrate surface wiring is also provided on the surface of the main surface 13a of the module substrate 13. A microstrip line 13g including a (surface layer wiring) 13c and a GND layer (ground conductor layer) 13f formed inside through the signal surface layer wiring 13c and the insulating layer 13e is formed.

  Therefore, the signal surface wiring 4c of the microstrip line 4g of the package substrate 4 and the core wire 7a of the coaxial cable 7 are connected via the signal surface wiring 13c of the microstrip line 13g of the module substrate 13.

  That is, since the thin ball electrode 34 which is an external connection terminal is formed on the main surface 4a on the flip chip connection side of the package substrate 4, the main surface 4a of the package substrate 4 and the main surface 13a of the module substrate 13 are opposed to each other. Thus, the signal surface wiring 4c of the package substrate 4 and the signal surface wiring 13c of the module substrate 13 can be connected via the thin ball electrode 34 made of solder or the like. The microstrip line 4 g of the package substrate 4 and the microstrip line 13 g of the module substrate 13 are connected via the thin ball electrode 34.

  Accordingly, the high-frequency package 1 of the second embodiment also directly receives a high-frequency (for example, 40 Gbps) signal from the coaxial cable 7 through the signal surface wiring 13c of the module substrate 13 and the thin ball electrode 34 and directly into the semiconductor chip 2. The high-frequency signal can be transmitted to all the surface layers of the package substrate 4 through the module substrate 13 only by the microstrip line.

  Thus, as with the high frequency package 1 of the first embodiment, the high frequency signal is transmitted only through the microstrip lines on the surface layer of the module substrate 13 and the package substrate 4 without via vias and the like, thereby improving the frequency characteristics. High frequency signals can be transmitted without loss.

  The low-frequency signal is sent to the outside through the internal signal wiring 4 d of the package substrate 4, the thin ball electrode 34, and the internal signal wiring 13 d of the module substrate 13.

  Further, the semiconductor chip 2 is disposed in the opening 13h of the module substrate 13 in a state of being flip-chip connected to the package substrate 4, and further, a heat dissipation block is provided on the back surface 2b of the semiconductor chip 2 via a heat conductive adhesive 10. A (heat radiating member) 26 is attached, and therefore, the heat radiating block 26 is disposed on the back surface 13 b side of the module substrate 13.

  In the high frequency package 1 of the second embodiment, the module substrate 13 is interposed between the coaxial cable 7 and the package substrate 4 without directly attaching the coaxial cable 7 to the package substrate 4. A structure in which the semiconductor chip 2 is flip-chip connected to the package substrate 4 can be handled as a product.

  In this case, the coaxial cable 7 is connected to the module substrate 13 on the user side, and the package substrate 4 and the module substrate 13 are connected on the user side via the thin ball electrode 34 to assemble the high-frequency package 1. .

  Thus, in the high-frequency package 1 using the module substrate 13 as a relay member, the package substrate 4 on which the semiconductor chip 2 is mounted and the module substrate 13 to which the coaxial cable 7 is connected are assembled separately and then both are connected. , Each yield can be carved out.

  That is, the yield risk can be divided between the assembly of the semiconductor chip 2 and the assembly of the coaxial cable 7, and the yield of the structure after connecting both assemblies can be improved.

  Moreover, in the high frequency package 1 using the module substrate 13, since the expensive coaxial connector 11 is not used, the cost of the high frequency package 1 can be reduced and the thickness can be reduced.

  Further, since all the external connection terminals are provided on the main surface 4a on the flip chip connection side of the package substrate 4, a selection test can be easily performed when selecting the high-frequency semiconductor chip 2 of 40 Gbps. .

  That is, since all external connection terminals of high frequency and low frequency are provided on one surface (main surface 4a) of the package substrate 4, it is easy to contact the probe needle during the sorting test, and it is complicated. The test can be performed without using a jig having a simple shape.

  As a result, the test time can be shortened.

  40, the cap 9 is first attached to the back surface 2b of the semiconductor chip 2 via the heat conductive adhesive 10, and the surface of the cap 9 is further bonded to the heat conductive adhesive. A heat dissipation block 26 is attached via the agent 10.

  In this case, the cap 9 is formed with an opening (a meat escape portion) 9a that insulates the cap 9 from the surface layer wiring such as the signal surface wiring 4c.

  Furthermore, in the high frequency package 1 shown in FIG. 40, not only the cap 9 but also the heat dissipation block 26 is provided on the cap 9, so that the heat dissipation of the high frequency package 1 can be further improved and the deterioration of the high frequency characteristics is prevented. be able to.

  Next, the high-frequency package 1 of the modification shown in FIG. 41 is the case where the relay member that connects the coaxial cable 7 and the signal surface wiring 4c of the package substrate 4 is the auxiliary substrate 32 that is the second package substrate, The auxiliary substrate 32 has a signal surface layer wiring (surface layer wiring) 32c on the surface layer of the main surface 32a, and a GND layer (grounding conductor layer) formed inside through the signal surface layer wiring 32c and the insulating layer 32e. ) 32f is formed as a microstrip line 32g.

  Therefore, the signal surface wiring 4c of the microstrip line 4g of the package substrate 4 and the core wire 7a of the coaxial cable 7 are connected via the signal surface wiring 32c of the microstrip line 32g of the auxiliary substrate 32.

  That is, the thin ball electrode 34 as an external connection terminal is formed on the main surface 4a on the flip chip connection side of the package substrate 4, and the main surface 4a of the package substrate 4 and the main surface 32a of the auxiliary substrate 32 are opposed to each other. Accordingly, the signal surface wiring 4c of the package substrate 4 and the signal surface wiring 32c of the auxiliary substrate 32 can be connected via the thin ball electrode 34 made of solder or the like. The microstrip line 4 g of the package substrate 4 and the microstrip line 32 g of the auxiliary substrate 32 are connected via the ball electrode 34.

  Therefore, the high-frequency package 1 of the modified example shown in FIG. 41 also uses a semiconductor device that directly receives a high-frequency (for example, 40 Gbps) signal from the coaxial cable 7 via the signal surface wiring 32c of the auxiliary substrate 32 and the thin ball electrode 34. A high-frequency signal can be transmitted to the entire surface of the package substrate 4 through the auxiliary substrate 32 only by the microstrip line.

  Thus, similar to the high frequency package 1 of the first embodiment, the high frequency signal is transmitted only by the microstrip line on the surface layer of the auxiliary substrate 32 and the package substrate 4 without via vias and the like, so that the frequency characteristics are improved. High frequency signals can be transmitted without loss.

  The signal on the low frequency side passes through the internal signal wiring 4d of the package substrate 4, the thin ball electrode 34, the internal signal wiring 32d of the auxiliary substrate 32, and the pin member (connection terminal) 33. Is transmitted to the module substrate 13 or the like.

  In addition, the semiconductor chip 2 is disposed in the opening 32 h of the auxiliary substrate 32 in a state of being flip-chip connected to the package substrate 4, and the cap 9 is disposed on the back surface 2 b of the semiconductor chip 2 via the heat conductive adhesive 10. Further, a heat radiating block (heat radiating member) 26 is attached to the surface of the cap 9. Therefore, the heat radiating block 26 is disposed on the back surface 32 b side of the auxiliary substrate 32.

  In the high-frequency package 1 according to the second embodiment, the components on the coaxial cable 7 side and the components on the semiconductor chip 2 side are separately selected, and non-defective products are connected to each other, thereby improving the yield as the high-frequency package 1. Can be achieved.

  That is, the chip side structure 36 shown in FIG. 42 in which the semiconductor chip 2 to which the cap 9 is attached is flip-chip connected, and the cable side structure 37 shown in FIG. 43 in which the coaxial cable 7 is connected to the auxiliary substrate 32 by the solder connection 31. Are assembled, and each structure is screened separately.

  As a result, since both structures include microstrip lines, high frequency tests can be performed as respective components, and the yields can be separated by connecting non-defective products. As a result, the yield risk can be divided between the chip-side structure 36 and the cable-side structure 37, and the yield of the high-frequency package 1 shown in FIG. 41 in which both structures are connected can be improved.

  Furthermore, the chip-side structure 36 and the cable-side structure 37 can be distributed as individual parts, and each can be obtained as a part.

  In addition, since all the external connection terminals are provided on the main surface 4a on the flip chip connection side of the package substrate 4, a sorting test can be easily performed when sorting the high-frequency semiconductor chip 2 of 40 Gbps. .

  That is, since all external connection terminals of high frequency and low frequency are provided on one surface (main surface 4a) of the package substrate 4, it is easy to contact the probe needle during the sorting test, and it is complicated. The test can be performed without using a jig having a simple shape.

  As a result, the test time can be shortened.

  Note that the auxiliary substrate 32 can be used as a testing substrate 35 as shown in FIG. 44, and can also be used as a socket in a sorting test of the package substrate 4.

  At this time, the package substrate 4 and the testing substrate 35 are brought into electrical contact via an interposer 35a such as an ACF (Anisotropic Conductive Film), and a test is performed by transmitting a signal to the outside via a pin member 35b.

  As in the auxiliary substrate 32, the testing substrate 35 includes a signal surface wiring 35c, an internal signal wiring 35d, a signal surface wiring 35c and a GND layer 35f disposed via an insulating layer 35e and a microstrip line. 35 g is formed.

  The chip-side structure 36 shown in FIG. 42 and the cable-side structure 37 shown in FIG. 43 are separately selected and tested, and after obtaining good products, the chip-side structure 36 and the cable-side structure 37 are separated. What is connected and assembled is a high-frequency package 1 of a modification of the second embodiment shown in FIG.

  Further, the heat conductive adhesive 10 is applied to the surface of the cap 9, and the heat dissipation block 26 is attached via the heat conductive adhesive 10, and the high frequency package 1 is connected to the module substrate of the optical module 14 via the pin member 33. What is mounted on 13 is the mounting structure shown in FIG.

  In the high-frequency package 1 shown in FIG. 41, a cap 9 is first attached to the back surface 2b of the semiconductor chip 2 via a heat conductive adhesive 10, and the heat conductive adhesive 10 is further applied to the surface of the cap 9. In the optical module 14, the module case 15 shares the role of the heat dissipation block 26, and the cap 9 includes the cap 9 and surface layer wiring such as the signal surface wiring 4c. An opening (a meat escape portion) 9a that insulates is formed.

  Therefore, also in the high frequency package 1 shown in FIG. 41, not only the cap 9 but also the cap 9 is provided with the heat dissipation block 26 (module case 15), so that the heat dissipation of the high frequency package 1 can be further improved. Deterioration of high frequency characteristics can be prevented.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments of the invention. However, the present invention is not limited to the embodiments of the invention, and various modifications can be made without departing from the scope of the invention. It goes without saying that it is possible.

  For example, in the first embodiment, the case where the semiconductor device is a ball grid array type semiconductor package has been described. However, the semiconductor device has a structure in which a plurality of external connection terminals are arranged on the surface of the package substrate. For example, an LGA (Land Grid Array) may be used.

  Further, in the first and second embodiments, the case where the semiconductor chip 2 is flip-chip connected to the package substrate 4 has been described, but the electrical connection method between the semiconductor chip 2 and the package substrate 4 is flip-chip. Not only the connection but also ribbon bonding using a flat metal wire may be used.

  The present invention is suitable for an electronic device using a coaxial cable.

1 High-frequency package (semiconductor device)
2 Semiconductor chip 2a Main surface 2b Back surface 3 Ball electrode (external connection terminal)
3a Support ball 4 Package board (wiring board)
4a Main surface 4b Back surface 4c Signal surface wiring (surface wiring)
4d Internal signal wiring 4e Insulating layer 4f GND layer (grounding conductor layer)
4g Microstrip line 4h Surface wiring for GND (surface wiring for grounding)
4i Via wiring 4j Solder resist 4k Step difference 4l Recess 5 Solder bump electrode 6 Underfill resin 7 Coaxial cable 7a Core wire 7b Shield 8 Frame member 9 Cap (heat dissipation member)
9a Opening (meat escape)
9b Leg 9c Notch (meat relief)
9d Base material 9e Conductive film 9f Non-conductive film 10 Thermally conductive adhesive 11 Coaxial connector (relay member)
12 Glass beads 13 Module substrate (relay member)
13a Main surface 13b Back surface 13c Signal surface layer wiring (surface layer wiring)
13d Internal signal wiring 13e Insulating layer 13f GND layer (grounding conductor layer)
13g Microstrip line 13h Opening 14 Optical module (semiconductor module device)
DESCRIPTION OF SYMBOLS 15 Module case 16 Fin 17 Module connector 18 Wind 19 Amplifier element 20 Photoelectric converter 21 Microstrip line structure 22 Coaxial structure 23 Coplanar structure 23a Coplanar line 24 Thin coaxial connector (plate-shaped member)
24a Signal surface wiring (surface wiring)
24b GND line (ground wiring)
24c Microstrip line 24d Step 25 Conductive material 26 Heat radiation block (heat radiation member)
27 Second semiconductor chip 28 Balancer 29 Screw member 30 Chip capacitor 31 Solder connection 32 Auxiliary substrate (relay member)
32a Main surface 32b Back surface 32c Signal surface layer wiring (surface layer wiring)
32d Internal signal wiring 32e Insulating layer 32f GND layer (grounding conductor layer)
32g microstrip line 32h opening 33 pin member (terminal for connection)
34 Thin ball electrode 35 Testing substrate 35a Interposer 35b Pin member 35c Signal surface layer wiring 35d Internal signal wiring 35e Insulating layer 35f GND layer 35g Microstrip line 36 Chip side structure 37 Cable side structure

Claims (6)

A semiconductor device incorporated in a semiconductor module device,
A wiring board having a surface layer wiring, and a ground conductor layer formed inside through the surface layer wiring and the insulating layer;
A semiconductor chip mounted in electrical connection with the wiring board;
Coaxial cable,
Electrically connecting the surface layer wiring of the wiring board and the coaxial cable, and having a signal surface layer wiring and a relay member provided with ground wiring formed on both sides of the wiring layer through insulating portions;
The surface layer wiring of the wiring board and the coaxial cable are connected via the signal surface layer wiring of the relay member,
The relay member is a module substrate of the semiconductor module device on which the semiconductor device is mounted, and includes a surface layer wiring and a ground conductor layer formed therein via an insulating layer, and the wiring of the semiconductor device A semiconductor device, wherein a surface layer wiring of a substrate and a core wire of the coaxial cable are connected via a surface layer wiring of the module substrate.   2. The semiconductor device according to claim 1, wherein an external connection terminal is formed on a main surface of the wiring board on a flip chip connection side, and a surface layer wiring of the wiring board and a surface layer wiring of the module board are connected via the external connection terminal. Is connected to the semiconductor device. A semiconductor device incorporated in a semiconductor module device,
A wiring board having a surface layer wiring, and a ground conductor layer formed inside through the surface layer wiring and the insulating layer;
A semiconductor chip mounted in electrical connection with the wiring board;
Coaxial cable,
Electrically connecting the surface layer wiring of the wiring board and the coaxial cable, and having a signal surface layer wiring and a relay member provided with ground wiring formed on both sides of the wiring layer through insulating portions;
The surface layer wiring of the wiring board and the coaxial cable are connected via the signal surface layer wiring of the relay member,
The relay member is an auxiliary board having a surface layer wiring and a ground conductor layer formed therein via an insulating layer and a connection terminal connected to the module board of the semiconductor module device. The semiconductor device, wherein a surface layer wiring of the wiring substrate of the semiconductor device and a core wire of the coaxial cable are electrically connected via a surface layer wiring of the auxiliary substrate.   4. The semiconductor device according to claim 3, wherein an external connection terminal is formed on a main surface of the wiring substrate on a flip chip connection side, and a surface layer wiring of the wiring substrate and a surface layer wiring of the auxiliary substrate are connected via the external connection terminal. Is connected to the semiconductor device. A semiconductor device incorporated in a semiconductor module device,
A wiring board having a surface layer wiring, and a ground conductor layer formed inside through the surface layer wiring and the insulating layer;
A semiconductor chip mounted in electrical connection with the wiring board;
Coaxial cable,
Electrically connecting the surface layer wiring of the wiring board and the coaxial cable, and having a signal surface layer wiring and a relay member provided with ground wiring formed on both sides of the wiring layer through insulating portions;
The surface layer wiring of the wiring board and the coaxial cable are connected via the signal surface layer wiring of the relay member,
A semiconductor device, wherein the semiconductor chip is flip-chip connected to the wiring substrate via a solder bump electrode, and a heat dissipation member is attached to the back surface of the semiconductor chip. A semiconductor device incorporated in a semiconductor module device,
A wiring board having a surface layer wiring, and a ground conductor layer formed inside through the surface layer wiring and the insulating layer;
A semiconductor chip mounted in electrical connection with the wiring board;
Coaxial cable,
Electrically connecting the surface layer wiring of the wiring board and the coaxial cable, and having a signal surface layer wiring and a relay member provided with ground wiring formed on both sides of the wiring layer through insulating portions;
The surface layer wiring of the wiring board and the coaxial cable are connected via the signal surface layer wiring of the relay member,
The semiconductor chip is flip-chip connected to the wiring substrate via a solder bump electrode, and a heat dissipation member partially disposed on the surface layer wiring is attached to the back surface of the semiconductor chip. A semiconductor device characterized in that a meat escape portion is formed that insulates this from the surface wiring.

Images