JP2003174114A - Semiconductor circuit board and semiconductor device - Google Patents
Semiconductor circuit board and semiconductor deviceInfo
- Publication number
- JP2003174114A JP2003174114A JP2001374496A JP2001374496A JP2003174114A JP 2003174114 A JP2003174114 A JP 2003174114A JP 2001374496 A JP2001374496 A JP 2001374496A JP 2001374496 A JP2001374496 A JP 2001374496A JP 2003174114 A JP2003174114 A JP 2003174114A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- semiconductor
- circuit board
- convex
- solder
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 115
- 229910000679 solder Inorganic materials 0.000 claims abstract description 28
- 239000000758 substrate Substances 0.000 claims description 28
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 30
- 229910052802 copper Inorganic materials 0.000 abstract description 25
- 239000010949 copper Substances 0.000 abstract description 25
- 239000011800 void material Substances 0.000 abstract description 9
- 229910052751 metal Inorganic materials 0.000 description 8
- 239000002184 metal Substances 0.000 description 8
- 239000000919 ceramic Substances 0.000 description 6
- 239000011889 copper foil Substances 0.000 description 5
- 229920001721 polyimide Polymers 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 230000002093 peripheral effect Effects 0.000 description 4
- 239000004642 Polyimide Substances 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 230000035882 stress Effects 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/10155—Shape being other than a cuboid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Die Bonding (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】この発明は、反った状態の半
導体チップを、反った状態そのままで接合可能とした半
導体回路基板およびその半導体基板を用いた半導体装置
に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor circuit board capable of joining a warped semiconductor chip in the warped state, and a semiconductor device using the semiconductor substrate.
【０００２】[0002]
【従来の技術】図６は、半導体チップを固着した従来の
半導体回路基板の要部断面図である。絶縁基板１と導電
部である銅電極２からなる半導体回路基板に、はんだ３
を介して半導体チップ４を接合（固着）する。半導体チ
ップ４は、図８に示すように、半導体基板１００と、表
面に選択的に被覆するポリイミド膜などの絶縁膜１０１
と、裏面にはＡｌ／Ｎｉ／Ａｕの三層金属膜などの裏面
金属膜１０２が形成される。これらの絶縁膜１０１や裏
面金属膜１０２と、半導体基板１００との熱膨張係数の
差と、これらの膜の膜厚により、半導体チップ４が凸状
に反ったり、凹状に反ったりする。１０ｍｍ□程度で、
５０μｍから１００μｍ程度の厚みの半導体チップ４で
は、その反り量は、０．１ｍｍ前後から０．２ｍｍ前後
にもなる。通常、ポリイミド膜や三層金属膜は、半導体
基板１００より熱膨張係数が大きいために、表面にポリ
イミドなどの絶縁膜１０１を被覆すると、表面が凹状に
反り、裏面に三層金属膜などの金属膜１０２を被覆する
と、裏面が凹状に、つまり、表面が凸状に反る。ポリイ
ミドより三層金属膜の方が熱膨張係数が大きいために、
通常は表面が凸状になるように反る。2. Description of the Related Art FIG. 6 is a cross-sectional view of a main part of a conventional semiconductor circuit board to which a semiconductor chip is fixed. Solder 3 on the semiconductor circuit board consisting of the insulating substrate 1 and the copper electrode 2 which is the conductive part.
The semiconductor chip 4 is bonded (fixed) via the. As shown in FIG. 8, the semiconductor chip 4 includes a semiconductor substrate 100 and an insulating film 101 such as a polyimide film that selectively covers the surface.
Then, a back surface metal film 102 such as an Al / Ni / Au three-layer metal film is formed on the back surface. Depending on the difference in thermal expansion coefficient between the insulating film 101 and the back surface metal film 102 and the semiconductor substrate 100 and the film thickness of these films, the semiconductor chip 4 may be warped in a convex shape or a concave shape. With about 10 mm □,
In the semiconductor chip 4 having a thickness of about 50 μm to 100 μm, the warp amount is about 0.1 mm to about 0.2 mm. Generally, since a polyimide film or a three-layer metal film has a larger thermal expansion coefficient than the semiconductor substrate 100, when the surface is covered with the insulating film 101 such as polyimide, the surface warps concavely and the back surface is made of a metal such as a three-layer metal film. When the film 102 is covered, the back surface warps concavely, that is, the surface warps convexly. Since the three-layer metal film has a larger coefficient of thermal expansion than polyimide,
Usually, the surface is warped so that it becomes convex.
【０００３】図６に示すように凸状に反った場合には、
銅電極２と半導体チップ４の間のはんだ３の中央部に空
隙５ができる場合がある。これは、凸状に反った半導体
チップ４をそのままの状態で、固形やペースト状のはん
だ３上に乗せると、半導体チップ４とはんだ３とが接触
しない中央部に空気層が形成され、その状態で、真空引
きしながら、はんだを溶融し、半導体チップ４と銅電極
２を接合しても、この空気が抜けきれないために、中央
部に空隙５が形成される。When it is warped in a convex shape as shown in FIG.
A void 5 may be formed in the central portion of the solder 3 between the copper electrode 2 and the semiconductor chip 4. This is because when the semiconductor chip 4 warped in a convex shape is placed on the solid or paste-like solder 3 as it is, an air layer is formed in the central portion where the semiconductor chip 4 and the solder 3 do not come into contact with each other. Even if the solder is melted and the semiconductor chip 4 and the copper electrode 2 are joined while being evacuated, the air cannot be completely exhausted, so that the void 5 is formed in the central portion.
【０００４】また、図７に示すように、半導体チップ４
が凹状に反っている場合には、半導体チップ４の端部
に、はんだ３が付かない箇所である空隙５ａが生じ易す
い。Further, as shown in FIG. 7, the semiconductor chip 4
If the warp has a concave shape, a void 5a, which is a portion where the solder 3 does not attach, is easily formed at the end of the semiconductor chip 4.
【０００５】[0005]
【発明が解決しようとする課題】いずれの場合でも、ワ
イヤボンディングなどの強制的な加圧力が、この空隙
５、５ａに加わると、半導体チップ４を平坦にしようと
する応力が加わり、半導体チップ４には、クラックや陥
没などの損傷２０が生じることがある。また、半導体チ
ップ４を損傷なしで組み立てた場合でも、空隙５、５ａ
があると、この箇所で熱抵抗が高くなり、半導体チップ
４の温度上昇が大きくなり、パワーサイクル耐量が低下
する。In any case, when a forcing force such as wire bonding is applied to the gaps 5 and 5a, a stress for flattening the semiconductor chip 4 is added, and the semiconductor chip 4 is flattened. In some cases, damage 20 such as cracks and depressions may occur. Even when the semiconductor chip 4 is assembled without damage, the voids 5, 5a
If so, the thermal resistance increases at this location, the temperature rise of the semiconductor chip 4 increases, and the power cycle resistance decreases.
【０００６】この発明の目的は、前記の課題を解決し
て、薄い半導体チップに損傷を生じさせずに、半導体チ
ップを固着できる半導体回路基板および半導体装置を提
供することにある。An object of the present invention is to solve the above problems and provide a semiconductor circuit board and a semiconductor device which can fix a semiconductor chip without damaging the thin semiconductor chip.
【０００７】[0007]
【課題を解決するための手段】この発明の目的を達成す
るために、パターン形成された導電膜（銅電極）が、絶
縁基板に固着する半導体回路基板において、半導体チッ
プが固着する箇所の前記導電膜の表面形状を、前記半導
体チップの反りに合せた凸形もしくは凹形とする構成と
する。In order to achieve the object of the present invention, a conductive film (copper electrode) having a pattern formed thereon is fixed to an insulating substrate. The surface shape of the film is a convex shape or a concave shape according to the warp of the semiconductor chip.
【０００８】また、前記凸形もしくは凹形の形状を、前
記導電膜のみを凸形もしくは凹形とし、該導電膜と前記
絶縁基板との固着面を平坦とする。また、前記凸形もし
くは凹形の形状を、前記絶縁基板を凸形もしくは凹形と
し、該絶縁基板上に同一厚みの前記導電膜を固着すると
よい。また、前記半導体チップの周囲の導電膜に、はん
だ溜（ピット）を形成するとよい。Further, the convex or concave shape is such that only the conductive film is convex or concave, and the fixing surface between the conductive film and the insulating substrate is flat. Further, it is preferable that the insulating substrate has a convex shape or a concave shape, and the conductive film having the same thickness is fixed onto the insulating substrate. Further, it is preferable to form a solder pool (pit) on the conductive film around the semiconductor chip.
【０００９】また、前記の半導体回路基板を用いて、前
記凸形もしくは凹形の半導体固着箇所にはんだを介して
半導体チップを固着して半導体装置とする。前記のよう
に、半導体チップを接合する銅電極の表面部分を凸状ま
たは凹状にすることにより、半導体チップが凸状または
凹状に反っていても、はんだ部の空隙を生じることな
く、半導体チップ全面で銅電極と接合が可能となり、薄
い半導体チップでも高い接合信頼性が実現できる。Further, using the above semiconductor circuit board, a semiconductor chip is fixed to the convex or concave semiconductor fixing portion via solder to obtain a semiconductor device. As described above, by making the surface portion of the copper electrode that joins the semiconductor chip convex or concave, even if the semiconductor chip is warped in a convex or concave shape, a void in the solder portion does not occur and the entire surface of the semiconductor chip is formed. With this, it is possible to bond with copper electrodes, and high bonding reliability can be realized even with thin semiconductor chips.
【００１０】また、ピットを設けることで、余分なはん
だで半導体チップが端面で短絡することが防止できる。Further, by providing the pits, it is possible to prevent the semiconductor chip from being short-circuited at the end face due to excess solder.
【００１１】[0011]
【発明の実施の形態】以下の説明で、図６と同一箇所に
は同一の符号を記した。図１は、この発明の第１実施例
の半導体回路基板の要部断面図である。この図は、１０
０μｍ以下の厚みの半導体チップ４を固着した断面図
で、半導体チップ４の裏面とはんだ３を介して接する銅
電極２の表面が凸状となっている。前記の図８に示すよ
うに、半導体チップ４は、半導体基板１００の表面にポ
リイミドなどの絶縁膜１０１、裏面にＡｌ／Ｎｉ／Ａｕ
の三層蒸着膜などの裏面金属膜１０２が形成され、通常
は表面が凸状に反っている（湾曲している）。BEST MODE FOR CARRYING OUT THE INVENTION In the following description, the same parts as those in FIG. FIG. 1 is a cross-sectional view of essential parts of a semiconductor circuit board according to a first embodiment of the present invention. This figure shows 10
In the cross-sectional view in which the semiconductor chip 4 having a thickness of 0 μm or less is fixed, the surface of the copper electrode 2 that is in contact with the back surface of the semiconductor chip 4 via the solder 3 is convex. As shown in FIG. 8, the semiconductor chip 4 has an insulating film 101 made of polyimide or the like on the front surface of the semiconductor substrate 100 and Al / Ni / Au on the back surface.
The back surface metal film 102 such as the three-layer vapor deposition film is formed, and the surface is usually warped in a convex shape (curved).
【００１２】この凸状に反った半導体チップ４を、はん
だ３で接合する銅電極２の表面は、凸状に湾曲させる。
この湾曲した面は、絶縁基板１の表面に凸状部６を形成
し、その上に均一な厚みの銅電極２を形成することで得
られる。また、この湾曲した面は、半導体チップ４の平
均的な反り状態に合わせて、丁度、半導体チップ４の裏
面の凹状に反った面と接触するように、銅電極２の表面
に凸状部を形成する。The surface of the copper electrode 2 which joins the semiconductor chip 4 warped in a convex shape with the solder 3 is curved in a convex shape.
This curved surface is obtained by forming the convex portion 6 on the surface of the insulating substrate 1 and forming the copper electrode 2 having a uniform thickness on the convex portion 6. In addition, a convex portion is formed on the front surface of the copper electrode 2 so that the curved surface is in contact with the concave warped surface of the back surface of the semiconductor chip 4 in accordance with the average warped state of the semiconductor chip 4. Form.
【００１３】反った半導体チップ４は、この湾曲面に沿
ってはんだ３を介して接合される。このとき、半導体チ
ップ４が接合される下面側にある銅電極２の表面の状態
が、半導体チップ４の反りの状態と同じように作ってあ
るため、はんだ接合時に、半導体チップ４と銅電極２を
接合しているはんだ３には空隙５が生ぜず、図示しない
ワイヤーボンディングを行っても半導体チップ４を損傷
することがない。The warped semiconductor chip 4 is bonded along the curved surface via the solder 3. At this time, since the state of the surface of the copper electrode 2 on the lower surface side to which the semiconductor chip 4 is joined is made to be the same as the warped state of the semiconductor chip 4, the semiconductor chip 4 and the copper electrode 2 are joined at the time of solder joining. A void 5 does not occur in the solder 3 that is joined to the semiconductor chip 4, and the semiconductor chip 4 is not damaged even if wire bonding (not shown) is performed.
【００１４】さらに、半導体チップ４の全面積で接合し
ているのでパワーサイクル耐量も向上する。図１に示す
半導体基板は、絶縁基板１の表面の凸形状の対となる下
面が凹状の金型と表面が平らな金型の２つを用い、原料
であるセラミックス粉をこの２つの金型の間に所定の厚
さの回路基板となるよう分量を置いた後、所定圧力・所
定温度にて焼成し、形成する。その後、表面が凹状にな
ったセラミックス板の上に乗せ、所定圧力・所定温度に
て接合する。セラミックス板と銅箔の接合には、一般的
にアルミナや窒化アルミなどが接合材として用いられ
る。Further, since the semiconductor chip 4 is bonded over the entire area, the power cycle resistance is also improved. The semiconductor substrate shown in FIG. 1 uses two molds, one having a concave lower surface and a mold having a flat surface, which form a convex pair on the surface of the insulating substrate 1. After that, a circuit board having a predetermined thickness is placed between the two and baked at a predetermined pressure and a predetermined temperature to form the circuit board. Then, it is placed on a ceramic plate having a concave surface and bonded at a predetermined pressure and a predetermined temperature. Alumina, aluminum nitride or the like is generally used as a joining material for joining the ceramic plate and the copper foil.
【００１５】図２は、この発明の第２実施例の半導体回
路基板の要部断面図である。図１との違いは土台となる
絶縁基板１には凸状部６がなく、その上部に設置される
銅電極２の表面に凸状部７を設けている点である。この
場合も図１と同様の効果が得られる。図２に示す半導体
回路基板は、上面および下面ともに平らな金型でセラミ
ックス板を作成しておき、この表面が平らなセラミック
ス板上に銅箔を乗せ、銅箔と接する面に凹状のへこみが
形成された金型面から、銅箔を乗せないもう一方のセラ
ミックス板面には平らな金型を配置氏、所定圧力・所定
温度にて銅箔とセラミックス板を接合する。こうするこ
とで、上に凸形状を持った銅電極２が形成される。FIG. 2 is a sectional view of the essential portions of a semiconductor circuit board according to the second embodiment of the present invention. The difference from FIG. 1 is that the base insulating substrate 1 does not have the convex portion 6 and the convex portion 7 is provided on the surface of the copper electrode 2 provided on the insulating substrate 1. Also in this case, the same effect as in FIG. 1 can be obtained. In the semiconductor circuit board shown in FIG. 2, a ceramic plate is prepared in advance with a flat mold on both the upper and lower surfaces, a copper foil is placed on the flat ceramic plate, and a concave dent is formed on the surface in contact with the copper foil. From the formed mold surface, a flat mold is placed on the other ceramic plate surface on which the copper foil is not placed, and the copper foil and the ceramic plate are bonded at a predetermined pressure and a predetermined temperature. By doing so, the copper electrode 2 having a convex shape is formed.
【００１６】図３は、この発明の第３実施例の半導体回
路基板の要部断面図である。この半導体回路基板は、図
１で示した絶縁基板１および銅電極２の凸状部６を、凹
状にしたものである。これは、半導体チップ４が凹状に
反っている場合に適用する。この場合も図１と同様の効
果が得られる。図３に示す半導体回路基板は、図１で示
した半導体回路基板の製作方法と同様に、絶縁基板１の
表面の凹形状と対となる下面が凹状の金型を用いること
で製作される。FIG. 3 is a cross-sectional view of essential parts of a semiconductor circuit board according to a third embodiment of the present invention. In this semiconductor circuit board, the convex portion 6 of the insulating substrate 1 and the copper electrode 2 shown in FIG. 1 is made concave. This is applied when the semiconductor chip 4 is warped in a concave shape. Also in this case, the same effect as in FIG. 1 can be obtained. The semiconductor circuit board shown in FIG. 3 is manufactured by using a mold having a concave lower surface that is paired with the concave shape of the surface of the insulating substrate 1, similarly to the method of manufacturing the semiconductor circuit board shown in FIG.
【００１７】図４は、この発明の第４実施例の半導体回
路基板の要部断面図である。この半導体回路基板は、図
２で示した銅電極２の凸状部７を、凹状にしたものであ
る。この場合にも図２と同様の効果が得られる。図４に
示す半導体回路基板は、図２で示した半導体回路基板の
製作方法と同様に、絶縁基板１の表面の凸形状と対とな
る下面が凸状の金型を用いることで製作される。FIG. 4 is a cross-sectional view of essential parts of a semiconductor circuit board according to a fourth embodiment of the present invention. In this semiconductor circuit board, the convex portion 7 of the copper electrode 2 shown in FIG. 2 is formed in a concave shape. In this case, the same effect as that of FIG. 2 can be obtained. The semiconductor circuit board shown in FIG. 4 is manufactured by using a mold having a convex lower surface which is paired with the convex shape of the surface of the insulating substrate 1, similarly to the method of manufacturing the semiconductor circuit substrate shown in FIG. .
【００１８】図５は、この発明の第５実施例の半導体回
路基板の要部断面図である。この半導体回路基板は、基
本的には図１の半導体回路基板と同じ構成であるが、半
導体チップ４を接合する部位の外周部に、余分なはんだ
３ａを流し込むピット１０（はんだ溜）を設置してあ
る。このピット１０は、余分なはんだ３ａが半導体チッ
プ４の外周部及びチップ表面まではみ出し、図に点線で
示すように、外周部で短絡するのを防止する働きがあ
り、信頼性を高めることができる。FIG. 5 is a cross-sectional view of essential parts of a semiconductor circuit board according to a fifth embodiment of the present invention. This semiconductor circuit board has basically the same configuration as that of the semiconductor circuit board of FIG. 1, but a pit 10 (solder reservoir) for pouring extra solder 3a is provided on the outer peripheral portion of the portion to which the semiconductor chip 4 is joined. There is. The pits 10 have a function of preventing excess solder 3a from protruding to the outer peripheral portion and the chip surface of the semiconductor chip 4 and short-circuiting in the outer peripheral portion as shown by a dotted line in the figure, and reliability can be improved. .
【００１９】このピット１０は、半導体チップ４を接合
する部位の外周部に設置するが、その深さ・幅の寸法は
半導体チップ４の表面積・はんだの量により様々で、は
み出したはんだがピット１０から溢れ出ないように設計
する。また、このピット１０は、銅電極２の表面にのみ
設けても良いし、さらに深いピットが必要ならば、図示
したように、銅電極２の下部に位置する絶縁基板１まで
達しても構わない。The pit 10 is provided on the outer peripheral portion of the portion to which the semiconductor chip 4 is joined. The depth and width of the pit 10 vary depending on the surface area of the semiconductor chip 4 and the amount of solder. Design so that it does not overflow. Further, the pit 10 may be provided only on the surface of the copper electrode 2, or if a deeper pit is required, as shown in the figure, it may reach the insulating substrate 1 located below the copper electrode 2. .
【００２０】また、このピットは、図２から図４にも設
けることで、同様の効果が得られる。By providing this pit also in FIGS. 2 to 4, the same effect can be obtained.
【００２１】[0021]
【発明の効果】この発明によると、半導体チップの反り
に合わせて銅電極を湾曲させ、はんだ接合することで、
半導体チップとはんだの間に空隙ができなくなり、ワイ
ヤボンディング時の加圧力で、半導体チップの損傷を防
止できる。また、空隙がないために、熱抵抗が増大せ
ず、パワーサイクル耐量が向上する。According to the present invention, by bending the copper electrode in accordance with the warp of the semiconductor chip and soldering it,
No void is formed between the semiconductor chip and the solder, and the semiconductor chip can be prevented from being damaged by the pressure applied during wire bonding. Further, since there are no voids, the thermal resistance does not increase and the power cycle withstand capability improves.
【００２２】さらに、半導体チップを接合する銅電極又
は銅電極と絶縁基板に余剰はんだを流し込むピットを設
置することにより、チップ動作時の熱応力に対する耐量
が向上し、高い接合信頼性を得ることができる。Furthermore, by providing a copper electrode for joining the semiconductor chip or a pit for pouring the excess solder on the insulating substrate and the copper electrode, the resistance against thermal stress at the time of chip operation is improved, and high joining reliability can be obtained. it can.
【図１】この発明の第１実施例の半導体チップが固着し
た半導体回路基板の要部断面図FIG. 1 is a sectional view of an essential part of a semiconductor circuit board to which a semiconductor chip according to a first embodiment of the present invention is fixed.
【図２】この発明の第２実施例の半導体チップが固着し
た半導体回路基板の要部断面図FIG. 2 is a cross-sectional view of an essential part of a semiconductor circuit board to which a semiconductor chip according to a second embodiment of the present invention is fixed.
【図３】この発明の第３実施例の半導体チップが固着し
た半導体回路基板の要部断面図FIG. 3 is a sectional view of an essential part of a semiconductor circuit board to which a semiconductor chip according to a third embodiment of the present invention is fixed.
【図４】この発明の第４実施例の半導体チップが固着し
た半導体回路基板の要部断面図FIG. 4 is a sectional view of an essential part of a semiconductor circuit board to which a semiconductor chip of a fourth embodiment of the present invention is fixed.
【図５】この発明の第５実施例の半導体チップが固着し
た半導体回路基板の要部断面図FIG. 5 is a sectional view of an essential part of a semiconductor circuit board to which a semiconductor chip according to a fifth embodiment of the present invention is fixed.
【図６】従来の凸状に反った半導体チップが固着した半
導体回路基板の要部断面図FIG. 6 is a cross-sectional view of a main part of a conventional semiconductor circuit board to which a semiconductor chip having a convex warp is fixed.
【図７】従来の凹状に反った半導体チップが固着した半
導体回路基板の要部断面図FIG. 7 is a cross-sectional view of a main portion of a conventional semiconductor circuit board to which a semiconductor chip warped in a concave shape is fixed.
【図８】反った半導体チップの要部断面図FIG. 8 is a sectional view of a main part of a warped semiconductor chip.
【符号の説明】 １ 絶縁基板 ２ 銅電極 ３ はんだ ３ａ 余分なはんだ ４ 半導体チップ ５、５ａ 空隙 ６ 絶縁基板１に付した凸状部 ７ 銅電極２に付した凸状部 ８ 絶縁基板に付した凹状部 ９ 銅電極２に付した凹状部 １０ ピット[Explanation of symbols] 1 Insulation board 2 Copper electrode 3 Solder 3a Extra solder 4 semiconductor chips 5, 5a void 6 Convex part attached to the insulating substrate 1 7 Convex part attached to copper electrode 2 8 Recessed part attached to the insulating substrate 9 Recessed part attached to copper electrode 2 10 pits
Claims (5)
固着する半導体回路基板において、半導体チップが固着
する箇所の前記導電膜の表面形状を、前記半導体チップ
の反りに合せた凸形もしくは凹形とすることを特徴とす
る半導体回路基板。1. In a semiconductor circuit substrate, in which a patterned conductive film is fixed to an insulating substrate, the surface shape of the conductive film at the position where the semiconductor chip is fixed is convex or concave in accordance with the warp of the semiconductor chip. A semiconductor circuit board having a shape.
基板を凸形もしくは凹形とし、該絶縁基板上に同一厚み
の前記導電膜を固着することで形成することを特徴とす
る請求項１に記載の半導体回路基板。2. The convex or concave shape is formed by making the insulating substrate convex or concave and fixing the conductive film having the same thickness on the insulating substrate. Item 2. The semiconductor circuit board according to Item 1.
膜のみを凸形もしくは凹形とし、該導電膜と前記絶縁基
板との固着面が平坦であることを特徴とする請求項１に
記載の半導体回路基板。3. The convex or concave shape, wherein only the conductive film is convex or concave, and a fixing surface between the conductive film and the insulating substrate is flat. The semiconductor circuit board according to.
導電膜に、はんだ溜を形成することを特徴とする請求項
１ないし３のいずれかに記載の半導体回路基板。4. The semiconductor circuit board according to claim 1, wherein a solder reservoir is formed on a conductive film around a portion to which the semiconductor chip is fixed.
半導体回路基板を用いて、前記凸形もしくは凹形の半導
体固着箇所にはんだを介して半導体チップを固着したこ
とを特徴とする半導体装置。5. A semiconductor chip using the semiconductor circuit board according to claim 1, wherein a semiconductor chip is fixed to the convex or concave semiconductor fixing portion via solder. apparatus.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001374496A JP2003174114A (en) | 2001-12-07 | 2001-12-07 | Semiconductor circuit board and semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001374496A JP2003174114A (en) | 2001-12-07 | 2001-12-07 | Semiconductor circuit board and semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2003174114A true JP2003174114A (en) | 2003-06-20 |
Family
ID=19183050
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2001374496A Pending JP2003174114A (en) | 2001-12-07 | 2001-12-07 | Semiconductor circuit board and semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2003174114A (en) |
Cited By (11)
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|---|---|---|---|---|
| WO2005078794A1 (en) * | 2004-02-16 | 2005-08-25 | Infineon Technologies Ag | Non-planar integrated circuit system |
| DE102004021633A1 (en) * | 2004-05-03 | 2005-12-01 | Infineon Technologies Ag | Method for connecting a semiconductor chip to a chip carrier and arrangement with a semiconductor chip and a chip carrier |
| JP2006173345A (en) * | 2004-12-15 | 2006-06-29 | Fujikura Ltd | Semiconductor component |
| US7387945B2 (en) | 2004-05-11 | 2008-06-17 | Seiko Epson Corporation | Semiconductor chip, semiconductor device and electronic equipment including warpage control film, and manufacturing method of same |
| JP2008288415A (en) * | 2007-05-18 | 2008-11-27 | Fuji Electric Device Technology Co Ltd | Semiconductor device and its manufacturing method |
| JP2009004760A (en) * | 2007-05-24 | 2009-01-08 | Sanyo Electric Co Ltd | Semiconductor laser device |
| US7869480B2 (en) | 2007-05-24 | 2011-01-11 | Sanyo Electric Co., Ltd. | Semiconductor laser device |
| US7907652B2 (en) | 2007-04-25 | 2011-03-15 | Sanyo Electric Co., Ltd. | Semiconductor laser device |
| US8121163B2 (en) | 2007-03-16 | 2012-02-21 | Sanyo Electric Co., Ltd. | Semiconductor laser diode apparatus and method of fabricating the same |
| DE102015219830B3 (en) * | 2015-10-13 | 2017-01-26 | Robert Bosch Gmbh | Method for producing a contact arrangement and contact arrangement |
| JP2020009902A (en) * | 2018-07-09 | 2020-01-16 | 日本特殊陶業株式会社 | Retainer |
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Cited By (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7633149B2 (en) | 2004-02-16 | 2009-12-15 | Infineon Technologies Ag | Integrated circuit arrangement |
| WO2005078794A1 (en) * | 2004-02-16 | 2005-08-25 | Infineon Technologies Ag | Non-planar integrated circuit system |
| US7511382B2 (en) | 2004-05-03 | 2009-03-31 | Infineon Technologies Ag | Semiconductor chip arrangement and method |
| DE102004021633A1 (en) * | 2004-05-03 | 2005-12-01 | Infineon Technologies Ag | Method for connecting a semiconductor chip to a chip carrier and arrangement with a semiconductor chip and a chip carrier |
| DE102004021633B4 (en) * | 2004-05-03 | 2006-04-06 | Infineon Technologies Ag | Method for connecting a semiconductor chip to a chip carrier and arrangement with a semiconductor chip and a chip carrier |
| US7387945B2 (en) | 2004-05-11 | 2008-06-17 | Seiko Epson Corporation | Semiconductor chip, semiconductor device and electronic equipment including warpage control film, and manufacturing method of same |
| JP2006173345A (en) * | 2004-12-15 | 2006-06-29 | Fujikura Ltd | Semiconductor component |
| US8121163B2 (en) | 2007-03-16 | 2012-02-21 | Sanyo Electric Co., Ltd. | Semiconductor laser diode apparatus and method of fabricating the same |
| US7907652B2 (en) | 2007-04-25 | 2011-03-15 | Sanyo Electric Co., Ltd. | Semiconductor laser device |
| JP2008288415A (en) * | 2007-05-18 | 2008-11-27 | Fuji Electric Device Technology Co Ltd | Semiconductor device and its manufacturing method |
| US8026566B2 (en) | 2007-05-18 | 2011-09-27 | Fuji Electric Systems Co., Ltd. | Semiconductor device and method for manufacturing semiconductor device |
| JP2009004760A (en) * | 2007-05-24 | 2009-01-08 | Sanyo Electric Co Ltd | Semiconductor laser device |
| JP4573882B2 (en) * | 2007-05-24 | 2010-11-04 | 三洋電機株式会社 | Semiconductor laser device |
| US7869480B2 (en) | 2007-05-24 | 2011-01-11 | Sanyo Electric Co., Ltd. | Semiconductor laser device |
| DE102015219830B3 (en) * | 2015-10-13 | 2017-01-26 | Robert Bosch Gmbh | Method for producing a contact arrangement and contact arrangement |
| JP2020009902A (en) * | 2018-07-09 | 2020-01-16 | 日本特殊陶業株式会社 | Retainer |
| JP7169793B2 (en) | 2018-07-09 | 2022-11-11 | 日本特殊陶業株式会社 | holding device |
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