JP2001298033A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP2001298033A JP2001298033A JP2000115840A JP2000115840A JP2001298033A JP 2001298033 A JP2001298033 A JP 2001298033A JP 2000115840 A JP2000115840 A JP 2000115840A JP 2000115840 A JP2000115840 A JP 2000115840A JP 2001298033 A JP2001298033 A JP 2001298033A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- solder
- lead frame
- electronic component
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
- H01L2224/26152—Auxiliary members for layer connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
- H01L2224/26175—Flow barriers
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
- H01L2224/27011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
- H01L2224/27013—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the layer connector, e.g. solder flow barrier
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
- H01L2224/331—Disposition
- H01L2224/3318—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/33181—On opposite sides of the body
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/83009—Pre-treatment of the layer connector or the bonding area
- H01L2224/83051—Forming additional members, e.g. dam structures
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- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83385—Shape, e.g. interlocking features
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- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
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- H01L2924/01033—Arsenic [As]
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- H01L2924/01078—Platinum [Pt]
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- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
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- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、任意幅で構成され
たリードフレームを用いた半導体素子及び電子部品を実
装する半導体装置に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device for mounting a semiconductor element and an electronic component using a lead frame having an arbitrary width.
【０００２】[0002]
【従来の技術】板厚の厚い（ｔ≧0.5）任意幅で構成さ
れたリードフレーム３は金属絶縁基板の様にエッチング
方式による生産ではエッチング時間がかかり量産でもコ
スト高になる。これを用いた一般的な構造を図５に示
す。2. Description of the Related Art A lead frame 3 having a large thickness (t.gtoreq.0.5) and an arbitrary width is required to be etched in a production method by an etching method like a metal insulating substrate, and the cost is high even in mass production. A general structure using this is shown in FIG.
【０００３】ベース板１、絶縁層２、該リードフレーム
３により構成されたパワー回路上に半導体素子６及び電
子部品をはんだ４で接続した従来の半導体素子及び電子
部品実装方式である。A conventional semiconductor element and electronic component mounting system in which a semiconductor element 6 and electronic parts are connected by a solder 4 on a power circuit constituted by a base plate 1, an insulating layer 2, and the lead frame 3.
【０００４】半導体素子６と該リードフレーム３は、は
んだ４によって電気的接続がされ、かつ位置固定され
る。The semiconductor element 6 and the lead frame 3 are electrically connected by solder 4 and fixed in position.
【０００５】リフローはんだ時半導体素子６の位置は、
はんだ４が溶融しはんだ流れが発生することで、はんだ
濡れ広がりｃの範囲内で該リードフレーム３上を移動す
る。同時に半導体素子６上に形成されたワイヤーボンデ
ィングパッド８の位置もはんだ流れ発生によりはんだ濡
れ広がりｃの範囲で移動することとなり、この時部材移
動距離ｄがワイヤーボンディング許容差ａ内におさまら
ない場合があり、ボンディングパッドの位置のずれが大
きいため、ワイヤーボンディング時の位置検出に時間を
かけて作業している。The position of the semiconductor element 6 during reflow soldering is
When the solder 4 is melted and a solder flow is generated, the solder 4 moves on the lead frame 3 within a range of the solder wetting spread c. At the same time, the position of the wire bonding pad 8 formed on the semiconductor element 6 also moves within the range of the solder wetting spread c due to the generation of the solder flow. At this time, the member moving distance d may not be within the wire bonding tolerance a. In addition, since the displacement of the bonding pad is large, it takes time to detect the position during wire bonding.
【０００６】また、図６は半導体素子６の搭載位置に部
品サイズ外周に、はんだフィレット成形可能な部材移動
制御距離ｂだけ距離をおき穴あけしたカーボン治具１３
を基板に正確にセットした後、カーボン治具１３の穴に
板はんだ１２と半導体素子６を落とし込み、リフローは
んだする従来の実装方法を用いて、任意幅で構成された
リードフレーム３に半導体素子６をはんだ１４によって
固着するものである。FIG. 6 shows a carbon jig 13 in which a hole is formed at the mounting position of the semiconductor element 6 on the outer periphery of the component size by a member movement control distance b capable of forming a solder fillet.
Is accurately set on the substrate, the plate solder 12 and the semiconductor element 6 are dropped into the hole of the carbon jig 13, and the semiconductor element 6 is mounted on the lead frame 3 having an arbitrary width by using a conventional mounting method of reflow soldering. Is fixed by the solder 14.
【０００７】半導体素子６の位置はカーボン治具１３の
穴の内壁までしか移動できない。カーボン治具１３はリ
フローはんだ時に板はんだ１２溶融時に発生するはんだ
流れを阻止し、また半導体素子６は部材移動制御距離ｂ
内で位置決めされる。この時半導体素子６上に形成され
たワイヤーボンディングパッド８がワイヤーボンディン
グ許容値ａ内の位置ずれにおさまる様に部材移動制御距
離ｂを決定することで、リフローはんだ時にはんだ流れ
による半導体素子６の部材移動距離ｄをワイヤーボンデ
ィング許容値ａ以内におさめ、ワイヤーボンディング時
に半導体素子６上に形成されたワイヤーボンディングパ
ッド８にワイヤー７を接合させるボンダー装置のボンデ
ィング位置調整を最小限とすることが出来る。The position of the semiconductor element 6 can move only up to the inner wall of the hole of the carbon jig 13. The carbon jig 13 prevents the solder flow generated when the plate solder 12 is melted during the reflow soldering, and the semiconductor element 6 moves the member movement control distance b.
Positioned within. At this time, the member movement control distance b is determined so that the wire bonding pad 8 formed on the semiconductor element 6 falls within the positional deviation within the allowable wire bonding value a, whereby the member of the semiconductor element 6 due to the solder flow during reflow soldering is determined. It is possible to keep the moving distance d within the allowable wire bonding value a and minimize the adjustment of the bonding position of the bonder device for bonding the wire 7 to the wire bonding pad 8 formed on the semiconductor element 6 at the time of wire bonding.
【０００８】しかし、上記実装方法にはパワー回路パタ
ーン毎に専用のカーボン治具１３が必要であり、またカ
ーボン治具１３のセット及び取り外し、板はんだ１２と
半導体素子６の落し込み工程を要しコスト低減のあい路
となっている。However, the above mounting method requires a dedicated carbon jig 13 for each power circuit pattern, and also requires the steps of setting and removing the carbon jig 13 and dropping the plate solder 12 and the semiconductor element 6. This is a way to reduce costs.
【０００９】[0009]
【発明が解決しようとする課題】図５において任意幅で
構成されたリードフレーム３上ではんだ４が溶融しはん
だ流れが発生する。In FIG. 5, the solder 4 is melted on the lead frame 3 having an arbitrary width to generate a solder flow.
【００１０】この時半導体素子６の位置は、はんだ濡れ
広がりｃの範囲で該リードフレーム３上を移動し同時に
半導体素子６上に形成されたワイヤーボンディングパッ
ド８の位置は、はんだ濡れ広がりｃの範囲で移動するこ
ととなり、はんだ流れによる部材移動距離ｄがワイヤー
ボンディング許容差ａよりも大きくる場合がある。At this time, the position of the semiconductor element 6 moves on the lead frame 3 within the range of the solder wetting spread c, and at the same time, the position of the wire bonding pad 8 formed on the semiconductor element 6 falls within the range of the solder wetting spread c. And the member movement distance d due to the solder flow may be larger than the wire bonding tolerance a.
【００１１】このためボンディングパッドの位置のずれ
が大きくワイヤーボンディング時の位置検出に時間をか
けて作業している。For this reason, the position of the bonding pad is largely displaced, and it takes time to detect the position during wire bonding.
【００１２】また、前記を解決するため図６に示すよう
に、半導体素子６の搭載位置に部品サイズ外周にはんだ
フィレット形成可能な部材移動制御距離ｂだけ距離をお
いて穴あけしたカーボン治具１３を基板に正確にセット
し、カーボン治具１３の穴に板はんだ１２と半導体素子
６を落し込み、リフローはんだする従来の実装方法を用
いて該リードフレーム３に半導体素子６をはんだ４によ
って固着させ、はんだ流れによる部材移動距離をワイヤ
ーボンディング許容値ａ以内に制御する必要がある。As shown in FIG. 6, in order to solve the above-mentioned problem, a carbon jig 13 is formed at a mounting position of the semiconductor element 6 with a member control distance b capable of forming a solder fillet on the outer periphery of a component size. The semiconductor element 6 is fixed to the lead frame 3 with the solder 4 by using a conventional mounting method in which the board solder 12 and the semiconductor element 6 are dropped into the holes of the carbon jig 13 and the reflow soldering is performed. It is necessary to control the moving distance of the member due to the solder flow within the allowable wire bonding value a.
【００１３】本発明はこれらの問題を解決し、ワイヤー
ボンディング時におけるボンダー装置のワイヤーボンデ
ィング位置調整を最小限とすることができ、また、電子
部品のはんだフィレットも確実に形成できる。The present invention solves these problems, can minimize the adjustment of the wire bonding position of the bonder device during wire bonding, and can reliably form a solder fillet for an electronic component.
【００１４】半導体素子及び電子部品搭載或いは実装時
においてはカーボン治具使用による実装方法を用いずに
正確な半導体素子位置決めを提供するものである。An object of the present invention is to provide accurate positioning of a semiconductor element and a semiconductor component without mounting method using a carbon jig when mounting or mounting the electronic component.
【００１５】[0015]
【課題を解決するための手段】本発明のはんだ流れ阻止
手段を施した半導体素子位置決め構造は任意幅で構成さ
れたリードフレーム上に形成した半導体素子及び電子部
品実装エリアの外周に、はんだフィレット形成可能な部
材移動制御距離をおいたはんだ流れ阻止手段を用いはん
だ流れを抑制するものである。According to the present invention, there is provided a semiconductor element positioning structure provided with a solder flow preventing means, comprising a solder fillet formed on an outer periphery of a semiconductor element and electronic component mounting area formed on a lead frame having an arbitrary width. The solder flow is suppressed by using a solder flow prevention unit having a possible member movement control distance.
【００１６】これによりリフローはんだ時における半導
体素子及び電子部品の部材移動距離をワイヤーボンディ
ング許容値内におさめることを可能とし、ワイヤーボン
ディング時におけるボンダー装置のワイヤーボンディン
グ位置調整を最小限とすることができる。また、電子部
品のはんだフィレットも確実に形成できる。This makes it possible to keep the movement distance of the semiconductor element and the electronic component members during the reflow soldering within the allowable range of the wire bonding, and to minimize the adjustment of the wire bonding position of the bonder device during the wire bonding. . In addition, a solder fillet for an electronic component can be reliably formed.
【００１７】半導体素子及び電子部品搭載時、或いは実
装時においてはカーボン治具使用による実装方法を用い
ずに正確な半導体素子及び電子部品の位置決め実装を実
現するものである。When a semiconductor element and an electronic component are mounted or mounted, accurate positioning and mounting of the semiconductor element and the electronic component are realized without using a mounting method using a carbon jig.
【００１８】本発明の任意幅で構成されたリードフレー
ム上にはんだ流れ阻止手段を施した半導体素子位置決め
構造はこれを有する半導体装置の該リードフレームに固
有の位置決め構造を持ち、はんだ流れを抑制するもので
ある。The semiconductor element positioning structure of the present invention in which the solder flow preventing means is provided on a lead frame having an arbitrary width has a positioning structure unique to the lead frame of a semiconductor device having the same, and suppresses the solder flow. Things.
【００１９】このことより半導体素子及び電子部品搭載
時或いは実装時にカーボン治具使用による実装方法を用
いずに正確な半導体素子及び電子部品の位置決め実装を
実現できる。また、電子部品のはんだフィレットを確実
に形成できる。Thus, accurate positioning and mounting of the semiconductor element and the electronic component can be realized without using a mounting method using a carbon jig when mounting or mounting the semiconductor element and the electronic component. Further, a solder fillet for an electronic component can be reliably formed.
【００２０】リフローはんだ時においては半導体素子及
び電子部品との部材移動距離をワイヤーボンディング許
容値内におさめることを可能とし、ワイヤーボンディン
グ時におけるボンダー装置のワイヤーボンディング位置
調整を最小限とすることができる。At the time of reflow soldering, it is possible to keep the member moving distance between the semiconductor element and the electronic component within the allowable value of wire bonding, and to minimize the adjustment of the wire bonding position of the bonder device at the time of wire bonding. .
【００２１】[0021]
【発明の実施の形態】図１において任意幅で構成された
リードフレーム３上に設けられた半導体素子実装エリア
１１の外周にはんだフィレット形成可能な部材移動制御
距離ｂだけ距離を置いたはんだ流れ阻止手段５を施し、
半導体素子実装エリア１１内にはんだ４を搭載或いは印
刷し、この上に半導体素子６を搭載する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In FIG. 1, a solder flow block is formed at a distance of a member movement control distance b capable of forming a solder fillet on an outer periphery of a semiconductor element mounting area 11 provided on a lead frame 3 having an arbitrary width. Apply means 5,
The solder 4 is mounted or printed in the semiconductor element mounting area 11, and the semiconductor element 6 is mounted thereon.
【００２２】この時部材移動制御距離ｂは半導体素子６
上に形成されたワイヤーボンディングパッド８の移動距
離がワイヤーボンディング許容値ａ以内となるものであ
れば良くｂ≦ａである必要はない。At this time, the member movement control distance b is
As long as the moving distance of the wire bonding pad 8 formed above is within the wire bonding allowable value a, it is not necessary to satisfy b ≦ a.
【００２３】半導体素子実装エリア１１に搭載及び印刷
されたはんだ４は、リフローはんだ時にはんだ流れ阻止
手段５により溶融したはんだが半導体素子実装エリア１
１外へ流れだすことをを阻止され、同時にはんだ４上に
搭載された半導体素子６は半導体素子実装エリア１１外
への移動を阻止される。The solder 4 mounted and printed on the semiconductor element mounting area 11 is the solder melted by the solder flow preventing means 5 during the reflow soldering.
1 is prevented from flowing out, and at the same time, the semiconductor element 6 mounted on the solder 4 is prevented from moving out of the semiconductor element mounting area 11.
【００２４】これにより半導体素子６ははんだ凝固時に
半導体素子実装エリア１１内に留まり、半導体素子６上
に形成されているボンディングパッド８はワイヤボンデ
ィング許容値ａ以内で位置決めされることとなる。As a result, the semiconductor element 6 remains in the semiconductor element mounting area 11 when the solder is solidified, and the bonding pads 8 formed on the semiconductor element 6 are positioned within the allowable wire bonding value a.
【００２５】また、本発明によるはんだ流れ阻止手段５
は図３に示す様に任意幅で構成されたリードフレーム３
上に半導体素子及び電子部品実装エリア１１を形成し同
一面の他のエリアとの境界線上に凹形状、或いは凸形状
を設けた構造であり、かつ図４に示すように半導体素子
及び電子部品実装エリア１１の外周全体を囲むもの、或
いは部分的に区切るもので実現される。Further, the solder flow preventing means 5 according to the present invention.
Is a lead frame 3 having an arbitrary width as shown in FIG.
A semiconductor element and electronic component mounting area 11 is formed thereon, and a concave shape or a convex shape is provided on a boundary line with another area on the same surface, and as shown in FIG. This is realized by surrounding the entire outer periphery of the area 11 or partially dividing the area.
【００２６】或いは図２に示すように任意幅で構成され
たリードフレーム３上に設けた半導体素子及び電子部品
実装エリア１１に該リードフレーム３と半導体素子６及
び電子部品とのはんだ溶着を促進させるメッキ９を施
し、他のエリアにはんだ濡れ広がりを抑制するメッキ１
０をエリア全体、或いはエリアとの境界線上に施してあ
るか、もしくははんだ濡れ広がりを抑制するメッキ１０
自体を施していないはんだ流れ阻止手段を用いても良
い。Alternatively, as shown in FIG. 2, solder welding of the lead frame 3 to the semiconductor element 6 and the electronic component is promoted in the semiconductor element and electronic component mounting area 11 provided on the lead frame 3 having an arbitrary width. Plating 9 that applies plating 9 and suppresses solder wetting spread in other areas
0 is applied on the entire area or on the boundary line with the area, or the plating 10 for suppressing the spread of solder wetting
It is also possible to use a means for preventing solder flow which is not applied.
【００２７】或いは図１において任意幅で構成されたリ
ードフレーム３上に設けた半導体素子及び電子部品実装
エリア１１の外周にソルダーレジストを用いてはんだ流
れ阻止手段５を他のエリア全体、或いはエリアとの境界
線上全体、または一部に形成したはんだ流れ阻止手段を
用いても良い。Alternatively, in FIG. 1, the solder flow preventing means 5 is provided on the outer periphery of the semiconductor element and electronic component mounting area 11 provided on the lead frame 3 having an arbitrary width by using a solder resist, and the solder flow preventing means 5 is connected to the entire other area or the area. Alternatively, solder flow blocking means formed entirely or partially on the boundary line may be used.
【００２８】[0028]
【発明の効果】本発明の半導体素子及び電子部品の正確
な位置決め構造により、ワイヤーボンディング時におけ
るボンダー装置のワイヤーボンディング位置調整を最小
限とすることができる。また、電子部品のはんだフィレ
ットも確実に形成できる。更にカーボン治具使用を廃止
できはんだ印刷法を適用出来る。According to the accurate positioning structure of the semiconductor element and the electronic component of the present invention, the adjustment of the wire bonding position of the bonder device during the wire bonding can be minimized. In addition, a solder fillet for an electronic component can be reliably formed. Furthermore, the use of a carbon jig can be eliminated and a solder printing method can be applied.
【図面の簡単な説明】[Brief description of the drawings]
【図１】本発明の一実施例における凸形はんだ流れ阻止
手段を有する半導体素子位置決め構造の断面及び上面視
図である。FIG. 1 is a cross-sectional view and a top view of a semiconductor element positioning structure having a convex solder flow prevention unit according to an embodiment of the present invention.
【図２】本発明の一実施例におけるメッキによるはんだ
流れ阻止手段を有する半導体素子位置決め構造の断面及
び上面視図である。FIG. 2 is a cross-sectional view and a top view of a semiconductor element positioning structure having a means for preventing solder flow by plating in one embodiment of the present invention.
【図３】本発明の一実施例における溝、突起を形成した
はんだ流れ阻止手段構造断面図である。FIG. 3 is a cross-sectional view of a structure of a solder flow prevention unit having grooves and protrusions according to an embodiment of the present invention.
【図４】本発明の一実施例における部分はんだ流れ阻止
手段構造断面図である。FIG. 4 is a sectional view showing a structure of a partial solder flow preventing means according to an embodiment of the present invention.
【図５】従来の半導体素子実装構造の断面及び上面視図
である。FIG. 5 is a sectional view and a top view of a conventional semiconductor element mounting structure.
【図６】カーボン治具使用により半導体素子実装を制御
する従来の実装方法を用いた半導体実装構造の断面及び
上面視図である。FIG. 6 is a cross-sectional view and a top view of a semiconductor mounting structure using a conventional mounting method for controlling semiconductor element mounting by using a carbon jig.
１…ベース板、２…絶縁層、３…−任意幅で構成された
リードフレーム、４…はんだ、５…はんだ流れ阻止手
段、６…半導体素子、７…ワイヤー、８…ボンディング
パッド、９…はんだ溶着を促進させるメッキ、１０…は
んだ溶着を抑制させるメッキ、１１…半導体素子実装エ
リア、 １２…板はんだ、 １３…カーボン治具、ａ…ワ
イヤボンディング許容値、ｂ…部材移動制御距離、ｃ…
はんだの濡れ広がり範囲、ｄ…半導体素子及び電子部品
の部材移動距離。DESCRIPTION OF SYMBOLS 1 ... Base plate, 2 ... Insulation layer, 3 ...- Lead frame comprised by arbitrary widths, 4 ... Solder, 5 ... Solder flow prevention means, 6 ... Semiconductor element, 7 ... Wire, 8 ... Bonding pad, 9 ... Solder Plating to promote welding, 10: Plating to suppress solder welding, 11: Semiconductor element mounting area, 12: Plate solder, 13: Carbon jig, a: Allowable wire bonding value, b: Member movement control distance, c ...
Solder spread range, d: moving distance of semiconductor element and electronic component.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 佐々木 康 千葉県習志野市東習志野七丁目１番１号 株式会社日立製作所産業機器グループ内 Ｆターム(参考） 5F047 AA11 AB03 AB06 BA01 5F067 AA16 BE02 DC14 ────────────────────────────────────────────────── ─── Continuing from the front page (72) Inventor Yasushi Sasaki 7-1-1, Higashi-Narashino, Narashino-shi, Chiba F-term in the Industrial Machinery Group, Hitachi, Ltd. 5F047 AA11 AB03 AB06 BA01 5F067 AA16 BE02 DC14
Claims (6)
んだによって該リードフレーム上に接続する半導体素子
及び電子部品を有する半導体装置において、半導体素子
及び電子部品を該リードフレーム上実装時に所定の位置
に接続するために施した位置決め構造を有する半導体装
置。1. A semiconductor device having a lead frame having an arbitrary width and a semiconductor element and an electronic component connected to the lead frame by soldering, wherein the semiconductor element and the electronic component are mounted on the lead frame at a predetermined position. A semiconductor device having a positioning structure for connecting to a semiconductor device.
位置精度をボンダー装置のボンディングデータを変更す
ること無くワイヤーボンディング許容値内とすることを
可能にした位置決め構造を有する半導体装置。2. The semiconductor device according to claim 1, wherein the positioning accuracy of the semiconductor element to be mounted is within the allowable wire bonding value without changing the bonding data of the bonder device.
設けた半導体素子及び電子部品実装エリアと他のエリア
との境界線全体、或いは一部分に凹または凸形状のはん
だ流れ阻止手段を用いたことを特徴とする位置決め構造
を有する半導体装置。3. The method according to claim 1, wherein a concave or convex solder flow preventing means is used on the whole or a part of the boundary between the semiconductor element and electronic component mounting area provided on the lead frame and another area. A semiconductor device having a positioning structure characterized by the above-mentioned.
設けた半導体素子及び電子部品実装エリアに該リードフ
レームと半導体素子及び電子部品とのはんだ溶着を促進
させるメッキを施し、他のエリアにはんだ溶着を抑制す
るメッキをエリア全体或いはエリア境界線上に施してあ
るかもしくはメッキ自体を施していないはんだ流れ阻止
手段を用いたことを特徴とする位置決め構造を有する半
導体装置。4. The semiconductor device according to claim 1, wherein the semiconductor element and the electronic component mounting area provided on the lead frame are plated to promote solder welding between the lead frame and the semiconductor element and the electronic component. A semiconductor device having a positioning structure, characterized in that plating for suppressing welding is applied to the entire area or the area boundary line, or a solder flow preventing means without plating is used.
設けた半導体素子及び電子部品実装エリアの外にソルダ
ーレジストを他のエリア全体、或いはエリア境界線上全
体または一部分に施したはんだ流れ阻止手段を用いたこ
とを特徴とする位置決め構造を有する半導体装置。5. A solder flow preventing means according to claim 1, wherein a solder resist is applied to the entire other area or the whole or a part of the area boundary line outside the semiconductor element and electronic component mounting area provided on the lead frame. A semiconductor device having a positioning structure characterized by using:
けた半導体素子及び電子部品実装エリア外周に施したは
んだ流れ阻止手段により、集積回路や抵抗、コンデンサ
等の電子部品のはんだフィットが確実に形成する事を特
徴とした位置決め構造を有する半導体装置。6. The solder fitting of an electronic component such as an integrated circuit, a resistor and a capacitor is reliably formed by means of a solder flow preventing means provided on an outer periphery of a semiconductor element and an electronic component mounting area provided on the lead frame according to claim 1. A semiconductor device having a positioning structure characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000115840A JP2001298033A (en) | 2000-04-12 | 2000-04-12 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000115840A JP2001298033A (en) | 2000-04-12 | 2000-04-12 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2001298033A true JP2001298033A (en) | 2001-10-26 |
Family
ID=18627389
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2000115840A Pending JP2001298033A (en) | 2000-04-12 | 2000-04-12 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2001298033A (en) |
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