JP2002271009A - Printed wiring board for high density mounting and base material therefor - Google Patents

Printed wiring board for high density mounting and base material therefor

Info

Publication number
JP2002271009A
JP2002271009A JP2001065620A JP2001065620A JP2002271009A JP 2002271009 A JP2002271009 A JP 2002271009A JP 2001065620 A JP2001065620 A JP 2001065620A JP 2001065620 A JP2001065620 A JP 2001065620A JP 2002271009 A JP2002271009 A JP 2002271009A
Authority
JP
Japan
Prior art keywords
opening
area
conductor
pad
solder resist
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001065620A
Other languages
Japanese (ja)
Inventor
Yoshiaki Sato
義明 佐藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toyo Communication Equipment Co Ltd
Original Assignee
Toyo Communication Equipment Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toyo Communication Equipment Co Ltd filed Critical Toyo Communication Equipment Co Ltd
Priority to JP2001065620A priority Critical patent/JP2002271009A/en
Publication of JP2002271009A publication Critical patent/JP2002271009A/en
Pending legal-status Critical Current

Links

Landscapes

  • Non-Metallic Protective Coatings For Printed Circuits (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

PROBLEM TO BE SOLVED: To solve all of various defects caused by a positional deviation of an SR film coating the surface of a printed wiring board at the same time, in the printed wiring board having such a structure that a solder resist film is formed on an insulation substrate formed with a wiring pattern and the SR film of the minimum width is disposed between two conductor pads disposed adjacently to each other with a very small spacing. SOLUTION: The distance between the two adjacent conductor pads 2a is made very small, and an area of each pad is made larger a than an area necessary for bonding an electrode 10a of an electronic component. A solder resist 3 is formed with openings 20 to expose each conductor pad, and an opening area of each opening is small enough for the opening to be included in the area of the conductor pad. In a normal state in which there is no positional deviation of the solder resist, each opening stays at the center of each conductor pad, with the distance between the periphery of the opening and that of the conductor pad being equal to or smaller than the maximum positional deviation of the solder resist.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は導体パッド間隔を従
来の限界値とされていた0.2mm未満に減縮して搭載
部品の実装密度を高めた場合においても、導体パッド間
に配置されるソルダーレジスト膜の位置ずれに起因した
種々の不具合が発生することがないようにした高密度実
装用プリント配線基板及びプリント配線基板母材に関す
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solder disposed between conductive pads even when the space between the conductive pads is reduced to less than 0.2 mm, which is the conventional limit value, to increase the mounting density of mounted components. The present invention relates to a printed wiring board for high-density mounting and a printed wiring board base material in which various problems due to a displacement of a resist film do not occur.

【0002】[0002]

【従来の技術】プリント配線基板は、絶縁基板上に銅等
の導体膜から成る配線パターンを形成し、更に配線パタ
ーンを構成する部品搭載用の導体パッドを回避した絶縁
基板面をソルダーレジスト膜(以下、SR膜、という)
によって被覆した構成を備えている。即ち、搭載部品の
小型化、高密度化が進むにつれて部品を搭載する導体パ
ターン間の間隔も狭くなるため、各導体パッド上にクリ
ームハンダを塗布したときにクリームハンダが導体パッ
ドからはみ出して絶縁基板上を流動し、他の導体部分と
の間でハンダブリッジ、短絡等の不具合をもたらす可能
性が増大する。このため、従来から導体パッドの外側へ
ハンダが流動しないように、ハンダの流動を阻止する性
質を有した樹脂材料から成るSR膜を、導体パッドを除
いた配線パターン及び絶縁基板上に被覆することが行わ
れている。
2. Description of the Related Art In a printed wiring board, a wiring pattern made of a conductive film such as copper is formed on an insulating substrate, and a surface of the insulating substrate which avoids conductive pads for mounting components constituting the wiring pattern is coated with a solder resist film ( Hereinafter, referred to as SR film)
And a configuration covered by That is, since the space between the conductor patterns on which the components are mounted becomes smaller as the mounted components become smaller and higher in density, the cream solder protrudes from the conductor pads when the cream solder is applied on the respective conductor pads, and the insulating substrate There is an increased likelihood of flowing over and causing defects such as solder bridges, short circuits, etc. with other conductor parts. For this reason, conventionally, an SR film made of a resin material having a property of preventing the flow of solder is coated on the wiring pattern and the insulating substrate excluding the conductive pad so that the solder does not flow outside the conductive pad. Has been done.

【0003】図3はプリント配線基板上に電子部品を搭
載した状態を示す平面図であり、プリント配線基板は、
絶縁基板1上に配線パターン2を形成した後で、図示し
ないマスク(シルクスクリーン)を用いたスクリーン印
刷等によってSR膜3を被覆形成した構成を備えてい
る。電子部品10は、両端に位置する電極10aを夫々
配線パターン2を構成する導体パッド2a上に載置した
状態でクリームハンダによって固定されている。異なっ
た電子部品を搭載する2つの導体パッド2aが近接する
場合や、一つの部品を搭載する2つの導体パッド間の間
隔が狭い場合には、導体パッド間に細幅帯状のSR膜3
aを配置して各導体パッド上のクリームハンダが流動す
ることを防止している。なお、周知のようにスクリーン
印刷においては、液状のソルダーレジストを通過させる
シルクスクリーンの面上の、各導体パッドに対応する位
置に、SRを透過しないフィルムを固定した構成を備え
ており、該フィルムによって隠蔽された導体パッド部分
だけにSR膜が形成されない状態となる。
FIG. 3 is a plan view showing a state in which electronic components are mounted on a printed wiring board.
After the wiring pattern 2 is formed on the insulating substrate 1, the SR film 3 is formed by screen printing using a mask (silk screen) (not shown). The electronic component 10 is fixed by cream solder in a state where the electrodes 10a located at both ends are placed on the conductor pads 2a constituting the wiring pattern 2, respectively. When the two conductor pads 2a on which different electronic components are mounted are close to each other, or when the interval between the two conductor pads on which one component is mounted is narrow, the narrow strip-shaped SR film 3 is provided between the conductor pads.
The arrangement of “a” prevents the cream solder on each conductor pad from flowing. As is well known, screen printing has a configuration in which a film that does not transmit SR is fixed at a position corresponding to each conductive pad on the surface of a silk screen through which a liquid solder resist passes. As a result, no SR film is formed only on the portion of the conductor pad concealed.

【0004】図4は隣接し合う導体パッド2a間に位置
する絶縁基板1面に細幅帯状のSR膜3aを配置して2
つの導体パッド間でのクリームハンダの流動を遮断する
構成を示す拡大図である。細幅帯状のSR膜3aの幅
は、SR膜3aを構成する材質による制限から、SR膜
3aと基板1との密着強度を十分に確保するためには、
最低でも0.1mmは必要とされている。SR膜3a
は、配線パターンを備えた絶縁基板面上に対して図示し
ないマスクを用いて形成されるが、この際、図4(a)
に示した如く位置精度よく両導体パッドの中間位置に成
膜される場合ばかりではなく、(b)に示した如く一方
の導体パッド側に位置ずれして成膜されることも多々あ
る。このようなSR膜の位置ずれの最大幅は、SRの成
膜装置の性能にもよるが、±0.05mm程度であるこ
とが多い。また、導体パッド2の一部にでもSR膜3a
が被さって形成された場合には、電子部品10の電極1
0aを搭載するために必要な導体パッドの面積が減縮さ
れることになり、ハンダによる部品保持強度が低下した
り、搭載部品10の位置ずれの原因となる。このため、
導体パッド間の間隔は、上記位置ずれの最大幅である±
0.05mmを考慮すると、最低0.2mm(0.1m
m+0.05mm×2)は必要とされることになる。つ
まり、このことは搭載部品間隔を0.2mm以下に狭め
ることができないことを意味する。
FIG. 4 shows a structure in which a narrow strip-shaped SR film 3a is arranged on the surface of an insulating substrate 1 located between adjacent conductive pads 2a.
It is an enlarged view which shows the structure which interrupt | blocks the flow of cream solder between two conductor pads. The width of the narrow strip-shaped SR film 3a is limited by the material constituting the SR film 3a. In order to sufficiently secure the adhesion strength between the SR film 3a and the substrate 1,
At least 0.1 mm is required. SR film 3a
Is formed on a surface of an insulating substrate provided with a wiring pattern by using a mask (not shown).
In addition to the case where a film is formed at an intermediate position between both conductor pads with high positional accuracy as shown in (b), the film is often displaced toward one of the conductor pads as shown in (b). The maximum width of the positional shift of the SR film depends on the performance of the SR film forming apparatus, but is often about ± 0.05 mm. Also, the SR film 3 a
Is formed so as to cover the electrode 1 of the electronic component 10.
As a result, the area of the conductor pad necessary for mounting the Oa is reduced, and the component holding strength by soldering is reduced and the mounted component 10 is displaced. For this reason,
The distance between the conductor pads is the maximum width of the above positional deviation ±
Considering 0.05mm, at least 0.2mm (0.1m
m + 0.05 mm × 2) will be required. That is, this means that the space between the mounted components cannot be reduced to 0.2 mm or less.

【0005】ところで、最近になってチップ部品とし
て、縦横寸法が0.6×0.3mm程度の小型のものが
出回るようになってきており、プリント配線基板上に実
装する電子部品の小型化に対応して配線パターンのさら
なる高密度化が求められる結果、導体パッド間隔につい
ても、0.2mm未満であることが強く求められてい
る。しかし、上記導体パッド間隔を0.2mm未満に減
縮した場合、形成可能な最小幅が0.1mmに制限され
るSR膜3aとの関係で、SR膜3aが導体パッド2a
に被さって導体パッドが部品の電極を支持する面積を減
少させる確率が大幅に増大する。即ち、図5(a)
(b)は、導体パッド間隔を0.15mmに減縮した状
態を示す図であり、この場合、0.1mmの幅を有する
SR膜3aと両導体パッド2aの端縁との間隔が更に減
少するため、SR膜3aの形成位置が±0.05mmの
範囲で位置ずれすることによって、図5(b)のように
SR膜3aが導体パッド2a上にオーバーラップする確
率が更に増大する。このようにSR膜が導体パッド上に
一部でも被さった場合には、導体パッドの有効接合面積
にばらつきが発生し、導体パッドが部品の電極10aを
接合する面積が狭くなる結果、部品を接合する強度が低
下する。また、理想的には、導体パッド2aの中心位置
に対して部品の電極10aの適正位置が整合した状態で
の接合が好ましいが、導体パッドの本来の中心位置がS
R膜による被覆によって位置ずれした場合には、該導体
パッド上に接合される部品の電極10aの適正位置との
間にずれが発生し、接合不良や部品の位置ずれが発生す
る原因となる。
In recent years, as chip components, small ones having a vertical and horizontal dimension of about 0.6.times.0.3 mm have come to be marketed, and electronic components mounted on a printed wiring board have been reduced in size. Correspondingly, further densification of the wiring pattern is required, and as a result, the spacing between the conductor pads is also strongly required to be less than 0.2 mm. However, when the above-mentioned conductor pad interval is reduced to less than 0.2 mm, the SR film 3a becomes smaller than the conductor pad 2a due to the relationship with the SR film 3a in which the minimum width that can be formed is limited to 0.1 mm.
The probability that the conductive pad reduces the area where the conductive pad supports the electrode of the component is greatly increased. That is, FIG.
(B) is a diagram showing a state where the conductor pad interval is reduced to 0.15 mm. In this case, the interval between the SR film 3a having a width of 0.1 mm and the edge of both conductor pads 2a is further reduced. Therefore, when the formation position of the SR film 3a is displaced within a range of ± 0.05 mm, the probability that the SR film 3a overlaps the conductor pad 2a as shown in FIG. 5B is further increased. If the SR film covers even a part of the conductor pad as described above, the effective bonding area of the conductor pad varies, and the area of the conductor pad that joins the electrode 10a of the component is reduced. The strength to be reduced. Ideally, it is preferable that the bonding is performed in a state where the proper position of the electrode 10a of the component is aligned with the center position of the conductor pad 2a.
If the position is shifted due to the covering with the R film, the position is shifted from the proper position of the electrode 10a of the component to be bonded on the conductive pad, which causes a bonding failure or a component position shift.

【0006】図6(a)(b)及び(c)はこの事情を
説明するためのプリント配線基板母材の平面図、電子部
品を搭載した状態の個片の拡大図及び部品未搭載状態の
個片の拡大図である。即ち、プリント配線基板母材は、
該母材を構成する絶縁基板1の部品搭載領域1Aを、配
線パターン2を構成する導体パッド2aだけを露出させ
た状態でソルダーレジスト膜(以下、SR膜、という)
3によってほぼ全面被覆した構成を備えている。また、
部品搭載領域1Aの外側に位置する外側領域(絶縁基板
面露出領域)1Bの適所、例えば4つの角隅部には、導
体パターンから成る認識マーク5が形成されている。こ
の認識マーク5は、対をなす導体パッド2a上に一つの
電子部品10を搭載する際に、部品搭載位置を知るため
の基準点となる部分である。即ち、電子部品を自動的に
搭載する装置は、画像読み取り手段等によって得た認識
マーク5の座標位置についての情報を基準として、予め
メモリされている各導体パッドについてのx、y座標値
から各導体パッド2aの位置を判定し、判定した座標位
置に部品を搭載するように構成されている。外側領域1
B上にも、認識マーク5を除いた全域にSR膜3が形成
されている。
FIGS. 6 (a), 6 (b) and 6 (c) are plan views of a printed wiring board base material for explaining this situation, an enlarged view of an individual piece with electronic components mounted thereon, and a state in which no components are mounted. It is an enlarged view of an individual piece. That is, the printed wiring board base material is
A solder resist film (hereinafter, referred to as an SR film) is formed on the component mounting area 1A of the insulating substrate 1 constituting the base material with only the conductor pads 2a constituting the wiring pattern 2 exposed.
3 to cover almost the entire surface. Also,
A recognition mark 5 made of a conductor pattern is formed at an appropriate position, for example, at four corners of an outer region (exposed region of the insulating substrate surface) 1B located outside the component mounting region 1A. The recognition mark 5 is a portion serving as a reference point for knowing a component mounting position when one electronic component 10 is mounted on the pair of conductor pads 2a. That is, the device that automatically mounts the electronic component uses the information about the coordinate position of the recognition mark 5 obtained by the image reading means or the like as a reference, and calculates the x and y coordinate values for each of the conductor pads stored in advance. The position of the conductive pad 2a is determined, and the component is mounted at the determined coordinate position. Outer area 1
Also on B, the SR film 3 is formed over the entire area excluding the recognition mark 5.

【0007】SR膜3を絶縁基板1上の部品搭載領域1
Aに形成する場合には、上記のように導体パッド2aに
対応する部分だけにSR膜3が付着しないように構成し
たシルクスクリーンを用いて、それ以外の部分にSR膜
3を一括してスクリーン印刷するが、この際に最大±
0.05mmの範囲でx方向、或いはy方向、その他の
方向に印刷位置がずれた場合には、図7(a)の右側の
電子部品のようにSR膜3aによって導体パッド2aの
一部が被覆されて、本来の導体パッド中心位置C(実線
図示)に対して、実際の導体パッド中心位置は鎖線で示
した中心位置C’に移動する。しかし、自動部品搭載装
置は、SR膜が導体パターンに被っていることを認識で
きないため、読み取った認識マーク5の座標位置を手が
かりとして一義的に各導体パッド上に電子部品を搭載す
る作業を実施する。従って、電子部品の電極10aは、
導体パッド本来の中心位置C(実線図示)を基準として
導体パッド上に載置されることとなる。このため、電極
の一部はクリームハンダ6が付着しにくいSR膜(導体
パッドとのオーバーラップ部)上にも跨って載置される
こととなり、接合に寄与する導体パッド面積(ハンダ
量)が減少するため、十分な接合強度を得ることが困難
となる。この結果、導体パッドごとに接合強度にばらつ
きを持つこととなり、品質が不安定となる。また、図7
(b)に示すように、前記導体パッド上に被さったSR
膜部分上にクリームハンダ6を介して電極の一部が載置
された場合には、リフロー時に溶融してから硬化する過
程で発生するハンダのセルフアラインメント作用によっ
て部品が位置ずれ(実際の露出面の中心位置C’への移
動)を起こす、という不具合がある。更に、導体パッド
上に被さったSR膜上にクリームハンダ6が印刷される
と、SR膜上のクリームハンダ6は溶融、固着しずらい
ため、ハンダボール6a等の不良現象が発生する。ハン
ダボールは基板上を転がって移動しやすい為、他の導体
部分に付着して導体間をショートさせる原因となる。
[0007] The SR film 3 is placed on the component mounting area 1 on the insulating substrate 1.
In the case where the SR film 3 is formed on the area A, a silk screen configured so that the SR film 3 does not adhere only to the portion corresponding to the conductor pad 2a is used, and the SR film 3 is collectively screened on other portions. Print, but at this time
When the printing position is shifted in the x direction, the y direction, or other directions within the range of 0.05 mm, a part of the conductor pad 2a is formed by the SR film 3a as in the electronic component on the right side of FIG. After being covered, the actual center position of the conductor pad moves to the center position C ′ indicated by a chain line with respect to the center position C of the original conductor pad (shown by a solid line). However, since the automatic component mounting apparatus cannot recognize that the SR film covers the conductor pattern, the work of uniquely mounting the electronic component on each conductor pad is performed using the coordinate position of the read recognition mark 5 as a clue. I do. Therefore, the electrode 10a of the electronic component is
The conductive pad is placed on the conductive pad with reference to the original center position C (shown by a solid line). For this reason, a part of the electrode is placed over the SR film (the overlap portion with the conductor pad) to which the cream solder 6 is not easily attached, and the area of the conductor pad (solder amount) contributing to the bonding is reduced. Because of the decrease, it is difficult to obtain sufficient bonding strength. As a result, the bonding strength varies among the conductive pads, and the quality becomes unstable. FIG.
(B) As shown in FIG.
When a part of the electrode is placed on the film portion via the cream solder 6, the component is misaligned (actually exposed surface) due to the self-alignment action of the solder generated in the process of melting and hardening during reflow. To the center position C '). Further, when the cream solder 6 is printed on the SR film covering the conductor pad, the cream solder 6 on the SR film is hardly melted and fixed, so that a defective phenomenon such as a solder ball 6a occurs. Since the solder balls roll easily on the substrate and move, they adhere to other conductor parts and cause a short circuit between the conductors.

【0008】[0008]

【発明が解決しようとする課題】本発明は上記に鑑みて
なされたものであり、配線パターンを備えた絶縁基板上
の特定領域にSR膜を被覆形成すると共に、0.2mm
未満の間隔で隣接配置された2つの導体パッド間に0.
1mm幅のSR膜を配置した構成を備えたプリント配線
基板において、プリント配線基板面を被覆するSR膜の
位置ずれに起因した種々の不具合が発生することがない
ようにした高密度実装用プリント配線基板及びソルダー
レジスト膜の形成方法を提供することを課題とする。具
体的には、従来、SR膜が位置ずれを起こして導体パッ
ド上に被さることによって発生していた電子部品の搭載
不良、導体パッド間のハンダブリッジ、その他の不具合
を一挙に解決することを課題とする。
SUMMARY OF THE INVENTION The present invention has been made in view of the above, and has been made in consideration of the above problem.
The distance between two conductive pads adjacent to each other at a distance of less than 0.1.
A printed wiring board for high-density mounting in which a printed wiring board having a configuration in which an SR film having a width of 1 mm is disposed is free from various problems due to a displacement of the SR film covering the printed wiring board surface. It is an object to provide a method for forming a substrate and a solder resist film. More specifically, it is an object of the present invention to solve at once a poor mounting of an electronic component, a solder bridge between the conductive pads, and other problems that have been caused by the SR film being displaced and covering the conductive pads. And

【0009】[0009]

【課題を解決するための手段】上記課題を解決するた
め、本発明の請求項1は、絶縁基板と、該絶縁基板面に
形成した導体パッドを含む配線パターンと、少なくとも
導体パッドを除いた絶縁基板表面を被覆するソルダーレ
ジストと、を備えた高密度実装用プリント配線基板にお
いて、隣接し合う前記導体パッド間の間隔を微小幅に設
定する一方で、各導体パッドの面積を電子部品の電極を
接合するために必要な面積よりも所要値だけ広くし、前
記ソルダーレジストは各導体パッドを露出させる開口部
を備え、該開口部の開口面積を該開口部が導体パッドの
面積内に包含されるように狭くし、前記ソルダーレジス
トが位置ずれを起こしていない正規の状態においては、
各開口部は導体パッドの中央部に包含された状態とな
り、この際の開口部周縁と導体パッド周縁との間隔は、
ソルダーレジストの最大位置ずれ量と同等か、それ以上
であることを特徴とする。
In order to solve the above problems, a first aspect of the present invention is an insulating substrate, a wiring pattern including a conductive pad formed on the insulating substrate surface, and an insulating pattern excluding at least the conductive pad. A solder resist that covers the surface of the substrate, and in a printed wiring board for high-density mounting, comprising: The solder resist is provided with an opening for exposing each conductive pad, and the opening area of the opening is included in the area of the conductive pad. In a normal state where the solder resist has not been misaligned,
Each opening is included in the center of the conductor pad, and the interval between the periphery of the opening and the periphery of the conductor pad at this time is
It is characterized in that it is equal to or larger than the maximum displacement of the solder resist.

【0010】請求項2は、面上に部品搭載用の導体パッ
ドを含む配線パターンを備えた絶縁基板個片を複数連結
した構造の部品搭載領域と、該部品搭載領域の外周縁に
連接配置され且つ少なくとも一つの認識マークを備えた
外側領域と、を一体化したプリント配線基板母材であっ
て、少なくとも前記導体パッドを除いた部品搭載領域
上、及び、少なくとも前記認識マークを除いた外側領域
上に夫々ソルダーレジストを被覆し、隣接し合う前記導
体パッド間の間隔を微小幅に設定する一方で、各導体パ
ッドの面積を電子部品の電極を接合するために必要な面
積よりも所要値だけ広くし、前記部品搭載領域を被覆す
るソルダーレジストは各導体パッドを露出させる開口部
を備え、該開口部の開口面積を該開口部が導体パッドの
面積内に包含されるように狭くし、前記ソルダーレジス
トが位置ずれを起こしていない正規の状態においては、
各開口部は導体パッドの中央部に包含された状態とな
り、この際の開口部周縁と導体パッド周縁との間隔は、
ソルダーレジストの最大位置ずれ量と同等か、それ以上
であり、前記外側領域を被覆するソルダーレジストは、
前記認識マークを露出させる外側開口部を備え、該外側
開口部の開口面積を該外側開口部が認識マークの面積内
に包含されるように狭くし、前記ソルダーレジストが位
置ずれを起こしていない正規の状態においては、外側開
口部は認識マークの中央部に包含された状態となり、こ
の際の外側開口部周縁と認識マーク周縁との間隔は、ソ
ルダーレジストの最大位置ずれ量と同等か、それ以上に
設定されていることを特徴とする。
According to a second aspect of the present invention, there is provided a component mounting region having a structure in which a plurality of insulating substrate pieces each having a wiring pattern including a component mounting conductor pad on a surface are connected, and an outer peripheral edge of the component mounting region. And an outer region provided with at least one recognition mark, and at least a component mounting region excluding the conductor pad and an outer region excluding at least the recognition mark. Each is covered with a solder resist, and the interval between the adjacent conductor pads is set to a minute width, while the area of each conductor pad is increased by a required value larger than the area required for joining the electrodes of the electronic component. The solder resist covering the component mounting area includes an opening for exposing each conductive pad, and the opening area of the opening is included in the area of the conductive pad. Uni narrowed, in the state of regular the solder resist is not misaligned, the
Each opening is included in the center of the conductor pad, and the interval between the periphery of the opening and the periphery of the conductor pad at this time is
The maximum displacement amount of the solder resist is equal to or greater than the maximum, and the solder resist covering the outer region is
An outer opening for exposing the recognition mark is provided, and the opening area of the outer opening is narrowed so that the outer opening is included in the area of the recognition mark. In the state of the above, the outer opening is included in the center of the recognition mark, and the interval between the outer opening periphery and the recognition mark periphery at this time is equal to or larger than the maximum displacement amount of the solder resist. Is set to.

【0011】[0011]

【発明の実施の形態】以下、本発明を図面に示した実施
の形態により詳細に説明する。図1(a)及び(b)は
本発明の一実施形態に係る高密度実装用プリント配線基
板の要部の構成を示す拡大平面図である。なお、図6を
併せて参照しつつ説明する。この高密度実装用プリント
配線基板(以下、単に、プリント配線基板、という)
は、配線パターン2を備えた絶縁基板1上に、配線パタ
ーン2を構成する導体パッド2aの一部が露出するよう
にスクリーン印刷によってソルダーレジスト膜(以下、
SR膜、という)3を被覆形成した構成を備えている。
具体的には、本実施形態においては、隣接し合う導体パ
ッド2a間の間隔をSR膜3形成時の最大ばらつき値で
ある0.05mmの2倍分(0.1mm)だけ狭くする
と同時に、導体パッド2aの面積を図4、図5などに示
した本来必要な接合面積よりも拡大した構成を備えてい
る。一方、SR膜3に関しては、導体パッド2aに対応
する位置に導体パッド2aの面積よりも狭い開口面積を
備えた開口部20を設けて開口部20内に導体パッド2
aの一部を露出させるように構成している。この開口部
20の開口面積は、接合対象である電子部品10の電極
10aをハンダ接合するのに本来必要な面積と同等に設
定する。従って例えば導体パッド2a間の間隔を微小
幅、例えば0.2mm未満(例えば0.15mm)に設
定した場合に、図1(a)に示すようにSR膜3が位置
ずれすることなく基板1上に印刷された場合には、開口
部20が導体パッド2aの面積内中央部に完全に収まる
ように構成する。なお、導体パッド2a間に位置するS
R膜3の幅は0.1mmを越えているため、絶縁基板面
との接合力は十分に確保されている。図1(a)に示し
た如くSR膜3が正規の位置に印刷された場合において
開口部20の内周縁と対応する導体パッド2aの外周縁
との間の幅は、少なくともSR膜3形成時の最大ばらつ
き値である0.05mmに相当しているため、仮に
(b)に示すようにSR膜3の形成位置が右方向へ最大
0.05mm位置ずれしたとしても、2つの開口部20
は各導体パッド2aの端縁を越えることがなく、依然と
して導体パッドの面積内に収まることができる。このこ
とは、開口部20内に露出する導体パッドの面積が常に
電子部品の電極の接合に必要十分な面積を維持している
ことを意味する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to embodiments shown in the drawings. FIGS. 1A and 1B are enlarged plan views showing the configuration of a main part of a printed wiring board for high-density mounting according to an embodiment of the present invention. The description will be made with reference to FIG. This printed wiring board for high-density mounting (hereinafter simply referred to as a printed wiring board)
A solder resist film (hereinafter, referred to as a screen resist) formed on the insulating substrate 1 provided with the wiring pattern 2 by screen printing so that a part of the conductor pad 2a constituting the wiring pattern 2 is exposed.
SR film 3).
Specifically, in the present embodiment, the interval between the adjacent conductor pads 2a is reduced by twice (0.1 mm) twice the maximum variation value of 0.05 mm when the SR film 3 is formed, and at the same time, the distance between the adjacent conductor pads 2a is reduced. The pad 2a has a configuration in which the area of the pad 2a is larger than the originally required bonding area shown in FIGS. On the other hand, regarding the SR film 3, an opening 20 having an opening area smaller than the area of the conductor pad 2a is provided at a position corresponding to the conductor pad 2a, and the conductor pad 2 is provided in the opening 20.
It is configured to expose a part of “a”. The opening area of the opening 20 is set to be equal to the area originally required for soldering the electrode 10a of the electronic component 10 to be joined. Therefore, for example, when the interval between the conductor pads 2a is set to a small width, for example, less than 0.2 mm (for example, 0.15 mm), the SR film 3 is not displaced on the substrate 1 as shown in FIG. Is printed so that the opening 20 completely fits in the center of the area of the conductive pad 2a. Note that S located between the conductor pads 2a
Since the width of the R film 3 exceeds 0.1 mm, the bonding strength with the insulating substrate surface is sufficiently ensured. When the SR film 3 is printed at a regular position as shown in FIG. 1A, the width between the inner peripheral edge of the opening 20 and the outer peripheral edge of the corresponding conductor pad 2a is at least at the time of forming the SR film 3. Therefore, even if the formation position of the SR film 3 is displaced by a maximum of 0.05 mm to the right as shown in FIG.
Does not exceed the edge of each conductor pad 2a and can still fit within the area of the conductor pad. This means that the area of the conductive pad exposed in the opening 20 always maintains a sufficient and necessary area for bonding the electrodes of the electronic component.

【0012】更に、本発明の特徴的な構成は、図6に示
した外側領域1Bに相当する絶縁基板面にもSR膜3を
被覆形成した構成にある。この外側領域1B上のSR膜
3は、円形の認識マーク5に相当する位置に小径円形の
外側開口部25を備えている。認識マーク5を露出させ
るために形成した外側開口部25は、その開口面積を該
外側開口部が認識マークの面積内に包含されるように狭
く(小径に)設定されている。つまり、ソルダーレジス
トが位置ずれを起こしていない正規の状態(図2(a)
の状態)においては、外側開口部25は認識マーク5の
中央部に同心円状に包含された状態となり、この際の外
側開口部周縁と認識マーク周縁との間隔Lは、ソルダー
レジストSR膜3の最大位置ずれ量(±0.05mm)
と同等か、それ以上に設定されている。これを換言すれ
ば、外側開口部25に対応する認識マーク5の面積は、
ソルダーレジスト膜SR3の最大位置ずれ量の2倍分だ
け直径が拡大されているため、いずれの方向にソルダー
レジスト膜が位置ずれを起こしたとしても外側開口部2
5は認識マーク5の面積内から脱落することがなくな
る。また、部品搭載領域1A内のソルダーレジストと外
側領域1B上のソルダーレジストは、いずれも単一のシ
ルクスクリーンを用いて一括して形成されるため、位置
ずれも全体として同一方向に同一距離だけ発生する。従
って、外側開口部25に位置ずれが発生している場合に
は、開口部20についても同一方向に同一距離だけ位置
ずれが発生していることになる。
Further, the characteristic configuration of the present invention is that the SR film 3 is formed so as to cover the insulating substrate surface corresponding to the outer region 1B shown in FIG. The SR film 3 on the outer region 1B has a small-diameter circular outer opening 25 at a position corresponding to the circular recognition mark 5. The outer opening 25 formed to expose the recognition mark 5 is set to have a narrow (small diameter) opening area such that the outer opening is included in the area of the recognition mark. In other words, a normal state where the solder resist has not been displaced (FIG. 2A)
In the state (2), the outer opening 25 is concentrically included in the center of the recognition mark 5. At this time, the distance L between the outer opening periphery and the recognition mark periphery is determined by the solder resist SR film 3. Maximum displacement (± 0.05mm)
Is equal to or greater than In other words, the area of the recognition mark 5 corresponding to the outer opening 25 is
Since the diameter is enlarged by twice the maximum displacement amount of the solder resist film SR3, even if the solder resist film is displaced in any direction, the outer opening 2 is formed.
5 does not fall out of the area of the recognition mark 5. In addition, since the solder resist in the component mounting area 1A and the solder resist in the outer area 1B are formed collectively by using a single silk screen, a positional shift occurs in the same direction and the same distance as a whole. I do. Therefore, when a position shift occurs in the outer opening 25, the position shift also occurs in the opening 20 by the same distance in the same direction.

【0013】外側開口部25と認識マーク5との関係と
同様に、開口部20と導体パッド2aとの関係について
も、どの方向にSR膜3の位置ずれが発生しようと、許
容される最大ずれ幅(例えば、±0.05mm)の範囲
内である限り、開口部20は導体パッド2aの面積内に
収まっている。一方、自動部品搭載装置は、外側開口2
5内に露出した円形の認識マーク5の中心部を読み取り
手段によって認識した上で、該中心部の座標に基づいて
各導体パッド2aの位置を割り出し、当該導体パッド上
に電子部品の電極が正しく載置されるように電子部品を
搭載する。従って、SR膜3の位置ずれ幅が、許容され
る最大ずれ幅の範囲内である限り、認識マーク5の中心
部を基準として判定される導体パッドの位置座標は常に
正確なものとなり、電子部品の電極は開口部20内に露
出した導体パッド面に正しく載置される。従って、導体
パッドと部品の電極との間の接合面積、及び接合に使用
可能なハンダの量は必要十分となり、接合不良の発生を
有効に防止できる。導体パッド間の接合力のばらつきに
起因したセルフアラインメントによる部品搭載位置のず
れも防止できる。また、部品搭載に先立って、開口部2
0内に露出した導体パッド面上だけに狙いを定めてクリ
ームハンダを正確に塗布することが可能となるため、導
体パッド面に被さったSR膜上にクリームハンダが付着
することが無くなり、ハンダボールの形成とそれに起因
した不具合が解決される。また、導体パッド間に0.1
mm以上の十分な幅を有したSR膜が介在することにな
るため、導体パッド間のハンダブリッジ発生率を大幅に
減少させることができる。
As with the relationship between the outer opening 25 and the recognition mark 5, the relationship between the opening 20 and the conductor pad 2a is the maximum allowable deviation regardless of the direction in which the SR film 3 is displaced. As long as the width is within a range (for example, ± 0.05 mm), the opening 20 is within the area of the conductive pad 2a. On the other hand, the automatic component mounting device
After recognizing the center of the circular recognition mark 5 exposed in the reading means 5 by the reading means, the position of each conductor pad 2a is determined based on the coordinates of the center, and the electrode of the electronic component is correctly positioned on the conductor pad. The electronic components are mounted so as to be mounted. Accordingly, as long as the positional shift width of the SR film 3 is within the range of the maximum allowable shift width, the positional coordinates of the conductor pads determined with reference to the center of the recognition mark 5 are always accurate, and Are correctly mounted on the conductor pad surface exposed in the opening 20. Therefore, the bonding area between the conductive pad and the electrode of the component and the amount of solder that can be used for bonding are necessary and sufficient, and the occurrence of poor bonding can be effectively prevented. The displacement of the component mounting position due to the self-alignment due to the variation in the bonding force between the conductive pads can be prevented. Prior to component mounting, the opening 2
The cream solder can be accurately applied by aiming only on the surface of the conductor pad exposed in the inside of the solder pad, so that the cream solder does not adhere to the SR film covering the conductor pad surface, and the solder ball And the problems caused by the formation are solved. Also, 0.1
Since the SR film having a sufficient width of at least mm is interposed, the occurrence rate of the solder bridge between the conductor pads can be significantly reduced.

【0014】なお、本発明に係る導体パッドの構成は、
隣接配置された少なくとも2つの導体パッド間の間隔を
0.2mm未満の値に狭く設定し、且つ該間隔内に最小
幅のSR膜を形成する場合に適用可能である。従って、
隣接し合う2つの電子部品を夫々搭載する各導体パッド
間の間隔が0.2mm未満である場合のみならず、一つ
の電子部品を搭載する複数の導体パッド間の間隔が0.
2mm未満である場合にも適用可能である。なお、プリ
ント配線基板母材において、外側領域の形状は図6
(a)に示した如く部品搭載領域1A全体を環状に包囲
する形状に限るわけではなく、部品搭載領域1Aの外周
縁に沿って連接された領域であればどのような形状であ
ってもよい。
The structure of the conductor pad according to the present invention is as follows.
The present invention can be applied to the case where the distance between at least two adjacently arranged conductor pads is set to a value smaller than 0.2 mm and the SR film having the minimum width is formed within the distance. Therefore,
Not only is the distance between each of the conductor pads on which two adjacent electronic components are mounted less than 0.2 mm, but also the distance between the plurality of conductor pads on which one electronic component is mounted is 0.
The present invention is applicable to a case where the distance is less than 2 mm. The shape of the outer region of the printed wiring board base material is shown in FIG.
As shown in (a), the shape is not limited to the shape surrounding the whole component mounting area 1A in a ring shape, but may be any shape as long as it is an area connected along the outer peripheral edge of the component mounting area 1A. .

【0015】[0015]

【発明の効果】以上のように本発明に依れば、配線パタ
ーンを備えた絶縁基板上にソルダーレジスト膜を被覆形
成すると共に、微小間隔(例えば、0.2mm未満の間
隔)で隣接配置された2つの導体パッド間に最小幅(例
えば、0.1mm幅)のSR膜を配置した構成を備えた
プリント配線基板において、プリント配線基板面を被覆
するSR膜の位置ずれに起因した種々の不具合、具体的
には、SR膜が位置ずれを起こして導体パッド上に被さ
ることによって発生していた電子部品の搭載不良、導体
パッド間のハンダブリッジ、その他の不具合を一挙に解
決することができる。
As described above, according to the present invention, a solder resist film is formed on an insulating substrate provided with a wiring pattern, and the solder resist film is disposed adjacently at a small interval (for example, an interval of less than 0.2 mm). In a printed wiring board having a configuration in which an SR film having a minimum width (for example, 0.1 mm width) is disposed between two conductive pads, various problems caused by a displacement of the SR film covering the printed wiring board surface More specifically, the mounting failure of the electronic component, the solder bridge between the conductive pads, and other problems caused by the SR film being displaced and covering the conductive pads can be solved at once.

【図面の簡単な説明】[Brief description of the drawings]

【図1】(a)(b)は本発明の一実施形態に係る高密
度実装用プリント配線基板の要部の構成を示す拡大平面
図。
FIGS. 1A and 1B are enlarged plan views showing a configuration of a main part of a printed wiring board for high-density mounting according to an embodiment of the present invention.

【図2】(a)(b)はソルダーレジストの位置関係を
説明する図。
FIGS. 2A and 2B are views for explaining a positional relationship between solder resists.

【図3】プリント配線基板上に電子部品を搭載した状態
を示す平面図。
FIG. 3 is a plan view showing a state where electronic components are mounted on a printed wiring board.

【図4】(a)(b)は隣接し合う導体パッド間に位置
する絶縁基板1面に細幅帯状のSR膜を配置して2つの
導体パッド間でのクリームハンダの流動を遮断する構成
を示す拡大図。
FIGS. 4A and 4B show a configuration in which a narrow strip-shaped SR film is arranged on the surface of an insulating substrate 1 located between adjacent conductive pads to block the flow of cream solder between two conductive pads; FIG.

【図5】(a)(b)は導体パッド間隔を0.15mm
に減縮した状態を示す図。
FIGS. 5 (a) and 5 (b) show conductor pad intervals of 0.15 mm.
FIG.

【図6】(a)(b)(c)は従来のプリント配線基板
母材の平面図、電子部品を搭載した状態の個片の拡大
図、及び部品未搭載状態の個片の拡大図。
6 (a), (b) and (c) are a plan view of a conventional printed wiring board base material, an enlarged view of an individual piece with electronic components mounted thereon, and an enlarged view of an individual piece with no components mounted thereon.

【図7】(a)(b)は従来例の欠点を説明する図。FIGS. 7A and 7B are diagrams for explaining the drawbacks of the conventional example.

【符号の説明】[Explanation of symbols]

1 絶縁基板、2 配線パターン、2a 導体パッド、
3、3a ソルダーレジスト膜(SR膜)、5 認識マ
ーク、6 クリームハンダ、10 電子部品、10a
電極、20 開口部、25 外側開口部。
1 insulating substrate, 2 wiring pattern, 2a conductive pad,
3, 3a Solder resist film (SR film), 5 recognition mark, 6 cream solder, 10 electronic components, 10a
Electrodes, 20 openings, 25 outer openings.

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 絶縁基板と、該絶縁基板面に形成した導
体パッドを含む配線パターンと、少なくとも導体パッド
を除いた絶縁基板表面を被覆するソルダーレジストと、
を備えた高密度実装用プリント配線基板において、 隣接し合う前記導体パッド間の間隔を微小幅に設定する
一方で、各導体パッドの面積を電子部品の電極を接合す
るために必要な面積よりも所要値だけ広くし、 前記ソルダーレジストは各導体パッドを露出させる開口
部を備え、該開口部の開口面積を該開口部が導体パッド
の面積内に包含されるように狭くし、 前記ソルダーレジストが位置ずれを起こしていない正規
の状態においては、各開口部は導体パッドの中央部に包
含された状態となり、この際の開口部周縁と導体パッド
周縁との間隔は、ソルダーレジストの最大位置ずれ量と
同等か、それ以上であることを特徴とする高密度実装用
プリント配線基板。
An insulating substrate, a wiring pattern including a conductive pad formed on the insulating substrate surface, a solder resist covering at least the insulating substrate surface excluding the conductive pad,
In the printed wiring board for high-density mounting provided with, while setting the interval between the adjacent conductor pads to a minute width, the area of each conductor pad is larger than the area required for joining the electrodes of the electronic component. The solder resist is provided with an opening for exposing each conductive pad, and the opening area of the opening is narrowed so that the opening is included in the area of the conductive pad. In a normal state where no displacement has occurred, each opening is included in the center of the conductor pad, and the interval between the periphery of the opening and the periphery of the conductor pad is the maximum displacement of the solder resist. A printed wiring board for high-density mounting, which is equal to or more than.
【請求項2】 面上に部品搭載用の導体パッドを含む配
線パターンを備えた絶縁基板個片を複数連結した構造の
部品搭載領域と、該部品搭載領域の外周縁に連接配置さ
れ且つ少なくとも一つの認識マークを備えた外側領域
と、を一体化したプリント配線基板母材であって、 少なくとも前記導体パッドを除いた部品搭載領域上、及
び、少なくとも前記認識マークを除いた外側領域上に夫
々ソルダーレジストを被覆し、 隣接し合う前記導体パッド間の間隔を微小幅に設定する
一方で、各導体パッドの面積を電子部品の電極を接合す
るために必要な面積よりも所要値だけ広くし、 前記部品搭載領域を被覆するソルダーレジストは各導体
パッドを露出させる開口部を備え、該開口部の開口面積
を該開口部が導体パッドの面積内に包含されるように狭
くし、 前記ソルダーレジストが位置ずれを起こしていない正規
の状態においては、各開口部は導体パッドの中央部に包
含された状態となり、この際の開口部周縁と導体パッド
周縁との間隔は、ソルダーレジストの最大位置ずれ量と
同等か、それ以上であり、 前記外側領域を被覆するソルダーレジストは、前記認識
マークを露出させる外側開口部を備え、該外側開口部の
開口面積を該外側開口部が認識マークの面積内に包含さ
れるように狭くし、 前記ソルダーレジストが位置ずれを起こしていない正規
の状態においては、外側開口部は認識マークの中央部に
包含された状態となり、この際の外側開口部周縁と認識
マーク周縁との間隔は、ソルダーレジストの最大位置ず
れ量と同等か、それ以上に設定されていることを特徴と
する高密度実装用プリント配線基板母材。
2. A component mounting region having a structure in which a plurality of insulating substrate pieces each having a wiring pattern including a component mounting conductor pad on a surface are connected, and at least one of the component mounting regions is connected to an outer peripheral edge of the component mounting region. A printed wiring board base material integrated with an outer region provided with two recognition marks, and at least on a component mounting region excluding the conductor pad and at least on an outer region excluding the recognition mark. While covering with a resist, the interval between the adjacent conductor pads is set to a very small width, while the area of each conductor pad is made larger by a required value than the area required for joining the electrodes of the electronic component, The solder resist covering the component mounting area has an opening for exposing each conductive pad, and the opening area of the opening is reduced so that the opening is included in the area of the conductive pad. However, in a normal state where the solder resist has not been displaced, each opening is included in the center of the conductor pad, and the gap between the periphery of the opening and the periphery of the conductor pad at this time is The maximum displacement of the resist is equal to or greater than the maximum, and the solder resist covering the outer region includes an outer opening for exposing the recognition mark, and the outer opening has an opening area of the outer opening. In a normal state in which the solder resist has not been displaced, the outer opening is in the state of being included in the center of the recognition mark. The distance between the periphery of the opening and the periphery of the recognition mark is set to be equal to or larger than the maximum positional deviation amount of the solder resist. Cement wiring substrate base material.
JP2001065620A 2001-03-08 2001-03-08 Printed wiring board for high density mounting and base material therefor Pending JP2002271009A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2001065620A JP2002271009A (en) 2001-03-08 2001-03-08 Printed wiring board for high density mounting and base material therefor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001065620A JP2002271009A (en) 2001-03-08 2001-03-08 Printed wiring board for high density mounting and base material therefor

Publications (1)

Publication Number Publication Date
JP2002271009A true JP2002271009A (en) 2002-09-20

Family

ID=18924237

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001065620A Pending JP2002271009A (en) 2001-03-08 2001-03-08 Printed wiring board for high density mounting and base material therefor

Country Status (1)

Country Link
JP (1) JP2002271009A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101008422B1 (en) 2008-10-27 2011-01-14 삼성전기주식회사 Printed circuit board manufacturing method
CN107529280A (en) * 2017-08-31 2017-12-29 郑州云海信息技术有限公司 The method and device that a kind of Foot print are established
CN110618658A (en) * 2019-08-20 2019-12-27 深圳模德宝科技有限公司 Method, system and readable storage medium for recording offset value of electrode center
CN113314498A (en) * 2021-05-25 2021-08-27 业成科技(成都)有限公司 Circuit board, lamp panel, backlight module and display device
WO2021235196A1 (en) * 2020-05-21 2021-11-25 パナソニックIpマネジメント株式会社 Mounting structure for chip component
JP2022014122A (en) * 2020-07-06 2022-01-19 日本特殊陶業株式会社 Wiring board

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101008422B1 (en) 2008-10-27 2011-01-14 삼성전기주식회사 Printed circuit board manufacturing method
CN107529280A (en) * 2017-08-31 2017-12-29 郑州云海信息技术有限公司 The method and device that a kind of Foot print are established
CN110618658A (en) * 2019-08-20 2019-12-27 深圳模德宝科技有限公司 Method, system and readable storage medium for recording offset value of electrode center
WO2021235196A1 (en) * 2020-05-21 2021-11-25 パナソニックIpマネジメント株式会社 Mounting structure for chip component
JP7522973B2 (en) 2020-05-21 2024-07-26 パナソニックIpマネジメント株式会社 Chip component mounting structure
JP2022014122A (en) * 2020-07-06 2022-01-19 日本特殊陶業株式会社 Wiring board
JP7386139B2 (en) 2020-07-06 2023-11-24 日本特殊陶業株式会社 wiring board
CN113314498A (en) * 2021-05-25 2021-08-27 业成科技(成都)有限公司 Circuit board, lamp panel, backlight module and display device
CN113314498B (en) * 2021-05-25 2023-05-05 业成科技(成都)有限公司 Circuit board, lamp panel, backlight module and display device

Similar Documents

Publication Publication Date Title
US7071574B1 (en) Semiconductor device and its wiring method
US10667387B2 (en) Accurate positioning and alignment of a component during processes such as reflow soldering
JP3656543B2 (en) Electronic component mounting method
JPH05144880A (en) Electrode structure of wiring board
KR20070011168A (en) Mounting board and electronic parts mounting method
JPH10189806A (en) Semiconductor device and junction structure of semiconductor device and substrate
JP2002271009A (en) Printed wiring board for high density mounting and base material therefor
JPH10284812A (en) Semiconductor device
JP3588800B2 (en) Method of transferring conductor pattern to film carrier and method of mounting electronic component element on film carrier
KR20070062079A (en) Printed circuit board having align mark and manufacturing method thereof
JPH1027950A (en) Printed wiring board
JP2002353578A (en) Substrate for surface-mounted component, and method of mounting the surface-mounted component on substrate
JPH05335438A (en) Leadless chip carrier
JPH09214114A (en) Printed wiring board manufacture
JPH0697634A (en) Printed wiring board for flip chip
JPH05283825A (en) Printed-circuit board with identification mark
JP2002280681A (en) Method for manufacturing part mounting board and printed wiring board
JPH06326446A (en) Board and manufacture thereof
JPH0613741A (en) Circuit board for surface mount component
JP4007343B2 (en) Method for transferring conductor pattern to film carrier and film carrier
JP2706673B2 (en) Printed wiring board
JPH09172037A (en) Semiconductor device and manufacturing method thereof
JPH0927666A (en) Mounting structure of chip component on wiring board
JPH0441580Y2 (en)
JPH0265295A (en) Printed board