JPS5853890A - Method of soldering electronic part - Google Patents

Method of soldering electronic part

Info

Publication number
JPS5853890A
JPS5853890A JP15245981A JP15245981A JPS5853890A JP S5853890 A JPS5853890 A JP S5853890A JP 15245981 A JP15245981 A JP 15245981A JP 15245981 A JP15245981 A JP 15245981A JP S5853890 A JPS5853890 A JP S5853890A
Authority
JP
Japan
Prior art keywords
soldering
solder
present
electronic components
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15245981A
Other languages
Japanese (ja)
Inventor
吉岡 公男
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Fuji Electric Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd, Fuji Electric Manufacturing Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP15245981A priority Critical patent/JPS5853890A/en
Publication of JPS5853890A publication Critical patent/JPS5853890A/en
Pending legal-status Critical Current

Links

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 本発明はプリント回路基板、及びノ1イブリッドICに
おける電子部品のはんだ付は方法に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to printed circuit boards and methods for soldering electronic components in hybrid ICs.

通常、電子部品の実親基板でははんだのぬれ残りがなく
、一様にはんだ付けされることが望まれる。
Normally, it is desired that the actual mother board of an electronic component be soldered uniformly without any residual solder.

第1図に、銅張機脂積層板1上に電子部品をはんだ付け
した状態の概略図を示す。この鴇の従来はんだ付は方法
は銅箔をエツチング勢の手段により所望の配線パターン
2に形成した後、はんだ付けの不必要な部分ヘソルダー
レジスト(図では示されていない)を形成すること番こ
より行なわれ、概略図ではリードを有する電子部品3が
丸形電極部4へ、リードレス電子部品5が角形電極部6
へ各々取り付けられている。
FIG. 1 shows a schematic diagram of electronic components soldered onto a copper-clad machine resin laminate 1. As shown in FIG. The conventional soldering method for this method is to form the copper foil into the desired wiring pattern 2 by etching, and then to form a solder resist (not shown in the figure) on the parts where soldering is unnecessary. In the schematic diagram, the electronic component 3 with leads is connected to the round electrode part 4, and the leadless electronic component 5 is connected to the square electrode part 6.
are attached to each.

このような構成において17本発明の対象とするところ
は、ソルダーレジストの形成方法にあり、以下にその従
来方法について説明する。
In such a configuration, the object of the present invention is a method of forming a solder resist, and a conventional method thereof will be described below.

第2図及び第3図は、第1図において示された一体の電
極部である丸形電極部4の拡大図である。
2 and 3 are enlarged views of the round electrode portion 4, which is an integral electrode portion shown in FIG. 1. FIG.

丸形電極部4は2つのリード挿入穴7を持ちはんだの不
要部分への付着防止の為、はんだ付は領域8以外はソル
ダーレジスト9(斜線部分)で種われている。第4図は
角形電極部6の拡大図であり、第5図に電子部品を搭載
した状態を示す。いずれの電極部においても、リード及
び電子部、品牽相対してはんだ付けする為、電極部のほ
ぼ中央近くでソルダーレジスト9により分離されている
The round electrode part 4 has two lead insertion holes 7, and in order to prevent solder from adhering to unnecessary parts, solder resist 9 (shaded areas) is used for soldering except for the area 8. FIG. 4 is an enlarged view of the rectangular electrode portion 6, and FIG. 5 shows a state in which electronic components are mounted. In any of the electrode parts, since the lead, electronic part, and component are soldered against each other, they are separated by a solder resist 9 near the center of the electrode part.

このような従来の構成では、溶融した牛田浴中法による
半田付けの場合、(l)電子部品形状の大きさ、(2)
はんだ浸漬の際の各電子部品の取付方向、(3)はんだ
浸漬の際の基板浸漬角度及び速さ、温度等のわずかな相
違によりはんだが付かない領域が生じるという欠点があ
った。特に角形電極部6においては、リードレス大形電
子部品の近くにリードレス小形電子部品を配置する場合
、小面−積の領域にははんだ付けがされiこくく時には
はんだが付着されていないこともしばしばあり、作業回
数の増加或は後工程における修正が増加され、工程の複
雑化のみならず安定した品質を得るにも大きな問題とな
っていた。
In such a conventional configuration, in the case of soldering by the molten Ushida bathing method, (l) the size of the electronic component shape, (2)
There is a drawback that some areas may not be soldered due to slight differences in the mounting direction of each electronic component during solder dipping, (3) substrate dipping angle and speed, temperature, etc. during solder dipping. Particularly in the square electrode part 6, when a small leadless electronic component is placed near a large leadless electronic component, solder is applied to a small area, and when the area is small, no solder is attached. This often results in an increase in the number of operations or an increase in corrections in post-processes, which not only complicates the process but also poses a major problem in obtaining stable quality.

ちなみに第6図に示すように、角形電極部6をソルダー
レジスト9によって分割しないということも考えられる
が、この方法ζこよると逆にはんだ量の過多となり品質
低下を招くことは避けられなかった。
Incidentally, as shown in Fig. 6, it is possible to not divide the rectangular electrode portion 6 by the solder resist 9, but this method inevitably results in an excessive amount of solder and a deterioration in quality. .

本発明はこれらの欠点を除去して、より確実な信頼性の
高いはんだ付けが容易に実現できるはんだ付は方法を提
供することを目的とする。
It is an object of the present invention to provide a soldering method that eliminates these drawbacks and can easily achieve more reliable and reliable soldering.

本発明は、従来の工程で使用しているソルダーレジスト
9のパターンをわずかに工夫することにより実現される
The present invention is realized by slightly modifying the pattern of the solder resist 9 used in the conventional process.

すなわち本発明によれば、一体の電極部に近接して2個
以上の電子部品をはんだ付けする際、各々のはんだ付は
領域を、ソルダーレジストで完全に区切らずわずかな幅
の帯状接続部で互いに連通させておくことにより、半田
デイツプ法あるいは半田パス法のどちらにおいてもその
目的を達成することができる。
That is, according to the present invention, when two or more electronic components are soldered in close proximity to a single electrode part, each soldering area is not completely separated by solder resist, but is performed using a band-shaped connection part with a small width. By communicating with each other, the purpose can be achieved in either the solder dip method or the solder pass method.

以下、図面と共に本発明の詳細な説明する。Hereinafter, the present invention will be described in detail with reference to the drawings.

第7図、第8図はリードを有する電子部品をはんだ付け
する為の本発明によるソルダーレジストパターン例であ
る。従来同様2つのリード挿入穴7を持った丸形電極部
4があり、はんだ付けの不必要な部分だけソルダーレジ
スト9により棲ゎれている。
FIGS. 7 and 8 are examples of solder resist patterns according to the present invention for soldering electronic components having leads. As in the conventional case, there is a round electrode part 4 having two lead insertion holes 7, and only the parts that do not require soldering are covered with a solder resist 9.

このような構成ζこおいて従来と異なる点は、はんだ付
は領域8間番ζは帯状接続部1Gが設けられ、ここには
はんだが付着する様にソルダーレジスト9が様っていな
い点である。
This configuration ζ is different from the conventional one in that the soldering area 8 ζ is provided with a band-shaped connection part 1G, and the solder resist 9 is not spread here so that the solder will adhere. be.

第9図は角形電極部6#こおける本発明の実施例、第1
0図はその実施例(第9図)に電子部品を搭  (載し
た状態を示す。また第11図は、丸形電極部4と角形電
極部6を形成した場合の本発明の実施例を示す。どの実
施例においても、本発明の特像とする帯状接続部10が
はんだ付は領域8゛関に設けられている。
FIG. 9 shows an embodiment of the present invention in the square electrode section 6#, the first
Figure 0 shows a state in which electronic components are mounted on the embodiment (Figure 9). Figure 11 shows an embodiment of the present invention in which a round electrode part 4 and a square electrode part 6 are formed. In each of the embodiments, the strip-shaped connecting portion 10, which is a feature of the present invention, is provided in the soldering region 8.

このように本発1141とよれば、一体の電極部の互に
近接する半田付は領域間にわずかな幅の帯状接続部lO
を設けること−こより、片側のはんだ付は領域にはんだ
が付くと他方のはんだ付は領域へも、はんだが伸びてい
くため双方とも確実にはんだ付けされ、従来特に角型電
極部6Jこおいて問題とされた電子部品によりはんだ付
けが妨げられるという欠点も解消され、かつはんだ量も
適正にコントロールされる。
In this way, according to the present invention 1141, the soldering of the integral electrode portions in close proximity to each other results in a band-shaped connecting portion lO with a small width between the regions.
- From this, when soldering on one side, when the solder sticks to the area, when soldering on the other side, the solder extends to the area, so both sides are reliably soldered. The problem of electronic components interfering with soldering is also eliminated, and the amount of solder is appropriately controlled.

尚、本発明は実施例において説明した銅板脂積層板に限
らず、金属板上へ絶縁層を介して適当な金属層を設けた
゛回路基板、及びセラミック等の絶縁物上へ印刷により
回路パターンを設けた厚膜回路用としても応用可能であ
る。
Note that the present invention is not limited to the copper plate/fat laminate described in the embodiments, but also applies to circuit boards in which a suitable metal layer is provided on a metal plate via an insulating layer, and a circuit pattern is printed on an insulating material such as a ceramic. It can also be applied to thick film circuits.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は電子部品の取付状態を示す概略図、第2図及び
第3図は丸形電極部こおける従来方法の部分拡大図、第
4図、第5図及び第6゛図は角形電極部こおける従来方
法の部分拡大図、第7図及び第8図は丸形電極における
本発明の一実施例を説明するための部分拡大図、第9図
及び第1θ図は角形電極における本発明の他の一実施例
を説明するための部分拡大図、第11図は丸形電極と角
形電極を組み合わせたものにおける本発明のざら暑と他
の実施例を説明するための部分拡大図である。 1:銅板樹脂積層板、2:配線パターン、3:リードを
有する電子部品、4:丸形電極部、5:リードレス電子
部品、6:角形電極部、7:!J−ド挿入穴、8:はん
だ付は領域、9:ソルダーレジスト、10:帯状接続部
Figure 1 is a schematic diagram showing the mounting state of electronic components, Figures 2 and 3 are partially enlarged views of the conventional method for round electrodes, and Figures 4, 5, and 6 are square electrodes. FIGS. 7 and 8 are partially enlarged views for explaining an embodiment of the present invention using a round electrode, and FIGS. 9 and 1θ are partially enlarged views of the conventional method using a square electrode. FIG. 11 is a partially enlarged view for explaining another embodiment of the present invention in which a round electrode and a square electrode are combined. . 1: Copper plate resin laminate, 2: Wiring pattern, 3: Electronic component with leads, 4: Round electrode section, 5: Leadless electronic component, 6: Square electrode section, 7:! J-card insertion hole, 8: Soldering area, 9: Solder resist, 10: Band-shaped connection part.

Claims (1)

【特許請求の範囲】[Claims] 回路基板上の一体の電極部に、互いに近接して2個以上
の電子部品をはんだ付けする方法において、はんだ付は
領域とその領域間に設けたわずかな幅の帯状接続部を残
してすべてをソルダーレジストで覆い、電子部品を所定
の位置に仮止めした後に一前記基板をはんだ浴に浸漬ま
たははんだ浴表面上を移動させることを特徴とする電子
部品のはんだ付は方法。
A method of soldering two or more electronic components in close proximity to one another on a single electrode on a circuit board. A method for soldering electronic components, which comprises covering the board with a solder resist and temporarily fixing the electronic component in a predetermined position, and then immersing the board in a solder bath or moving the board over the surface of the solder bath.
JP15245981A 1981-09-26 1981-09-26 Method of soldering electronic part Pending JPS5853890A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15245981A JPS5853890A (en) 1981-09-26 1981-09-26 Method of soldering electronic part

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15245981A JPS5853890A (en) 1981-09-26 1981-09-26 Method of soldering electronic part

Publications (1)

Publication Number Publication Date
JPS5853890A true JPS5853890A (en) 1983-03-30

Family

ID=15540974

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15245981A Pending JPS5853890A (en) 1981-09-26 1981-09-26 Method of soldering electronic part

Country Status (1)

Country Link
JP (1) JPS5853890A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61131593A (en) * 1984-11-30 1986-06-19 日本電気ホームエレクトロニクス株式会社 Solder land for printed circuit board
JPS62121732U (en) * 1986-01-25 1987-08-01
JPS63302595A (en) * 1987-06-02 1988-12-09 Murata Mfg Co Ltd Mounting structure of chip component
US5638870A (en) * 1992-03-31 1997-06-17 Daiwa Seiko, Inc. Fiber-reinforced thermoplastic tubular body

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61131593A (en) * 1984-11-30 1986-06-19 日本電気ホームエレクトロニクス株式会社 Solder land for printed circuit board
JPS62121732U (en) * 1986-01-25 1987-08-01
JPH0514418Y2 (en) * 1986-01-25 1993-04-16
JPS63302595A (en) * 1987-06-02 1988-12-09 Murata Mfg Co Ltd Mounting structure of chip component
US5638870A (en) * 1992-03-31 1997-06-17 Daiwa Seiko, Inc. Fiber-reinforced thermoplastic tubular body

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