JP2003124903A5 - - Google Patents
Download PDFInfo
- Publication number
- JP2003124903A5 JP2003124903A5 JP2002282218A JP2002282218A JP2003124903A5 JP 2003124903 A5 JP2003124903 A5 JP 2003124903A5 JP 2002282218 A JP2002282218 A JP 2002282218A JP 2002282218 A JP2002282218 A JP 2002282218A JP 2003124903 A5 JP2003124903 A5 JP 2003124903A5
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US09/967,390 US7106227B2 (en) | 2001-09-28 | 2001-09-28 | Method and apparatus for synchronizing a multiple-stage multiplexer |
| US09/967390 | 2001-09-28 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2003124903A JP2003124903A (ja) | 2003-04-25 |
| JP2003124903A5 true JP2003124903A5 (enExample) | 2005-11-10 |
Family
ID=25512723
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2002282218A Pending JP2003124903A (ja) | 2001-09-28 | 2002-09-27 | 多段マルチプレクサを同期化する装置及び方法 |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US7106227B2 (enExample) |
| EP (1) | EP1298823B1 (enExample) |
| JP (1) | JP2003124903A (enExample) |
| DE (1) | DE60211822T2 (enExample) |
Families Citing this family (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7020210B2 (en) * | 2001-10-23 | 2006-03-28 | Broadcom Corporation | Inter-device adaptable interfacing clock skewing |
| US7672301B2 (en) * | 2002-05-02 | 2010-03-02 | Ciena Corporation | Distribution stage for enabling efficient expansion of a switching network |
| US7319706B2 (en) * | 2002-08-12 | 2008-01-15 | Broadcom Corporation | Symmetrical clock distribution in multi-stage high speed data conversion circuits |
| US7443890B2 (en) * | 2002-08-12 | 2008-10-28 | Broadcom Corporation | Multi-stage multiplexing chip set having switchable forward/reverse clock relationship |
| US7266133B2 (en) * | 2002-11-13 | 2007-09-04 | General Instrument Corporation | Methods and apparatus for statistical multiplexing with distributed multiplexers |
| US7342977B2 (en) * | 2002-11-26 | 2008-03-11 | Lsi Logic Corporation | Serial data transmitter with bit doubling |
| US7471752B2 (en) * | 2004-08-06 | 2008-12-30 | Lattice Semiconductor Corporation | Data transmission synchronization |
| US7848318B2 (en) | 2005-08-03 | 2010-12-07 | Altera Corporation | Serializer circuitry for high-speed serial data transmitters on programmable logic device integrated circuits |
| US7245240B1 (en) * | 2006-03-07 | 2007-07-17 | Altera Corporation | Integrated circuit serializers with two-phase global master clocks |
| US8417810B2 (en) * | 2007-01-10 | 2013-04-09 | Broadcom Corporation | System and method for managing counters |
| TW200835151A (en) * | 2007-02-15 | 2008-08-16 | Univ Nat Chiao Tung | Low-power dynamic sequential controlling multiplexer |
| US8989214B2 (en) | 2007-12-17 | 2015-03-24 | Altera Corporation | High-speed serial data signal receiver circuitry |
| US7948975B2 (en) * | 2008-03-03 | 2011-05-24 | IPLight Ltd. | Transparent switching fabric for multi-gigabit transport |
| TWI449342B (zh) * | 2012-01-20 | 2014-08-11 | Silicon Motion Inc | 串化器及資料串化方法 |
| US9246616B2 (en) * | 2014-02-06 | 2016-01-26 | Cisco Technologies, Inc. | Clock phase compensator for multi-stage time division multiplexer |
| US10110334B2 (en) * | 2016-04-25 | 2018-10-23 | Macom Connectivity Solutions, Llc | High speed serializer using quadrature clocks |
| US10340904B2 (en) * | 2016-06-28 | 2019-07-02 | Altera Corporation | Method and apparatus for phase-aligned 2X frequency clock generation |
| US10193556B2 (en) * | 2016-11-11 | 2019-01-29 | Skyworks Solutions, Inc. | Method and apparatus for configurable control of an electronic device |
| WO2021201247A1 (ja) * | 2020-04-03 | 2021-10-07 | 凸版印刷株式会社 | 信号検出回路、駆動検出回路、センサアレイおよびセンサシステム |
Family Cites Families (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE2811851C2 (de) * | 1978-03-17 | 1980-03-27 | Siemens Ag, 1000 Berlin Und 8000 Muenchen | Verfahren zur Rahmensynchronisierung eines Zeitmultiplexsystems |
| JPH02165744A (ja) * | 1988-12-20 | 1990-06-26 | Toshiba Corp | データ時分割処理装置 |
| DE69029122T2 (de) * | 1989-06-16 | 1997-04-03 | Advantest Corp | Prüfmustergenerator |
| JPH03201735A (ja) | 1989-12-28 | 1991-09-03 | Advantest Corp | データ多重化装置 |
| US5157277A (en) | 1990-12-28 | 1992-10-20 | Compaq Computer Corporation | Clock buffer with adjustable delay and fixed duty cycle output |
| US5182467A (en) * | 1991-08-22 | 1993-01-26 | Triquint Semiconductor, Inc. | High performance multiplexer for improving bit error rate |
| JP3233773B2 (ja) * | 1994-03-18 | 2001-11-26 | 富士通株式会社 | 試験回路、自己試験方法及び通常試験方法 |
| JPH0832425A (ja) * | 1994-07-18 | 1996-02-02 | Fujitsu Ltd | データ読み取りタイミング可変回路 |
| JPH0955667A (ja) * | 1995-08-10 | 1997-02-25 | Mitsubishi Electric Corp | マルチプレクサ，及びデマルチプレクサ |
| US5969655A (en) * | 1995-12-15 | 1999-10-19 | Matsushida Electric Industrial Co., Ltd. | Digital convergence correction device outputting an analog correction signal |
| US5856753A (en) * | 1996-03-29 | 1999-01-05 | Cypress Semiconductor Corp. | Output circuit for 3V/5V clock chip duty cycle adjustments |
| US6026076A (en) * | 1997-08-29 | 2000-02-15 | Lucent Technologies Inc. | Detecting digital multiplexer faults |
| US6201829B1 (en) * | 1998-04-03 | 2001-03-13 | Adaptec, Inc. | Serial/parallel GHZ transceiver with pseudo-random built in self test pattern generator |
| JP2000013347A (ja) * | 1998-06-19 | 2000-01-14 | Nec Eng Ltd | 多重化回路及びその多重化のための並直列変換用ラッチクロック生成回路 |
| US6442085B1 (en) * | 2000-10-02 | 2002-08-27 | International Business Machines Corporation | Self-Test pattern to detect stuck open faults |
| US6961317B2 (en) * | 2001-09-28 | 2005-11-01 | Agilent Technologies, Inc. | Identifying and synchronizing permuted channels in a parallel channel bit error rate tester |
-
2001
- 2001-09-28 US US09/967,390 patent/US7106227B2/en not_active Expired - Fee Related
-
2002
- 2002-07-25 EP EP02016662A patent/EP1298823B1/en not_active Expired - Lifetime
- 2002-07-25 DE DE60211822T patent/DE60211822T2/de not_active Expired - Fee Related
- 2002-09-27 JP JP2002282218A patent/JP2003124903A/ja active Pending