JP2003124258A - Mounting method of semiconductor chip and mounting structure of semiconductor chip - Google Patents

Mounting method of semiconductor chip and mounting structure of semiconductor chip

Info

Publication number
JP2003124258A
JP2003124258A JP2001311035A JP2001311035A JP2003124258A JP 2003124258 A JP2003124258 A JP 2003124258A JP 2001311035 A JP2001311035 A JP 2001311035A JP 2001311035 A JP2001311035 A JP 2001311035A JP 2003124258 A JP2003124258 A JP 2003124258A
Authority
JP
Japan
Prior art keywords
semiconductor chip
semiconductor chips
substrate
connection terminal
bumps
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001311035A
Other languages
Japanese (ja)
Inventor
Hideji Haraoka
秀次 原岡
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
Original Assignee
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Priority to JP2001311035A priority Critical patent/JP2003124258A/en
Publication of JP2003124258A publication Critical patent/JP2003124258A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83101Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83192Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body

Landscapes

  • Liquid Crystal (AREA)
  • Wire Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a mounting method of a semiconductor chip and the mounting structure of the semiconductor chip, which are capable of surely conducting the bumps of respective semiconductor chips to connecting terminal units on a substrate, in the case that a plurality of semiconductor chips are mounted on the substrate through an anisotropic conductive film. SOLUTION: A plurality of semiconductor chips, on which a plurality of bumps are formed so as to be projected, are mounted on the substrate, on the surface of which a plurality of connecting terminal units are formed so as to be opposed to each bumps respectively so that the bumps are conducted to each connecting terminals through the anisotropic conductive film. The plurality of semiconductor chips are formed so that thicknesses are different from each other as a whole and when the semiconductor chips are mounted, the chips are welded by pressure onto the substrate sequentially from the chip having a thinner thickness to the same having a thicker thickness.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本願発明は、基板上に異方性
導電膜を介して複数の半導体チップを実装する半導体チ
ップの実装方法、および半導体チップの実装構造に関す
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor chip mounting method for mounting a plurality of semiconductor chips on a substrate via an anisotropic conductive film, and a semiconductor chip mounting structure.

【0002】[0002]

【従来の技術】半導体チップの実装構造には、複数のバ
ンプが突出形成されている複数の半導体チップが、上記
各バンプのそれぞれと対応する複数の接続端子部が表面
に形成されている基板上に異方性導電膜を介して実装さ
れているものがある。この種の従来の半導体チップの実
装構造の一例を図7に示す。この半導体チップの実装構
造は、たとえば液晶テレビや携帯型電話機などに組み込
まれている液晶表示モジュール100に適用されたもの
であり、2つの半導体チップ101,102を、液晶表
示面となる一方のガラス基板3上に直接実装した構造、
いわゆるCOG(Chip On Glass)方式のものである。
2. Description of the Related Art In a semiconductor chip mounting structure, a plurality of semiconductor chips having a plurality of bumps formed thereon are formed on a substrate on which a plurality of connection terminal portions corresponding to the respective bumps are formed on the surface. In some cases, it is mounted via an anisotropic conductive film. An example of this type of conventional semiconductor chip mounting structure is shown in FIG. This semiconductor chip mounting structure is applied to a liquid crystal display module 100 incorporated in, for example, a liquid crystal television or a mobile phone, and the two semiconductor chips 101 and 102 are used as a glass for one of the liquid crystal display surfaces. Structure mounted directly on the board 3,
The so-called COG (Chip On Glass) system is used.

【0003】この液晶表示モジュール100は、重なり
合った2枚のガラス基板3,3′を有しており、その間
には、液晶封止部が形成されている。一方の基板3は、
他方の基板3′の側部からはみ出るように形成された延
出部3Aを有しており、この延出部3Aの表面に2つの
半導体チップ101,102が実装されている。より詳
細には、延出部3Aの表面には液晶封止部から引き出す
ようにして透明電極パターンが形成されており、この透
明電極パターンの各所には、図8に示すように、各半導
体チップ101,102に設けられた複数のバンプ11
のそれぞれと対応する複数の接続端子部31が形成され
ている。各半導体チップ101,102は、異方性導電
膜4を介して各バンプ11と各接続端子部31とが導通
するように実装されている。
This liquid crystal display module 100 has two glass substrates 3 and 3'which are overlapped with each other, and a liquid crystal sealing portion is formed between them. One substrate 3 is
It has an extending portion 3A formed so as to protrude from the side portion of the other substrate 3 ', and two semiconductor chips 101 and 102 are mounted on the surface of this extending portion 3A. More specifically, a transparent electrode pattern is formed on the surface of the extending portion 3A so as to be pulled out from the liquid crystal sealing portion, and each portion of the transparent electrode pattern is formed on each semiconductor chip as shown in FIG. A plurality of bumps 11 provided on 101 and 102
A plurality of connection terminal portions 31 corresponding to each of the above. The semiconductor chips 101 and 102 are mounted so that the bumps 11 and the connection terminal portions 31 are electrically connected via the anisotropic conductive film 4.

【0004】2つの半導体チップ102,103は、こ
の液晶表示モジュールを駆動するためのICであり、そ
の全体としての厚みが略同等とされている。また、これ
ら2つの半導体チップ101,102は、この液晶表示
モジュール100の小型化などのため、基板3上におい
て互いに隣接するように配置されており、これに伴っ
て、この液晶表示モジュール100では、異方性導電膜
4として、半導体チップ101,102の両者に共通の
ものが用いられている。
The two semiconductor chips 102 and 103 are ICs for driving the liquid crystal display module, and have substantially the same thickness as a whole. Further, these two semiconductor chips 101 and 102 are arranged adjacent to each other on the substrate 3 in order to miniaturize the liquid crystal display module 100 and the like, and accordingly, in the liquid crystal display module 100, As the anisotropic conductive film 4, the one common to both the semiconductor chips 101 and 102 is used.

【0005】異方性導電膜4は、たとえば、図9(a)
および図9(b)に示すように、樹脂製のボール41a
の表面にNiあるいはAuなどの導電層41bをメッキ
することにより形成された導電性粒子41を、エポキシ
樹脂など絶縁性を有する接着母材42中に分散混入した
ものである。このような異方性導電膜4を用いれば、バ
ンプ11と接続端子部31との厚み方向に沿う隙間に、
導電性粒子41を挟み込むように介在させることによっ
て、これらの導電性粒子41を介して各バンプ11と各
接続端子部31とを導通させることができる。
The anisotropic conductive film 4 is, for example, as shown in FIG.
And as shown in FIG. 9B, resin balls 41a
Conductive particles 41 formed by plating a conductive layer 41b such as Ni or Au on the surface of are dispersed and mixed in an adhesive base material 42 having an insulating property such as an epoxy resin. If such an anisotropic conductive film 4 is used, a gap along the thickness direction between the bump 11 and the connection terminal portion 31 will be formed.
By interposing the conductive particles 41 so as to sandwich the conductive particles 41, the bumps 11 and the connection terminal portions 31 can be electrically connected via the conductive particles 41.

【0006】上記半導体チップ101、102を実装す
るには、基板3上に上記異方性導電膜4を形成してお
き、半導体チップ101,102をそれぞれ、各バンプ
11が各接続端子部31と対応するように基板3上に載
置する。その後、半導体チップ101,102を基板3
上に圧着する。半導体101,102の圧着に際して
は、図8に示すように、半導体チップ101,102を
加熱しつつ基板3に向けて押圧する周知の圧着ヘッドD
を用いるのが一般的である。このような圧着ヘッドDを
用いることによって、上記接着母材42が軟化させられ
て、半導体チップ101,102が基板3上に接合さ
れ、かつ、上記導電性粒子41が各バンプ11と各接続
端子部31との間で狭持されることにより各バンプ11
と各接続端子部31との導通が達成されうる。このよう
にして、半導体チップ101,102は、基板3上に熱
圧着される。なお、圧着ヘッドDは、一般的に、半導体
チップ101,102に比してその大きさが大とされて
おり、2つの半導体チップ101,102は、上述した
ように、全体としての厚みが略同等とされているととも
に、互いに隣接するように配置されているので、2つの
半導体チップ101,102の基板3への熱圧着は、一
括して行なわれる。
In order to mount the semiconductor chips 101 and 102, the anisotropic conductive film 4 is formed on the substrate 3, and the bumps 11 are connected to the connection terminal portions 31 of the semiconductor chips 101 and 102, respectively. It is placed on the substrate 3 in a corresponding manner. After that, the semiconductor chips 101 and 102 are mounted on the substrate 3
Crim on top. When crimping the semiconductors 101 and 102, as shown in FIG. 8, a well-known crimping head D that presses the semiconductor chips 101 and 102 toward the substrate 3 while heating them.
Is generally used. By using such a pressure bonding head D, the adhesive base material 42 is softened, the semiconductor chips 101 and 102 are bonded onto the substrate 3, and the conductive particles 41 are connected to the bumps 11 and the connection terminals. Each bump 11 is sandwiched between the bumps 11 and the portion 31.
The electrical connection between the connection terminal portion 31 and each of the connection terminal portions 31 can be achieved. In this way, the semiconductor chips 101 and 102 are thermocompression bonded onto the substrate 3. The crimping head D is generally larger in size than the semiconductor chips 101 and 102, and the two semiconductor chips 101 and 102 have a substantially total thickness as described above. Since they are equivalent and are arranged adjacent to each other, thermocompression bonding of the two semiconductor chips 101 and 102 to the substrate 3 is performed collectively.

【0007】しかしながら、2つの半導体チップ10
1,102は、全体としての厚みが略同等とされている
とはいえども、たとえば、異方性導電膜4上に載置され
た状態において上面が同一平面上に配置されていない場
合や、圧着ヘッドDと各半導体チップ101,102の
上面とが平行に配置されていない場合などでは、圧着ヘ
ッドDを用いて2つの半導体チップ101,102を一
括して押圧する際に、半導体チップ101,102にか
かる押圧力が、部位ごとに異なることがあった。これに
より、たとえば、図9(a)に示すように、半導体チッ
プ101,102のバンプ11と接続端子部31との間
で上記導電性粒子41が押しつぶされることにより、導
電性粒子41の表面の導電層41bにクラック40が発
生することがあった。また、たとえば、図9(b)に示
すように、バンプ11と接続端子部31との間の距離が
導電性粒子41の直径よりも大となり、導電性粒子41
がバンプ11と接続端子部31の両者に当接しないこと
があった。これらの場合では、導電性粒子41がバンプ
11と接続端子部31との間を導通させることができな
くなるため、半導体チップ101,102の接続不良が
発生するという問題が生じていた。
However, the two semiconductor chips 10
Although the total thicknesses of the layers 1, 102 are substantially equal to each other, for example, when the upper surfaces are not placed on the same plane when placed on the anisotropic conductive film 4, or When the pressure bonding head D and the upper surfaces of the respective semiconductor chips 101 and 102 are not arranged in parallel, when the pressure bonding head D is used to collectively press the two semiconductor chips 101 and 102, The pressing force applied to 102 may vary from part to part. As a result, for example, as shown in FIG. 9A, the conductive particles 41 are crushed between the bumps 11 of the semiconductor chips 101 and 102 and the connection terminal portions 31, so that the surface of the conductive particles 41 is removed. The crack 40 may occur in the conductive layer 41b. In addition, for example, as shown in FIG. 9B, the distance between the bump 11 and the connection terminal portion 31 becomes larger than the diameter of the conductive particle 41, and the conductive particle 41.
May not come into contact with both the bump 11 and the connection terminal portion 31. In these cases, the conductive particles 41 cannot electrically connect the bump 11 and the connection terminal portion 31 to each other, which causes a problem that the semiconductor chips 101 and 102 have a poor connection.

【0008】[0008]

【発明が解決しようとする課題】本願発明は、上記した
事情のもとで考え出されたものであって、複数の半導体
チップを、異方性導電膜を介して基板に実装する場合に
おいて、各半導体チップのバンプと基板上の接続端子部
とを確実に導通させることができる半導体チップの実装
方法、および半導体チップの実装構造を提供することを
その課題とする。
The present invention has been conceived under the above-mentioned circumstances, and in the case of mounting a plurality of semiconductor chips on a substrate through an anisotropic conductive film, It is an object of the present invention to provide a semiconductor chip mounting method and a semiconductor chip mounting structure capable of surely connecting the bumps of the respective semiconductor chips to the connection terminal portions on the substrate.

【0009】[0009]

【発明の開示】上記課題を解決するため、本願発明で
は、次の技術的手段を講じている。
DISCLOSURE OF THE INVENTION In order to solve the above problems, the present invention takes the following technical means.

【0010】すなわち、本願発明の第1の側面により提
供される半導体チップの実装方法は、複数のバンプが突
出形成されている複数の半導体チップを、上記各バンプ
のそれぞれと対応する複数の接続端子部が表面に形成さ
れている基板に対して、上記各バンプと上記各接続端子
部とが異方性導電膜を介して導通するようにして実装す
る方法であって、上記複数の半導体チップは、全体とし
ての厚みが互いに異なるように形成されており、実装さ
れる際には、その厚みが薄いものから順に、上記基板上
に圧着されることを特徴としている。
That is, in the semiconductor chip mounting method provided by the first aspect of the present invention, a plurality of semiconductor chips having a plurality of bumps formed thereon are formed into a plurality of connection terminals corresponding to the respective bumps. A method of mounting the bumps and the connection terminal portions so that the bumps and the connection terminal portions are electrically connected to each other through an anisotropic conductive film on a substrate having a portion formed on the surface, and the plurality of semiconductor chips are It is characterized in that they are formed so as to have different thicknesses as a whole, and when they are mounted, they are pressure-bonded onto the substrate in order from the smallest thickness.

【0011】好ましい実施の形態においては、上記基板
は、液晶表示装置の表示部用として重ね合わせられた2
枚の透明基板のうちの一方の透明基板であり、上記各半
導体チップはそれぞれ、上記液晶表示装置を駆動するた
めのICである構成とされる。
In a preferred embodiment, the substrates are stacked for use as a display portion of a liquid crystal display device.
One of the transparent substrates is a transparent substrate, and each of the semiconductor chips is an IC for driving the liquid crystal display device.

【0012】本願発明の第2の側面により提供される半
導体チップの実装構造は、複数のバンプが突出形成され
ている複数の半導体チップを、上記各バンプのそれぞれ
と対応する複数の接続端子部が表面に形成されている基
板上に対して、上記各バンプと上記各接続端子部とが異
方性導電膜を介して導通するようにして実装した半導体
チップの実装構造であって、上記各半導体チップは、全
体としての厚みが互いに異なるように形成されていると
ともに、共通の異方性導電膜を介して、互いに隣接して
実装されていることを特徴としている。
In the semiconductor chip mounting structure provided by the second aspect of the present invention, a plurality of semiconductor chips having a plurality of bumps protrudingly formed are provided with a plurality of connection terminal portions corresponding to the respective bumps. A mounting structure of a semiconductor chip, in which the bumps and the connection terminal portions are mounted on a substrate formed on the surface so as to be electrically connected through an anisotropic conductive film, The chips are characterized in that they are formed so as to have different thicknesses as a whole, and are mounted adjacent to each other via a common anisotropic conductive film.

【0013】一般に、半導体チップを基板に対して異方
性導電膜を介して実装する場合には、半導体チップを基
板に向けて押圧する圧着ヘッドが用いられる。本願発明
において、複数の半導体チップは、互いに隣接して実装
されるが、全体としての厚みが互いに異なるように形成
されているので、その厚みが薄いものから順に圧着され
ていくことによって、厚みがより厚い半導体チップを圧
着ヘッドで押圧する際に、圧着ヘッドが、既に実装し
た、厚みのより薄い半導体チップに当接することがな
い。これにより、厚みがより薄い半導体チップは、実装
された状態から基板に対してさらに押圧されない。ま
た、厚みがより厚い半導体チップを基板に対して所望の
押圧力で押圧することができる。すなわち、各半導体チ
ップを基板に対して押圧する押圧力を各半導体チップご
とに制御することができる。したがって、上記各半導体
チップの各バンプと上記各接続端子部との間で異方性導
電膜内の導電性粒子を適切な圧力で挟み込むことができ
る。その結果、従来例のように、導電性粒子にクラック
が発生したり、各バンプと各接続端子部との間の導電性
粒子がそれら両者に当接しない状態が生じるのを防止す
ることができ、各バンプと各接続端子部とを確実に導通
させることができる。
Generally, when a semiconductor chip is mounted on a substrate via an anisotropic conductive film, a pressure bonding head for pressing the semiconductor chip toward the substrate is used. In the present invention, the plurality of semiconductor chips are mounted adjacent to each other, but since they are formed so as to have different thicknesses as a whole, the thickness of the semiconductor chips is reduced by sequentially pressing them in order from the smallest thickness. When the thicker semiconductor chip is pressed by the pressure bonding head, the pressure bonding head does not come into contact with the already mounted thinner semiconductor chip. As a result, the semiconductor chip having a smaller thickness is not further pressed against the substrate from the mounted state. Moreover, a semiconductor chip having a larger thickness can be pressed against the substrate with a desired pressing force. That is, the pressing force that presses each semiconductor chip against the substrate can be controlled for each semiconductor chip. Therefore, the conductive particles in the anisotropic conductive film can be sandwiched between the bumps of the semiconductor chips and the connection terminal portions with an appropriate pressure. As a result, it is possible to prevent the generation of a crack in the conductive particles or the state in which the conductive particles between each bump and each connection terminal portion do not contact them, as in the conventional example. The bumps and the connection terminal portions can be surely brought into conduction.

【0014】本願発明のその他の特徴および利点につい
ては、以下に行う発明の実施の形態の説明から、より明
らかになるであろう。
Other features and advantages of the present invention will be more apparent from the following description of the embodiments of the invention.

【0015】[0015]

【発明の実施の形態】以下、本願発明の好ましい実施の
形態について、図面を参照して具体的に説明する。
BEST MODE FOR CARRYING OUT THE INVENTION Preferred embodiments of the present invention will be specifically described below with reference to the drawings.

【0016】図1は、本願発明に係る半導体チップの実
装構造の一例を示す概略斜視図、図2は、図1のII−II
線に沿う断面図、図3は、図1のIII−III線に沿う断面
図である。また、図4(a)ないし図6は、本願発明に
係る半導体チップの実装方法を説明するための一連の図
である。なお、これらの図において、従来例を示す図7
ないし図9に表された部材、部分等と同等のものにはそ
れぞれ同一の符号を付してある。
FIG. 1 is a schematic perspective view showing an example of a semiconductor chip mounting structure according to the present invention, and FIG. 2 is a line II-II in FIG.
3 is a sectional view taken along the line III-III in FIG. 1. In addition, FIGS. 4A to 6 are a series of diagrams for explaining a semiconductor chip mounting method according to the present invention. In addition, in these figures, FIG.
The same members and portions as those shown in FIG. 9 are designated by the same reference numerals.

【0017】図1に示すように、半導体チップの実装構
造Aは、液晶表示モジュールに適用されたものであっ
て、2枚の基板3,3′を有しており、そのうちの一方
の基板3上に2つの半導体チップ1,2が異方性導電膜
4を介して実装されている。
As shown in FIG. 1, a semiconductor chip mounting structure A is applied to a liquid crystal display module and has two substrates 3 and 3 ′, one of which is a substrate 3. Two semiconductor chips 1 and 2 are mounted on the upper surface of the semiconductor chip 1 through an anisotropic conductive film 4.

【0018】上記2枚の基板3,3′は、液晶表示面を
形成するための部材であって、たとえばガラスなどによ
り形成された透明基板であり、互いに重ね合わせられて
いる。これら2枚の基板3,3′間には、図2に示すよ
うに、その間隔を一定の狭隙に保つように、かつ互いに
重なり合う部分の周囲を囲むように形成されたシール材
33が狭持されており、このシール材33の内側には液
晶30が封止されている。
The two substrates 3 and 3'are members for forming a liquid crystal display surface, and are transparent substrates made of, for example, glass or the like, and are superposed on each other. As shown in FIG. 2, a sealing material 33 is formed between the two substrates 3 and 3 ′ so as to maintain a constant gap between them and to surround a portion where they overlap each other. The liquid crystal 30 is held inside the sealing material 33.

【0019】これらの基板3,3′のうち、一方の基板
3には、上記半導体チップ1,2を実装するための延出
部3Aが設けられており、この延出部3Aは、他方の基
板3′の側部からはみ出るように形成されている。各基
板3,3′の内面には、図2に示すように、たとえばI
TO(Indium Tin Oxide)を蒸着するなどして形成され
た透明電極パターン32,32′が設けられており、こ
れらのうち、一方の基板3に形成された透明電極パター
ン32は、延出部3A上まで連続している。この透明電
極パターン32における延出部3A上の各所には、半導
体チップ1,2を接続するための複数の接続端子部31
が形成されている。これら複数の接続端子部31は、図
3に示すように、各半導体チップ1,2の後述する複数
のバンプ11のそれぞれと対応するように配置されてい
る。
Of these substrates 3, 3 ', one substrate 3 is provided with an extending portion 3A for mounting the semiconductor chips 1, 2, and the extending portion 3A is the other portion. It is formed so as to protrude from the side portion of the substrate 3 '. As shown in FIG. 2, the inner surface of each substrate 3, 3'is, for example, I
The transparent electrode patterns 32 and 32 'are formed by vapor-depositing TO (Indium Tin Oxide), and the transparent electrode pattern 32 formed on one of the substrates 3 is the extended portion 3A. It continues to the top. A plurality of connection terminal portions 31 for connecting the semiconductor chips 1 and 2 are provided at various places on the extending portion 3A in the transparent electrode pattern 32.
Are formed. As shown in FIG. 3, the plurality of connection terminal portions 31 are arranged so as to correspond to a plurality of bumps 11 of the semiconductor chips 1 and 2 which will be described later.

【0020】上記2つの半導体チップ1,2はそれぞ
れ、この液晶表示モジュールを駆動するためのICであ
り、図3に示すように、その裏面側に接点となる複数の
バンプ11が突出形成されている。各半導体チップ1,
2は、これら各バンプ11と各接続端子部31とが異方
性導電膜4を介して導通するようにして基板3に実装さ
れる。これら2つの半導体チップ1,2は、この液晶表
示モジュールAの小型化などのため、図1に示すよう
に、基板3上において互いに隣接するように配置されて
おり、これに伴って、この液晶表示モジュールAでは、
図3に示すように、異方性導電膜4として、半導体チッ
プ1,2の両者に共通する1つのものが用いられてい
る。
Each of the two semiconductor chips 1 and 2 is an IC for driving the liquid crystal display module. As shown in FIG. 3, a plurality of bumps 11 serving as contacts are formed on the back surface of the IC chips so as to project therefrom. There is. Each semiconductor chip 1,
2 is mounted on the substrate 3 so that the bumps 11 and the connection terminal portions 31 are electrically connected to each other through the anisotropic conductive film 4. These two semiconductor chips 1 and 2 are arranged so as to be adjacent to each other on the substrate 3 as shown in FIG. 1 in order to downsize the liquid crystal display module A. In display module A,
As shown in FIG. 3, as the anisotropic conductive film 4, one common to both the semiconductor chips 1 and 2 is used.

【0021】各半導体チップ1,2は、その外装とし
て、たとえば樹脂などにより形成されたパッケージを有
しており、このようなパッケージを形成する際に、その
厚みを変えるなどして、図3に示すように、2つの半導
体チップ1,2のそれぞれにおける全体としての厚みが
互いに異なるように構成されている。具体的には、半導
体チップ1の全体としての厚みtが、半導体チップ1の
全体としての厚みt′よりも小とされている。
Each of the semiconductor chips 1 and 2 has a package formed of, for example, a resin as the exterior thereof, and when the package is formed, the thickness thereof is changed so that the package shown in FIG. As shown, the two semiconductor chips 1 and 2 are configured so that their respective total thicknesses are different from each other. Specifically, the total thickness t of the semiconductor chip 1 is smaller than the total thickness t ′ of the semiconductor chip 1.

【0022】上記異方性導電膜4は、図3に示すよう
に、絶縁性を有する接着母材42内に多数の導電性粒子
41を分散混入させたものである。接着母材42は、た
とえばエポキシ樹脂などの熱硬化性樹脂から形成され、
熱硬化させる前の段階においてフィルム状(固体状)の
ものや粘液状のものがある。各導電粒子41は、たとえ
ば、図5および図6に示すように、粒径が約3μm〜1
5μm程度とされた樹脂製のボール41aの表面にNi
およびAuなどの導電層41bをメッキすることによっ
て形成される。このような異方性導電膜4は、半導体チ
ップ1,2を実装する際、加圧・加熱などされることに
よって接着母材42が軟化させられ、その後、冷却・固
化されることによって、半導体チップ1,2の裏面と基
板3の表面とを接合する。このとき、バンプ11と接続
端子部31との間では、異方性導電膜4の厚みが比較的
小となり、この間に導電性粒子41が挟み込まれるよう
に介在することによって、半導体チップ1,2と接続端
子部31とが電気的に接続される。一方、異方性導電膜
4の厚みが比較的大となる部位では、各導電性粒子41
が分散したままの状態となり、絶縁性が維持される。
As shown in FIG. 3, the anisotropic conductive film 4 has a large number of conductive particles 41 dispersed and mixed in an adhesive base material 42 having an insulating property. The adhesive base material 42 is formed of a thermosetting resin such as an epoxy resin,
There are film-like (solid) and viscous ones in the stage before heat curing. Each conductive particle 41 has, for example, as shown in FIGS. 5 and 6, a particle size of about 3 μm to 1 μm.
Ni on the surface of the resin ball 41a having a thickness of about 5 μm
And a conductive layer 41b such as Au is plated. When the semiconductor chips 1 and 2 are mounted, the anisotropic conductive film 4 is pressed and heated to soften the adhesive base material 42, and then cooled and solidified to form a semiconductor. The back surfaces of the chips 1 and 2 are joined to the front surface of the substrate 3. At this time, the thickness of the anisotropic conductive film 4 is relatively small between the bump 11 and the connection terminal portion 31, and the conductive particles 41 are interposed so as to be sandwiched therebetween, so that the semiconductor chips 1 and 2 are formed. And the connection terminal portion 31 are electrically connected. On the other hand, in the portion where the thickness of the anisotropic conductive film 4 is relatively large, each conductive particle 41
Will remain dispersed and the insulation will be maintained.

【0023】以下、半導体チップの実装方法を順を追っ
て説明する。
The method of mounting the semiconductor chip will be described below step by step.

【0024】上記2つの半導体チップ1,2を基板3の
延出部3A上に実装するには、まず、図4(a)および
図4(b)に示すように、基板3の延出部3A上に異方
性導電膜4を形成する。より詳細には、図4(a)に示
すように、この異方性導電膜4は、上記接着母材42が
フィルム状に形成されているタイプのものであり、延出
部3Aにおける上記接続端子部31を含む所定の領域を
覆うようなサイズとされたものが、基板3上に載置され
る。そして、この異方性導電膜4は、基板3上において
不用意に位置ずれしないように、たとえば加熱あるいは
接着されるなどして、図4(b)に示すように、基板3
の表面に仮固定される。
In order to mount the two semiconductor chips 1 and 2 on the extending portion 3A of the substrate 3, first, as shown in FIGS. 4 (a) and 4 (b), the extending portion of the substrate 3 is formed. An anisotropic conductive film 4 is formed on 3A. More specifically, as shown in FIG. 4A, the anisotropic conductive film 4 is of a type in which the adhesive base material 42 is formed in a film shape, and the connection in the extending portion 3A is performed. The one sized so as to cover a predetermined area including the terminal portion 31 is placed on the substrate 3. Then, the anisotropic conductive film 4 is heated or adhered, for example, so as not to be inadvertently displaced on the substrate 3, as shown in FIG.
Is temporarily fixed to the surface of.

【0025】次いで、図5および図6に示すように、2
つの半導体チップ1,2を、その厚みが薄いものから順
に基板3上に実装する。
Then, as shown in FIG. 5 and FIG.
The two semiconductor chips 1 and 2 are mounted on the substrate 3 in order of decreasing thickness.

【0026】すなわち、まず、図5に示すように、厚み
が薄い半導体チップ1を、基板3に対して、各バンプ1
1が各接続端子部31に対応するように熱圧着する。こ
の工程においては、予め半導体チップ1を異方性導電膜
4上に吸着コレットなどにより載置しておき、周知の圧
着ヘッドDを用いて、半導体チップ1を加熱しつつ所定
の押圧力で基板3に向けて押しつける。これにより、上
記接着母材42は、軟化させられ、その後、冷却・固化
されることによって、半導体チップ1の裏面と基板3の
表面とを接合する。一方、上記導電性粒子41は、各接
続端子部31と半導体チップ1の各バンプ11との間で
適切な圧力で挟み込まれた状態となり、各バンプ11と
各接続端子部31とを導通させることが可能となる。
That is, first, as shown in FIG. 5, the semiconductor chip 1 having a small thickness is formed on the substrate 3 by the bumps 1
Thermocompression bonding is performed so that 1 corresponds to each connection terminal portion 31. In this step, the semiconductor chip 1 is previously placed on the anisotropic conductive film 4 by a suction collet or the like, and the well-known pressure bonding head D is used to heat the semiconductor chip 1 and apply a predetermined pressing force to the substrate. Press toward 3. As a result, the adhesive base material 42 is softened, and then cooled and solidified to bond the back surface of the semiconductor chip 1 to the front surface of the substrate 3. On the other hand, the conductive particles 41 are sandwiched between each connection terminal portion 31 and each bump 11 of the semiconductor chip 1 with an appropriate pressure, and each bump 11 and each connection terminal portion 31 are electrically connected. Is possible.

【0027】そして、半導体チップ1の場合と同様の手
順により、図6に示すように、圧着ヘッドDを用いて半
導体チップ2を基板3上に熱圧着する。このとき、半導
体チップ2は、半導体チップ1よりも厚みが大とされて
いるので、上述したように半導体チップ1と半導体チッ
プ2とが互いに隣接して実装される場合でも、圧着ヘッ
ドDは、半導体チップ2を押圧している状態において、
先に実装した半導体チップ1に当接することがない。こ
れにより、各接続端子部31と半導体チップ2の各バン
プ11との間で、導電性粒子41を適切な圧力で挟み込
むことができ、かつ、各接続端子部31と先に実装した
半導体チップ1の各バンプ11との間の導電性粒子41
がさらに加圧されるのを防止することができる。
Then, as shown in FIG. 6, the semiconductor chip 2 is thermocompression-bonded onto the substrate 3 by using the pressure-bonding head D in the same procedure as the case of the semiconductor chip 1. At this time, since the semiconductor chip 2 is thicker than the semiconductor chip 1, even if the semiconductor chip 1 and the semiconductor chip 2 are mounted adjacent to each other as described above, the pressure bonding head D is While pressing the semiconductor chip 2,
It does not come into contact with the previously mounted semiconductor chip 1. Thereby, the conductive particles 41 can be sandwiched between each connection terminal portion 31 and each bump 11 of the semiconductor chip 2 with an appropriate pressure, and each connection terminal portion 31 and the semiconductor chip 1 previously mounted. Conductive particles 41 between each bump 11 of the
Can be prevented from being further pressurized.

【0028】したがって、各接続端子部31と、半導体
チップ1,2の双方における各バンプ11との間で導電
性粒子41を適切な圧力で挟み込むことができる。すな
わち、従来例のように、各接続端子部31と各バンプ1
1との間の距離が導電性粒子41の直径よりも大となる
のを防止することができるとともに、各接続端子部31
と各バンプ11との間で導電性粒子41がつぶれて上記
導電層41bにクラックが発生するのを防止することが
できる。その結果、各バンプ11と各接続端子部31と
を確実に導通させることができ、半導体チップの接続不
良を防止することができる。
Therefore, the conductive particles 41 can be sandwiched between the connection terminal portions 31 and the bumps 11 on both the semiconductor chips 1 and 2 with an appropriate pressure. That is, as in the conventional example, each connection terminal portion 31 and each bump 1
It is possible to prevent the distance between the first and second conductive particles 41 from becoming larger than the diameter of the conductive particles 41, and at the same time, to connect each connection terminal portion 31.
It is possible to prevent the conductive particles 41 from being crushed between the bumps 11 and the bumps 11 and cracking in the conductive layer 41b. As a result, the bumps 11 and the connection terminal portions 31 can be surely brought into conduction with each other, and defective connection of the semiconductor chip can be prevented.

【0029】もちろん、この発明の範囲は上述した実施
の形態に限定されるものではない。たとえば、本実施形
態では、半導体チップの実装構造は、液晶表示モジュー
ルに適用されているが、これを他の装置に適用すること
もできる。
Of course, the scope of the present invention is not limited to the above embodiments. For example, in the present embodiment, the semiconductor chip mounting structure is applied to the liquid crystal display module, but it can also be applied to other devices.

【0030】また、たとえば、本実施形態では、基板に
対して2つの半導体チップが実装されるが、3つ以上の
半導体チップが実装されてもよい。
Further, for example, in this embodiment, two semiconductor chips are mounted on the substrate, but three or more semiconductor chips may be mounted.

【図面の簡単な説明】[Brief description of drawings]

【図1】本願発明に係る半導体チップの実装構造の一例
を示す概略斜視図である。
FIG. 1 is a schematic perspective view showing an example of a semiconductor chip mounting structure according to the present invention.

【図2】図1のII−II線に沿う断面図である。FIG. 2 is a sectional view taken along line II-II in FIG.

【図3】図1のIII−III線に沿う断面図である。FIG. 3 is a sectional view taken along the line III-III in FIG.

【図4】(a)および(b)は、本願発明に係る半導体
チップの実装方法を説明するための一連の図である。
FIG. 4A and FIG. 4B are a series of diagrams for explaining a semiconductor chip mounting method according to the present invention.

【図5】本願発明に係る半導体チップの実装方法を説明
するための一連の図である。
FIG. 5 is a series of diagrams for explaining a semiconductor chip mounting method according to the present invention.

【図6】本願発明に係る半導体チップの実装方法を説明
するための一連の図である。
FIG. 6 is a series of diagrams for explaining a semiconductor chip mounting method according to the present invention.

【図7】従来の半導体チップの実装構造の一例を示す概
略斜視図である。
FIG. 7 is a schematic perspective view showing an example of a conventional semiconductor chip mounting structure.

【図8】図7のVIII−VIII線に沿う断面図である。8 is a cross-sectional view taken along the line VIII-VIII of FIG.

【図9】(a)および(b)は、図8の要部を拡大して
示す図である。
9A and 9B are enlarged views of a main part of FIG. 8.

【符号の説明】[Explanation of symbols]

1,2 半導体チップ 3 基板 4 異方性導電膜 11 バンプ 31 接続端子部 A 半導体チップの実装構造 1, 2 semiconductor chips 3 substrates 4 Anisotropic conductive film 11 bumps 31 Connection terminal part A Semiconductor chip mounting structure

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 複数のバンプが突出形成されている複数
の半導体チップを、上記各バンプのそれぞれと対応する
複数の接続端子部が表面に形成されている基板に対し
て、上記各バンプと上記各接続端子部とが異方性導電膜
を介して導通するようにして実装する方法であって、 上記複数の半導体チップは、全体としての厚みが互いに
異なるように形成されており、実装される際には、その
厚みが薄いものから順に、上記基板上に圧着されること
を特徴とする、半導体チップの実装方法。
1. A plurality of semiconductor chips having a plurality of bumps formed thereon are formed on a substrate having a plurality of connection terminal portions corresponding to the respective bumps formed on the surface thereof. A method of mounting such that the connection terminal portions are electrically connected through an anisotropic conductive film, and the plurality of semiconductor chips are formed so as to have different thicknesses as a whole, and are mounted. In this case, a method for mounting a semiconductor chip is characterized in that the semiconductor chips are pressure-bonded on the substrate in order of decreasing thickness.
【請求項2】 上記基板は、液晶表示装置の表示部用と
して重ね合わせられた2枚の透明基板のうちの一方の透
明基板であり、 上記各半導体チップはそれぞれ、上記液晶表示装置を駆
動するためのICである、請求項1に記載の半導体チッ
プの実装方法。
2. The substrate is one of two transparent substrates stacked for a display section of a liquid crystal display device, wherein each of the semiconductor chips drives the liquid crystal display device. The method for mounting a semiconductor chip according to claim 1, wherein the mounting method is a semiconductor integrated circuit.
【請求項3】 複数のバンプが突出形成されている複数
の半導体チップを、上記各バンプのそれぞれと対応する
複数の接続端子部が表面に形成されている基板上に対し
て、上記各バンプと上記各接続端子部とが異方性導電膜
を介して導通するようにして実装した半導体チップの実
装構造であって、 上記各半導体チップは、全体としての厚みが互いに異な
るように形成されているとともに、共通の異方性導電膜
を介して、互いに隣接して実装されていることを特徴と
する、半導体チップの実装構造。
3. A plurality of semiconductor chips having a plurality of bumps formed thereon are formed on a substrate having a plurality of connection terminal portions corresponding to the respective bumps formed on the surface thereof. A mounting structure of a semiconductor chip mounted so as to be electrically connected to each of the connection terminal portions via an anisotropic conductive film, wherein each of the semiconductor chips is formed to have a different total thickness. In addition, a semiconductor chip mounting structure, which is mounted adjacent to each other via a common anisotropic conductive film.
JP2001311035A 2001-10-09 2001-10-09 Mounting method of semiconductor chip and mounting structure of semiconductor chip Pending JP2003124258A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2001311035A JP2003124258A (en) 2001-10-09 2001-10-09 Mounting method of semiconductor chip and mounting structure of semiconductor chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001311035A JP2003124258A (en) 2001-10-09 2001-10-09 Mounting method of semiconductor chip and mounting structure of semiconductor chip

Publications (1)

Publication Number Publication Date
JP2003124258A true JP2003124258A (en) 2003-04-25

Family

ID=19129928

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001311035A Pending JP2003124258A (en) 2001-10-09 2001-10-09 Mounting method of semiconductor chip and mounting structure of semiconductor chip

Country Status (1)

Country Link
JP (1) JP2003124258A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100804879B1 (en) * 2005-03-15 2008-02-20 가시오게산키 가부시키가이샤 Mounting structure and mounting method of a semictonductor device, and liquid crystal display device
US8337049B2 (en) 2008-07-07 2012-12-25 Panasonic Corporation Bulb-type lighting source
WO2018159186A1 (en) * 2017-02-28 2018-09-07 富士フイルム株式会社 Semiconductor device, laminate, semiconductor device manufacturing method, and laminate manufacturing method

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100804879B1 (en) * 2005-03-15 2008-02-20 가시오게산키 가부시키가이샤 Mounting structure and mounting method of a semictonductor device, and liquid crystal display device
US8337049B2 (en) 2008-07-07 2012-12-25 Panasonic Corporation Bulb-type lighting source
WO2018159186A1 (en) * 2017-02-28 2018-09-07 富士フイルム株式会社 Semiconductor device, laminate, semiconductor device manufacturing method, and laminate manufacturing method
TWI729267B (en) * 2017-02-28 2021-06-01 日商富士軟片股份有限公司 Semiconductor device, laminate, method of manufacturing semiconductor device, and method of manufacturing laminate

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