JP3810064B2 - Liquid crystal display - Google Patents

Liquid crystal display Download PDF

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Publication number
JP3810064B2
JP3810064B2 JP2002071403A JP2002071403A JP3810064B2 JP 3810064 B2 JP3810064 B2 JP 3810064B2 JP 2002071403 A JP2002071403 A JP 2002071403A JP 2002071403 A JP2002071403 A JP 2002071403A JP 3810064 B2 JP3810064 B2 JP 3810064B2
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semiconductor element
layer
conductive particles
electrode terminal
hardness
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JP2003273163A (en
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幸広 小坂
剛 石亀
光 藤田
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Panasonic Corp
Panasonic Holdings Corp
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Panasonic Corp
Matsushita Electric Industrial Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector

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  • Liquid Crystal (AREA)
  • Wire Bonding (AREA)

Description

【０００１】
【発明の属する技術分野】
本発明は、表面に電極端子が形成された半導体素子実装用基板又は半導体素子を用いた液晶表示装置に関する。
【０００２】
【従来の技術】
近年、電子機器の小型化の要求に対応するため、より高密度の半導体素子の実装が要求される。この高密度の実装を行う方法として一般的にフェイスダウンによる実装方法がある。図６に半導体素子ＩＣ１を半導体素子実装用基板１４にフェイスダウンにより実装した状態を示す。このフェイスダウンによる実装は、半導体素子ＩＣ１のバンプ１Ｂと半導体実装用基板１４の電極端子１１とを対向させて、圧着ツールを使用して半導体素子ＩＣ１の上側から加熱加圧し、半導体素子ＩＣ１を半導体実装基板１４である透明なガラス基板に導電粒子ｒを含む異方性導電膜（Anisotropic Conductive Film：ACF）８を介して固着することにより、半導体素子ＩＣ１を半導体実装基板１４に実装する方法であり、異方性導電膜８を接続端子間に介在させることにより高密度実装を可能にするようになってきている（ファインピッチ化）。この実装方法によれば、ワイヤボンディング等による通常の実装方法に比べて、半導体素子ＩＣ１を高密度に実装できるという利点がある。
【０００３】
このようにフェイスダウンにより実装された半導体素子ＩＣ１のバンプ１Ｂと半導体実装基板１の電極端子１１との電気的接続は、異方性導電膜８の導電粒子ｒをバンプ１Ｂと電極端子１１との間に挟持されることで導通状態が得られるが、その電気的接続は、半導体素子ＩＣを上側から押圧する押圧力（熱圧着）により導電粒子ｒを押し潰して接続抵抗を小さくすることによって確実なものとされる。
【０００４】
電極端子１１の材料としては、アルミニウム（Ａｌ）やクロム（Ｃｒ）、金（Ａｕ）、ＩＴＯ等が用いられており、バンプ１Ｂの材料としては、金（Ａｕ）等が用いられている。異方性導電膜８は、絶縁性を有する接着剤中に導電粒子ｒが分散され厚み方向（接続方向）に導電性を有し、面方向（横方向）に絶縁性を有するペースト状又はフィルム状の接着剤８であり、導電粒子ｒには、ニッケル粒子や、樹脂製の粒子に金メッキを施したもの等が用いられている。
【０００５】
かかるフェイスダウンにより実装された半導体素子ＩＣ１のバンプ１Ｂと半導体素子実装用基板１４の電極端子１１との導通検査には様々な方法があるが、その一つとして導電粒子ｒの圧痕（熱圧着による痕跡）の有無により検査する方法がある。この検査方法は、主にガラスやプラスチック等の透明なガラス基板１４に半導体素子ＩＣが実装されるＣＯＧ実装の場合に用いられる検査方法であり、実装工程において半導体素子ＩＣを上側から押圧すると、電極端子１１に導電粒子ｒが押し当てられ電極端子１１が隆起して圧痕が生じるが、この圧痕の数や大きさや高さ等を透明なガラス基板１４の裏側から観察することにより導通状態を判断する方法である。この検査方法によれば、導電粒子ｒの圧痕の数や大きさや高さに所定の基準を設けて、基準より高い場合は導通良好であり、低い場合は導通不良と判断される。なお、液晶表示パネルにおける半導体素子の実装では、ガラス基板上の電極端子（接続用電極又は電極パッド）に直接半導体素子を接続するＣＯＧ（chip on glass）実装が主流となって来ているが、ＣＯＧ実装等は、前記異方性導電膜（ＡＣＦ）を使用して、バンプを有する半導体素子を実装することが通常であり、この検査方法は液晶表示パネルの導通検査に用いられることが多い。
【０００６】
【発明が解決しようとする課題】
しかしながら、前記従来の構成では、例えば電極端子１１にアルミニウム（Ａｌ）等のような硬度の低い材料を使用した場合は、図７に示すように、圧着ツールＳ２で半導体素子ＩＣ１を押圧すると（図中矢印方向）、導電粒子ｒが硬度の低い電極端子１１に埋もれ過ぎてしまい潰れないことがあった。すなわち、圧着ツールからの押圧力がバンプ１Ｂと電極端子１１との間に挟持された導電粒子ｒに加わり電極端子１１に埋もれるが、更にその導電粒子ｒを潰すまでの押圧力が加わらないため、潰れないことがあった。このため、バンプ１Ｂと導電粒子ｒとの接地面積が小さくなり、接続抵抗が高くなって電極端子１１とバンプ１Ｂとの間に導通不良が生じることがあり、電気的接続の信頼性が低いという問題があった。また、硬度の低い電極端子１１は衝撃や熱等に弱く、経時的変化によって導通不良が生じることがあり、初期検査時においては導通不良が発生していない場合でも、出荷後等において導通不良が発生する場合もあった。経時的変化としては、例えば、温度変化や他の部品の実装や組み立てによる影響等により形状等が変化する。
【０００７】
かかる問題は、特に導電粒子ｒの硬度よりも電極端子１１の硬度が低い場合に生じていた。すなわち、導電粒子ｒがニッケル粒子等の材料で形成されており、電極端子１１がニッケル等よりも硬度の低いアルミニウム等の材料で形成されている場合には、導電粒子ｒが電極端子１１に埋もれてしまい押し潰されないため、導通不良が発生していた。
【０００８】
一方、電極端子１１にニッケル（Ｎｉ）等の硬度が高い材料を使用した場合は、導電粒子ｒが電極端子１１に埋もれ過ぎることがなく上記問題は生じないが、図８（ａ）に示すように、複数のバンプ１Ｂ，１Ｂの高さにバラツキがある場合は、高さの低いバンプ１Ｂ１では導電粒子ｒが十分に加圧されず潰れなかったり、図８（ｂ）に示すように、製造不良等によりバンプ１Ｂ（１Ｂ１）の表面に凹部（クレーター）がある場合は、凹部の個所では導電粒子ｒが十分に加圧されず潰されなかったり、図８（ｃ）に示すように、半導体素子ＩＣの厚みが不均一であり部分的に薄くなっている場合は、半導体素子ＩＣの厚みが薄くなっている方のバンプ１Ｂ１では導電粒子ｒが十分に加圧されず潰されないため、導電粒子ｒとバンプ１Ｂ（１Ｂ１）及び導電粒子ｒと電極端子１１との接続抵抗が高くなり、導通不良が生じていた。
【０００９】
これらの問題は、電極端子１１の表面に凹部がある場合（バンプ表面や電極端子表面には凹凸があり、熱圧着により高さで約１〜２μｍ程度変形する。）や、電極端子１１の高さにバラツキがある場合、半導体素子実装用基板１４の厚みが不均一な場合にも同様に生じていた。
【００１０】
また、導電粒子ｒの圧痕により導通状態を検査する検査方法においては、電極端子１１に硬度の低い材料を用いると、電極端子１１に圧痕が出現しにくいため、半導体実装用基板１４の裏側から圧痕が認識し難く、顕微鏡等を使用した目視検査が行い難くなったり、検査精度が低下したりする等の問題が生じていた。
【００１１】
そこで本発明の目的は、導電粒子が埋もれ過ぎることがなく、半導体素子のバンプや半導体素子実装用基板の電極端子の表面に凹部がある場合や、高さにバラツキがある場合、半導体素子や半導体素子実装用基板の厚みが不均一な場合等でも導通状態を良好にすることができ、経時的変化による導通不良の発生も少なく、また、導通粒子の圧痕も出現し易い半導体素子実装用基板又は半導体素子を用いた液晶表示装置に関する。
【００１２】
【課題を解決するための手段】
本発明の請求項１記載の液晶表示装置は、一対の基板の間に液晶を挟持する液晶表示装置において、前記一対の基板の一方側基板に電極端子が形成され、バンプを有する半導体素子が導電粒子を含む異方性導電膜を介してＣＯＧ実装されており、上記電極端子は、基板側から順に一層以上の下位層と最上位層が積層された複数層で構成されており、最上位層は少なくとも一の下位層よりも硬度が高く、且つ前記最上位層の硬度は導電粒子の硬度よりも高いことを特徴とする。一以上の下位層は、一層でも良く、二層以上でも良い。
【００１３】
この発明によれば、導電粒子を含む異方性導電膜を介してバンプを有する半導体素子を熱圧着により実装する際、電極端子の最上位層は少なくとも一の下位層よりも硬度が高いので、硬度の高い最上位層ではバンプと電極端子との間に挟持された導電粒子が埋もれ過ぎず、導電粒子が潰され易くなるとともに、硬度の低い少なくとも一の下位層により、バンプや半導体素子の表面の凹部や高さのバラツキや、半導体素子の厚みの不均一を吸収することができる。また、最上位層の硬度が導電粒子の硬度よりも高いため、導電粒子は最上位層に埋もれ過ぎることなく、確実に潰されることとなる。
【００１４】
本発明の請求項２記載の液晶表示装置は、一対の基板の間に液晶を挟持する液晶表示装置において、前記一対の基板の一方側基板に電極端子が形成され、バンプを有する半導体素子が導電粒子を含む異方性導電膜を介してＣＯＧ実装されるとともに、前記一方側基板が前記電極端子を裏面側から透視可能な透明な基板からなり、上記電極端子は、基板側から順に最下位層、一層以上の内層、最上位層が積層された複数層で構成されており、最上位層及び最下位層は少なくとも一の内層よりも硬度が高く、且つ前記最上位層の硬度は導電粒子の硬度よりも高いことを特徴とする。一層以上の内層は、一層でも良く、二層以上でも良い。
【００１５】
この発明によれば、導電粒子を含む異方性導電膜を介してバンプを有する半導体素子を熱圧着により実装する際、電極端子の最上位層は少なくとも一の内層よりも硬度が高いので、半導体素子を載置して押圧すると、硬度の高い最上位層ではバンプと電極端子との間に挟持された導電粒子が埋もれ過ぎず、導電粒子が潰され易くなるとともに、硬度の低い少なくとも一の下位層により、バンプや半導体素子の表面の凹部や高さのバラツキや、半導体素子の厚みの不均一を吸収することができる。また、半導体素子実装用基板は透明な基板からなるとともに電極端子の最下位層は硬度が高いので、半導体素子実装用基板半導体素子実装用基板の裏側から導電粒子の圧痕が認識し易くなり、導電粒子の圧痕による導通検査が行い易くなる。
【００１６】
本発明の請求項３記載の液晶表示装置は、請求項２記載の発明を前提として、前記電極端子の厚みをＴとし、前記一以上の内層の厚みをｔとし、電極端子の層数をａとすると、ｔ≦３Ｔ／ａを満たすことを特徴とする。
【００１７】
この発明によれば、一以上の内層の厚みが厚くなり過ぎすることがないので、半導体素子を載置して押圧しても、その押圧力が内層により吸収され過ぎることがない。すなわち、本願発明者等は、内層の厚さが厚いと、導電粒子を潰す確率が低くなることを認識しているが、上記関係式を満たすことにより、導電粒子に適当な押圧力（熱圧着力）、特に上方からの押圧力が加えることにより、導電粒子が硬度の高い最上位層に潰され易くなる。また、押圧力が最下位層に伝達され易くなるため最下位層に導電粒子の圧痕が更に出現し易くなる。
【００２２】
本発明の請求項５記載の液晶表示装置は、請求項１から４記載の発明を前提として、上記バンプは、半導体素子側から順に一層以上の下位層と最上位層が積層された複数層で構成されており、最上位層は下位層のうち少なくとも一の下位層よりも硬度が高く、且つ前記バンプの最上位層の硬度は、前記導電粒子の硬度よりも高いことを特徴とする。
【００２３】
この発明によれば、バンプの最上位層は少なくとも一の下位層よりも硬度が高いので、半導体素子を載置して押圧すると、硬度の高い最上位層では突起電極と電極端子との間に挟持された導電粒子が埋もれ過ぎることがなく、硬度の低い少なくとも一の下位層ではバンプや半導体素子の高さのバラツキや、半導体素子の厚みの不均一を吸収することができる。したがって、導電粒子が潰され易くなり、電極端子とバンプとの導通の信頼性を高めることができる。導電粒子との接続部分は硬度が高い層なので、接続部分の経時的変化による導通不良も生じにくい。
【００２８】
【発明の実施の形態】
以下、本発明の実施の形態を図面に基づいて説明する。
【００２９】
（第１の実施の形態）本発明の第１の実施の形態は、バンプＢを有する半導体素子ＩＣが実装される半導体素子実装用基板４である。図１（ａ）は、本発明の第１の実施の形態の半導体素子実装用基板４を示す図である。半導体素子実装用基板４の表面には、半導体素子ＩＣのバンプＢとの間に導電粒子ｒを挟持して導通する電極端子１が形成されている。電極端子１には中央を露出して両端部を覆うように絶縁膜２が形成されており、さらに電極端子１と絶縁膜２の上にはＩＴＯ層３が形成されている。半導体素子実装用基板４はガラス製の透明基板であるが、フレキシブル基板等のその他の基板でもよい。
【００３０】
電極端子１は半導体素子実装用基板４側から順に下位層１ａと最上位層１ｃが積層された二層が突出するように構成されており、最上位層１ｃは下位層１ａよりも硬度が高くなっている。具体的には、最上位層１ｃはチタン（Ｔｉ）であり、下位層１ａはアルミニウム（Ａｌ）であり、フォトリソグラフィとメッキによる方法等により形成されている。電極端子１の材料は、かかる材料に限られるものではなく、下位層１ａよりも最上位層１ｃの方が硬度が高い導電性の材料であれば良い。なお、本実施の形態の電極端子１は下位層１ａが一層で最上位層１ｃが一層の二層構造であるが、下位層が二層以上で最上位層が一層の三層以上の構造でも良い。下位層が二層以上の場合は、最上位層が下位層のうち少なくとも１つの層よりも硬度が高ければ良い。また、最上位層と下位層の材料はチタンとアルミニウムに限らず、ニッケル（Ｎｉ）とアルミニウム（Ａｌ）や、純度の高い金（Ａｕ）と純度の低い金（Ａｕ）等のその他の材料でも良い。
【００３１】
次に、本実施の形態の半導体素子実装用基板４に半導体素子ＩＣを実装する方法について説明する。図１（ｂ）は本実施の形態の半導体素子実装用基板４に異方性導電膜８を介して半導体素子ＩＣを実装した状態の図である。半導体素子ＩＣの裏面には、外周辺に沿って突起状電極であるバンプＢが多数形成されている。半導体素子ＩＣを実装する場合は、半導体素子実装用基板４の電極端子１の上に導電粒子ｒを含む異方性導電膜８を配置して（仮接着して）、半導体素子ＩＣのバンプＢが半導体素子実装用基板４の電極端子１に対応するように半導体素子ＩＣを位置合わせし、その後、圧着ツールＳ１とＳ２により加熱しながら加圧して（熱圧着して）、半導体素子ＩＣを半導体素子実装用基板４に実装する。電極端子１とバンプＢとの間には導電粒子ｒが挟持され、導電粒子ｒを介して導通が図られる。異方性導電膜８は、絶縁性を有する接着剤中に導電粒子ｒが分散され厚み方向（接続方向）に導電性を有し、面方向（横方向）に絶縁性を有するペースト状又はフィルム状の接着剤８である。導電粒子ｒは、ニッケル粒子や、樹脂製の粒子に金メッキを施したものや、その他のものでも良い。接着剤はエポキシ樹脂等の熱硬化性樹脂に限らず、熱可塑性樹脂を用いても良い。
【００３２】
圧着ツールＳ１とＳ２により挟まれると、電極端子１の最上位層１ｃは、下位層１ａよりも硬度が高いので、突起電極（バンプ）Ｂと電極端子１との間に挟持された導電粒子ｒが最上位層１ｃに埋もれ過ぎることがなく潰され易くなる。すなわち、導電粒子ｒの埋もれる量が減少した分、導電粒子ｒに加わる力（圧着力）が増加することにより、これまで加圧が十分に加わらず（届かず）に潰しきれなかった導電粒子ｒを潰す確率が高くなる。このため、初期の導通検査時には導通不良が起きていないが、電極端子１の形状の経時的変化を原因とする導通不良も生じにくくなる。また、バンプＢの表面に凹部が生じていたり、バンプＢ１とバンプＢ２の高さにバラツキがあったり、半導体素子ＩＣの厚みが不均一であるような事態等（更に、バンプＢと導電粒子ｒ又は導電粒子ｒと電極端子１との間への異物の混入等）が生じていても、圧着ツールＳ２により上方から押圧されると、下位層１ａは最上位層１ｃよりも硬度が低いため、バンプＢの表面の凹部や高さのバラツキや、半導体素子ＩＣの厚みの不均一を吸収することができる。したがって、電極端子１とバンプＢとの導通の信頼性を高めることができる。
【００３３】
（第２の実施の形態）本発明の第２の実施の形態は、半導体素子実装用基板４の表面に形成される電極端子１は、半導体素子実装用基板４側から順に最下位層１ａ、内層１ｂ、最上位層１ｃが積層された三層で突出するように構成されており、最上位層１ｃ及び最下位層１ａは内層１ｂよりも硬度が高くなっている。具体的には、最上位層１ｃ及び最下位層１ａはチタン（Ｔｉ）であり、内層１ｂはアルミニウム（Ａｌ）である。半導体素子実装用基板４はガラス製の透明基板であるが、透明基板であれば、プラスチック樹脂等のその他の材料で形成されていても良い。
【００３４】
本実施の形態の電極端子１は、電極端子１の厚みをＴとし、内層１ｂの厚みをｔとし、電極端子１の層数をａとすると、ｔ≦３Ｔ／ａを満たす。本実施の形態の電極端子１の層数は３層であるからａ＝３である。
【００３５】
ここで、本実施の形態の電極端子１は、最下位層１ａ、内層１ｂ、最上位層１ｃがそれぞれ一層の三層構造であるが、最下位層１ａと最上位層１ｃが内層１ｂのうち少なくとも１つの層よりも硬度が高ければ、内層１ｃが二層以上であり最下位層１ａと最上位層１ｃがそれぞれ１層の四層以上の構造でも良い。また、図１のように、電極端子１や絶縁膜２の上に透明電極層（ＩＴＯ）が形成されていても良い。
【００３６】
図２（ｂ）は本実施の形態の半導体素子実装用基板４に半導体素子ＩＣを実装した状態の図である。電極端子１の最上位層１ｃ及び最下位層１ａは内層１ｂよりも硬度が高いので、突起電極Ｂと電極端子１との間に挟持された導電粒子ｒが最上位層１ｃに埋もれ過ぎることなく潰され易くなる。すなわち、導電粒子ｒの埋もれる量が減少した分、導電粒子ｒに加わる力が増加することにより、これまで潰しきれなかった導電粒子ｒが潰れる確立が高くなる。また、バンプＢの表面に凹凸（バンプ表面や電極端子表面には凹凸があり、熱圧着により高さで約１〜２μｍ程度変形する。凹部はクレータとも呼ばれる）が生じていたり、バンプＢ１とバンプＢ２の高さにバラツキがあったり、半導体素子ＩＣの厚みが不均一であっても、内層１ｂは最下位層１ａ及び最上位層１ｃよりも硬度が低いため、これらの不均一等を効果的に吸収することとなる。したがって、電極端子１とバンプＢとの導通の信頼性を高めることができる。最下位層１ｃは硬度が高いため導電粒子ｒの圧痕が出現し易くなる。また、透明な半導体素子実装用基板４の裏側から導電粒子ｒの圧痕が認識し易くなるため、導電粒子ｒの圧痕による導通検査が行い易くなり、検査精度も高めることができる。
【００３７】
さらに、内層１ｂの厚みｔがｔ≦３Ｔ／ａを満たすことで、厚くなり過ぎすることがないので、半導体素子ＩＣを載置して上側から押圧しても、その押圧力が内層により吸収され過ぎることがない。したがって、導電粒子ｒに適当な押圧力が加わるため、導電粒子ｒが更に潰され易くなり、押圧力が最下位層１ａに伝達され易くなるため最下位層１ａに導電粒子ｒの圧痕が更に出現し易くなる。
【００３８】
（第２の実施の形態の応用例）第２の実施の形態の応用例として、４層構造の電極端子１が形成された半導体素子実装用基板４を説明する。図３は本実施の形態の応用例の半導体素子実装用基板４を示す図である。本実施の形態の応用例の半導体素子実装用基板４は、電極端子１が、半導体素子実装用基板４側から順に、最下位層１ａと下側の内層１ｂ１と上側の内層１ｂ２と最上位層１ｃとが積層された四層構造となっており、最下位層１ａ及び最上位層１ｃは２つの内層１ｂ１，１ｂ２よりも硬度が高くなっている。具体的には最下位層１ｃ及び最上位層１ａがチタン（Ｔｉ）であり、下側の内層１ｂ１がニッケル（Ｎｉ）であり、上側の内層１ｂ２がアルミニウム（Ａｌ）である。本実施の形態の応用例では、最下位層１ａ及び最上位層１ｃがいずれの内層１ｂ１，１ｂ２よりも硬度が高くなっているが、内層１ｂ１，１ｂ２のうち少なくとも一の内層よりも硬度が高ければ良い。
【００３９】
（第３の実施の形態）本発明の第３の実施の形態の半導体素子ＩＣは、電極端子１が形成された半導体素子実装用基板４に実装される半導体素子ＩＣであり、電極端子１との間に導電粒子ｒを挟持して導通する突起電極であるバンプＢが形成されている。図４（ａ）は、本発明の第３の実施の形態の半導体素子ＩＣを示す図である。半導体素子ＩＣの裏面には、外周辺に沿って突起状電極であるバンプＢが多数形成されている。
【００４０】
バンプＢは半導体素子ＩＣ側から順に下位層Ｂａと最上位層Ｂｃが積層された二層で構成されており、最上位層Ｂｃは下位層Ｂａよりも硬度が高くなっている。具体的には、最上位層Ｂｃはチタン（Ｔｉ）であり、下位層ＢａはアルミニウムＡｌであり、フォトリソグラフィとメッキによる方法等によりバンプＢが形成されている。バンプＢの材料は、かかる材料に限られるものではなく、下位層Ｂａよりも最上位層Ｂｃの方が硬度が高い導電性の材料であれば良い。なお、本実施の形態のバンプＢは下位層Ｂａが一層で最上位層Ｂｃが一層の二層構造であるが、下位層Ｂａが二層以上で最上位層Ｂｃが一層の三層以上の構造でも良い。下位層Ｂａが二層以上の場合は、最上位層Ｂｃが下位層Ｂａのうち少なくとも一の層よりも硬度が高ければ良い。また、最上位層Ｂｃと下位層Ｂａの材料はチタンとアルミニウムに限らず、純度の高い金（Ａｕ）と純度の低い金（Ａｕ）や、ニッケル（Ｎｉ）とアルミニウム等のその他の材料でも良い。
【００４１】
次に、本実施の形態のバンプＢが形成された半導体素子ＩＣを半導体素子実装用基板４に実装する方法について説明する。図４（ｂ）は本実施の形態の半導体素子ＩＣを半導体素子実装用基板４に実装した状態の図である。バンプＢの最上位層Ｂｃは下位層Ｂａよりも硬度が高いので、突起電極Ｂと電極端子１との間に挟持された導電粒子ｒが最上位層Ｂｃに埋もれ過ぎることなく潰され易くなる。また、バンプＢの表面に凹部があったり、バンプＢ１とバンプＢ２の高さにバラツキがあったり、半導体素子ＩＣの厚みが不均一であっても、下位層Ｂａは最上位層Ｂｃよりも硬度が低く潰れ易いため、バンプＢの表面の凹部や高さのバラツキや、半導体素子ＩＣの厚みの不均一等を吸収することができる。
【００４２】
（第４の実施の形態）本実施の形態の半導体素子実装用基板又は半導体素子は、前記第１の実施の形態又は第２の実施の形態の半導体素子実装用基板４、または前記第３の実施の形態の半導体素子ＩＣであり、導電粒子ｒは樹脂に金メッキを施した導電粒子ｒである。半導体素子実装用基板４に形成された電極端子１の最上位層１ｃはチタンであり、導電粒子ｒの硬度よりも高いため、導電粒子ｒは最上位層１ｃに埋もれ過ぎることなく、潰され易くなる（図１（ｂ）、図２（ｂ）参照）。また、第３の実施の形態の半導体素子ＩＣに形成されたバンプＢの最上位層Ｂｃはチタンであり、前記導電粒子ｒの硬度よりも高いため、導電粒子ｒがバンプＢの最上位層Ｂｃに埋もれ過ぎることなく、潰され易くなる（図４（ｂ）参照）。
【００４３】
（液晶表示装置への適用例）以下、具体的な例として、本発明の半導体素子実装用基板４又は本発明の半導体素子ＩＣをＣＯＧ実装の液晶表示装置に適用した場合を説明する。図５はＣＯＧ実装の液晶表示装置を示す図である。液晶パネルＬＣＤは、現在使用されている代表的なアクティブ素子であるＴＦＴを用いた反射型液晶表示装置ＬＣＤである。
【００４４】
液晶パネルＬＣＤの一方の基板（一方の基板：ＡＭ基板ともアレイ基板とも呼ばれる）４は、他方の基板５よりも大きく、このため両基板４，５を重ね合わせると、ＡＭ基板４の周辺に一部張り出した半導体素子ＩＣの実装領域６が形成されている。このＡＭ基板４の実装領域６には、半導体実装用の配線パターン７が形成されている。なお、ＡＭ基板４としてはガラス基板の他、合成樹脂製のフレキシブル基板でも良い。
【００４５】
本実施の形態の半導体素子ＩＣは、ＡＭ基板４の実装領域６に、導電粒子ｒを含む異方性導電膜８を介して実装されている。半導体素子ＩＣの裏面側には、外周辺に沿ってバンプＢが対向して多数形成されている。
【００４６】
配線パターン７の端部には、半導体素子ＩＣに接続する電極端子１がパターン形成されている。一方側（図５中左側）の電極端子１は入力電極であり、他方側（図５中右側）の電極端子１は出力電極である。そして、液晶パネルＬＣＤを駆動させる半導体素子ＩＣは、接着剤に導電粒子ｒを含んだ異方性導電膜（ＡＣＦ）８を介して実装されている。
【００４７】
かかる液晶パネルＬＣＤに本発明の半導体素子実装用基板４を適用する場合は、ＡＭ基板４として使用する。つまり、実装領域５の従来の電極端子１を上記実施の形態の電極端子１とする。また、本発明の半導体素子ＩＣを適用する場合は、実装領域５に配される半導体素子ＩＣとして使用する。つまり、実装領域５に配される半導体素子ＩＣのバンプＢを上記実施の形態のバンプＢとする。本発明の電極端子１を形成した半導体素子実装用基板４と、本発明のバンプＢを形成した半導体素子ＩＣは、液晶表示パネルＬＣＤに同時に適用しても良いし、いずれか一方のみを適用しても良い。
【００４８】
本発明の適用例では、ＣＯＧ実装の液晶表示装置を例に説明したが、フレキシブル基板に接着剤を介して半導体素子を実装するＣＯＦ実装の液晶表示装置や、その他電子機器にも適用可能である。
【００４９】
【発明の効果】
以上説明したように、本発明によれば、最上位層及び最下位層は少なくとも一の内層よりも硬度が高いので、半導体素子を載置して押圧すると、硬度の高い最上位層では突起電極と電極端子との間に挟持された導電粒子が埋もれ過ぎることなく潰され易くなり、硬度の低い少なくとも一の内層ではバンプや半導体素子の表面の凹部や高さのバラツキを吸収することができる。導電粒子との接続部分は硬度が高い層なので、接続部分の経時的変化による導通不良も生じにくいしたがって、本発明の半導体素子実装用基板、又は本発明の半導体素子によれば、バンプと電極端子との導通の信頼性を高めることができる。また、最下位層は硬度が高いため、導電粒子の圧痕を出現させ易くすることができる。したがって、半導体素子実装用基板の裏側から導電粒子の圧痕が認識し易くなるため、導電粒子の圧痕による導通検査が行い易くなり、検査精度も高めることができる。
【００５０】
【図面の簡単な説明】
【図１】（ａ）は第１の実施の形態の半導体素子実装用基板を示す図、（ｂ）はその半導体素子実装用基板に半導体素子を実装した状態の図
【図２】（ａ）は第２の実施の形態の半導体素子実装用基板を示す図、（ｂ）はその半導体素子実装用基板に半導体素子を実装した状態の図
【図３】（ａ）は第２の実施の形態の応用例の半導体素子実装用基板を示す図、（ｂ）はその半導体素子実装用基板に半導体素子を実装した状態の図
【図４】（ａ）は第３の実施の形態の半導体素子を示す図、（ｂ）はその半導体素子を半導体素子実装基板に実装した状態の図
【図５】本発明の半導体素子実装用基板と半導体素子を適用した液晶表示パネルを示す図
【図６】半導体素子を半導体素子実装用基板にフェイスダウンにより実装した状態を示す図
【図７】導電粒子が電極端子に埋もれてしまい潰れていない状態を示す図
【図８】（ａ）はバンプの表面が凹形状になっている状態、（ｂ）は複数のバンプの高さにバラツキがある状態、（ｃ）は半導体素子の厚みが不均一な状態を示す図
【符号の説明】
ＩＣ、ＩＣ１ 半導体素子
１、１１ 電極端子
１ａ 電極端子の下位層、最下位層
１ｂ 電極端子の内層
１ｃ 電極端子の最上位層
２ 絶縁膜
３ ＩＴＯ
４、１４ 半導体素子実装用基板、一方の基板（ＡＭ基板）
５ 他方の基板
６ 実装領域
７ 配線パターン
８ 異方性導電膜
ｒ 導電粒子
Ｂ、１Ｂ バンプ
Ｂａ バンプの下位層
Ｂｃ バンプの最上位層
ｔ 電極端子の内層の厚み
Ｔ 電極端子の厚み
ＬＣＤ 液晶表示パネル[0001]
BACKGROUND OF THE INVENTION
  The present invention relates to a substrate for mounting a semiconductor element having an electrode terminal formed on the surface or a liquid crystal display device using the semiconductor element.
[0002]
[Prior art]
In recent years, mounting of higher-density semiconductor elements is required to meet the demand for downsizing electronic devices. As a method of performing this high-density mounting, there is generally a mounting method by face-down. FIG. 6 shows a state in which the semiconductor element IC1 is mounted on the semiconductor element mounting substrate 14 by face-down. In this face-down mounting, the bump 1B of the semiconductor element IC1 and the electrode terminal 11 of the semiconductor mounting substrate 14 are made to face each other and heated and pressed from above the semiconductor element IC1 using a crimping tool to In this method, the semiconductor element IC1 is mounted on the semiconductor mounting substrate 14 by being fixed to the transparent glass substrate, which is the mounting substrate 14, via an anisotropic conductive film (ACF) 8 containing conductive particles r. Further, high-density mounting has become possible by interposing the anisotropic conductive film 8 between the connection terminals (fine pitch). According to this mounting method, there is an advantage that the semiconductor element IC1 can be mounted at a high density as compared with a normal mounting method such as wire bonding.
[0003]
Thus, the electrical connection between the bump 1B of the semiconductor element IC1 mounted by face-down and the electrode terminal 11 of the semiconductor mounting substrate 1 is performed by connecting the conductive particles r of the anisotropic conductive film 8 between the bump 1B and the electrode terminal 11. The conductive state is obtained by being sandwiched between them, but the electrical connection is ensured by reducing the connection resistance by crushing the conductive particles r by pressing force (thermocompression) that presses the semiconductor element IC from above. It is assumed.
[0004]
Aluminum (Al), chromium (Cr), gold (Au), ITO or the like is used as the material of the electrode terminal 11, and gold (Au) or the like is used as the material of the bump 1B. The anisotropic conductive film 8 is a paste or film having conductive particles r dispersed in an insulating adhesive, conductive in the thickness direction (connection direction), and insulative in the surface direction (lateral direction). The conductive adhesive r is made of nickel particles, resin-made particles plated with gold, or the like.
[0005]
There are various methods for inspecting the continuity between the bump 1B of the semiconductor element IC1 mounted by the face-down and the electrode terminal 11 of the semiconductor element mounting substrate 14, and one of them is an indentation (by thermocompression bonding) of the conductive particles r. There is a method of inspection based on the presence or absence of traces. This inspection method is an inspection method mainly used in the case of COG mounting in which a semiconductor element IC is mounted on a transparent glass substrate 14 such as glass or plastic. When the semiconductor element IC is pressed from above in the mounting process, The conductive particles r are pressed against the terminals 11 and the electrode terminals 11 are raised to form indentations, and the conduction state is determined by observing the number, size, height, and the like of these indentations from the back side of the transparent glass substrate 14. Is the method. According to this inspection method, a predetermined standard is set for the number, size, and height of the indentations of the conductive particles r, and when it is higher than the standard, it is determined that conduction is good, and when it is low, it is determined that conduction is poor. In addition, in the mounting of the semiconductor element in the liquid crystal display panel, COG (chip on glass) mounting in which the semiconductor element is directly connected to the electrode terminal (connection electrode or electrode pad) on the glass substrate has become mainstream. In COG mounting or the like, a semiconductor element having bumps is usually mounted using the anisotropic conductive film (ACF), and this inspection method is often used for a continuity inspection of a liquid crystal display panel.
[0006]
[Problems to be solved by the invention]
However, in the conventional configuration, when a material with low hardness such as aluminum (Al) is used for the electrode terminal 11, for example, as shown in FIG. 7, when the semiconductor element IC1 is pressed with the crimping tool S2 (FIG. In the middle arrow direction), the conductive particles r may be buried too much in the electrode terminal 11 having a low hardness and may not be crushed. That is, the pressing force from the crimping tool is applied to the conductive particles r sandwiched between the bumps 1B and the electrode terminals 11 and buried in the electrode terminals 11, but further no pressing force is applied until the conductive particles r are crushed. Sometimes it didn't collapse. For this reason, the grounding area between the bump 1B and the conductive particles r is reduced, the connection resistance is increased, and a conduction failure may occur between the electrode terminal 11 and the bump 1B, and the reliability of electrical connection is low. There was a problem. In addition, the electrode terminal 11 with low hardness is vulnerable to shock, heat, etc., and a continuity failure may occur due to changes over time. Even if no continuity failure has occurred during the initial inspection, the continuity failure will not occur after shipment. Sometimes it occurred. As the change over time, for example, the shape or the like changes due to a change in temperature or the influence of mounting or assembling of other components.
[0007]
Such a problem occurs particularly when the hardness of the electrode terminal 11 is lower than the hardness of the conductive particles r. That is, when the conductive particles r are formed of a material such as nickel particles and the electrode terminal 11 is formed of a material such as aluminum having a lower hardness than nickel, the conductive particles r are buried in the electrode terminal 11. Since it was not crushed, continuity failure occurred.
[0008]
On the other hand, when a material having high hardness such as nickel (Ni) is used for the electrode terminal 11, the conductive particles r are not buried too much in the electrode terminal 11, and the above problem does not occur. However, as shown in FIG. In addition, when there are variations in the heights of the plurality of bumps 1B, 1B, the conductive particles r are not sufficiently pressed and are not crushed by the bumps 1B1 having a low height, as shown in FIG. When there is a recess (crater) on the surface of the bump 1B (1B1) due to a defect or the like, the conductive particles r are not sufficiently pressed at the location of the recess and are not crushed, as shown in FIG. When the thickness of the element IC is not uniform and partially thinned, the conductive particles r are not sufficiently pressed and crushed by the bump 1B1 where the thickness of the semiconductor element IC is thin. r and bump 1B (1B1 Contact resistivity of the conductive particles r and the electrode terminal 11 increases, conduction failure has occurred.
[0009]
These problems are caused when there is a recess on the surface of the electrode terminal 11 (the bump surface or the electrode terminal surface has irregularities and deforms by about 1 to 2 μm in height by thermocompression bonding), or the height of the electrode terminal 11 is high. In the case where the thickness varies, the same problem occurs when the thickness of the semiconductor element mounting substrate 14 is not uniform.
[0010]
  Further, in the inspection method for inspecting the conduction state by the indentation of the conductive particles r, when a material having low hardness is used for the electrode terminal 11, the electrode terminal 11 has an indentation.Because it is hard to appear,The indentation is difficult to recognize from the back side of the semiconductor mounting substrate 14, and it has become difficult to perform a visual inspection using a microscope or the like, and the inspection accuracy is lowered.
[0011]
  Therefore, an object of the present invention is to prevent the conductive particles from being buried too much, and when there is a recess in the surface of the bump of the semiconductor element or the electrode terminal of the substrate for mounting the semiconductor element, or when the height varies, the semiconductor element or semiconductor Even when the thickness of the element mounting substrate is not uniform, the conductive state can be made good, the occurrence of poor conduction due to change over time is small, and the indentation of conductive particles is likely to appear or The present invention relates to a liquid crystal display device using a semiconductor element.
[0012]
[Means for Solving the Problems]
  According to claim 1 of the present inventionThe liquid crystal display device is a liquid crystal display device in which liquid crystal is sandwiched between a pair of substrates, an anisotropic conductive film in which electrode terminals are formed on one side of the pair of substrates, and a semiconductor element having bumps includes conductive particles The electrode terminal is composed of a plurality of layers in which one or more lower layers and an uppermost layer are laminated in order from the substrate side, and the uppermost layer is more than at least one lower layer. The hardness is high and the hardness of the uppermost layer is higher than the hardness of the conductive particles.One or more lower layers may be a single layer or two or more layers.
[0013]
  According to this invention, when mounting a semiconductor element having a bump via an anisotropic conductive film containing conductive particles by thermocompression bonding, the uppermost layer of the electrode terminal is higher in hardness than at least one lower layer, In the uppermost layer having high hardness, the conductive particles sandwiched between the bumps and the electrode terminals are not buried too much, and the conductive particles are easily crushed, and at least one lower layer having low hardness makes the surface of the bump or semiconductor element. It is possible to absorb unevenness of the recesses and height, and uneven thickness of the semiconductor element.Further, since the hardness of the uppermost layer is higher than the hardness of the conductive particles, the conductive particles are surely crushed without being buried in the uppermost layer.
[0014]
  According to claim 2 of the present inventionThe liquid crystal display device is a liquid crystal display device in which liquid crystal is sandwiched between a pair of substrates, an anisotropic conductive film in which electrode terminals are formed on one side of the pair of substrates, and a semiconductor element having bumps includes conductive particles The one side substrate is made of a transparent substrate through which the electrode terminal can be seen through from the back surface side, and the electrode terminal is composed of the lowest layer, one or more inner layers, the highest layer in order from the substrate side. The uppermost layer and the lowermost layer are higher in hardness than at least one inner layer, and the hardness of the uppermost layer is higher than the hardness of the conductive particles. To do.The one or more inner layers may be one layer or two or more layers.
[0015]
According to the present invention, when a semiconductor element having bumps is mounted by thermocompression bonding through an anisotropic conductive film containing conductive particles, the uppermost layer of the electrode terminal is higher in hardness than at least one inner layer. When the element is placed and pressed, the conductive particles sandwiched between the bumps and the electrode terminals are not buried too much in the uppermost layer having high hardness, and the conductive particles are easily crushed and at least one lower layer having low hardness. The layer can absorb bumps, recesses in the surface of the semiconductor element, variations in height, and unevenness in the thickness of the semiconductor element. In addition, since the semiconductor element mounting substrate is made of a transparent substrate and the bottom layer of the electrode terminal is high in hardness, the indentation of the conductive particles can be easily recognized from the back side of the semiconductor element mounting substrate. It becomes easy to conduct a continuity test by indentation of particles.
[0016]
  According to claim 3 of the present inventionLiquid crystal displayAssuming that the thickness of the electrode terminal is T, the thickness of the one or more inner layers is t, and the number of electrode terminal layers is a, on the premise of the invention of claim 2, t ≦ 3T / a is satisfied. It is characterized by.
[0017]
According to this invention, since the thickness of one or more inner layers does not become too thick, even if a semiconductor element is placed and pressed, the pressing force is not absorbed too much by the inner layer. That is, the inventors of the present application recognize that if the inner layer is thick, the probability of crushing the conductive particles decreases, but by satisfying the above relational expression, an appropriate pressing force (thermocompression bonding) is applied to the conductive particles. Force), in particular, by applying a pressing force from above, the conductive particles are easily crushed by the uppermost layer having high hardness. Further, since the pressing force is easily transmitted to the lowest layer, the indentation of the conductive particles is more likely to appear in the lowest layer.
[0022]
  In the liquid crystal display device according to claim 5 of the present invention, on the premise of the invention according to claims 1 to 4, the bump is a plurality of layers in which one or more lower layers and uppermost layers are laminated in order from the semiconductor element side. The uppermost layer is harder than at least one lower layer of the lower layers, and the uppermost layer of the bumps is higher in hardness than the conductive particles.
[0023]
  According to this invention,BumpSince the uppermost layer has a higher hardness than at least one lower layer, when the semiconductor element is placed and pressed, the uppermost layer having a higher hardness embeds the conductive particles sandwiched between the protruding electrode and the electrode terminal too much. In other words, at least one lower layer having a low hardness can absorb variations in the heights of bumps and semiconductor elements and uneven thickness of the semiconductor elements. Therefore, the conductive particles are easily crushed, and the reliability of conduction between the electrode terminal and the bump can be improved. Since the connection portion with the conductive particles is a layer having a high hardness, poor conduction due to the change of the connection portion over time hardly occurs.
[0028]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0029]
(First Embodiment) A first embodiment of the present invention is a semiconductor element mounting substrate 4 on which a semiconductor element IC having bumps B is mounted. FIG. 1A is a diagram showing a semiconductor element mounting substrate 4 according to the first embodiment of the present invention. On the surface of the semiconductor element mounting substrate 4, electrode terminals 1 are formed which are electrically connected by sandwiching the conductive particles r between the bumps B of the semiconductor element IC. An insulating film 2 is formed on the electrode terminal 1 so as to expose the center and cover both ends, and an ITO layer 3 is formed on the electrode terminal 1 and the insulating film 2. The semiconductor element mounting substrate 4 is a glass transparent substrate, but may be another substrate such as a flexible substrate.
[0030]
The electrode terminal 1 is configured such that two layers in which the lower layer 1a and the uppermost layer 1c are stacked in order from the semiconductor element mounting substrate 4 side protrude, and the uppermost layer 1c has higher hardness than the lower layer 1a. It has become. Specifically, the uppermost layer 1c is titanium (Ti), and the lower layer 1a is aluminum (Al), and is formed by a method such as photolithography and plating. The material of the electrode terminal 1 is not limited to such a material, and any material may be used as long as the uppermost layer 1c has a higher hardness than the lower layer 1a. The electrode terminal 1 according to the present embodiment has a two-layer structure in which the lower layer 1a is one layer and the uppermost layer 1c is one layer. However, the electrode terminal 1 may have a structure in which the lower layer is two layers or more and the uppermost layer is one layer or more. good. When there are two or more lower layers, it is sufficient that the uppermost layer has a higher hardness than at least one of the lower layers. In addition, the material of the uppermost layer and the lower layer is not limited to titanium and aluminum, but may be other materials such as nickel (Ni) and aluminum (Al), high purity gold (Au), and low purity gold (Au). good.
[0031]
Next, a method for mounting the semiconductor element IC on the semiconductor element mounting substrate 4 of the present embodiment will be described. FIG. 1B is a diagram showing a state in which a semiconductor element IC is mounted on the semiconductor element mounting substrate 4 of the present embodiment via an anisotropic conductive film 8. A large number of bumps B that are protruding electrodes are formed on the back surface of the semiconductor element IC along the outer periphery. When mounting the semiconductor element IC, the anisotropic conductive film 8 including the conductive particles r is disposed (temporarily bonded) on the electrode terminals 1 of the semiconductor element mounting substrate 4, and the bump B of the semiconductor element IC is mounted. The semiconductor element IC is aligned so as to correspond to the electrode terminal 1 of the substrate 4 for mounting the semiconductor element, and then pressed (thermocompression bonding) while being heated by the crimping tools S1 and S2, so that the semiconductor element IC is a semiconductor. Mounted on the element mounting board 4. Conductive particles r are sandwiched between the electrode terminals 1 and the bumps B, and conduction is achieved through the conductive particles r. The anisotropic conductive film 8 is a paste or film having conductive particles r dispersed in an insulating adhesive, conductive in the thickness direction (connection direction), and insulative in the surface direction (lateral direction). This is an adhesive 8 in the form of a tape. The conductive particles r may be nickel particles, resin particles plated with gold, or other particles. The adhesive is not limited to a thermosetting resin such as an epoxy resin, and a thermoplastic resin may be used.
[0032]
When sandwiched between the crimping tools S1 and S2, the uppermost layer 1c of the electrode terminal 1 has a higher hardness than the lower layer 1a, so that the conductive particles r sandwiched between the protruding electrode (bump) B and the electrode terminal 1 are used. However, it is easy to be crushed without being buried too much in the uppermost layer 1c. That is, as the amount of the conductive particles r buried is reduced, the force (crimping force) applied to the conductive particles r is increased, so that the conductive particles r that have not been fully crushed without being sufficiently pressurized (not reached) until now. The probability of crushing is increased. For this reason, no continuity failure has occurred during the initial continuity test, but continuity failures due to changes in the shape of the electrode terminal 1 over time are less likely to occur. In addition, the surface of the bump B has a recess, the height of the bump B1 and the bump B2 varies, or the thickness of the semiconductor element IC is not uniform (in addition, the bump B and the conductive particle r). (Alternatively, even if foreign particles are mixed between the conductive particles r and the electrode terminals 1), when pressed from above by the crimping tool S2, the lower layer 1a has lower hardness than the uppermost layer 1c. It is possible to absorb the recesses and height variations on the surface of the bump B and the uneven thickness of the semiconductor element IC. Therefore, the reliability of conduction between the electrode terminal 1 and the bump B can be improved.
[0033]
(Second Embodiment) In the second embodiment of the present invention, the electrode terminals 1 formed on the surface of the semiconductor element mounting substrate 4 are arranged in order from the semiconductor element mounting substrate 4 side to the lowest layer 1a, The inner layer 1b and the uppermost layer 1c are configured to protrude in three layers, and the uppermost layer 1c and the lowermost layer 1a are higher in hardness than the inner layer 1b. Specifically, the uppermost layer 1c and the lowermost layer 1a are titanium (Ti), and the inner layer 1b is aluminum (Al). The semiconductor element mounting substrate 4 is a glass transparent substrate, but may be formed of other materials such as a plastic resin as long as it is a transparent substrate.
[0034]
The electrode terminal 1 of the present embodiment satisfies t ≦ 3T / a, where T is the thickness of the electrode terminal 1, t is the thickness of the inner layer 1b, and a is the number of layers of the electrode terminal 1. Since the number of layers of the electrode terminal 1 of the present embodiment is three, a = 3.
[0035]
Here, the electrode terminal 1 of the present embodiment has a three-layer structure in which the lowermost layer 1a, the inner layer 1b, and the uppermost layer 1c are each one layer, but the lowermost layer 1a and the uppermost layer 1c are of the inner layer 1b. If the hardness is higher than that of at least one layer, the inner layer 1c may have two or more layers, and the lowermost layer 1a and the uppermost layer 1c may each have a structure of four or more layers. Further, as shown in FIG. 1, a transparent electrode layer (ITO) may be formed on the electrode terminal 1 or the insulating film 2.
[0036]
FIG. 2B is a diagram showing a state in which the semiconductor element IC is mounted on the semiconductor element mounting substrate 4 of the present embodiment. Since the uppermost layer 1c and the lowermost layer 1a of the electrode terminal 1 are harder than the inner layer 1b, the conductive particles r sandwiched between the protruding electrode B and the electrode terminal 1 are not buried too much in the uppermost layer 1c. It becomes easy to be crushed. That is, as the amount of the conductive particles r buried is reduced, the force applied to the conductive particles r is increased, thereby increasing the probability that the conductive particles r that have not been crushed so far will be crushed. In addition, bump B has irregularities (the bump surface and the surface of the electrode terminal have irregularities and deforms by about 1 to 2 μm in height by thermocompression bonding. The concave is also called a crater), or bump B1 and bump Even if the height of B2 varies or the thickness of the semiconductor element IC is not uniform, the inner layer 1b has a lower hardness than the lowermost layer 1a and the uppermost layer 1c. Will be absorbed. Therefore, the reliability of conduction between the electrode terminal 1 and the bump B can be improved. Since the lowermost layer 1c has a high hardness, an indentation of the conductive particles r tends to appear. In addition, since the indentation of the conductive particles r can be easily recognized from the back side of the transparent semiconductor element mounting substrate 4, it is easy to conduct a continuity inspection using the indentations of the conductive particles r, and the inspection accuracy can be improved.
[0037]
Furthermore, when the thickness t of the inner layer 1b satisfies t ≦ 3T / a, the inner layer 1b does not become too thick. Therefore, even if the semiconductor element IC is placed and pressed from above, the pressing force is absorbed by the inner layer. Never too much. Accordingly, since an appropriate pressing force is applied to the conductive particles r, the conductive particles r are further easily crushed, and the pressing force is easily transmitted to the lowermost layer 1a, so that an indentation of the conductive particles r appears in the lowermost layer 1a. It becomes easy to do.
[0038]
(Application Example of Second Embodiment) As an application example of the second embodiment, a semiconductor element mounting substrate 4 on which a four-layer electrode terminal 1 is formed will be described. FIG. 3 is a diagram showing a semiconductor element mounting substrate 4 of an application example of the present embodiment. In the semiconductor element mounting substrate 4 of the application example of the present embodiment, the electrode terminals 1 are arranged in order from the semiconductor element mounting substrate 4 side, the lowest layer 1a, the lower inner layer 1b1, the upper inner layer 1b2, and the uppermost layer. The lowermost layer 1a and the uppermost layer 1c have higher hardness than the two inner layers 1b1 and 1b2. Specifically, the lowermost layer 1c and the uppermost layer 1a are titanium (Ti), the lower inner layer 1b1 is nickel (Ni), and the upper inner layer 1b2 is aluminum (Al). In the application example of the present embodiment, the lowermost layer 1a and the uppermost layer 1c have higher hardness than any of the inner layers 1b1 and 1b2, but the hardness is higher than at least one of the inner layers 1b1 and 1b2. It ’s fine.
[0039]
(Third Embodiment) A semiconductor element IC according to a third embodiment of the present invention is a semiconductor element IC mounted on a semiconductor element mounting substrate 4 on which an electrode terminal 1 is formed. Bumps B are formed as protruding electrodes that are electrically connected with the conductive particles r interposed therebetween. FIG. 4A is a diagram showing a semiconductor element IC according to the third embodiment of the present invention. A large number of bumps B that are protruding electrodes are formed on the back surface of the semiconductor element IC along the outer periphery.
[0040]
The bump B is composed of two layers in which the lower layer Ba and the uppermost layer Bc are laminated in order from the semiconductor element IC side, and the uppermost layer Bc has higher hardness than the lower layer Ba. Specifically, the uppermost layer Bc is titanium (Ti), the lower layer Ba is aluminum Al, and the bumps B are formed by a method such as photolithography and plating. The material of the bump B is not limited to such a material, and any material may be used as long as the uppermost layer Bc has a higher hardness than the lower layer Ba. The bump B of the present embodiment has a two-layer structure in which the lower layer Ba is one layer and the uppermost layer Bc is one layer. However, the lower layer Ba has two or more layers and the uppermost layer Bc has one layer or more. But it ’s okay. When the lower layer Ba is two or more layers, it is sufficient that the uppermost layer Bc has a higher hardness than at least one of the lower layers Ba. The materials of the uppermost layer Bc and the lower layer Ba are not limited to titanium and aluminum, but may be other materials such as high-purity gold (Au) and low-purity gold (Au), nickel (Ni) and aluminum, or the like. .
[0041]
Next, a method for mounting the semiconductor element IC on which the bumps B of the present embodiment are formed on the semiconductor element mounting substrate 4 will be described. FIG. 4B is a diagram showing a state in which the semiconductor element IC of the present embodiment is mounted on the semiconductor element mounting substrate 4. Since the uppermost layer Bc of the bump B has a higher hardness than the lower layer Ba, the conductive particles r sandwiched between the protruding electrode B and the electrode terminal 1 are easily crushed without being buried in the uppermost layer Bc. Further, even if the surface of the bump B has a recess, the height of the bumps B1 and B2 varies, or the thickness of the semiconductor element IC is not uniform, the lower layer Ba is harder than the uppermost layer Bc. Since it is low and easily crushed, it is possible to absorb the recesses and height variations on the surface of the bump B, the uneven thickness of the semiconductor element IC, and the like.
[0042]
(Fourth Embodiment) The semiconductor element mounting substrate or semiconductor element of the present embodiment is the same as the semiconductor element mounting substrate 4 of the first embodiment or the second embodiment, or the third embodiment. In the semiconductor element IC of the embodiment, the conductive particles r are conductive particles r obtained by applying gold plating to a resin. Since the uppermost layer 1c of the electrode terminal 1 formed on the semiconductor element mounting substrate 4 is titanium and has a higher hardness than the conductive particles r, the conductive particles r are easily crushed without being buried in the uppermost layer 1c. (See FIG. 1B and FIG. 2B). Further, since the uppermost layer Bc of the bump B formed in the semiconductor element IC of the third embodiment is titanium and is higher than the hardness of the conductive particle r, the conductive particle r is the uppermost layer Bc of the bump B. It becomes easy to be crushed without being buried too much (see FIG. 4B).
[0043]
(Application Example to Liquid Crystal Display Device) Hereinafter, as a specific example, a case where the semiconductor element mounting substrate 4 of the present invention or the semiconductor element IC of the present invention is applied to a COG mounted liquid crystal display device will be described. FIG. 5 is a diagram showing a liquid crystal display device mounted with COG. The liquid crystal panel LCD is a reflective liquid crystal display device LCD using a TFT which is a typical active element currently used.
[0044]
One substrate (one substrate: also referred to as AM substrate or array substrate) 4 of the liquid crystal panel LCD is larger than the other substrate 5, so when both substrates 4, 5 are overlapped, one substrate is placed around the AM substrate 4. An overhanging semiconductor element IC mounting region 6 is formed. A wiring pattern 7 for semiconductor mounting is formed in the mounting area 6 of the AM substrate 4. The AM substrate 4 may be a glass substrate or a synthetic resin flexible substrate.
[0045]
The semiconductor element IC of the present embodiment is mounted on the mounting region 6 of the AM substrate 4 via an anisotropic conductive film 8 containing conductive particles r. A large number of bumps B are formed on the back side of the semiconductor element IC so as to face each other along the outer periphery.
[0046]
An electrode terminal 1 connected to the semiconductor element IC is formed in a pattern at the end of the wiring pattern 7. The electrode terminal 1 on one side (left side in FIG. 5) is an input electrode, and the electrode terminal 1 on the other side (right side in FIG. 5) is an output electrode. The semiconductor element IC for driving the liquid crystal panel LCD is mounted via an anisotropic conductive film (ACF) 8 containing conductive particles r in an adhesive.
[0047]
When the semiconductor element mounting substrate 4 of the present invention is applied to such a liquid crystal panel LCD, it is used as the AM substrate 4. That is, the conventional electrode terminal 1 in the mounting region 5 is used as the electrode terminal 1 in the above embodiment. When the semiconductor element IC of the present invention is applied, it is used as a semiconductor element IC disposed in the mounting region 5. That is, the bump B of the semiconductor element IC disposed in the mounting region 5 is used as the bump B of the above embodiment. The semiconductor element mounting substrate 4 on which the electrode terminals 1 of the present invention are formed and the semiconductor element IC on which the bumps B of the present invention are formed may be applied simultaneously to the liquid crystal display panel LCD, or only one of them may be applied. May be.
[0048]
In the application example of the present invention, a COG-mounted liquid crystal display device has been described as an example. However, the present invention can also be applied to a COF-mounted liquid crystal display device in which a semiconductor element is mounted on a flexible substrate via an adhesive, and other electronic devices. .
[0049]
【The invention's effect】
As described above, according to the present invention, the uppermost layer and the lowermost layer are higher in hardness than at least one inner layer. Therefore, when the semiconductor element is placed and pressed, the uppermost layer having high hardness has a protruding electrode. The conductive particles sandwiched between the electrode terminal and the electrode terminal are easily crushed without being buried too much, and at least one inner layer having a low hardness can absorb bumps, recesses on the surface of the semiconductor element, and variations in height. Since the connection portion with the conductive particles is a layer having a high hardness, it is difficult to cause a conduction failure due to a change in the connection portion over time. Therefore, according to the semiconductor element mounting substrate of the present invention or the semiconductor element of the present invention, the bump and the electrode terminal The reliability of conduction with can be increased. Moreover, since the lowest layer has high hardness, it can make it easy to make the impression of an electroconductive particle appear. Therefore, since the indentation of the conductive particles can be easily recognized from the back side of the semiconductor element mounting substrate, it is easy to perform a continuity inspection using the indentation of the conductive particles, and the inspection accuracy can be improved.
[0050]
[Brief description of the drawings]
FIG. 1A is a diagram showing a semiconductor element mounting substrate according to a first embodiment, and FIG. 1B is a diagram showing a state in which a semiconductor element is mounted on the semiconductor element mounting substrate.
2A is a diagram showing a semiconductor element mounting substrate according to a second embodiment, and FIG. 2B is a diagram showing a state in which the semiconductor element is mounted on the semiconductor element mounting substrate;
3A is a diagram showing a semiconductor element mounting substrate according to an application example of the second embodiment, and FIG. 3B is a diagram showing a state in which the semiconductor element is mounted on the semiconductor element mounting substrate;
4A is a diagram showing a semiconductor element according to a third embodiment, and FIG. 4B is a diagram showing a state in which the semiconductor element is mounted on a semiconductor element mounting substrate;
FIG. 5 is a diagram showing a liquid crystal display panel to which the semiconductor element mounting substrate of the present invention and the semiconductor element are applied.
FIG. 6 is a diagram showing a state in which a semiconductor element is mounted on a semiconductor element mounting substrate by face-down.
FIG. 7 is a diagram showing a state in which conductive particles are buried in electrode terminals and are not crushed.
8A is a state in which the surface of the bump is concave, FIG. 8B is a state in which the height of a plurality of bumps varies, and FIG. 8C is a state in which the thickness of the semiconductor element is not uniform. Illustration
[Explanation of symbols]
IC, IC1 Semiconductor element
1,11 electrode terminal
1a Lower layer and lowest layer of electrode terminals
1b Inner layer of electrode terminal
1c Top layer of electrode terminals
2 Insulating film
3 ITO
4, 14 Semiconductor device mounting substrate, one substrate (AM substrate)
5 The other board
6 Mounting area
7 Wiring pattern
8 Anisotropic conductive film
r Conductive particles
B, 1B Bump
Ba Bump lower layer
Bc Bump top layer
t Thickness of inner layer of electrode terminal
T electrode terminal thickness
LCD liquid crystal display panel

Claims (5)

一対の基板の間に液晶を挟持する液晶表示装置において、In a liquid crystal display device that sandwiches liquid crystal between a pair of substrates,
前記一対の基板の一方側基板に電極端子が形成され、バンプを有する半導体素子が導電粒子を含む異方性導電膜を介してＣＯＧ実装されており、  Electrode terminals are formed on one side of the pair of substrates, and a semiconductor element having bumps is COG-mounted via an anisotropic conductive film containing conductive particles,
上記電極端子は、基板側から順に一層以上の下位層と最上位層が積層された複数層で構成されており、最上位層は少なくとも一の下位層よりも硬度が高く、且つ前記最上位層の硬度は導電粒子の硬度よりも高いことを特徴とする液晶表示装置。The electrode terminal is composed of a plurality of layers in which one or more lower layers and an uppermost layer are laminated in order from the substrate side, the uppermost layer being harder than at least one lower layer, and the uppermost layer The liquid crystal display device is characterized in that the hardness of is higher than the hardness of the conductive particles. 一対の基板の間に液晶を挟持する液晶表示装置において、In a liquid crystal display device that sandwiches liquid crystal between a pair of substrates,
前記一対の基板の一方側基板に電極端子が形成され、バンプを有する半導体素子が導電粒子を含む異方性導電膜を介してＣＯＧ実装されるとともに、前記一方側基板が前記電極端子を裏面側から透視可能な透明な基板からなり、  Electrode terminals are formed on one side of the pair of substrates, and a semiconductor element having bumps is COG-mounted via an anisotropic conductive film containing conductive particles, and the one side of the pair of substrates is connected to the back side of the electrode terminals. It consists of a transparent substrate that can be seen through,
上記電極端子は、基板側から順に最下位層、一層以上の内層、最上位層が積層された複数層で構成されており、最上位層及び最下位層は少なくとも一の内層よりも硬度が高く、且つ前記最上位層の硬度は導電粒子の硬度よりも高いことを特徴とする液晶表示装置。The electrode terminal is composed of a plurality of layers in which the lowermost layer, one or more inner layers, and the uppermost layer are laminated in order from the substrate side, and the uppermost layer and the lowermost layer have higher hardness than at least one inner layer. And the hardness of the uppermost layer is higher than the hardness of the conductive particles. 前記電極端子の厚みをＴとし、前記一以上の内層の厚みをｔとし、電極端子の層数をａとすると、ｔ≦３Ｔ／ａを満たすことを特徴とする請求項２記載の液晶表示装置。 3. The liquid crystal display device according to claim 2, wherein t ≦ 3T / a is satisfied, where T is the thickness of the electrode terminal, t is the thickness of the one or more inner layers, and a is the number of electrode terminal layers. . 前記導電粒子が樹脂に金メッキを施した導電粒子であることを特徴とする請求項１から３のいずれか１項記載の液晶表示装置。4. The liquid crystal display device according to claim 1, wherein the conductive particles are conductive particles obtained by applying gold plating to a resin. 上記バンプは、半導体素子側から順に一層以上の下位層と最上位層が積層された複数層で構成されており、最上位層は下位層のうち少なくとも一の下位層よりも硬度が高く、且つ前記バンプの最上位層の硬度は、前記導電粒子の硬度よりも高いことを特徴とする請求項１から４のいずれか１項記載の液晶表示装置。The bump is composed of a plurality of layers in which one or more lower layers and an uppermost layer are laminated in order from the semiconductor element side, and the uppermost layer has higher hardness than at least one lower layer of the lower layers, and The liquid crystal display device according to claim 1, wherein the hardness of the uppermost layer of the bump is higher than the hardness of the conductive particles.
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