JP2003114260A5 - - Google Patents

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Publication number
JP2003114260A5
JP2003114260A5 JP2002214658A JP2002214658A JP2003114260A5 JP 2003114260 A5 JP2003114260 A5 JP 2003114260A5 JP 2002214658 A JP2002214658 A JP 2002214658A JP 2002214658 A JP2002214658 A JP 2002214658A JP 2003114260 A5 JP2003114260 A5 JP 2003114260A5
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JP
Japan
Prior art keywords
integrated circuit
test
signal
processing core
routine
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Withdrawn
Application number
JP2002214658A
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English (en)
Japanese (ja)
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JP2003114260A (ja
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Publication date
Priority claimed from US09/917,972 external-priority patent/US7418642B2/en
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Publication of JP2003114260A publication Critical patent/JP2003114260A/ja
Publication of JP2003114260A5 publication Critical patent/JP2003114260A5/ja
Withdrawn legal-status Critical Current

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JP2002214658A 2001-07-30 2002-07-24 Ａｓｉｃの埋め込みメモリ及びプロセッサを用いた内蔵自己テスト法 Withdrawn JP2003114260A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/917,972 US7418642B2 (en) 2001-07-30 2001-07-30 Built-in-self-test using embedded memory and processor in an application specific integrated circuit
US917972 2001-07-30

Publications (2)

Publication Number Publication Date
JP2003114260A JP2003114260A (ja) 2003-04-18
JP2003114260A5 true JP2003114260A5 (https=) 2005-10-27

Family

ID=25439587

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002214658A Withdrawn JP2003114260A (ja) 2001-07-30 2002-07-24 Ａｓｉｃの埋め込みメモリ及びプロセッサを用いた内蔵自己テスト法

Country Status (7)

Country Link
US (6) US7418642B2 (https=)
EP (1) EP1282041B1 (https=)
JP (1) JP2003114260A (https=)
KR (1) KR100932562B1 (https=)
DE (1) DE60212271T2 (https=)
SG (1) SG94870A1 (https=)
TW (1) TWI276107B (https=)

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US20150026528A1 (en) * 2013-07-16 2015-01-22 Manuel A. d'Abreu Controller based memory evaluation
US10126362B2 (en) 2014-12-15 2018-11-13 International Business Machines Corporation Controlling a test run on a device under test without controlling the test equipment testing the device under test
US9417952B2 (en) 2014-12-18 2016-08-16 Freescale Semiconductor, Inc. Direct memory access (DMA) unit with error detection
US9690681B1 (en) * 2015-09-03 2017-06-27 Cadence Design Systems, Inc. Method and system for automatically generating executable system-level tests
CN106646191A (zh) * 2016-11-25 2017-05-10 天津津航计算技术研究所 针对SiP内嵌存储器的功能测试方法
US10490291B1 (en) 2018-04-24 2019-11-26 The United States Of America, As Represented By The Secretary Of The Navy Memory check ASIC for fuzes and safety and arming devices
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