JP2003068939A - Semiconductor device and its manufacturing method - Google Patents
Semiconductor device and its manufacturing methodInfo
- Publication number
- JP2003068939A JP2003068939A JP2001259789A JP2001259789A JP2003068939A JP 2003068939 A JP2003068939 A JP 2003068939A JP 2001259789 A JP2001259789 A JP 2001259789A JP 2001259789 A JP2001259789 A JP 2001259789A JP 2003068939 A JP2003068939 A JP 2003068939A
- Authority
- JP
- Japan
- Prior art keywords
- circuit board
- bare chip
- semiconductor device
- opening
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
- H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Wire Bonding (AREA)
- Light Receiving Elements (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、回路基板上に半導
体ベアチップがフリップチップ実装された半導体装置及
びその製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which a semiconductor bare chip is flip-chip mounted on a circuit board, and a manufacturing method thereof.
【０００２】[0002]
【従来の技術】図３は、従来の半導体装置の構成を示す
断面図であり、図４は、前記半導体装置を構成している
プリント回路基板の概略を示す斜視図である。2. Description of the Related Art FIG. 3 is a sectional view showing a structure of a conventional semiconductor device, and FIG. 4 is a perspective view showing an outline of a printed circuit board forming the semiconductor device.
【０００３】図示されている従来の半導体装置は、プリ
ント回路基板１０１に形成された基板上電極３に、半導
体ベアチップ２がバンプ４を介してフリップチップ実装
され、プリント回路基板１０１と半導体ベアチップ２と
の間に封止樹脂５が充填された構成である。半導体ベア
チップ２には、プリント回路基板１０１と対向する面に
受光素子２ａが設けられている。プリント回路基板１０
１には開口部１ａが設けられており、この開口部１ａは
受光素子２ａの位置に対応して設けられている。すなわ
ち、受光素子２ａは、プリント回路基板１０１側から開
口部１ａを介して照射される紫外線等を受光する。In the conventional semiconductor device shown in the figure, a semiconductor bare chip 2 is flip-chip mounted on a substrate electrode 3 formed on a printed circuit board 101 via bumps 4, and the printed circuit board 101 and the semiconductor bare chip 2 are connected to each other. The sealing resin 5 is filled in between. The semiconductor bare chip 2 is provided with a light receiving element 2a on the surface facing the printed circuit board 101. Printed circuit board 10
1, an opening 1a is provided, and the opening 1a is provided corresponding to the position of the light receiving element 2a. That is, the light receiving element 2a receives the ultraviolet light or the like emitted from the printed circuit board 101 side through the opening 1a.
【０００４】図５及び図６には、前記従来の半導体装置
の製造工程におけるフリップチップ実装工程例がそれぞ
れ示されている。図５に示す例は、プリント回路基板１
０１上に半導体ベアチップ２を実装した後に、注入機６
を用いて、プリント回路基板１０１と半導体ベアチップ
２との間に封止樹脂５となる樹脂を注入する方法であ
る。また、図６に示す例は、プリント回路基板１０１の
基板上電極３に予め熱硬化性接着剤７が塗布されてお
り、半導体ベアチップ２に形成されたバンプ４を介し、
半導体ベアチップ２を加圧加熱ヘッド８によりプリント
回路基板１０１に押しつけることで、熱硬化性接着剤７
を硬化させてプリント回路基板１０１上に半導体ベアチ
ップ２を実装する方法である。熱硬化性接着剤７は実装
後に封止樹脂５と同様に機能する。FIG. 5 and FIG. 6 show examples of flip-chip mounting processes in the manufacturing process of the conventional semiconductor device, respectively. The example shown in FIG. 5 is a printed circuit board 1.
After mounting the semiconductor bare chip 2 on 01, the injection machine 6
Is used to inject a resin to be the sealing resin 5 between the printed circuit board 101 and the semiconductor bare chip 2. In the example shown in FIG. 6, the thermosetting adhesive 7 is applied in advance to the on-board electrodes 3 of the printed circuit board 101, and the bumps 4 formed on the semiconductor bare chip 2 are interposed between
By pressing the semiconductor bare chip 2 against the printed circuit board 101 by the pressure heating head 8, the thermosetting adhesive 7
Is cured to mount the semiconductor bare chip 2 on the printed circuit board 101. The thermosetting adhesive 7 functions similarly to the sealing resin 5 after mounting.
【０００５】[0005]
【発明が解決しようとする課題】しかしながら、上記従
来の構成の半導体装置では、フリップチップ実装工程に
おいて、次のような問題が生じていた。However, in the semiconductor device having the above-mentioned conventional structure, the following problems occur in the flip chip mounting process.
【０００６】図５に示すフリップチップ実装工程では、
封止樹脂の流れ込みにより半導体ベアチップ２上の受光
素子２ａを汚染してしまうという問題があった。さら
に、封止樹脂５がプリント回路基板１０１の開口部１ａ
から流出して、プリント回路基板１０１と半導体ベアチ
ップ２との間の封止樹脂５の量が減少し、ヒートサイク
ル等の信頼性評価時に寿命を縮めるという問題もあっ
た。In the flip chip mounting process shown in FIG.
There is a problem that the light receiving element 2a on the semiconductor bare chip 2 is contaminated by the flow of the sealing resin. Further, the sealing resin 5 is applied to the opening 1a of the printed circuit board 101.
There is also a problem that the amount of the sealing resin 5 flowing out from the printed circuit board 101 and the semiconductor bare chip 2 is reduced, and the life is shortened during reliability evaluation such as heat cycle.
【０００７】また、図６に示すフリップチップ実装工程
では、加圧加熱ヘッド８での加熱時に、熱硬化性接着剤
７の粘度低下による流動性の増加によって熱硬化性接着
剤７が受光素子２ａ部分に流れ込み、受光素手２ａを汚
染してしまうという問題があった。さらに、熱硬化性接
着剤７がプリント回路基板１０１の開口部１ａから流出
し、プリント回路基板１０１と半導体ベアチップ２との
間の熱硬化性接着剤７の量が減少することにより、ヒー
トサイクル等の信頼性評価時に寿命を締めるという問題
点があった。Further, in the flip-chip mounting process shown in FIG. 6, when the pressure heating head 8 is used for heating, the thermosetting adhesive 7 increases in fluidity due to a decrease in the viscosity of the thermosetting adhesive 7, so that the thermosetting adhesive 7 becomes light receiving element 2a. There is a problem that it flows into the part and contaminates the light-receiving bare hand 2a. Further, the thermosetting adhesive 7 flows out from the opening 1a of the printed circuit board 101, and the amount of the thermosetting adhesive 7 between the printed circuit board 101 and the semiconductor bare chip 2 is reduced, so that heat cycle or the like is performed. There was a problem that the life was shortened at the time of reliability evaluation.
【０００８】本発明はこれらの問題を解決するために、
半導体ベアチップ上の受光素子が汚染されず、信頼性の
高い半導体装置を提供することを目的とする。In order to solve these problems, the present invention provides
An object of the present invention is to provide a highly reliable semiconductor device in which a light receiving element on a semiconductor bare chip is not contaminated.
【０００９】[0009]
【課題を解決するための手段】上記の目的を達成するた
めに、本発明の半導体装置は、受光素子を備えた半導体
ベアチップが回路基板上にフリップチップ実装されてお
り、前記回路基板には前記受光素子に対応する位置に開
口部が設けられ、前記半導体ベアチップと前記回路基板
との間が封止樹脂にて封止されている半導体装置におい
て、前記回路基板には前記開口部の周縁部に枠状の突起
部が設けられており、前記半導体ベアチップが、前記突
起部の頂部に当接して実装されていることを特徴として
いる。In order to achieve the above object, in a semiconductor device of the present invention, a semiconductor bare chip having a light receiving element is flip-chip mounted on a circuit board, and the circuit board has the above-mentioned structure. In a semiconductor device in which an opening is provided at a position corresponding to a light receiving element, and a gap between the semiconductor bare chip and the circuit board is sealed with a sealing resin, the circuit board has a peripheral edge portion of the opening. A frame-shaped protrusion is provided, and the semiconductor bare chip is mounted in contact with the top of the protrusion.
【００１０】この構成によれば、開口部の周縁部に設け
られた突起部が、実装工程時において、受光素子部分へ
の封止樹脂の流れ込みを防ぐので、封止樹脂により半導
体ベアチップ上の受光素子が汚染されることがない。さ
らに、前記突起部は、回路基板の開口部からの封止樹脂
の流出を防ぐので、封止樹脂の減少に起因する信頼性の
低下も生じない。According to this structure, the protrusion provided on the peripheral edge of the opening prevents the sealing resin from flowing into the light receiving element during the mounting process. The element is not contaminated. Furthermore, since the protrusion prevents the sealing resin from flowing out from the opening of the circuit board, the reliability is not deteriorated due to the reduction of the sealing resin.
【００１１】これにより、半導体ベアチップ上の受光素
子が汚染されず、且つ高い信頼性を備えた半導体装置を
提供することができる。This makes it possible to provide a highly reliable semiconductor device in which the light receiving element on the semiconductor bare chip is not contaminated.
【００１２】また、本発明の半導体装置は、受光素子を
備えた半導体ベアチップが、接着剤が塗布された回路基
板上にフリップチップ実装されており、前記回路基板に
は前記受光素子に対応する位置に開口部が設けられてい
る半導体装置において、前記回路基板には前記開口部の
周縁部に枠状の突起部が設けられており、前記半導体ベ
アチップが、前記突起部の頂部に当接して実装されてい
ることを特徴とすることもできる。In the semiconductor device of the present invention, a semiconductor bare chip having a light receiving element is flip-chip mounted on a circuit board coated with an adhesive, and the circuit board has a position corresponding to the light receiving element. In the semiconductor device in which the opening is provided in the circuit board, the circuit board is provided with a frame-shaped projection on the peripheral edge of the opening, and the semiconductor bare chip is mounted by abutting on the top of the projection. It can also be characterized by being.
【００１３】この構成によれば、開口部の周縁部に設け
られた突起部が、実装工程時において、受光素子部分へ
の接着剤の流れ込みを防ぐので、接着剤により半導体ベ
アチップ上の受光素子が汚染されることがない。さら
に、前記突起部は、回路基板の開口部からの接着剤の流
出を防ぐので、半導体ベアチップと回路基板との間の接
着剤の減少に起因する信頼性の低下も生じない。According to this structure, the protrusion provided on the peripheral edge of the opening prevents the adhesive from flowing into the light receiving element during the mounting process, so that the light receiving element on the semiconductor bare chip is protected by the adhesive. Will not be contaminated. Furthermore, since the protrusion prevents the adhesive from flowing out from the opening of the circuit board, the reliability is not reduced due to the decrease in the adhesive between the semiconductor bare chip and the circuit board.
【００１４】これにより、半導体ベアチップ上の受光素
子が汚染されず、且つ高い信頼性を備えた半導体装置を
提供することができる。This makes it possible to provide a highly reliable semiconductor device in which the light receiving element on the semiconductor bare chip is not contaminated.
【００１５】本発明の半導体装置の製造方法は、開口部
を有する回路基板上に、受光素子を備えた半導体ベアチ
ップを該受光素子が前記回路基板の開口部に対応するよ
うに配置してフリップチップ実装する第１の工程と、前
記回路基板と前記半導体ベアチップとの間を封止樹脂に
て封止する第２の工程とを含む半導体装置の製造方法に
おいて、前記回路基板には前記開口部の周縁部に予め枠
状の突起部が形成されており、前記第１の工程で、前記
半導体ベアチップは前記突起部の頂部に当接してフリッ
プチップ実装されることを特徴としている。According to the method of manufacturing a semiconductor device of the present invention, a semiconductor bare chip provided with a light receiving element is arranged on a circuit board having an opening so that the light receiving element corresponds to the opening of the circuit board. A method of manufacturing a semiconductor device, comprising: a first step of mounting; and a second step of sealing a space between the circuit board and the semiconductor bare chip with a sealing resin. A frame-shaped protrusion is formed in advance on the peripheral portion, and in the first step, the semiconductor bare chip is brought into contact with the top of the protrusion to be flip-chip mounted.
【００１６】また、本発明の半導体装置の製造方法は、
開口部を有する回路基板上に接着剤を塗布する第１の工
程と、前記回路基板上に、受光素子を備えた半導体ベア
チップを該受光素子が前記開口部に対応するように配置
してフリップチップ実装する第２の工程とを含む半導体
装置の製造方法において、前記回路基板には前記開口部
の周縁部に予め枠状の突起部が形成されており、前記第
２の工程で、前記半導体ベアチップは前記突起部の頂部
に当接してフリップチップ実装されることを特徴とする
ことも可能である。The semiconductor device manufacturing method of the present invention is
A first step of applying an adhesive on a circuit board having an opening, and a flip chip by disposing a semiconductor bare chip having a light receiving element on the circuit board so that the light receiving element corresponds to the opening. In the method for manufacturing a semiconductor device, including a second step of mounting, in the circuit board, a frame-shaped protrusion is formed in advance on a peripheral portion of the opening, and in the second step, the semiconductor bare chip is formed. Can be affixed to the top of the protrusion for flip-chip mounting.
【００１７】これらの方法によれば、上述した効果を実
現する本発明の半導体装置を製造することが可能とな
る。According to these methods, it is possible to manufacture the semiconductor device of the present invention which realizes the above-mentioned effects.
【００１８】[0018]
【発明の実施の形態】以下、本発明の一実施形態につい
て、図面を参照しながら説明する。BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described below with reference to the drawings.
【００１９】図２は本発明の一実施形態に係る半導体装
置の構成の概略を示す断面図であり、図１は、前記半導
体装置を構成しているプリント回路基板の形状の概略を
示す斜視図である。FIG. 2 is a sectional view showing the outline of the configuration of a semiconductor device according to an embodiment of the present invention, and FIG. 1 is a perspective view showing the outline of the shape of a printed circuit board that constitutes the semiconductor device. Is.
【００２０】図２に示すように、本実施形態の半導体装
置は、図３に示した従来の半導体装置において、プリン
ト回路基板１０１の代わりにプリント回路基板１を設け
た構成であり、その他の構成は従来の半導体装置と同じ
である。本実施形態のプリント回路基板１は、図１に示
すように、開口部１ａの周縁部に枠状の突起部１ｂが設
けられて構成されている。半導体ベアチップ２をプリン
ト回路基板１上にフリップチップ実装する際には、半導
体ベアチップ２を突起部１ｂの頂部に当接させる。As shown in FIG. 2, the semiconductor device of this embodiment has a configuration in which the printed circuit board 1 is provided in place of the printed circuit board 101 in the conventional semiconductor device shown in FIG. 3, and other configurations are provided. Is the same as the conventional semiconductor device. As shown in FIG. 1, the printed circuit board 1 of the present embodiment is configured such that a frame-shaped protrusion 1b is provided on the peripheral edge of the opening 1a. When the semiconductor bare chip 2 is flip-chip mounted on the printed circuit board 1, the semiconductor bare chip 2 is brought into contact with the top of the protrusion 1b.
【００２１】プリント回路基板１を以上のような形状と
することにより、図５に示したフリップチップ実装工程
において、受光素子２ａ部分への封止樹脂５の流れ込
み、及び開口部１ａからの封止樹脂５の流出を突起部１
ｂにより抑制することができる。従って、本実施形態の
半導体装置によれば、封止樹脂５の流れ込みによる受光
素子２ａの汚染の問題を解決することができる。さら
に、本実施形態の半導体装置によれば、封止樹脂５がプ
リント回路基板１上の開口部１ａから流出することを抑
制できるので封止樹脂５が減少せず、ヒートサイクル等
の信頼性評価において寿命を高めることができる。By forming the printed circuit board 1 into the shape as described above, in the flip-chip mounting process shown in FIG. 5, the sealing resin 5 flows into the light receiving element 2a and the sealing from the opening 1a. The outflow of the resin 5
It can be suppressed by b. Therefore, according to the semiconductor device of the present embodiment, it is possible to solve the problem of contamination of the light receiving element 2a due to the flow of the sealing resin 5. Further, according to the semiconductor device of the present embodiment, the sealing resin 5 can be prevented from flowing out from the opening 1a on the printed circuit board 1, so that the sealing resin 5 does not decrease and reliability evaluation such as heat cycle is performed. The life can be increased in.
【００２２】なお、本実施形態においては、図５に示し
たフリップチップ実装工程により形成される半導体装置
について説明したが、プリント回路基板１を用いること
により、図６に示したフリップチップ実装工程により形
成される半導体装置においても、開口部１ａからの熱硬
化性樹脂の流れ込み及び流出を抑制して、同様の効果を
得ることができる。In this embodiment, the semiconductor device formed by the flip chip mounting process shown in FIG. 5 has been described. However, by using the printed circuit board 1, the flip chip mounting process shown in FIG. Also in the formed semiconductor device, the same effect can be obtained by suppressing the inflow and outflow of the thermosetting resin from the opening 1a.
【００２３】[0023]
【発明の効果】以上に説明したように、本発明の半導体
装置よれば、半導体ベアチップ上に配置された受光素子
が汚染されず、且つ高い信頼性を備えた半導体装置を提
供できる。As described above, according to the semiconductor device of the present invention, it is possible to provide a semiconductor device having high reliability in which the light receiving element arranged on the semiconductor bare chip is not contaminated.
【図１】 本発明の一実施形態に係る半導体装置のプリ
ント回路基板の概略を示す斜視図である。FIG. 1 is a perspective view showing an outline of a printed circuit board of a semiconductor device according to an embodiment of the present invention.
【図２】 上記半導体装置の構成を示す断面図である。FIG. 2 is a sectional view showing a configuration of the semiconductor device.
【図３】 従来の半導体装置の構成を示す断面図であ
る。FIG. 3 is a sectional view showing a configuration of a conventional semiconductor device.
【図４】 上記半導体装置のプリント回路基板の概略を
示す斜視図である。FIG. 4 is a perspective view showing an outline of a printed circuit board of the semiconductor device.
【図５】 上記半導体装置の製造工程におけるフリップ
チップ実装工程の一例を示す断面図である。FIG. 5 is a cross-sectional view showing an example of a flip chip mounting process in the manufacturing process of the semiconductor device.
【図６】 上記半導体装置の製造工程におけるフリップ
チップ実装工程の一例を示す断面図である。FIG. 6 is a cross-sectional view showing an example of a flip chip mounting process in the manufacturing process of the semiconductor device.
１ プリント回路基板（回路基板） １ａ 開口部 １ｂ 突起部 ２ 半導体ベアチップ ５ 封止樹脂 ７ 熱硬化性接着剤（接着剤） 1 Printed circuit board (circuit board) 1a opening 1b protrusion 2 Semiconductor bare chip 5 Sealing resin 7 Thermosetting adhesive (adhesive)
───────────────────────────────────────────────────── フロントページの続き (72)発明者 吉野 道朗 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 Ｆターム(参考） 4M109 AA01 DA05 DA06 DB07 GA01 5F044 KK01 LL13 5F088 BA16 BA20 JA03 JA06 JA09 ─────────────────────────────────────────────────── ─── Continued front page (72) Inventor Michiro Yoshino 1006 Kadoma, Kadoma-shi, Osaka Matsushita Electric Sangyo Co., Ltd. F-term (reference) 4M109 AA01 DA05 DA06 DB07 GA01 5F044 KK01 LL13 5F088 BA16 BA20 JA03 JA06 JA09
Claims (4)
路基板上にフリップチップ実装されており、前記回路基
板には前記受光素子に対応する位置に開口部が設けら
れ、前記半導体ベアチップと前記回路基板との間が封止
樹脂にて封止されている半導体装置において、 前記回路基板には前記開口部の周縁部に枠状の突起部が
設けられており、 前記半導体ベアチップが、前記突起部の頂部に当接して
実装されていることを特徴とする半導体装置。1. A semiconductor bare chip provided with a light receiving element is flip-chip mounted on a circuit board, and an opening is provided in the circuit board at a position corresponding to the light receiving element, and the semiconductor bare chip and the circuit board are provided. In the semiconductor device in which the space between and is sealed with a sealing resin, the circuit board is provided with a frame-shaped protrusion at the peripheral edge of the opening, the semiconductor bare chip, A semiconductor device, which is mounted in contact with a top portion.
接着剤が塗布された回路基板上にフリップチップ実装さ
れており、前記回路基板には前記受光素子に対応する位
置に開口部が設けられている半導体装置において、 前記回路基板には前記開口部の周縁部に枠状の突起部が
設けられており、 前記半導体ベアチップが、前記突起部の頂部に当接して
実装されていることを特徴とする半導体装置。2. A semiconductor bare chip having a light receiving element,
In a semiconductor device, which is flip-chip mounted on a circuit board coated with an adhesive, and in which an opening is provided in the circuit board at a position corresponding to the light receiving element, the circuit board is provided with an opening of the opening. A semiconductor device, wherein a frame-shaped protrusion is provided on a peripheral portion, and the semiconductor bare chip is mounted in contact with a top of the protrusion.
を備えた半導体ベアチップを該受光素子が前記回路基板
の開口部に対応するように配置してフリップチップ実装
する第１の工程と、 前記回路基板と前記半導体ベアチップとの間を封止樹脂
にて封止する第２の工程とを含む半導体装置の製造方法
において、 前記回路基板には前記開口部の周縁部に予め枠状の突起
部が形成されており、 前記第１の工程で、前記半導体ベアチップは前記突起部
の頂部に当接してフリップチップ実装されることを特徴
とする半導体装置の製造方法。3. A first step of flip-chip mounting a semiconductor bare chip having a light-receiving element on a circuit board having an opening so that the light-receiving element corresponds to the opening of the circuit board. A method of manufacturing a semiconductor device, comprising: a second step of sealing a space between the circuit board and the semiconductor bare chip with a sealing resin, wherein the circuit board has a frame-shaped protrusion in advance on a peripheral portion of the opening. A portion is formed, and in the first step, the semiconductor bare chip is brought into contact with the top of the protrusion to be flip-chip mounted.
布する第１の工程と、 前記回路基板上に、受光素子を備えた半導体ベアチップ
を該受光素子が前記開口部に対応するように配置してフ
リップチップ実装する第２の工程とを含む半導体装置の
製造方法において、 前記回路基板には前記開口部の周縁部に予め枠状の突起
部が形成されており、 前記第２の工程で、前記半導体ベアチップは前記突起部
の頂部に当接してフリップチップ実装されることを特徴
とする半導体装置の製造方法。4. A first step of applying an adhesive on a circuit board having an opening, and a semiconductor bare chip having a light receiving element on the circuit board so that the light receiving element corresponds to the opening. A second step of arranging and flip-chip mounting the semiconductor device, wherein a frame-shaped protrusion is formed in advance on the peripheral edge of the opening in the circuit board, and the second step The method of manufacturing a semiconductor device is characterized in that the semiconductor bare chip is flip-chip mounted by contacting the top of the protrusion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001259789A JP2003068939A (en) | 2001-08-29 | 2001-08-29 | Semiconductor device and its manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001259789A JP2003068939A (en) | 2001-08-29 | 2001-08-29 | Semiconductor device and its manufacturing method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2003068939A true JP2003068939A (en) | 2003-03-07 |
Family
ID=19087108
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2001259789A Withdrawn JP2003068939A (en) | 2001-08-29 | 2001-08-29 | Semiconductor device and its manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2003068939A (en) |
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| JP2006186288A (en) * | 2004-09-14 | 2006-07-13 | Sony Chem Corp | Functional element mounted module and manufacturing method thereof |
| WO2007099677A1 (en) * | 2006-03-03 | 2007-09-07 | Sony Chemical & Information Device Corporation | Functional-element-mounted module, process for producing the same, resin sealing plate for use therein, and substrate structure for resin sealing |
| WO2007100037A1 (en) * | 2006-03-02 | 2007-09-07 | Sony Chemical & Information Device Corporation | Function element mounting module and method for manufacturing same |
| JP2008047830A (en) * | 2006-08-21 | 2008-02-28 | Hamamatsu Photonics Kk | Semiconductor device and manufacturing method of semiconductor device |
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2001
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| WO2007099677A1 (en) * | 2006-03-03 | 2007-09-07 | Sony Chemical & Information Device Corporation | Functional-element-mounted module, process for producing the same, resin sealing plate for use therein, and substrate structure for resin sealing |
| JP2008047830A (en) * | 2006-08-21 | 2008-02-28 | Hamamatsu Photonics Kk | Semiconductor device and manufacturing method of semiconductor device |
| JP2010075824A (en) * | 2008-09-25 | 2010-04-08 | Sony Corp | Device and nozzle for liquid coating |
| CN102054794A (en) * | 2009-10-26 | 2011-05-11 | 瑞萨电子株式会社 | Electronic device and fabrication method thereof |
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