JP2007305814A - Semiconductor integrated circuit device and its packaging method - Google Patents

Semiconductor integrated circuit device and its packaging method Download PDF

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JP2007305814A
JP2007305814A JP2006133164A JP2006133164A JP2007305814A JP 2007305814 A JP2007305814 A JP 2007305814A JP 2006133164 A JP2006133164 A JP 2006133164A JP 2006133164 A JP2006133164 A JP 2006133164A JP 2007305814 A JP2007305814 A JP 2007305814A
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semiconductor element
wiring board
integrated circuit
circuit device
semiconductor
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Kimihito Kuwabara
公仁 桑原
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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Priority to JP2006133164A priority Critical patent/JP2007305814A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body

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  • Semiconductor Integrated Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device in which a good fillet is formed even at a corner portion. <P>SOLUTION: Arrangement density per unit area of bump electrodes 3 formed on the backside at the corner portions 6a-6d of a semiconductor element 1 is set lower than the arrangement density of bump electrodes 3 formed on the sides 1a, 1b, 1c and 1d touching the corner portions 6a-6d of the semiconductor element 1 so that outflow of sealing resin material 5 is guided to the corner portions 6a-6d. <P>COPYRIGHT: (C)2008,JPO&amp;INPIT

Description

本発明はフリップチップ実装タイプの半導体集積回路装置に関するものである。   The present invention relates to a flip-chip mounting type semiconductor integrated circuit device.

フリップチップ実装タイプの半導体集積回路装置は図１２（ａ）〜（ｃ）に示すように構成されている。
半導体素子１を配線基板２に実装したこの種の半導体集積回路装置は、半導体素子１の裏面に形成された外部接続用の突起電極３が、配線基板２の上に形成された基板電極４に当設し、半導体素子１と配線基板２の間には硬化した封止樹脂材５が設けられている。封止樹脂材５は半導体素子１が配線基板２の実装位置から移動しないように固定する役目と、突起電極３と基板電極４との接触部を封止して良好な電気接続状態を維持する役目を果たしている。 The flip-chip mounting type semiconductor integrated circuit device is configured as shown in FIGS.
In this type of semiconductor integrated circuit device in which the semiconductor element 1 is mounted on the wiring substrate 2, the protruding electrode 3 for external connection formed on the back surface of the semiconductor element 1 is formed on the substrate electrode 4 formed on the wiring substrate 2. A cured sealing resin material 5 is provided between the semiconductor element 1 and the wiring board 2. The sealing resin material 5 serves to fix the semiconductor element 1 so as not to move from the mounting position of the wiring board 2 and seals the contact portion between the protruding electrode 3 and the substrate electrode 4 to maintain a good electrical connection state. Playing a role.

実装の工程は図１３のように実施されている。
図１３（ａ）（ｂ）に示すように、配線基板２の基板電極４の上に、シート状の封止樹脂材５を貼り付ける。次に図１３（ｃ）に示すように、半導体素子１を、この半導体素子１の突起電極３が形成されている裏面を配線基板２の側に向けて、熱可塑性の封止樹脂材５の上に配置し、熱をかけながら半導体素子１を配線基板２の側に押し付けると、封止樹脂材５が軟化して図１２（ｂ）に示すように半導体素子１の外側に流動する。このとき、半導体素子１の突起電極３と配線基板２の基板電極４とが当設して導通する。この状態で、温度を下げて封止樹脂材５を硬化させると、図１３（ｄ）に示すように配線基板２における半導体素子１の位置が、硬化した封止樹脂材５によって固定されて実装が完了する。
特開２００１−３５８１７５公報（図１） 特開２００２−１３４５５９公報（図１） The mounting process is performed as shown in FIG.
As shown in FIGS. 13A and 13B, a sheet-shaped sealing resin material 5 is attached on the substrate electrode 4 of the wiring substrate 2. Next, as shown in FIG. 13C, the semiconductor element 1 is made of the thermoplastic sealing resin material 5 with the back surface of the semiconductor element 1 on which the protruding electrode 3 is formed facing the wiring substrate 2 side. When the semiconductor element 1 is pressed on the wiring substrate 2 side while being placed on top and applying heat, the sealing resin material 5 is softened and flows to the outside of the semiconductor element 1 as shown in FIG. At this time, the protruding electrode 3 of the semiconductor element 1 and the substrate electrode 4 of the wiring board 2 are placed in contact with each other. When the sealing resin material 5 is cured by lowering the temperature in this state, the position of the semiconductor element 1 on the wiring board 2 is fixed by the cured sealing resin material 5 and mounted as shown in FIG. Is completed.
JP 2001-358175 A (FIG. 1) JP 2002-134559 A (FIG. 1)

図１２（ｂ）は図１２（ａ）のＡ−Ａ断面図、図１２（ｃ）は図１２（ａ）のＢ−Ｂ断面図を示しているが、平面形状が矩形の半導体素子１の場合には、４つの辺１ａ，１ｂ，１ｃ，１ｄから外側へは封止樹脂材５の十分な量の流出が発生して、硬化した封止樹脂材５によって半導体素子１を配線基板２に十分な接合力で係止できる。しかし、図１２（ｃ）に示すように半導体素子１のコーナー６への封止樹脂材５の流出の不足のために、硬化した封止樹脂材５による良好なフィレットが形成されない。   12B is a cross-sectional view taken along the line AA in FIG. 12A, and FIG. 12C is a cross-sectional view taken along the line BB in FIG. 12A. The planar shape of the semiconductor element 1 is rectangular. In this case, a sufficient amount of the sealing resin material 5 flows out from the four sides 1a, 1b, 1c, and 1d to the outside, and the cured sealing resin material 5 causes the semiconductor element 1 to be attached to the wiring board 2. Can be locked with sufficient bonding force. However, as shown in FIG. 12 (c), a satisfactory fillet is not formed by the cured sealing resin material 5 due to insufficient outflow of the sealing resin material 5 to the corner 6 of the semiconductor element 1.

これは、半導体素子１の薄型化などのために、図１４に示すように半導体素子１に反りが発生した場合には、突起電極３と基板電極４との導通の不良が発生する。
なお、（特許文献１）には、中央部での接合力の不足を改善することを目的として、接合材料が不均一にはみ出すことを規制するために、半導体回路素子１の突起電極配列の大きな隙間にダミーの突起電極としての接合材料流動規制部材３を設けて接合材料の分布の均一化を図ることが記載されており、（特許文献２）には、中央部での接合力の不足を改善することを目的として、接合材料が不均一にはみ出すことを規制するために、配線基板としての回路形成体６−１の側に接合材料流動規制部材３０３を設けて接合材料の分布の均一化を図ることが記載されている。しかし、このように構成しても、図１２（ｃ）に示したようなコーナー６に良好なフィレットを形成できない。 This is because when the semiconductor element 1 is warped as shown in FIG. 14 due to a reduction in the thickness of the semiconductor element 1, poor conduction between the protruding electrode 3 and the substrate electrode 4 occurs.
Note that (Patent Document 1) describes a large protruding electrode array of the semiconductor circuit element 1 in order to prevent the bonding material from protruding unevenly for the purpose of improving the shortage of the bonding force at the center. It is described that a bonding material flow restricting member 3 as a dummy protruding electrode is provided in the gap so as to make the distribution of the bonding material uniform. (Patent Document 2) describes a lack of bonding force at the center. For the purpose of improving, the bonding material flow regulating member 303 is provided on the circuit forming body 6-1 side as a wiring board in order to restrict the bonding material from protruding unevenly, thereby making the distribution of the bonding material uniform. Is described. However, even with this configuration, a good fillet cannot be formed at the corner 6 as shown in FIG.

本発明はコーナーにも良好なフィレットを形成できる半導体集積回路装置を提供することを目的とする。   An object of the present invention is to provide a semiconductor integrated circuit device capable of forming a good fillet at a corner.

本発明の請求項１記載の半導体集積回路装置は、半導体素子を配線基板にフリップチップ実装し、半導体素子と配線基板の間に介在する封止樹脂材によって半導体素子を配線基板に係止した半導体集積回路装置であって、半導体素子のコーナー部の裏面に形成された突起電極の単位面積あたりの配設密度を、前記半導体素子のコーナー部に接した辺に形成された突起電極の配設密度よりも低く形成したことを特徴とする。   A semiconductor integrated circuit device according to claim 1 of the present invention is a semiconductor in which a semiconductor element is flip-chip mounted on a wiring board, and the semiconductor element is locked to the wiring board by a sealing resin material interposed between the semiconductor element and the wiring board. In the integrated circuit device, the arrangement density per unit area of the projection electrodes formed on the back surface of the corner portion of the semiconductor element is the arrangement density of the projection electrodes formed on the side in contact with the corner portion of the semiconductor element. It is characterized by being formed lower than.

本発明の請求項２記載の半導体集積回路装置は、請求項１において、前記半導体素子のコーナー部に接した辺に沿って前記半導体素子の裏面の外周より内周側にかけて複数列にわたって突起電極を配設し、前記半導体素子の外周側よりも内周側の列の突起電極の数が少ないことを特徴とする。   A semiconductor integrated circuit device according to a second aspect of the present invention is the semiconductor integrated circuit device according to the first aspect, wherein the protruding electrodes are provided in a plurality of rows from the outer periphery to the inner peripheral side of the back surface of the semiconductor element along the side in contact with the corner portion of the semiconductor element. The number of protruding electrodes in the inner circumferential side row is smaller than the outer circumferential side of the semiconductor element.

本発明の請求項３記載の半導体集積回路装置は、請求項２において、前記半導体素子の裏面の中央部から前記半導体素子のコーナー部に向かって、突起電極が形成されていない低流動抵抗領域を形成したことを特徴とする。   A semiconductor integrated circuit device according to a third aspect of the present invention is the semiconductor integrated circuit device according to the second aspect, wherein the low flow resistance region in which no protruding electrode is formed is formed from the center of the back surface of the semiconductor element toward the corner of the semiconductor element. It is formed.

本発明の請求項４記載の半導体集積回路装置は、請求項２において、前記半導体素子の裏面の中央部から前記半導体素子のコーナー部に向かって、突起電極が形成されていない単一幅の低流動抵抗領域を形成したことを特徴とする。   According to a fourth aspect of the present invention, there is provided a semiconductor integrated circuit device according to the second aspect of the present invention, wherein the protruding electrode is not formed from the center of the back surface of the semiconductor element toward the corner of the semiconductor element. A flow resistance region is formed.

本発明の請求項５記載の半導体集積回路装置は、請求項２において、前記半導体素子の裏面の中央部から前記半導体素子のコーナー部に向かって、突起電極が形成されていない幅が前記中央部から前記コーナー部にかけて次第に広くなる低流動抵抗領域を形成したことを特徴とする。   A semiconductor integrated circuit device according to a fifth aspect of the present invention is the semiconductor integrated circuit device according to the second aspect, wherein a width in which no protruding electrode is formed from the central portion of the back surface of the semiconductor element toward the corner portion of the semiconductor element is the central portion. A low flow resistance region that gradually increases from the corner portion to the corner portion is formed.

本発明の請求項６記載の半導体集積回路装置は、半導体素子を配線基板にフリップチップ実装し、半導体素子と配線基板の間に介在する封止樹脂材によって半導体素子を配線基板に係止した半導体集積回路装置であって、前記半導体素子のコーナー部に接した辺に形成された突起電極のピッチを、前記コーナー部に近いほど大きく形成したことを特徴とする。   A semiconductor integrated circuit device according to claim 6 of the present invention is a semiconductor in which a semiconductor element is flip-chip mounted on a wiring board, and the semiconductor element is locked to the wiring board by a sealing resin material interposed between the semiconductor element and the wiring board. In the integrated circuit device, the pitch of the protruding electrodes formed on a side in contact with the corner portion of the semiconductor element is formed so as to be closer to the corner portion.

本発明の請求項７記載の半導体集積回路装置は、請求項６において、前記半導体素子のコーナー部に接した辺に沿って前記半導体素子の裏面の外周より内周側にかけて複数列にわたって突起電極を配設し、前記半導体素子の外周側よりも内周側の列の突起電極の数が少ないことを特徴とする。   A semiconductor integrated circuit device according to a seventh aspect of the present invention is the semiconductor integrated circuit device according to the sixth aspect, wherein the protruding electrodes are provided over a plurality of columns from the outer periphery to the inner peripheral side of the back surface of the semiconductor element along the side in contact with the corner portion of the semiconductor element. The number of protruding electrodes in the inner circumferential side row is smaller than the outer circumferential side of the semiconductor element.

本発明の請求項８記載の半導体集積回路装置は、請求項１〜請求項７において、前記配線基板の側で、実装された半導体素子のコーナー部と前記配線基板との対向個所から前記半導体素子よりも外側の位置に、軟化した前記封止樹脂材に対する濡れ性が前記配線基板の表面より良好な濡れ性改善領域を形成したことを特徴とする。   The semiconductor integrated circuit device according to an eighth aspect of the present invention is the semiconductor integrated circuit device according to any one of the first to seventh aspects, wherein the semiconductor element is formed on a side of the wiring board from a facing portion between a corner portion of the mounted semiconductor element and the wiring board. Further, a wettability improving region having better wettability with respect to the softened sealing resin material than the surface of the wiring board is formed at a position outside.

本発明の請求項９記載の半導体集積回路装置は、請求項１〜請求項７において、前記配線基板の側で、実装された半導体素子の中央部から前記半導体素子のコーナー部の下方位置に向かって、軟化した前記封止樹脂材に対する濡れ性が前記配線基板の表面より良好な濡れ性改善領域を形成したことを特徴とする。   A semiconductor integrated circuit device according to a ninth aspect of the present invention is the semiconductor integrated circuit device according to any one of the first to seventh aspects, wherein the wiring board side faces from a central portion of the mounted semiconductor element to a position below the corner portion of the semiconductor element. Thus, a wettability improving region having better wettability with respect to the softened sealing resin material than the surface of the wiring board is formed.

本発明の請求項１０記載の半導体集積回路装置は、請求項１〜請求項７において、前記配線基板の側で、実装された半導体素子の中央部から前記半導体素子のコーナー部に接した辺との間に、軟化した前記封止樹脂材に対する濡れ性が前記配線基板の表面より悪い濡れ性低減領域を形成したことを特徴とする。   A semiconductor integrated circuit device according to a tenth aspect of the present invention is the semiconductor integrated circuit device according to any one of the first to seventh aspects, wherein the wiring substrate side has a side in contact with a corner portion of the semiconductor element from a central portion of the mounted semiconductor element. In the meantime, a wettability reduction region is formed in which the wettability with respect to the softened sealing resin material is worse than the surface of the wiring board.

本発明の請求項１１記載の半導体集積回路装置の実装方法は、半導体素子を配線基板にフリップチップ実装するに際し、半導体素子のコーナー部の裏面に形成された突起電極の単位面積あたりの配設密度を、前記半導体素子のコーナー部に接した辺に形成された突起電極の配設密度よりも低く形成し、平面形状が前記半導体素子の平面形状と相似形でシート状の封止樹脂材を、半導体素子と配線基板の間に挟み、前記半導体素子と配線基板の間の隙間を小さくして、流れ出す前記封止樹脂材を半導体素子の前記コーナー部へ導くことを特徴とする。   According to the semiconductor integrated circuit device mounting method of the present invention, when the semiconductor element is flip-chip mounted on the wiring substrate, the disposition density per unit area of the protruding electrodes formed on the back surface of the corner portion of the semiconductor element. Is formed lower than the disposition density of the protruding electrodes formed on the side in contact with the corner portion of the semiconductor element, the planar shape is similar to the planar shape of the semiconductor element, a sheet-like sealing resin material, The sealing resin material is sandwiched between a semiconductor element and a wiring board, and a gap between the semiconductor element and the wiring board is reduced to guide the sealing resin material flowing out to the corner portion of the semiconductor element.

本発明の請求項１２記載の半導体集積回路装置の実装方法は、半導体素子を配線基板にフリップチップ実装し、半導体素子と配線基板の間に介在する封止樹脂材によって半導体素子を配線基板に係止した半導体集積回路装置であって、前記半導体素子のコーナー部に接した辺に形成された突起電極のピッチを、前記コーナー部に近いほど大きく形成し、平面形状が前記半導体素子の平面形状と相似形でシート状の封止樹脂材を、半導体素子と配線基板の間に挟み、前記半導体素子と配線基板の間の隙間を小さくして、流れ出す前記封止樹脂材を半導体素子の前記コーナー部へ導くことを特徴とする。   According to a twelfth aspect of the present invention, there is provided a semiconductor integrated circuit device mounting method in which a semiconductor element is flip-chip mounted on a wiring board, and the semiconductor element is connected to the wiring board by a sealing resin material interposed between the semiconductor element and the wiring board. The semiconductor integrated circuit device is stopped, and the pitch of the protruding electrodes formed on the side in contact with the corner portion of the semiconductor element is formed so as to be closer to the corner portion, and the planar shape is the same as the planar shape of the semiconductor element. A similar sheet-shaped sealing resin material is sandwiched between the semiconductor element and the wiring board, the gap between the semiconductor element and the wiring board is reduced, and the sealing resin material flowing out is used as the corner portion of the semiconductor element. It is characterized by leading to.

この構成によると、半導体素子のコーナー部の裏面に形成された突起電極の単位面積あたりの配設密度を、前記コーナー部に接した辺に形成された突起電極の配設密度よりも低く形成したり、前記半導体素子のコーナー部に接した辺に形成された突起電極のピッチを、前記コーナー部に近いほど大きく形成したため、半導体素子のコーナーと前記配線基板との間にも良好なフィレットを形成できる。   According to this configuration, the arrangement density per unit area of the protruding electrodes formed on the back surface of the corner portion of the semiconductor element is lower than the arrangement density of the protruding electrodes formed on the side in contact with the corner portion. In addition, since the pitch of the protruding electrodes formed on the side in contact with the corner portion of the semiconductor element is increased as it is closer to the corner portion, a good fillet is also formed between the corner of the semiconductor element and the wiring board. it can.

以下、本発明の各実施の形態を図１〜図１１に基づいて説明する。
（実施の形態１）
図１と図２は本発明の（実施の形態１）を示す。 Embodiments of the present invention will be described below with reference to FIGS.
(Embodiment 1)
1 and 2 show (Embodiment 1) of the present invention.

図１（ａ）〜（ｃ）は、図２に示した半導体素子１を配線基板２にフリップチップ実装した半導体集積回路装置を示す。
半導体素子１の裏面に形成されている突起電極３は、半導体素子１の四隅のコーナー６を有するコーナー部６ａ，６ｂ，６ｃ，６ｄの単位面積あたりの配設密度が、それに接した辺の場合よりも低くなるように形成されている。具体的には、コーナー部６ａに接した辺１ａ，１ｂに形成された突起電極３の配設密度よりも低く形成し、コーナー部６ｂに接した辺１ｂ，１ｃに形成された突起電極３の配設密度よりも低く形成し、コーナー部６ｃに接した辺１ｃ，１ｄに形成された突起電極３の配設密度よりも低く形成し、コーナー部６ｄに接した辺１ａ，１ｄに形成された突起電極３の配設密度よりも低く形成されている。 1A to 1C show a semiconductor integrated circuit device in which the semiconductor element 1 shown in FIG. 2 is flip-chip mounted on a wiring board 2.
The protruding electrode 3 formed on the back surface of the semiconductor element 1 has a case where the arrangement density per unit area of the corner portions 6a, 6b, 6c, and 6d having the four corners 6 of the semiconductor element 1 is a side in contact with the corners 6a, 6b, 6c, 6d. It is formed to be lower. Specifically, it is formed lower than the arrangement density of the protruding electrodes 3 formed on the sides 1a and 1b in contact with the corner 6a, and the protruding electrodes 3 formed on the sides 1b and 1c in contact with the corner 6b. Formed lower than the arrangement density, formed lower than the arrangement density of the protruding electrodes 3 formed on the sides 1c and 1d in contact with the corner 6c, and formed on the sides 1a and 1d in contact with the corner 6d. It is formed lower than the arrangement density of the protruding electrodes 3.

この半導体素子１を配線基板２の上に封止樹脂材５で熱圧着する。その工程は図１３（ａ）（ｂ）と同じように、平面形状が半導体素子１の外形と相似形の封止樹脂材５を配線基板２の上に貼り付け、熱可塑性の封止樹脂材５の上に、半導体素子１を、この半導体素子１の突起電極３が形成されている裏面を配線基板２の側に向けて配置し、熱をかけながら半導体素子１を配線基板２の側に押し付けて熱圧着する。   The semiconductor element 1 is thermocompression bonded onto the wiring substrate 2 with a sealing resin material 5. 13A and 13B, the process is affixed on the wiring board 2 with a sealing resin material 5 having a planar shape similar to the outer shape of the semiconductor element 1, and a thermoplastic sealing resin material. The semiconductor element 1 is placed on the wiring board 2 side with the back surface of the semiconductor element 1 on which the protruding electrodes 3 are formed facing the wiring board 2 side. Press and thermocompression.

半導体素子１を配線基板２に押し付ける図１３（ｃ）と図１３（ｄ）の間には、軟化した封止樹脂材５は次のように半導体素子１の外側に押し広げられる。
配線基板２に貼り付けられ熱圧着によって軟化した封止樹脂材５は、半導体素子１の辺１ａ〜１ｄと配線基板２との間から外側に流動し、図１（ｂ）に示すように半導体素子１の辺１ａ〜１ｄと配線基板２との間に良好なフィレットが形成される。 Between FIG. 13C and FIG. 13D in which the semiconductor element 1 is pressed against the wiring board 2, the softened sealing resin material 5 is pushed out to the outside of the semiconductor element 1 as follows.
The sealing resin material 5 attached to the wiring board 2 and softened by thermocompression flows outward from between the sides 1a to 1d of the semiconductor element 1 and the wiring board 2, and the semiconductor as shown in FIG. A good fillet is formed between the sides 1 a to 1 d of the element 1 and the wiring board 2.

従来では良好なフィレットの形成が期待できなかったコーナー６については、突起電極３の配設密度を辺１ａ〜１ｄよりも低く形成したため、コーナー６にも軟化した封止樹脂材５が良好に流動し、図１（ｃ）に示すように半導体素子１のコーナー６と配線基板２の間にも良好なフィレットを形成する。   In the corner 6 in which good fillet formation could not be expected in the past, the disposition density of the protruding electrodes 3 was formed lower than the sides 1a to 1d, and the softened sealing resin material 5 also flowed well in the corner 6. Then, a good fillet is also formed between the corner 6 of the semiconductor element 1 and the wiring substrate 2 as shown in FIG.

したがって、半導体素子１のコーナー６を従来に比べて強固に配線基板２に係止することができ、半導体素子１の反りの防止に有効である。
なお、ここではコーナー部６ａ〜６ｄの単位面積あたりの突起電極３の配設密度が、それに接した辺の場合よりも低くなるように形成して、半導体素子１の４つのコーナー部の全部の反りを防止するように構成したが、半導体素子１の４つのコーナー部の内の特定のコーナー部の単位面積あたりの突起電極３の配設密度が、それに接した辺の場合よりも低くなるように形成した場合も実施可能である。 Therefore, the corner 6 of the semiconductor element 1 can be firmly locked to the wiring board 2 as compared with the conventional case, and this is effective in preventing the warp of the semiconductor element 1.
Here, it is formed so that the arrangement density of the protruding electrodes 3 per unit area of the corner portions 6a to 6d is lower than that of the side in contact with the corner portions 6a to 6d. Although configured to prevent warping, the arrangement density of the protruding electrodes 3 per unit area of a specific corner portion of the four corner portions of the semiconductor element 1 is lower than that in the case of the side in contact with it. It can also be implemented when formed.

（実施の形態２）
図３は本発明の（実施の形態２）を示す。
この（実施の形態２）は、（実施の形態１）の構成に加えて、半導体素子１の裏面の外周より内周側にかけて前記辺１ａ〜１ｄに沿って複数列、図３では２列の突起電極を配設し、外周側の列の突起電極３の数よりも内周側の列の突起電極３の数が少なく配列されている。 (Embodiment 2)
FIG. 3 shows (Embodiment 2) of the present invention.
In addition to the configuration of (Embodiment 1), this (Embodiment 2) includes a plurality of rows along the sides 1a to 1d from the outer periphery to the inner periphery of the back surface of the semiconductor element 1, and two rows in FIG. Protruding electrodes are arranged, and the number of protruding electrodes 3 in the inner circumferential row is smaller than the number of protruding electrodes 3 in the outer circumferential row.

このように形成したため、配線基板２に貼り付けられ熱圧着によって軟化した封止樹脂材５は、半導体素子１の辺１ａ〜１ｄと配線基板２との間から外側に流動し、図１（ｂ）に示すように半導体素子１の辺１ａ〜１ｄと配線基板２との間に良好なフィレットが形成される。また、各コーナー部６ａ〜６ｄでは、半導体素子１の外側に押し広げられる流動性を持った封止樹脂材５が、ｐ１〜ｐ３で示す複数の突起電極３によって矢印１０で示すようにガイドされながら半導体素子１のコーナー６に向かって流動するので、半導体素子１の各コーナー６と配線基板２の間により良好なフィレットを形成できる。   Since the sealing resin material 5 that is attached to the wiring board 2 and is softened by thermocompression bonding flows to the outside from between the sides 1a to 1d of the semiconductor element 1 and the wiring board 2 because it is formed in this way, FIG. As shown in FIG. 2, good fillets are formed between the sides 1 a to 1 d of the semiconductor element 1 and the wiring board 2. Moreover, in each corner part 6a-6d, the sealing resin material 5 with the fluidity | liquidity pushed and spread to the outer side of the semiconductor element 1 is guided as shown by the arrow 10 by the some protruding electrode 3 shown by p1-p3. However, since it flows toward the corner 6 of the semiconductor element 1, a better fillet can be formed between each corner 6 of the semiconductor element 1 and the wiring board 2.

なお、ここでは半導体素子１の辺１ａ〜１ｄについて２列の突起電極３を形成したが、特定の辺にだけ形成した場合も実施可能である。
（実施の形態３）
図４は本発明の（実施の形態３）を示す。 Here, two rows of protruding electrodes 3 are formed on the sides 1a to 1d of the semiconductor element 1, but it is also possible to form the protruding electrodes 3 only on specific sides.
(Embodiment 3)
FIG. 4 shows (Embodiment 3) of the present invention.

図３では２列の突起電極を配設されていたが、図４では３列の突起電極を配設し、外周側の列の突起電極３の数よりも内周側の列の突起電極３の数が少なく配列されており、半導体素子１の外側に押し広げられる流動性を持った封止樹脂材５が、ｐ１〜ｐ４で示す複数の突起電極３によって矢印１０で示すようにガイドされながら半導体素子１のコーナー６に向かってより確実に流動させることができ、図１（ｂ）（ｃ）と同じように良好なフィレットを形成できる。   In FIG. 3, two rows of protruding electrodes are provided, but in FIG. 4, three rows of protruding electrodes are provided, and the protruding electrodes 3 in the inner circumferential row than the number of protruding electrodes 3 in the outer circumferential row. The sealing resin material 5 having fluidity that is spread out to the outside of the semiconductor element 1 is guided as indicated by an arrow 10 by a plurality of protruding electrodes 3 indicated by p1 to p4. It can be made to flow more reliably toward the corner 6 of the semiconductor element 1, and a good fillet can be formed in the same manner as in FIGS.

なお、ここでは半導体素子１の辺１ａ〜１ｄについて３列の突起電極３を形成したが、特定の辺にだけ形成した場合も実施可能である。
（実施の形態４）
図５は本発明の（実施の形態４）を示す。 Although the three rows of protruding electrodes 3 are formed on the sides 1a to 1d of the semiconductor element 1 here, it is also possible to form the protruding electrodes 3 only on specific sides.
(Embodiment 4)
FIG. 5 shows (Embodiment 4) of the present invention.

この（実施の形態４）は、（実施の形態１）の構成に加えて、半導体素子１の裏面の中央部Ｓ０から前記コーナー部６ａ〜６ｄに向かって、突起電極３が形成されていない低流動抵抗領域Ｓ１，Ｓ２，Ｓ３，Ｓ４が形成されており、半導体素子１の外側に押し広げられる流動性を持った封止樹脂材５が、流動抵抗が突起電極３が形成されている領域よりも低い低流動抵抗領域Ｓ１，Ｓ２，Ｓ３，Ｓ４によって半導体素子１のコーナー９に向かって流動させることができ、図１（ｂ）（ｃ）と同じように良好なフィレットを形成できる。   In this (Embodiment 4), in addition to the configuration of (Embodiment 1), the protruding electrode 3 is not formed from the central portion S0 on the back surface of the semiconductor element 1 toward the corner portions 6a to 6d. Flow resistance regions S 1, S 2, S 3, S 4 are formed, and the sealing resin material 5 having fluidity to be spread outside the semiconductor element 1 has a flow resistance higher than that of the region where the protruding electrodes 3 are formed. 1 can be made to flow toward the corner 9 of the semiconductor element 1 by the low low flow resistance regions S1, S2, S3, S4, and a good fillet can be formed as in FIGS.

なお、ここでは４つのコーナー部６ａ〜６ｄに向かって、低流動抵抗領域Ｓ１，Ｓ２，Ｓ３，Ｓ４を形成したが、特定のコーナー部に向かって低流動抵抗領域を形成した場合も実施可能である。   Here, the low flow resistance regions S1, S2, S3, and S4 are formed toward the four corner portions 6a to 6d, but the present invention can also be implemented when the low flow resistance region is formed toward the specific corner portion. is there.

（実施の形態５）
図６は本発明の（実施の形態５）を示す。
この実施の形態では、低流動抵抗領域Ｓ１，Ｓ２，Ｓ３，Ｓ４の形状が、中央部Ｓ０からコーナー部６ａ〜６ｄにかけて仮想線１２で示すように次第に幅が広くなる点だけが、単一幅であった図５の低流動抵抗領域Ｓ１，Ｓ２，Ｓ３，Ｓ４と異なっている。 (Embodiment 5)
FIG. 6 shows (Embodiment 5) of the present invention.
In this embodiment, the shape of the low flow resistance regions S1, S2, S3, S4 is a single width only in that the width gradually increases from the central portion S0 to the corner portions 6a to 6d as indicated by the virtual line 12. This is different from the low flow resistance regions S1, S2, S3, S4 of FIG.

この構成によると、半導体素子１の外側に押し広げられる流動性を持った封止樹脂材５が、流動抵抗が突起電極３が形成されている領域よりも低い低流動抵抗領域Ｓ１，Ｓ２，Ｓ３，Ｓ４によって半導体素子１のコーナー６に向かってより確実に流動させることができ、図１（ｂ）（ｃ）と同じように良好なフィレットを形成できる。   According to this configuration, the sealing resin material 5 having fluidity that is spread outside the semiconductor element 1 has a low flow resistance region S1, S2, S3 in which the flow resistance is lower than the region where the protruding electrodes 3 are formed. , S4, the semiconductor element 1 can be made to flow more reliably toward the corner 6 and a good fillet can be formed as in FIGS.

なお、ここでは４つのコーナー部６ａ〜６ｄに向かって、低流動抵抗領域Ｓ１，Ｓ２，Ｓ３，Ｓ４を形成したが、特定のコーナー部に向かって低流動抵抗領域を形成した場合も実施可能である。   Here, the low flow resistance regions S1, S2, S3, and S4 are formed toward the four corner portions 6a to 6d, but the present invention can also be implemented when the low flow resistance region is formed toward the specific corner portion. is there.

（実施の形態６）
図７は本発明の（実施の形態６）を示す。
半導体素子１の裏面に形成されている突起電極３は、半導体素子１のコーナー部６ａ〜６ｄに接した辺１ａ，１ｂ，１ｃ，１ｄに形成された突起電極３のピッチを、コーナー部６ａ〜６ｄに近いほど大きく、Ｐ３ ＞ Ｐ２ ＞ Ｐ１に形成されている。 (Embodiment 6)
FIG. 7 shows (Embodiment 6) of the present invention.
The protruding electrodes 3 formed on the back surface of the semiconductor element 1 have the pitches of the protruding electrodes 3 formed on the sides 1a, 1b, 1c, and 1d in contact with the corner portions 6a to 6d of the semiconductor element 1 set to the corner portions 6a to 6d. The closer to 6d, the larger, and P3>P2> P1.

このように構成したため、この半導体素子１を配線基板２の上に封止樹脂材５で熱圧着すると、軟化した封止樹脂材５は、半導体素子１の辺１ａ〜１ｄと配線基板２との間から外側に流動し、図１（ｂ）に示すように半導体素子１の辺１ａ〜１ｄと配線基板２との間に良好なフィレットが形成されるとともに、突起電極３のピッチがコーナー部６ａ〜６ｄに近いほど大きく形成されているため、コーナー部６ａ〜６ｄにも軟化した封止樹脂材５が良好に流動し、図１（ｃ）に示すように半導体素子１の各コーナー６と配線基板２の間にも良好なフィレットを形成する。   Since it comprised in this way, when this semiconductor element 1 is thermocompression-bonded with the sealing resin material 5 on the wiring board 2, the softened sealing resin material 5 will be the edge | side 1a-1d of the semiconductor element 1, and the wiring board 2 As shown in FIG. 1B, a good fillet is formed between the sides 1a to 1d of the semiconductor element 1 and the wiring board 2 as shown in FIG. 1B, and the pitch of the protruding electrodes 3 is set to the corner portion 6a. Since it is formed larger as it is closer to ˜6d, the softened sealing resin material 5 flows well in the corners 6a to 6d, and each corner 6 and the wiring of the semiconductor element 1 are wired as shown in FIG. A good fillet is also formed between the substrates 2.

したがって、半導体素子１のコーナー部６ａ〜６ｄを従来に比べて強固に配線基板２に係止することができ、半導体素子１の反りの防止に有効である。
なお、ここでは半導体素子１の辺１ａ〜１ｄについて突起電極３のピッチを、コーナー部６ａ〜６ｄに近いほど大きく形成したが、特定の辺にについて突起電極３のピッチを、コーナー部６ａ〜６ｄに近いほど大きく形成した場合も実施可能である。 Therefore, the corner portions 6a to 6d of the semiconductor element 1 can be firmly locked to the wiring board 2 as compared with the conventional case, which is effective in preventing warpage of the semiconductor element 1.
Here, the pitch of the protruding electrodes 3 is formed so as to be closer to the corner portions 6a to 6d with respect to the sides 1a to 1d of the semiconductor element 1, but the pitch of the protruding electrodes 3 is set to the corner portions 6a to 6d with respect to a specific side. It is also possible to make it larger as it is closer to.

（実施の形態７）
図８は本発明の（実施の形態７）を示す。
この（実施の形態７）は、（実施の形態６）の構成に加えて、半導体素子１の裏面の外周より内周側にかけて前記辺１ａ〜１ｄに沿って複数列、図８では２列の突起電極を配設し、外周側の列の突起電極３の数よりも内周側の列の突起電極３の数が少なく配列されている。 (Embodiment 7)
FIG. 8 shows (Embodiment 7) of the present invention.
In addition to the configuration of (Embodiment 6), this (Embodiment 7) includes a plurality of rows along the sides 1a to 1d from the outer periphery to the inner periphery of the back surface of the semiconductor element 1, and two rows in FIG. Protruding electrodes are arranged, and the number of protruding electrodes 3 in the inner circumferential row is smaller than the number of protruding electrodes 3 in the outer circumferential row.

このように形成したため、配線基板２に貼り付けられ熱圧着によって軟化した封止樹脂材５は、半導体素子１の辺１ａ〜１ｄと配線基板２との間から外側に流動し、図１（ｂ）に示すように半導体素子１の辺１ａ〜１ｄと配線基板２との間に良好なフィレットが形成される。また、各コーナー部６ａ〜６ｄでは、半導体素子１の外側に押し広げられる流動性を持った封止樹脂材５が、ｐ１〜ｐ３で示す複数の突起電極３によって矢印１０で示すようにガイドされながら半導体素子１のコーナー６に向かって流動するので、半導体素子１の各コーナー６と配線基板２の間により良好なフィレットを形成できる。   Since the sealing resin material 5 that is attached to the wiring board 2 and is softened by thermocompression bonding flows to the outside from between the sides 1a to 1d of the semiconductor element 1 and the wiring board 2 because it is formed in this way, FIG. As shown in FIG. 2, good fillets are formed between the sides 1 a to 1 d of the semiconductor element 1 and the wiring board 2. Moreover, in each corner part 6a-6d, the sealing resin material 5 with the fluidity | liquidity pushed and spread to the outer side of the semiconductor element 1 is guided as shown by the arrow 10 by the some protruding electrode 3 shown by p1-p3. However, since it flows toward the corner 6 of the semiconductor element 1, a better fillet can be formed between each corner 6 of the semiconductor element 1 and the wiring board 2.

なお、ここでは半導体素子１の辺１ａ〜１ｄについて突起電極３のピッチを、コーナー部６ａ〜６ｄに近いほど大きく形成したが、特定の辺にについて突起電極３のピッチを、コーナー部６ａ〜６ｄに近いほど大きく形成した場合も実施可能である。   Here, the pitch of the protruding electrodes 3 is formed so as to be closer to the corner portions 6a to 6d with respect to the sides 1a to 1d of the semiconductor element 1, but the pitch of the protruding electrodes 3 is set to the corner portions 6a to 6d with respect to a specific side. It is also possible to make it larger as it is closer to.

（実施の形態８）
図９は本発明の（実施の形態８）を示す。
この（実施の形態８）の半導体集積回路装置は、（実施の形態１）の構成に加えて、配線基板２には、実装される半導体素子１のコーナー部６に対応して、濡れ性改善領域１１ａ〜１１ｄが形成されている。濡れ性改善領域１１ａ〜１１ｄは、配線基板２の表面を化学処理することによって、軟化した封止樹脂材５に対する濡れ性がその周辺部より良好に加工されている。一例としては、濡れ性改善領域１１ａ〜１１ｄの部分にだけプラズマが照射されるように配線基板２の上にマスクをセットし、プラズマを照射することによって、プラズマの照射を受けた部分の濡れ角が小さく加工されている。 (Embodiment 8)
FIG. 9 shows (Embodiment 8) of the present invention.
In addition to the configuration of (Embodiment 1), the semiconductor integrated circuit device of (Embodiment 8) has improved wettability on wiring board 2 corresponding to corner portion 6 of semiconductor element 1 to be mounted. Regions 11a to 11d are formed. In the wettability improvement regions 11a to 11d, the wettability with respect to the softened sealing resin material 5 is processed better than the peripheral portion by chemically treating the surface of the wiring board 2. As an example, by setting a mask on the wiring substrate 2 so that only the portions of the wettability improving regions 11a to 11d are irradiated with plasma and irradiating the plasma, the wetting angle of the portion irradiated with the plasma Is processed small.

このように構成したため、平面形状が半導体素子１の平面形状と相似形でシート状の封止樹脂材５を、半導体素子１と配線基板２の間に挟み、半導体素子１を配線基板２に熱圧着すると、流れ出した封止樹脂材５によって、図５（ｂ）に示すように半導体素子１の辺１ａ，１ｂ，１ｃ，１ｄと配線基板２との間に良好なフィレットが形成される。また、濡れ性改善領域１１ａ〜１１ｄの作用によって、従来よりも多くの封止樹脂材５がコーナー６へ導びかれて、図５（ｃ）に示すように半導体素子１の各コーナー６と配線基板２の間に良好なフィレットを形成することができ、半導体素子１のコーナー６を従来に比べて強固に配線基板２に係止することができ、半導体素子１の反りの防止に有効である。   With this configuration, the planar shape is similar to the planar shape of the semiconductor element 1, and the sheet-like sealing resin material 5 is sandwiched between the semiconductor element 1 and the wiring board 2, and the semiconductor element 1 is heated to the wiring board 2. When the pressure bonding is performed, a good fillet is formed between the sides 1a, 1b, 1c, 1d of the semiconductor element 1 and the wiring board 2 as shown in FIG. In addition, due to the action of the wettability improving regions 11a to 11d, more sealing resin material 5 than before is led to the corner 6, and each corner 6 of the semiconductor element 1 and the wiring are connected as shown in FIG. A good fillet can be formed between the substrates 2 and the corners 6 of the semiconductor element 1 can be firmly locked to the wiring substrate 2 as compared with the prior art, which is effective in preventing warpage of the semiconductor element 1. .

なお、半導体素子１の４つのコーナー部のそれぞれに対応して濡れ性改善領域１１ａ〜１１ｄを形成したが、半導体素子１の４つのコーナー部の内の特定のコーナー部に対応して濡れ性改善領域を形成して、封止樹脂材を半導体素子１の前記特定のコーナー部だけへ導くように形成した場合も実施可能である。   Although the wettability improvement regions 11a to 11d are formed corresponding to the four corner portions of the semiconductor element 1, the wettability improvement is performed corresponding to a specific corner portion of the four corner portions of the semiconductor element 1. It is also possible to form the region so that the sealing resin material is led only to the specific corner portion of the semiconductor element 1.

また、この（実施の形態８）では（実施の形態１）の配線基板２に濡れ性改善領域１１ａ〜１１ｄを形成した場合を例に挙げて説明したが、（実施の形態２）〜（実施の形態７）の配線基板２に濡れ性改善領域１１ａ〜１１ｄを形成した場合も同様に実施できる。   Moreover, in this (Embodiment 8), although the case where the wettability improvement area | regions 11a-11d were formed in the wiring board 2 of (Embodiment 1) was mentioned as an example, (Embodiment 2)-(implementation) The case where the wettability improving regions 11a to 11d are formed on the wiring board 2 of the seventh embodiment can be similarly implemented.

（実施の形態９）
図１０は本発明の（実施の形態９）を示す。
この（実施の形態９）の半導体集積回路装置は、（実施の形態１）の構成に加えて、配線基板２には、半導体素子１の実装位置の中央部からコーナー６の下方位置に向かって、軟化した封止樹脂材５に対する濡れ性が配線基板２の表面より良好な濡れ性改善領域１１を形成されている点が（実施の形態８）と異なっている。 (Embodiment 9)
FIG. 10 shows (Embodiment 9) of the present invention.
In addition to the configuration of (Embodiment 1), the semiconductor integrated circuit device of (Embodiment 9) is provided on the wiring board 2 from the center of the mounting position of the semiconductor element 1 toward a position below the corner 6. The difference from (Embodiment 8) is that a wettability improving region 11 having better wettability with respect to the softened sealing resin material 5 than the surface of the wiring board 2 is formed.

このように構成したため、封止樹脂材５を挟んで配線基板２に半導体装置１を積み重ねて、熱圧着することによって、濡れ性改善領域１１の作用によって、従来よりも多くの封止樹脂材５がコーナー６へ導びかれて、図５（ｃ）に示すように半導体素子１の各コーナー６と配線基板２の間に良好なフィレットを形成することができ、半導体素子１のコーナー６を従来に比べて強固に配線基板２に係止することができ、半導体素子１の反りの防止に有効である。   With this configuration, the semiconductor device 1 is stacked on the wiring board 2 with the sealing resin material 5 interposed therebetween, and is subjected to thermocompression bonding, so that more sealing resin materials 5 than the conventional one can be obtained by the action of the wettability improving region 11. As shown in FIG. 5C, a good fillet can be formed between each corner 6 of the semiconductor element 1 and the wiring board 2 as shown in FIG. As compared with the above, it can be firmly locked to the wiring board 2 and is effective in preventing the warp of the semiconductor element 1.

なお、半導体素子１の４つのコーナー部のそれぞれに対応して濡れ性改善領域１１を形成したが、半導体素子１の４つのコーナー部の内の特定のコーナー部に対応して濡れ性改善領域を形成して、封止樹脂材を半導体素子１の前記特定のコーナー部だけへ導くように形成した場合も実施可能である。   Although the wettability improvement regions 11 are formed corresponding to the four corner portions of the semiconductor element 1, the wettability improvement regions corresponding to specific corner portions of the four corner portions of the semiconductor element 1 are formed. It is also possible to form the sealing resin material so as to lead only to the specific corner portion of the semiconductor element 1.

また、この（実施の形態９）では（実施の形態１）の配線基板２に濡れ性改善領域１１を形成した場合を例に挙げて説明したが、（実施の形態２）〜（実施の形態７）の配線基板２に濡れ性改善領域１１を形成した場合も同様に実施できる。   Further, in this (Embodiment 9), the case where the wettability improving region 11 is formed on the wiring substrate 2 of (Embodiment 1) has been described as an example, but (Embodiment 2) to (Embodiment 2) The same can be done when the wettability improving region 11 is formed on the wiring board 2 of 7).

（実施の形態１０）
図１１は本発明の（実施の形態１０）を示す。
この（実施の形態１０）の半導体集積回路装置は、（実施の形態１）の構成に加えて、配線基板２には、濡れ性低減領域７ａ〜７ｄが形成されている。具体的には、半導体素子１の実装位置の基板電極４よりも実装位置の内側にかけて濡れ性低減領域７ａ〜７ｄが形成されている。濡れ性低減領域７ａ〜７ｄは、配線基板２の表面を化学処理することによって、軟化した封止樹脂材５に対する濡れ性がその周辺部より悪く加工されている。一例としては、濡れ性低減領域７ａ〜７ｄの部分の表面荒さを周辺部よりも荒くして濡れ角が大きく加工されている。 (Embodiment 10)
FIG. 11 shows (Embodiment 10) of the present invention.
In the semiconductor integrated circuit device of (Embodiment 10), in addition to the configuration of (Embodiment 1), wettability reduction regions 7a to 7d are formed in the wiring board 2. Specifically, wettability reduction regions 7a to 7d are formed from the substrate electrode 4 at the mounting position of the semiconductor element 1 to the inside of the mounting position. The wettability reduction regions 7a to 7d are processed such that the wettability with respect to the softened sealing resin material 5 is worse than the peripheral portion by chemically treating the surface of the wiring board 2. As an example, the surface roughness of the wettability reduction regions 7a to 7d is made rougher than that of the peripheral portion so that the wetting angle is increased.

このように構成したため、配線基板２に貼り付けられ熱圧着によって軟化した封止樹脂材５は、濡れ性低減領域７ａ〜７ｄを越えて半導体素子１の辺１ａ〜１ｄと配線基板２との間から外側に流動し、図１（ｂ）に示すように半導体素子１の辺１ａ〜１ｄと配線基板２との間に良好なフィレットが形成される。また、濡れ性低減領域７ａ〜７ｄの部分は濡れ角が大きいため、封止樹脂材５の一部が濡れ性低減領域７ａ〜７ｄに沿って矢印１３で示すように、半導体素子１のコーナー６に向かって流動する。したがって、図１（ｃ）に示すように半導体素子１の各コーナー６と配線基板２の間にも良好なフィレットを形成することができ、半導体素子１のコーナー６を従来に比べて強固に配線基板２に係止することができ、半導体素子１の反りの防止に有効である。   With this configuration, the sealing resin material 5 attached to the wiring board 2 and softened by thermocompression bonding is between the sides 1a to 1d of the semiconductor element 1 and the wiring board 2 beyond the wettability reduction regions 7a to 7d. As shown in FIG. 1B, a good fillet is formed between the sides 1 a to 1 d of the semiconductor element 1 and the wiring board 2. Further, since the wettability reduction regions 7a to 7d have a large wetting angle, a part 6 of the sealing resin material 5 is shown along the wettability reduction regions 7a to 7d as indicated by the arrow 13 in the corner 6 of the semiconductor element 1. It flows toward. Therefore, as shown in FIG. 1C, a good fillet can be formed between each corner 6 of the semiconductor element 1 and the wiring board 2, and the corner 6 of the semiconductor element 1 can be wired more firmly than in the prior art. It can be locked to the substrate 2 and is effective in preventing warpage of the semiconductor element 1.

また、この（実施の形態１０）では（実施の形態１）の配線基板２に濡れ性低減領域７ａ〜７ｄを形成した場合を例に挙げて説明したが、（実施の形態２）〜（実施の形態７）の配線基板２に濡れ性低減領域７ａ〜７ｄを形成した場合も同様に実施できる。   Further, in this (Embodiment 10), the case where the wettability reduction regions 7a to 7d are formed on the wiring board 2 of (Embodiment 1) has been described as an example, but (Embodiment 2) to (Embodiment 2). In the case where the wettability reducing regions 7a to 7d are formed on the wiring board 2 of the form 7), the same can be applied.

上記の各実施の形態において封止樹脂材５は、非導電性の封止樹脂材であっても、導電異方性樹脂材であっても、実施できる。   In each of the above-described embodiments, the sealing resin material 5 may be a non-conductive sealing resin material or a conductive anisotropic resin material.

半導体集積回路装置の高信頼性化に寄与できる。   This contributes to high reliability of the semiconductor integrated circuit device.

本発明の（実施の形態１）の半導体集積回路装置の平面図とそのＡ−Ａ線とＢ−Ｂ線に沿う断面図The top view of the semiconductor integrated circuit device of (Embodiment 1) of this invention, and sectional drawing which follows the AA line and BB line 同実施の形態の半導体素子の正面図とその底面図Front view and bottom view of the semiconductor element of the embodiment 本発明の（実施の形態２）の半導体集積回路装置に使用する半導体素子の底面図The bottom view of the semiconductor element used for the semiconductor integrated circuit device of (Embodiment 2) of this invention 本発明の（実施の形態３）の半導体集積回路装置に使用する半導体素子の底面図The bottom view of the semiconductor element used for the semiconductor integrated circuit device of (Embodiment 3) of this invention 本発明の（実施の形態４）の半導体集積回路装置に使用する半導体素子の底面図The bottom view of the semiconductor element used for the semiconductor integrated circuit device of (Embodiment 4) of this invention 本発明の（実施の形態５）の半導体集積回路装置に使用する半導体素子の底面図The bottom view of the semiconductor element used for the semiconductor integrated circuit device of (Embodiment 5) of this invention 本発明の（実施の形態６）の半導体集積回路装置に使用する半導体素子の底面図The bottom view of the semiconductor element used for the semiconductor integrated circuit device of (Embodiment 6) of this invention 本発明の（実施の形態７）の半導体集積回路装置に使用する半導体素子の底面図The bottom view of the semiconductor element used for the semiconductor integrated circuit device of (Embodiment 7) of this invention 本発明の（実施の形態８）の半導体集積回路装置に使用する配線基板の平面図The top view of the wiring board used for the semiconductor integrated circuit device of (Embodiment 8) of this invention 本発明の（実施の形態９）の半導体集積回路装置に使用する配線基板の平面図The top view of the wiring board used for the semiconductor integrated circuit device of (Embodiment 9) of this invention 本発明の（実施の形態１０）の半導体集積回路装置に使用する配線基板の平面図A plan view of a wiring board used in a semiconductor integrated circuit device according to (Embodiment 10) of the present invention. 従来の半導体集積回路装置の平面図とそのＡ−Ａ線とＢ−Ｂ線に沿う断面図A plan view of a conventional semiconductor integrated circuit device and a sectional view taken along lines AA and BB 一般的な実装工程を示す断面図Sectional view showing the general mounting process 半導体素子に反りが発生した場合の断面図Sectional view when warpage occurs in semiconductor element

符号の説明Explanation of symbols

１ 半導体素子
１ａ，１ｂ，１ｃ，１ｄ 半導体素子１のコーナー部に接した辺
２ 配線基板
３ 突起電極
４ 基板電極
５ 封止樹脂材
６ 半導体素子１のコーナー
６ａ，６ｂ，６ｃ，６ｄ 半導体素子１のコーナー部
７ａ〜７ｄ 濡れ性低減領域
１１，１１ａ〜１１ｄ 濡れ性改善領域
Ｓ１，Ｓ２，Ｓ３，Ｓ４ 低流動抵抗領域 DESCRIPTION OF SYMBOLS 1 Semiconductor element 1a, 1b, 1c, 1d The side which contact | connected the corner part of the semiconductor element 1 2 Wiring board 3 Protrusion electrode 4 Substrate electrode 5 Sealing resin material 6 Corner 6a, 6b, 6c, 6d of the semiconductor element 1 Semiconductor element 1 Corner portions 7a to 7d wettability reduction region 11, 11a to 11d wettability improvement region S1, S2, S3, S4 low flow resistance region

Claims (12)

半導体素子を配線基板にフリップチップ実装し、半導体素子と配線基板の間に介在する封止樹脂材によって半導体素子を配線基板に係止した半導体集積回路装置であって、
半導体素子のコーナー部の裏面に形成された突起電極の単位面積あたりの配設密度を、前記半導体素子のコーナー部に接した辺に形成された突起電極の配設密度よりも低く形成した
半導体集積回路装置。 A semiconductor integrated circuit device in which a semiconductor element is flip-chip mounted on a wiring board, and the semiconductor element is locked to the wiring board by a sealing resin material interposed between the semiconductor element and the wiring board,
A semiconductor integrated circuit in which the disposition density per unit area of the bump electrodes formed on the back surface of the corner portion of the semiconductor element is lower than the disposition density of the bump electrodes formed on the side in contact with the corner portion of the semiconductor element. Circuit device. 前記半導体素子のコーナー部に接した辺に沿って前記半導体素子の裏面の外周より内周側にかけて複数列にわたって突起電極を配設し、前記半導体素子の外周側よりも内周側の列の突起電極の数が少ない
請求項１記載の半導体集積回路装置。 Protruding electrodes are arranged over a plurality of rows from the outer periphery to the inner peripheral side of the back surface of the semiconductor element along the side in contact with the corner portion of the semiconductor element, and the protrusions in the inner peripheral row from the outer peripheral side of the semiconductor element 2. The semiconductor integrated circuit device according to claim 1, wherein the number of electrodes is small. 前記半導体素子の裏面の中央部から前記半導体素子のコーナー部に向かって、突起電極が形成されていない低流動抵抗領域を形成した
請求項２記載の半導体集積回路装置。 3. The semiconductor integrated circuit device according to claim 2, wherein a low flow resistance region in which no protruding electrode is formed is formed from a central portion of the back surface of the semiconductor element toward a corner portion of the semiconductor element. 前記半導体素子の裏面の中央部から前記半導体素子のコーナー部に向かって、突起電極が形成されていない単一幅の低流動抵抗領域を形成した
請求項２記載の半導体集積回路装置。 3. The semiconductor integrated circuit device according to claim 2, wherein a low-flow resistance region having a single width in which no protruding electrode is formed is formed from a central portion of the back surface of the semiconductor element toward a corner portion of the semiconductor element. 前記半導体素子の裏面の中央部から前記半導体素子のコーナー部に向かって、突起電極が形成されていない幅が前記中央部から前記コーナー部にかけて次第に広くなる低流動抵抗領域を形成した
請求項２記載の半導体集積回路装置。 The low flow resistance region in which a width where no protruding electrode is formed gradually widens from the central part to the corner part from the central part of the back surface of the semiconductor element toward the corner part of the semiconductor element is formed. Semiconductor integrated circuit device. 半導体素子を配線基板にフリップチップ実装し、半導体素子と配線基板の間に介在する封止樹脂材によって半導体素子を配線基板に係止した半導体集積回路装置であって、
前記半導体素子のコーナー部に接した辺に形成された突起電極のピッチを、前記コーナー部に近いほど大きく形成した
半導体集積回路装置。 A semiconductor integrated circuit device in which a semiconductor element is flip-chip mounted on a wiring board, and the semiconductor element is locked to the wiring board by a sealing resin material interposed between the semiconductor element and the wiring board,
A semiconductor integrated circuit device in which a pitch of protruding electrodes formed on a side in contact with a corner portion of the semiconductor element is formed to be larger as it is closer to the corner portion. 前記半導体素子のコーナー部に接した辺に沿って前記半導体素子の裏面の外周より内周側にかけて複数列にわたって突起電極を配設し、前記半導体素子の外周側よりも内周側の列の突起電極の数が少ない
請求項６記載の半導体集積回路装置。 Protruding electrodes are arranged over a plurality of rows from the outer periphery to the inner peripheral side of the back surface of the semiconductor element along the side in contact with the corner portion of the semiconductor element, and the protrusions in the inner peripheral row from the outer peripheral side of the semiconductor element The semiconductor integrated circuit device according to claim 6, wherein the number of electrodes is small. 前記配線基板の側で、実装された半導体素子のコーナー部と前記配線基板との対向個所から前記半導体素子よりも外側の位置に、軟化した前記封止樹脂材に対する濡れ性が前記配線基板の表面より良好な濡れ性改善領域を形成した
請求項１〜請求項７のいずれかに記載の半導体集積回路装置。 On the side of the wiring board, the surface of the wiring board has wettability to the softened sealing resin material at a position outside the semiconductor element from a position where the corner portion of the mounted semiconductor element and the wiring board face each other. 8. The semiconductor integrated circuit device according to claim 1, wherein a better wettability improving region is formed. 前記配線基板の側で、実装された半導体素子の中央部から前記半導体素子のコーナー部の下方位置に向かって、軟化した前記封止樹脂材に対する濡れ性が前記配線基板の表面より良好な濡れ性改善領域を形成した
請求項１〜請求項７のいずれかに記載の半導体集積回路装置。 On the wiring board side, the wettability with respect to the softened sealing resin material is better than the surface of the wiring board from the central part of the mounted semiconductor element toward the lower position of the corner part of the semiconductor element. 8. The semiconductor integrated circuit device according to claim 1, wherein an improvement region is formed. 前記配線基板の側で、実装された半導体素子の中央部から前記半導体素子のコーナー部に接した辺との間に、
軟化した前記封止樹脂材に対する濡れ性が前記配線基板の表面より悪い濡れ性低減領域を形成した
請求項１〜請求項７のいずれかに記載の半導体集積回路装置。 Between the side of the wiring board and the side in contact with the corner of the semiconductor element from the center of the mounted semiconductor element,
8. The semiconductor integrated circuit device according to claim 1, wherein a wettability reduction region is formed in which the wettability with respect to the softened sealing resin material is worse than the surface of the wiring substrate. 半導体素子を配線基板にフリップチップ実装するに際し、
半導体素子のコーナー部の裏面に形成された突起電極の単位面積あたりの配設密度を、前記半導体素子のコーナー部に接した辺に形成された突起電極の配設密度よりも低く形成し、
平面形状が前記半導体素子の平面形状と相似形でシート状の封止樹脂材を、半導体素子と配線基板の間に挟み、前記半導体素子と配線基板の間の隙間を小さくして、流れ出す前記封止樹脂材を半導体素子の前記コーナー部へ導く
半導体集積回路装置の実装方法。 When flip chip mounting a semiconductor element on a wiring board,
The arrangement density per unit area of the protruding electrodes formed on the back surface of the corner portion of the semiconductor element is lower than the arrangement density of the protruding electrodes formed on the side in contact with the corner portion of the semiconductor element,
The sealing resin material having a planar shape similar to the planar shape of the semiconductor element is sandwiched between the semiconductor element and the wiring board, the gap between the semiconductor element and the wiring board is reduced, and the seal flows out. A method for mounting a semiconductor integrated circuit device, wherein a stop resin material is led to the corner portion of a semiconductor element. 半導体素子を配線基板にフリップチップ実装し、半導体素子と配線基板の間に介在する封止樹脂材によって半導体素子を配線基板に係止した半導体集積回路装置であって、
前記半導体素子のコーナー部に接した辺に形成された突起電極のピッチを、前記コーナー部に近いほど大きく形成し、
平面形状が前記半導体素子の平面形状と相似形でシート状の封止樹脂材を、半導体素子と配線基板の間に挟み、前記半導体素子と配線基板の間の隙間を小さくして、流れ出す前記封止樹脂材を半導体素子の前記コーナー部へ導く
半導体集積回路装置の実装方法。 A semiconductor integrated circuit device in which a semiconductor element is flip-chip mounted on a wiring board, and the semiconductor element is locked to the wiring board by a sealing resin material interposed between the semiconductor element and the wiring board,
The pitch of the protruding electrodes formed on the side in contact with the corner portion of the semiconductor element is formed so as to be closer to the corner portion,
The sealing resin material having a planar shape similar to the planar shape of the semiconductor element is sandwiched between the semiconductor element and the wiring board, the gap between the semiconductor element and the wiring board is reduced, and the seal flows out. A method for mounting a semiconductor integrated circuit device, wherein a stop resin material is led to the corner portion of a semiconductor element.
JP2006133164A 2006-05-12 2006-05-12 Semiconductor integrated circuit device and its packaging method Pending JP2007305814A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007305813A (en) * 2006-05-12 2007-11-22 Matsushita Electric Ind Co Ltd Semiconductor integrated circuit device and its packaging method
JP2008004674A (en) * 2006-06-21 2008-01-10 Fujitsu Ltd Semiconductor device formed of semiconductor element and circuit board
US10959328B2 (en) 2019-07-01 2021-03-23 Shinko Electric Industries Co., Ltd. Wiring substrate, stacked wiring substrate, and manufacturing method of wiring substrate

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007305813A (en) * 2006-05-12 2007-11-22 Matsushita Electric Ind Co Ltd Semiconductor integrated circuit device and its packaging method
JP4731397B2 (en) * 2006-05-12 2011-07-20 パナソニック株式会社 Semiconductor integrated circuit device
JP2008004674A (en) * 2006-06-21 2008-01-10 Fujitsu Ltd Semiconductor device formed of semiconductor element and circuit board
JP4732252B2 (en) * 2006-06-21 2011-07-27 富士通株式会社 Semiconductor device comprising semiconductor element and circuit board
US10959328B2 (en) 2019-07-01 2021-03-23 Shinko Electric Industries Co., Ltd. Wiring substrate, stacked wiring substrate, and manufacturing method of wiring substrate

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