JP2003010506A - Game machine - Google Patents

Abstract

PROBLEM TO BE SOLVED: To return to a normal state without giving to a player a sense of incompatibility when a subcontrol portion does not normally function in a game machine which has a main control portion and a subcontrol portion for controlling an electrical device in accepting a command output from the main control portion. SOLUTION: The subcontrol portion 100 has a CPU 102, and a first monitoring circuit 116 and a second monitoring circuit 118 which are cleared every predetermined cycle by the CPU 102. The first monitoring circuit 116 outputs an abnormal signal when not cleared before the first time elapses from clearance and the second monitoring circuit 118 outputs an abnormal signal when not cleared before the second time, which is longer than the first time, elapses from clearance. The CPU 102 performs treatment based on a command output from a main control portion 200, stores backup information every predetermined cycle, performs return treatment by using the backup information when receiving an abnormal signal outputted from the first monitoring circuit 116, and performs initialization treatment when receiving an abnormal signal outputted from the second monitoring circuit 118.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gaming machine provided with a main control unit and a sub control unit that performs a predetermined process in accordance with a command from the main control unit, and in particular, the CPU of the sub control unit has some cause. The present invention relates to a technique for returning a sub control unit to a normal state when the sub control unit does not function normally.

[0002]

2. Description of the Related Art For example, in a pachinko machine, which is one of the gaming machines, various electric devices (eg, a symbol display device, a voice output device, a lamp device, etc.) operate in accordance with the progress of the game. These electric devices are controlled by a control system configured by a main control unit that totally controls the entire gaming machine and a sub control unit that is provided for each electric device. That is, the main control unit outputs a command to each sub control unit,
Each sub-control unit operates the electrical equipment according to the output command. In such a gaming machine, there is a demand to diversify the game effect performed by the electric device (for example, diversify the image effect on the symbol display device) in order to improve the interest of the game. As one technique for satisfying this demand, a technique has been developed in which the number of commands output from the main control unit to the sub control unit is minimized and the sub control unit freely determines and executes the game effect. The above-mentioned conventional technology will be specifically described by taking a case where a special symbol is variably displayed on the symbol display device as an example. The main control unit outputs to the display control unit (one of sub-control units) a command designating a stop symbol and a variation pattern of the special symbol when the variation of the special symbol starts, and also outputs a confirmation command when the variation stops. The display control unit determines the display effect from the stop pattern and the variation pattern instructed by the command received when the variation starts. Then, the special symbol is variably displayed on the symbol display device according to the decided display effect, and when the confirmation command is received, the special symbol is confirmed and displayed. As is clear from the above description, in this conventional technique, the main control unit outputs a command to the sub control unit only at the start and end of the game effect, and during the game effect, the sub control unit is based on the game effect determined by itself. Control electrical equipment. Therefore, in this conventional technique, the sub-control unit determines the game performance of the electric device, and the like, thereby making full use of the processing capacity thereof and diversifying the game performance.

[0003]

By the way, in the gaming machine controlled by the main control unit and the sub-control unit, the sub-control unit causes some cause (for example, noise) during the game performance.
When it stops working properly (when it freezes)
In addition, there is a gap between the main control unit and the sub control unit. That is, when the sub control unit does not function normally, the process being executed is reset and initialized. On the other hand, even if the sub-control unit is initialized, the main control unit performs the process as if the sub-control unit is functioning normally, so that the two processes are in conflict. In such a case, in the above conventional technique, the main control unit outputs the command to the sub control unit only at the start and end of the game effect, so that the state where the processes of the main control unit and the sub control unit are different from each other continues for a long time. Become. It is not preferable that such a state in which the processing of the main control unit and the processing of the sub control unit are different from each other continues for a long time, which gives the player a feeling of strangeness. As a method of solving such a problem, backup information for restoring the processing of the sub control unit is saved every predetermined period, and the backup information is used when the sub control unit does not function normally. Then, a method of self-recovering can be considered. However, in such a method, if the backed up information itself is destroyed or freezes during the restoration process using the backed up information, the sub control unit cannot be restored to the normal state and forced. Therefore, the normal state cannot be restored until the power is cut off.

The present invention has been made in view of the above points, and by providing a plurality of monitoring circuits for monitoring the state of the sub-control unit, it is possible to appropriately return the sub-control unit to the normal state. The purpose is to provide.

[0005]

In order to solve the above-mentioned problems, the invention according to claim 1 is a sub-control for controlling an electric device by receiving a command output from the main control unit and the main control unit. In a gaming machine having a section,
The sub-control unit has a CPU, a first monitoring circuit that is cleared by the CPU in every first cycle, and a second monitoring circuit that is cleared by the CPU in every second cycle. The first monitoring circuit outputs an abnormal signal when the first monitoring circuit is not cleared before the first time elapses after the clearing, and the second monitoring circuit outputs the second time longer than the first time after being cleared. An abnormal signal is output when it is not cleared before the elapse. The CPU performs processing based on a command output from the main control unit, saves backup information at predetermined intervals, and when an abnormal signal output from the first monitoring circuit is received, restore processing is performed using the backup information. When an abnormal signal output from the second monitoring circuit is received, initialization processing is performed. In the above gaming machine, when the CPU of the sub control unit is in an abnormal state, first, an abnormal signal is output from the first monitoring circuit. When the abnormal signal is output from the first monitoring circuit, the CPU performs the restoration process using the backup information. When the restoration process using the backup information ends normally, the CPU restarts the clearing of the first monitoring circuit and the second monitoring circuit, so that the abnormal signal is not output from the second monitoring circuit. On the other hand, when the restoration process using the backup information is not normally completed, the CPU does not clear the second monitoring circuit, so that the abnormal signal is output from the second monitoring circuit and the CPU is initialized. Therefore, the CPU of the sub-control unit can be returned to a normal state without shutting down the power source. Here, the above-mentioned "backup information" is information that can restore the state of the CPU to the state at the past time (for example, the time when the backup information was saved) when the CPU does not function normally. It doesn't matter what kind or configuration it is.

In the above gaming machine, the abnormal signal output from the first monitoring circuit is input to the NMI terminal of the CPU, and the abnormal signal output from the second monitoring circuit is input to the reset terminal of the CPU. Is preferred. According to such a configuration, the abnormal signal from the first monitoring circuit is NM.
Since the input is made to the I terminal, the restoration process using the backup information is immediately started. Since the abnormal signal output from the second monitoring circuit is input to the reset terminal, the processing of the CPU of the sub control unit is forcibly reset and initialized.

In the above gaming machine, the first cycle for clearing the first monitoring circuit and the second cycle for clearing the second monitoring circuit
It is preferable that the cycles are the same. With such a configuration, the first monitoring circuit and the second monitoring circuit are cleared in the same cycle, so that the two circuits can be easily synchronized.

The above problem can be solved by the gaming machine according to the fourth aspect. That is, the gaming machine according to claim 4 is a gaming machine having a main control unit and a sub-control unit that receives a command output from the main control unit and controls the electrical device, wherein the sub-control unit is a CPU. , CPU
It has a first monitoring circuit and a second monitoring circuit for monitoring the operation of. The first monitoring circuit outputs an abnormal signal when a first time period has elapsed after the CPU operation has become abnormal, and the second monitoring circuit has a first time period after the CPU operation has become abnormal. After a lapse of a predetermined time, an abnormal signal is output when the predetermined time has elapsed, and the CPU performs processing based on the command output from the main control unit and saves backup information at predetermined intervals. Then, when the operation becomes abnormal, the CPU first performs a recovery process using the backup information stored with the abnormal signal output from the first monitoring circuit as a trigger. When the normal state cannot be restored, further initialization is triggered by an abnormal signal output from the second monitoring circuit. In the above-mentioned gaming machine, the sub-control unit is provided with two monitoring circuits for monitoring the CPU. When the CPU of the sub-control unit becomes abnormal, first, the backup information is used to perform the restoration process, and the restoration process causes normal operation. If it cannot return to the normal state, it is initialized. Therefore, when the self-recovery is possible, it is possible to prevent the player from feeling uncomfortable by performing the recovery process, and even when the recovery process cannot be performed, the initialization is performed without a method such as power-off.

[0009]

BEST MODE FOR CARRYING OUT THE INVENTION The gaming machine described in each of the above claims can be suitably implemented in the following modes. (Mode 1) The first cycle and the second cycle are the same cycle, and the first monitoring circuit and the second monitoring circuit are cleared at the same timing. According to this mode, the clearing process of the first monitoring circuit and the clearing process of the second monitoring circuit can be simultaneously performed in one process. (Mode 2) In Mode 1, the second time period is
The first time is set to be longer than the time obtained by adding the time required for the restoration process and the time required for outputting the clear signal after the restoration. According to such a form, C
When each monitoring circuit is no longer cleared by the PU, an abnormal signal is first output from the first monitoring circuit and a recovery process is performed. Then, when the recovery processing is performed favorably and the CPU restarts the clearing of each monitoring circuit, the abnormal signal is not output from the second monitoring circuit and the initialization processing of the CPU is not performed. On the other hand, if the CPU cannot resume the clearing of each monitoring circuit without the restoration process being properly performed, the second monitoring circuit outputs an abnormal signal to initialize the CPU. (Mode 3) The sub control unit performs a process of displaying a required image on the image display device based on a command output from the main control unit. Each time the CPU of the sub-control unit creates image data for one screen, the CPU outputs the data to the image display device and stores it as backup information. (Mode 4) The first monitoring circuit and the second monitoring circuit are each configured by a watchdog timer circuit. In each watchdog timer circuit, the time from being cleared by adjusting the resistor R and the capacitor C until the abnormal signal is output is adjusted.

[0010]

Embodiment A pachinko machine according to an embodiment of the present invention will be described with reference to FIGS. 1 to 6. FIG. 1 is a front view showing an appearance of a type 1 pachinko machine according to the present embodiment, FIG. 2 is a block diagram showing a configuration of a control unit of the pachinko machine shown in FIG. 1, and FIG. 3 is a display control unit. RA of CPU
FIG. 5 is a diagram showing a data structure of M, FIG. 4 is a flowchart showing a processing procedure of a display control unit when a signal is inputted to a reset terminal, and FIG. 5 is a flow chart of a display control unit when a signal is inputted to an NMI terminal. 6 is a flowchart showing a processing procedure, and FIG. 6 is a timing chart showing states of input / output signals of the CPU, the first watchdog timer circuit, and the second watchdog timer circuit.

As shown in FIG. 1, on the game board surface 12 of the pachinko machine 10, a symbol display device 14, a first type starting opening 30, a special winning opening 34, etc. are appropriately arranged. Type 1 starting port 30
Has a starting opening sensor, and when a pachinko ball wins a prize, a prize ball (prize ball) is paid out in the same manner as a normal winning opening. The special winning opening 34 has an opening / closing lid 36, and the flattening lid 36 is opened / closed by a solenoid. Open / close lid 36
The period during which the game is opened ends, for example, when a predetermined number of pachinko balls (generally 10) are won in the special winning opening 34 or after 30 seconds elapses, whichever comes first.

A symbol display device 14 is attached to the approximate center of the game board surface 12. The symbol display device 14 is provided with a symbol display 22 and a holding ball lamp 28 for displaying the number of times the special symbol is changed and held. The symbol display 22 is composed of a liquid crystal display of 256 × 1024 dots, and is controlled by the display control unit 200 described later. Three special symbols are variably displayed on the screen of the liquid crystal display 22. The special symbol that is variably displayed on the symbol display device 22 has a role of making the player recognize whether or not to shift to the big hit game state (the state where the special winning opening 34 is opened) by the combination of the symbols when the fluctuation is stopped. Fulfill The liquid crystal display used in this embodiment is the same as that used in a known pachinko machine, and its structure and the like do not particularly characterize the present invention, so a detailed description thereof will be omitted.

In addition to the game board surface 12 described above, the gaming machine 10 has a lower tray 40 for temporarily storing pachinko balls including prize balls and ball rental balls, an ashtray 42 for storing cigarette butts,
An upper plate 46, which is a tray for prize balls, and a speaker 52, which is provided inside the upper plate 46 and generates a sound effect according to a game state, are provided. Further, at appropriate positions on the front of the pachinko machine 10, there are provided lamps 16 and the like that emit light according to the gaming state of the pachinko machine 10. Since the structures and the like of these devices are the same as those used in a known pachinko machine, detailed description thereof will be omitted.

Next, the structure of a control system for displaying a symbol on the symbol display 22 provided in the pachinko machine 10 will be described with reference to FIGS. 2 and 3. The main control unit 200 and the display control unit 100 that form the control system are both provided on the back side of the pachinko machine 10. The main control unit 200 includes a CPU, ROM, and RAM,
It is configured by a so-called microcomputer and controls each electric device arranged in the pachinko machine 10 and performs a process of creating command data for instructing a variation of a special symbol and a process of transmitting the created command data to the display control unit 100. . The command data created by the main control unit 200 and output to the display control unit 100 is command data instructing a variation pattern of the special symbol, command data instructing a stop symbol of the three special symbols displayed on the symbol display 22. , Command data for instructing stop of fluctuation of special symbols is included. The main control unit 200 is the same as that used in a conventionally known pachinko machine, and its structure, operation, and the like do not particularly characterize the present invention, and thus detailed description thereof will be omitted.

Next, the configuration of the display control unit 100 which receives the command data transmitted from the main control unit 200 and controls the symbol display 22 will be described. Display control unit 1
As shown in FIG. 2, reference numeral 00 denotes a control ROM 104, a character ROM 106, a V, a CPU 102 that receives command data transmitted from the main control unit 200.
RAM 108, color palette RAM 110, video display processor 112 (hereinafter, simply referred to as VDP), D / A converter 114, first watchdog timer circuit 116, second watchdog timer circuit 118.
Composed of. The CPU 102 is the main control unit 200.
Command data sent from the control ROM 1
VDP according to the control program stored in 04.
The process of outputting the control signal is performed. The specific processing procedure will be described in detail later. In the RAM built in the CPU 102, as shown in FIG. 3, a main memory area for storing various data and a backup area are formed. In the main memory area, execution processing information and the like generated according to the progress of the game are stored. In the backup area, a backup area 1 and a backup area 2 are formed, and in each of these backup areas 1 and 2, information of the main work area is provided as execution processing information necessary for restoration processing, as will be described later. Is stored.

The VDP 112 receives the control signal output from the CPU 102, creates display data for one image from each data stored in the character ROM 106, the color palette RAM 110, and the VRAM 108, and displays the created display data as an image. D / A converter 1 as signal
Processing for outputting to the symbol display 22 via 14 is performed. Here, the character ROM 106 displays the display character (0
The display data for displaying the numbers up to 9, such as *, etc.) on the symbol display device 22 is stored (for example, 32 × 32 dots). This display data is specified by designating the color of each dot forming the display data by a color number. The color palette RAM 110 stores color data for each color number. Specifically, if 1 dot is 4 bits, 16 colors of color data are stored, and if 1 dot is 8 bits, 256 colors of color data are stored. The VRAM 108 stores data designating at which position on the actual image the display data stored in the character ROM 106 is arranged. Therefore, VDP
112 reads the display data from the character ROM 106 according to the control signal output from the CPU 102, and arranges the read display data at a position designated by the data stored in the VRAM 108. At this time, the display data in the character ROM 106 is converted from color numbers into color data by the data stored in the color palette RAM 110. When the display data for one image is created by these processes, VDP1
12 outputs the display data as an image signal to the symbol display 22 via the D / A converter 114. The above-described display data creation processing and the processing of outputting the created display data to the symbol display device 22 are the same as the processing performed by the VDP of a conventionally known pachinko machine, and particularly characterize the present invention. Since this is not the case, detailed description thereof will be omitted here.

The first watchdog timer circuit 116 is
It is a circuit that monitors whether the CPU 102 is normal or abnormal depending on whether a clear signal output from the CPU 102 in every predetermined cycle is detected (specifically, a rising edge of the signal is detected). Specifically, when the next clear signal is not received within a predetermined time after receiving the clear signal, it is determined that the CPU 102 is abnormal, and a signal is output to the NMI terminal (non-massable interrupt terminal) of the CPU 102. Second
The watchdog timer circuit 118, like the first watchdog timer circuit 116, is a circuit that monitors whether the CPU 102 is normal or abnormal. However, in the second watchdog timer circuit 118, compared with the first watchdog timer circuit 116, the CPU 1
This is different from the first watchdog timer circuit 116 in that the time until the signal is output to 02 is set long and the output signal is input to the reset terminal of the CPU 102. Therefore, when a predetermined time elapses after the output of the clear signal of the CPU 102 is interrupted, first, the signal is output from the first watchdog timer circuit 116 to the NMI terminal of the CPU 102. Then, when the output of the clear signal of the CPU 102 further passes a predetermined time, a signal is output from the second watchdog timer circuit 118 to the reset terminal of the CPU 102. The timing of outputting the clear signal of each watchdog timer circuit 116, 118 is determined by the external resistor R and capacitor C.

Next, the processing executed by the CPU 102 when a signal is input to the reset terminal of the CPU 102 will be described with reference to the flowchart shown in FIG. In addition to the signal output from the second watchdog timer circuit 118 described above, the reset terminal of the CPU 102 also receives a signal for initialization output when the pachinko machine is powered on. ing. As shown in FIG. 4, when a signal is input to the reset terminal of the CPU 102, the CPU 102 is first initialized (S).
10). By this initialization processing, the setting of each input / output port of the CPU 102 is initialized. Next, the CPU 102
The RAM (see Fig. 3) built in is cleared (S1
2) Then, the VDP 112 is further initialized (S14).
By the processing of these steps S10 to S14, the CPU 1
02, the VDP 112 is initialized (the state when the power is turned on).

When the initialization process is completed, the CPU 102
Determines whether the VDP 112 is executing the DMA process (direct memory access transfer process) (S16).
That is, in this embodiment, when the VDP 112 creates display data for one image (created on the first RAM incorporated in the VDP 112) by the processing of steps S20 and S22 described later, the VDP 112 displays the display data. From the first RAM to the second RAM (also VDP112
Built-in). By this transfer processing, it becomes possible to create display data for an image to be displayed next on the first RAM. The data transferred to the second RAM will be sequentially output to the symbol display 22 via the D / A converter 114. If the DMA process is being executed [YES in step S16], the process waits until the DMA process is completed, and if the DMA process is not being executed [NO in step S16], the process proceeds to step S18. In step S18, the state of the watchdog timer port of the CPU 102 is set to HIGH. here,
The watchdog timer port is connected to the clear signal input terminal of the first watchdog timer circuit 116 and the clear signal input terminal of the second watchdog timer circuit 118. Therefore, the state of each clear signal input terminal of the first watchdog timer circuit 116 and the second watchdog timer circuit 118 becomes the HIGH state by the processing of step S18. Therefore, the watchdog timer circuits 116 and 118 are cleared by detecting the rising edge of this signal.

In step S20, the main controller 200
Analyzes the command output from. Specifically, the command output from the main control unit 200 is CP
When it is stored in the input buffer of U102 (that is, when the CPU 102 receives the command output from the main control unit 200), the stored command is analyzed, while the CPU 102
If the command has not been received, the step S20
Processing is skipped and the process proceeds to step S22. In step S22, a process of outputting a control signal to VDP 112 is performed based on the command analyzed in step S20. According to the control signal output from the CPU 102, the VDP 112 performs a process of creating display data of an image displayed on the symbol display 22. Symbol display 2
As an example, the case of variably displaying special symbols in 2 will be explained.
The PU 102 first analyzes the received command data to identify the stop symbol of the special symbol and the fluctuation pattern data (scheduler data). Next, the control ROM 104
Then, the scheduler data is read out, the read scheduler data is sequentially decoded, converted into a control signal that can be handled by the VDP 112, and the converted control signal is output to the VDP 112. VDP112
When receiving the control signal output from the CPU 102, the display data is created based on the received control signal. The output process of the control signal from the CPU 102 to the VDP 112 in step S22 is performed for each image displayed on the symbol display 22.

In step S24, the checksum of the main memory area of the CPU 102 is calculated. This checksum is data for determining whether the data stored in the RAM of the CPU 102 is normal, and is calculated by adding the data in the main memory area by a predetermined method. When the checksum is calculated, it is determined whether the timer count is even (S26). This timer count is a numerical value that is incremented by one each time the processing of step S22 (processing for instructing the VDP 112 to create display data for one image) is performed. Therefore, the CPU 102 causes the VDP 112 to proceed through the process of step S22.
When the control signal is output to, the timer count value changes from odd number → even number → odd number. If the timer count is an even number [YES in step S26], the data stored in the main memory area (specifically, the execution process information of the main work area) is transferred as backup data to the backup area 1 and stored. Yes (S2
8). On the contrary, if the timer count is odd [Step S
26 is NO], the execution process information of the main work area is transferred to the backup area 2 and stored (S3).
2). When the backup of the data stored in the main memory area is completed in step S28 and step S32, the CPU that is in the HIGH state in step S18
The state of the watchdog timer port 102 is set to the LOW state (S30). When step S30 ends, the process returns to step S16 and the processes from step S16 are repeated.

As is clear from the above description, the CPU 1
When a signal is input to the reset terminal of 02, the CPU 102
And VDP 112 is initialized. CPU10
When the initialization process of No. 2 is performed, the CPU 102 outputs a clear pulse signal to each of the watchdog timer circuits 116 and 118 at a predetermined cycle thereafter (every time when the processes of steps S16 to S30 are performed). To be done. Further, every time the processing of steps S16 to S30 is performed (every time the display data for one image is created by the VDP 112), the information in the main memory area is alternately transferred to the backup area 1 and the backup area 2. .

Next, the processing executed by the CPU 102 when a signal is input to the NMI terminal of the CPU 102 will be described with reference to the flowchart shown in FIG. As shown in FIG. 5, when a signal is input to the NMI terminal of the CPU 102, the CPU 102 is first initialized (S40). This initialization process is similar to the initialization process of step S10 in FIG. Next, CP
The checksum of the main memory area of U102 is calculated (S42), and it is determined whether the calculated checksum is normal (S44). If the checksum calculated in step S42 is normal [Y in step S44
In the case of ES], since the data in the main memory area of the CPU 102 is normal, the process proceeds to step S60, the display system is initialized, and the process proceeds to step S16 of FIG.

If the checksum of the main memory area is abnormal [NO in step S44], first,
Calculate the checksum of backup area 1 (S4
6) It is determined whether the calculated checksum is normal (S48). When the checksum of backup area 1 is normal [YES in step S48]
Transfers the data stored in the backup area 1 to the main memory area (S50), and proceeds to step S60. Therefore, CPU 102 performs the restoration process using the data stored in backup area 1.

On the contrary, when the checksum of the backup area 1 is abnormal [NO in step S48]
Next, the checksum of the backup area 2 is calculated (S52), and it is determined whether the calculated checksum is normal (S54). If the checksum of the backup area 2 is normal [YES in step S54
In the case of S], the data stored in the backup area 2 is transferred to the main memory area (S56), and the process proceeds to step S60. Therefore, CPU 102 performs the restoration process using the data stored in backup area 2. If the checksum of the backup area 2 is abnormal [NO in step S54]
Clears the RAM of the CPU 102 (S58),
In step S60, the display system is initialized, and the display system shown in FIG.
Then, the process proceeds to step S16.

The display control unit 10 processed as described above.
The operation of each circuit of 0 will be described with reference to the timing chart shown in FIG. As shown in FIG. 6, when the power of the pachinko machine is turned on, the states of the output signals of the first watchdog timer circuit 116 and the second watchdog timer circuit 18 are HIGH level (the signal is OFF) accordingly.
Becomes The CPU 102 is supplied with power and the processing shown in FIG. 4 is started, and a pulse signal is output to each of the watchdog timer circuits 116 and 118 at predetermined intervals. Therefore, each of the watchdog timer circuits 116 and 118 is cleared every predetermined period, and the state of the output signal thereof does not become the LOW level (the signal is in the ON state). If the CPU 102 stops functioning normally for some reason in such a state, the CPU 102 causes each watchdog timer circuit 1 to operate.
No pulse signal is output to 16, 118. Therefore, the first watchdog timer circuit 11 is started t1 time after the pulse signal of the CPU 102 is not output.
The state of the output signal of 6 becomes LOW level. For this reason,
In the CPU 102, a signal is input to the NMI terminal and a restoration process using the backup information stored in the backup area is performed. When the CPU 102 returns to the normal state by this return processing, the CPU 102 outputs the pulse signal to each of the watchdog timer circuits 116 and 118 again. Therefore, the second watchdog timer circuit 1
The state of the output signal of 18 never becomes LOW level. Normally, the CPU has an INT terminal (interrupt terminal) as an interrupt terminal other than the NMI terminal.
Since the user can inhibit the interrupt at the T terminal by software (program), the signal of the first watchdog timer circuit 116 is input to the NMI terminal that can be immediately executed in this embodiment. On the contrary, when the CPU 102 cannot return to the normal state by the above-mentioned return processing (for example, when the information such as the system register that cannot be set by the user when the CPU 102 is reset changes and freezes during the processing), FIG. As shown in FIG.
T2 time (t
After a time longer than the time required for the recovery process of FIG. 5 to be added to 1 hour), the second watchdog timer circuit 11
The state of the output signal of 8 becomes LOW level. For this reason,
The CPU 102 is initialized by the input of a signal to the reset terminal and returns to a normal state. That is, it is initialized to the same state as when the power was turned on.

As is apparent from the above description, in the pachinko machine according to this embodiment, when the CPU 102 does not function normally, first, the self-recovery process is performed using the backup information stored every predetermined period. Then, when the self-recovery process cannot restore the normal state, the initialization process is performed. Therefore, when the self-recovery is possible, the self-recovery process is performed to correct the inconsistency in the processes of the main control unit and the display control unit, and prevent the player from feeling uncomfortable. Further, when the restoration process using the backed up information is frozen, the CPU 102 is reset and initialized. Therefore, even if the self-recovery process using the backup information fails to restore the normal state, the CPU 102 can be returned to the normal state without the power interruption or the like.

In the above-mentioned embodiment, the present invention is applied to the display control section for controlling the symbol display device, but the present invention is also applied to other control sections connected to the main control section. be able to. For example, the present invention can be applied to a sound control unit that outputs a voice from a speaker based on a command of the main control unit and a lamp control unit that causes a lamp to emit light based on a command of the main control unit. In particular, since the processing of the sound control unit and the lamp control unit is related to the device related to the game effect and is easily recognized by the player, it is effective to apply the technique of the present invention.

Although specific examples of the present invention have been described in detail above, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above. Further, the technical elements described in the present specification or the drawings are
The technical usefulness is exhibited alone or in various combinations, and is not limited to the combinations described in the claims at the time of filing. Further, the technique illustrated in the present specification or the drawings achieves a plurality of purposes at the same time, and achieving the one purpose among them has technical utility.

[Brief description of drawings]

FIG. 1 is a front view showing the outer appearance of a type 1 pachinko machine according to this embodiment.

2 is a block diagram showing a configuration of a control unit of the pachinko machine shown in FIG.

FIG. 3 is a diagram schematically showing a structure of a RAM of a CPU of a display control unit.

FIG. 4 is a flowchart showing processing of the CPU of the display control unit when a signal is input to the reset terminal of the CPU of the display control unit.

FIG. 5 is a flowchart showing processing of the CPU of the display control unit when a signal is input to the NMI terminal of the CPU of the display control unit.

FIG. 6 is a timing chart showing states of input / output signals of the CPU of the display control unit, the first watchdog timer circuit, and the second watchdog timer circuit.

[Explanation of symbols]

100 ... Display control unit 102 ... CPU 104 ... Control ROM 106..Character ROM 108 ... VRAM 110 ... Color palette RAM 112 ... VDP 116. First watchdog timer circuit 118. Second watchdog timer circuit 200 Main control unit

Continued front page    (72) Inventor Kazushige Tanaka             Nishinokawa, Okimura, Nishiharu-cho, Nishikasugai-gun, Aichi Prefecture             No. 1 Omanai Co., Ltd. F-term (reference) 2C088 BC56 CA08 CA16

Claims (4)

[Claims] 1. A gaming machine having a main control unit and a sub control unit for controlling an electric device by receiving a command output from the main control unit, wherein the sub control unit has a CPU and a first cycle by the CPU. A first monitoring circuit that is cleared every time, and a second monitoring circuit that is cleared by the CPU in every second cycle. The first monitoring circuit is cleared from the time when the first time elapses. When it is not cleared, it outputs an abnormal signal, and the second monitoring circuit outputs an abnormal signal when it is not cleared by the time when the second time, which is longer than the first time, has passed after being cleared. The processing is performed based on the command output from the unit, the backup information is saved in every predetermined cycle, and when the abnormal signal output from the first monitoring circuit is received, the backup information is used to restore the information. Performs processing, gaming machine and performing initialization processing when receiving the abnormality signal output from the second monitoring circuit. 2. The abnormal signal output from the first monitoring circuit is input to the NMI terminal of the CPU, and the abnormal signal output from the second monitoring circuit is input to the reset terminal of the CPU. The gaming machine according to claim 1. 3. The gaming machine according to claim 1, wherein the first cycle for clearing the first monitoring circuit and the second cycle for clearing the second monitoring circuit are the same cycle. 4. A gaming machine having a main control section and a sub control section for controlling an electric device by receiving a command output from the main control section, wherein the sub control section monitors the CPU and the operation of the CPU. First
The first monitoring circuit has a monitoring circuit and a second monitoring circuit.
When the time of has passed, an abnormal signal is output, and the second monitoring circuit is
After a lapse of time, when a predetermined time has elapsed, an abnormal signal is output, and the CPU performs processing based on a command output from the main control unit and saves backup information at predetermined intervals. When the operation becomes abnormal, first,
When the restoration processing is performed by using the backup information stored as an opportunity for the abnormal signal output from the first monitoring circuit and the restoration processing cannot restore the normal state, the second monitoring circuit further outputs the information. A gaming machine that is initialized when an abnormal signal is given.