|
US6519754B1
(en)
*
|
1999-05-17 |
2003-02-11 |
Synplicity, Inc. |
Methods and apparatuses for designing integrated circuits
|
|
US6691286B1
(en)
*
|
2000-10-31 |
2004-02-10 |
Synplicity, Inc. |
Methods and apparatuses for checking equivalence of circuits
|
|
US6801884B2
(en)
*
|
2001-02-09 |
2004-10-05 |
Hewlett-Packard Development Company, L.P. |
Method and apparatus for traversing net connectivity through design hierarchy
|
|
JP2003030269A
(ja)
*
|
2001-05-16 |
2003-01-31 |
Internatl Business Mach Corp <Ibm> |
メタモデルを用いた単一マイクロプロセッサ上の並列シミュレーションのための方法
|
|
US7082104B2
(en)
*
|
2001-05-18 |
2006-07-25 |
Intel Corporation |
Network device switch
|
|
US6807651B2
(en)
|
2001-06-15 |
2004-10-19 |
Cadence Design Systems, Inc. |
Procedure for optimizing mergeability and datapath widths of data flow graphs
|
|
US7093224B2
(en)
|
2001-08-28 |
2006-08-15 |
Intel Corporation |
Model-based logic design
|
|
US7073156B2
(en)
*
|
2001-08-29 |
2006-07-04 |
Intel Corporation |
Gate estimation process and method
|
|
US20030046051A1
(en)
*
|
2001-08-29 |
2003-03-06 |
Wheeler William R. |
Unified design parameter dependency management method and apparatus
|
|
US7107201B2
(en)
*
|
2001-08-29 |
2006-09-12 |
Intel Corporation |
Simulating a logic design
|
|
US7130784B2
(en)
*
|
2001-08-29 |
2006-10-31 |
Intel Corporation |
Logic simulation
|
|
US6983427B2
(en)
*
|
2001-08-29 |
2006-01-03 |
Intel Corporation |
Generating a logic design
|
|
US20030046054A1
(en)
*
|
2001-08-29 |
2003-03-06 |
Wheeler William R. |
Providing modeling instrumentation with an application programming interface to a GUI application
|
|
US6859913B2
(en)
*
|
2001-08-29 |
2005-02-22 |
Intel Corporation |
Representing a simulation model using a hardware configuration database
|
|
US7197724B2
(en)
*
|
2002-01-17 |
2007-03-27 |
Intel Corporation |
Modeling a logic design
|
|
US20030145311A1
(en)
*
|
2002-01-25 |
2003-07-31 |
Wheeler William R. |
Generating simulation code
|
|
FR2836734B1
(fr)
*
|
2002-03-01 |
2004-07-02 |
Prosilog S A |
Procede d'extraction de la topologie d'un systeme a partir de sa description textuelle
|
|
US6848084B1
(en)
*
|
2002-07-02 |
2005-01-25 |
Cadence Design Systems, Inc. |
Method and apparatus for verification of memories at multiple abstraction levels
|
|
US7155708B2
(en)
*
|
2002-10-31 |
2006-12-26 |
Src Computers, Inc. |
Debugging and performance profiling using control-dataflow graph representations with reconfigurable hardware emulation
|
|
US6983456B2
(en)
*
|
2002-10-31 |
2006-01-03 |
Src Computers, Inc. |
Process for converting programs in high-level programming languages to a unified executable for hybrid computing platforms
|
|
US7627842B1
(en)
|
2003-06-03 |
2009-12-01 |
Cadence Design Systems, Inc. |
Method and system for verification of circuits with encoded signals
|
|
JP4414690B2
(ja)
*
|
2003-07-14 |
2010-02-10 |
株式会社日立ハイテクノロジーズ |
半導体製造システム
|
|
US7584460B2
(en)
*
|
2003-07-22 |
2009-09-01 |
Lsi Corporation |
Process and apparatus for abstracting IC design files
|
|
US7100134B2
(en)
*
|
2003-08-18 |
2006-08-29 |
Aprio Technologies, Inc. |
Method and platform for integrated physical verifications and manufacturing enhancements
|
|
JP4183182B2
(ja)
*
|
2003-08-22 |
2008-11-19 |
株式会社リコー |
設計支援装置および設計支援方法
|
|
US7493492B2
(en)
*
|
2004-04-17 |
2009-02-17 |
International Business Machines Corporation |
Limiting access to publicly available object-oriented interfaces via password arguments
|
|
JP2006079447A
(ja)
*
|
2004-09-10 |
2006-03-23 |
Fujitsu Ltd |
集積回路設計支援装置、集積回路設計支援方法及び集積回路設計支援プログラム
|
|
US7155688B2
(en)
*
|
2004-11-17 |
2006-12-26 |
Lsi Logic Corporation |
Memory generation and placement
|
|
US7509599B1
(en)
*
|
2004-12-10 |
2009-03-24 |
Synopsys, Inc |
Method and apparatus for performing formal verification using data-flow graphs
|
|
EP1736905A3
(en)
*
|
2005-06-21 |
2007-09-05 |
Nvidia Corporation |
Building integrated circuits using logical units
|
|
US7483823B2
(en)
|
2005-06-21 |
2009-01-27 |
Nvidia Corporation |
Building integrated circuits using logical units
|
|
US7363610B2
(en)
*
|
2005-06-21 |
2008-04-22 |
Nvidia Corporation |
Building integrated circuits using a common database
|
|
US7191412B1
(en)
*
|
2005-09-28 |
2007-03-13 |
Xilinx, Inc. |
Method and apparatus for processing a circuit description for logic simulation
|
|
US7392492B2
(en)
*
|
2005-09-30 |
2008-06-24 |
Rambus Inc. |
Multi-format consistency checking tool
|
|
US7424687B2
(en)
*
|
2005-11-16 |
2008-09-09 |
Lsi Corporation |
Method and apparatus for mapping design memories to integrated circuit layout
|
|
US8653857B2
(en)
|
2006-03-09 |
2014-02-18 |
Tela Innovations, Inc. |
Circuitry and layouts for XOR and XNOR logic
|
|
US9035359B2
(en)
|
2006-03-09 |
2015-05-19 |
Tela Innovations, Inc. |
Semiconductor chip including region including linear-shaped conductive structures forming gate electrodes and having electrical connection areas arranged relative to inner region between transistors of different types and associated methods
|
|
US8225261B2
(en)
*
|
2006-03-09 |
2012-07-17 |
Tela Innovations, Inc. |
Methods for defining contact grid in dynamic array architecture
|
|
US7956421B2
(en)
|
2008-03-13 |
2011-06-07 |
Tela Innovations, Inc. |
Cross-coupled transistor layouts in restricted gate level layout architecture
|
|
US8658542B2
(en)
|
2006-03-09 |
2014-02-25 |
Tela Innovations, Inc. |
Coarse grid design methods and structures
|
|
US8245180B2
(en)
*
|
2006-03-09 |
2012-08-14 |
Tela Innovations, Inc. |
Methods for defining and using co-optimized nanopatterns for integrated circuit design and apparatus implementing same
|
|
US8541879B2
(en)
|
2007-12-13 |
2013-09-24 |
Tela Innovations, Inc. |
Super-self-aligned contacts and method for making the same
|
|
US9009641B2
(en)
|
2006-03-09 |
2015-04-14 |
Tela Innovations, Inc. |
Circuits with linear finfet structures
|
|
US9563733B2
(en)
|
2009-05-06 |
2017-02-07 |
Tela Innovations, Inc. |
Cell circuit and layout with linear finfet structures
|
|
US7763534B2
(en)
*
|
2007-10-26 |
2010-07-27 |
Tela Innovations, Inc. |
Methods, structures and designs for self-aligning local interconnects used in integrated circuits
|
|
US8448102B2
(en)
|
2006-03-09 |
2013-05-21 |
Tela Innovations, Inc. |
Optimizing layout of irregular structures in regular layout context
|
|
US9230910B2
(en)
|
2006-03-09 |
2016-01-05 |
Tela Innovations, Inc. |
Oversized contacts and vias in layout defined by linearly constrained topology
|
|
US8247846B2
(en)
*
|
2006-03-09 |
2012-08-21 |
Tela Innovations, Inc. |
Oversized contacts and vias in semiconductor chip defined by linearly constrained topology
|
|
US8839175B2
(en)
|
2006-03-09 |
2014-09-16 |
Tela Innovations, Inc. |
Scalable meta-data objects
|
|
US7932545B2
(en)
|
2006-03-09 |
2011-04-26 |
Tela Innovations, Inc. |
Semiconductor device and associated layouts including gate electrode level region having arrangement of six linear conductive segments with side-to-side spacing less than 360 nanometers
|
|
US7446352B2
(en)
*
|
2006-03-09 |
2008-11-04 |
Tela Innovations, Inc. |
Dynamic array architecture
|
|
US7943967B2
(en)
*
|
2006-03-09 |
2011-05-17 |
Tela Innovations, Inc. |
Semiconductor device and associated layouts including diffusion contact placement restriction based on relation to linear conductive segments
|
|
US8225239B2
(en)
*
|
2006-03-09 |
2012-07-17 |
Tela Innovations, Inc. |
Methods for defining and utilizing sub-resolution features in linear topology
|
|
US8302042B2
(en)
*
|
2006-07-24 |
2012-10-30 |
Oasys Design Systems |
Generating a convergent circuit design from a functional description using entities having access to the functional description and to physical design information
|
|
US7979829B2
(en)
|
2007-02-20 |
2011-07-12 |
Tela Innovations, Inc. |
Integrated circuit cell library with cell-level process compensation technique (PCT) application and associated methods
|
|
US8286107B2
(en)
*
|
2007-02-20 |
2012-10-09 |
Tela Innovations, Inc. |
Methods and systems for process compensation technique acceleration
|
|
US7888705B2
(en)
*
|
2007-08-02 |
2011-02-15 |
Tela Innovations, Inc. |
Methods for defining dynamic array section with manufacturing assurance halo and apparatus implementing the same
|
|
US8667443B2
(en)
|
2007-03-05 |
2014-03-04 |
Tela Innovations, Inc. |
Integrated circuit cell library for multiple patterning
|
|
US8453094B2
(en)
|
2008-01-31 |
2013-05-28 |
Tela Innovations, Inc. |
Enforcement of semiconductor structure regularity for localized transistors and interconnect
|
|
US7939443B2
(en)
|
2008-03-27 |
2011-05-10 |
Tela Innovations, Inc. |
Methods for multi-wire routing and apparatus implementing same
|
|
KR101903975B1
(ko)
*
|
2008-07-16 |
2018-10-04 |
텔라 이노베이션스, 인코포레이티드 |
동적 어레이 아키텍쳐에서의 셀 페이징과 배치를 위한 방법 및 그 구현
|
|
US9122832B2
(en)
*
|
2008-08-01 |
2015-09-01 |
Tela Innovations, Inc. |
Methods for controlling microloading variation in semiconductor wafer layout and fabrication
|
|
US9489477B2
(en)
|
2008-09-24 |
2016-11-08 |
Synopsys, Inc. |
Method and apparatus for word-level netlist reduction and verification using same
|
|
US8104000B2
(en)
*
|
2008-10-27 |
2012-01-24 |
Synopsys, Inc. |
Method and apparatus for memory abstraction and for word level net list reduction and verification using same
|
|
US8136063B2
(en)
*
|
2008-11-14 |
2012-03-13 |
Synopsys, Inc. |
Unfolding algorithm in multirate system folding
|
|
US8661392B2
(en)
*
|
2009-10-13 |
2014-02-25 |
Tela Innovations, Inc. |
Methods for cell boundary encroachment and layouts implementing the Same
|
|
US9159627B2
(en)
|
2010-11-12 |
2015-10-13 |
Tela Innovations, Inc. |
Methods for linewidth modification and apparatus implementing the same
|
|
WO2014108737A1
(en)
*
|
2013-01-08 |
2014-07-17 |
Freescale Semiconductor, Inc. |
Method and apparatus for performing logic synthesis
|
|
CN107967704A
(zh)
*
|
2016-10-20 |
2018-04-27 |
上海复旦微电子集团股份有限公司 |
一种fpga芯片版图连线显示方法
|
|
US10755017B2
(en)
|
2018-07-12 |
2020-08-25 |
International Business Machines Corporation |
Cell placement in a circuit with shared inputs and outputs
|
|
US10742218B2
(en)
|
2018-07-23 |
2020-08-11 |
International Business Machines Corpoartion |
Vertical transport logic circuit cell with shared pitch
|
|
US10733341B1
(en)
*
|
2019-03-27 |
2020-08-04 |
Architecture Technology Corporation |
Version control of an integrated circuit design and tracking of pre-fabrication, fabrication, and post-fabrication processes
|
|
US11087059B2
(en)
*
|
2019-06-22 |
2021-08-10 |
Synopsys, Inc. |
Clock domain crossing verification of integrated circuit design using parameter inference
|
|
US12175191B2
(en)
*
|
2020-11-30 |
2024-12-24 |
Synopsys, Inc. |
Automated translation of design specifications of electronic circuits
|
|
WO2025127015A1
(ja)
*
|
2023-12-11 |
2025-06-19 |
株式会社Fsmc |
設計支援システム、設計支援装置および設計支援方法
|