JP2002524881A - 炭化ケイ素接合型電界効果トランジスタ - Google Patents
炭化ケイ素接合型電界効果トランジスタInfo
- Publication number
- JP2002524881A JP2002524881A JP2000569455A JP2000569455A JP2002524881A JP 2002524881 A JP2002524881 A JP 2002524881A JP 2000569455 A JP2000569455 A JP 2000569455A JP 2000569455 A JP2000569455 A JP 2000569455A JP 2002524881 A JP2002524881 A JP 2002524881A
- Authority
- JP
- Japan
- Prior art keywords
- silicon carbide
- field effect
- effect transistor
- conductive
- trench
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 title claims abstract description 75
- 229910010271 silicon carbide Inorganic materials 0.000 title claims abstract description 75
- 230000005669 field effect Effects 0.000 title claims abstract description 27
- 239000000758 substrate Substances 0.000 claims description 9
- 239000002800 charge carrier Substances 0.000 claims description 3
- 230000008021 deposition Effects 0.000 claims description 3
- 238000005468 ion implantation Methods 0.000 claims description 3
- 230000000149 penetrating effect Effects 0.000 claims 2
- 229910052782 aluminium Inorganic materials 0.000 description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 5
- 238000000407 epitaxy Methods 0.000 description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 4
- 238000000151 deposition Methods 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- 229910001030 Iron–nickel alloy Inorganic materials 0.000 description 1
- 229910000990 Ni alloy Inorganic materials 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910000889 permalloy Inorganic materials 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
- H01L21/048—Making electrodes
- H01L21/0485—Ohmic electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/1608—Silicon carbide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7838—Field effect transistors with field effect produced by an insulated gate without inversion channel, e.g. buried channel lateral MISFETs, normally-on lateral MISFETs, depletion-mode lateral MISFETs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Manufacturing & Machinery (AREA)
- Composite Materials (AREA)
- Junction Field-Effect Transistors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
有する炭化ケイ素接合型電界効果トランジスタ(FET)に関し、この電界効果
トランジスタはp導電層とn導電層を有する。
ード回路に使用することができる。この種の電界効果トランジスタは比較的安価
に製造できるという利点を有する。なぜならここでは、ドーピングを打ち込みに
より簡単に実行することができるからである。
せず、その集積度が炭化ケイ素体の裏面にあるドレイン電極のため問題であった
。
供することであり、かつ簡単に製造でき、大きな高電圧耐力を有するようにする
。
て本発明により、 解決される。
ピング濃度が1013電荷担体/cm2を越えない。ソース電極およびゲート電極に
対するトレンチがドレイン電極に対するトレンチを少なくとも部分的に取り囲む
と有利である。n導電性炭化ケイ素層とp導電性炭化ケイ素層とは、炭化ケイ素
基体へのイオン打ち込みとエピタキシャルデポジットにより形成することができ
る。
ケイ素接合型電界効果トランジスタを提供するものである。
ットされ、これがエピタクシー構造体を形成する。このエピタクシー構造体には
対でn導電性とp導電性の炭化ケイ素層が包含され、これらはn導電性ないしp
導電性のドープ物質、例えば窒素ないしボロンおよび/またはアルミニウムのイ
オン打ち込みによって形成される。このエピタクシー構造体の最上層はドープさ
れないままである。
いトレンチは次に、ソース電極およびドレイン電極に対しては例えばn+ドープ
された炭化ケイ素により、ゲート電極に対しては絶縁層のデポジットの後にp+
ドープされた炭化ケイ素によりエピタキシャルに充填される。ソース、ドレイン
およびゲートに対するトレンチにこのように被着されたn+導電性およびp+導電
性の炭化ケイ素層は続いて、最上のドープされない炭化ケイ素層までエッチバッ
クされ、このようにして構造化される。
電極を取り囲むような幾何形状を選択することができる。
通常のように行うことができる。有利には例えばアルミニウムまたは多結晶シリ
コンからなる導体路を使用することができる。
m-2を越えてはならない。この上限によって、ドレイン電圧を印加した際にp導
電性およびn導電性の炭化ケイ素層が、破壊が生じるより前に側方ないし横方向
に排除され、これにより炭化ケイ素接合型電界効果トランジスタは高い破壊耐力
を特徴とする。言い替えれば本発明の炭化ケイ素接合型電界効果トランジスタは
小さいスイッチオン抵抗においても高い破壊電圧を有する。
層が対でエピタクシー構造体に埋め込まれている。
図である。
平面図である。
炭化ケイ素からなるエピタクシー構造体2が設けられており、この構造体にはp
導電性の炭化ケイ素層3とn導電性の炭化ケイ素層4が対で埋め込まれている。
このp導電性の炭化ケイ素層3とn導電性の炭化ケイ素層4は、1013電荷担体
cm-2を越えないドーピング濃度を有する。これにより、製造した炭化ケイ素接
合型電界効果トランジスタにドレイン電圧を印加する際、破壊が発生する前に層
3,4が横方向ないしラテラル方向に排除される。このようにして接合トレンチ
電界効果トランジスタと同じように、スイッチオン抵抗が小さくても高い破壊電
圧が達成される。
体1に段階的にエピタキシャル層を被着し、このときに層3に対してはボロンお
よび/またはアルミニウムによりイオン打ち込みを行い、層4に対しては窒素に
よりイオン打ち込みをそれぞれ行うのである。
体にさらに最上のドープされない層(図2参照)を被着した後、このようにして
得られた構造体に、ソース、ドレインおよびゲートに対する細いトレンチを炭化
ケイ素基体1までエッチングする。このトレンチは、ソース電極5ないしドレイ
ン電極6に対してはn+ドープされた炭化ケイ素により充填される。ゲート電極
7に対するトレンチは、まずその側壁に絶縁層8が設けられ、次にその内室がp
+ドープされた炭化ケイ素により充填される。絶縁層8は熱的酸化により設ける
ことができる。ソース電極、ドレイン電極およびゲート電極に対するトレンチを
このように充填することはエピタキシャルに行うことができる。トレンチに充填
されたn+導電性層ないしp+導電性層の上側は、最上のドープされない炭化ケイ
素層に達するまでエッチバックされるか、または研磨される。ソースS、ドレイ
ンDおよびゲートGに対して例えばアルミニウムからなる電極9,10,11を
設けた後に、図2に示した炭化ケイ素接合型電界効果トランジスタが存在する。
ここではソース電極9およびドレイン電極10を作製するために、スパッタリン
グまたは蒸着により被着された、有利にはニッケルまたはパーマロイ(NiFe
)からなる層を所望のレイアウト(例えば図3参照)に相応してエッチングする
こともでき、ゲート電極11に対しては有利にはNi−Al合金を使用する。こ
の金属化部は次に有利には980℃で熱処理され、続いてワイヤボンディングの
ために付加的に被着されたアルミニウムまたはハンダ可能な金属部(例えばNi
Ag)により強化される。
たこのような炭化ケイ素接合型電界効果トランジスタに対する可能なレイアウト
(平面図)を示す。ここでソース電極9とゲート電極11は、これらがドレイン
電極10を取り囲むように配置することができる。
層が対でエピタクシー構造体に埋め込まれている。
図である。
平面図である。
Claims (4)
- 【請求項1】 炭化ケイ素体(1,2)と、ソース電極、ドレイン電極およ
びゲート電極(5,6,7)とを有する炭化ケイ素接合型電界効果トランジスタ
であって、前記炭化ケイ素体にはp導電性層とn導電性層(3,4)とが設けら
れている形式の炭化ケイ素接合型電界効果トランジスタにおいて、 p導電性の炭化ケイ素層とn導電性の炭化ケイ素層(3,4)とは対でラテラ
ル方向に、炭化ケイ素体(1,2)の主表面に対して平行に当該炭化ケイ素体に
埋め込まれており、 ソース電極およびドレイン電極(5,6)は、一方の導電形式の炭化ケイ素が
強くドープされたトレンチからなり、 該トレンチは、p導電性およびn導電性の炭化ケイ素層(3,4)が主表面か
ら貫通されており、 ゲート電極(7)は、前記導電形式とは反対の導電形式の炭化ケイ素が強くド
ープされたトレンチからなり、 該トレンチは、p導電性およびn導電性の炭化ケイ素層(3,4)が主表面か
ら貫通されており、かつ当該トレンチの側壁には絶縁層(8)が設けられている
、 ことを特徴とする炭化ケイ素接合型電界効果トランジスタ。 - 【請求項2】 p導電性の炭化ケイ素層とn導電性の炭化ケイ素層(3,4
)のドーピング濃度は1013電荷担体/cm2を越えない、請求項1記載の炭化ケ
イ素接合型電界効果トランジスタ。 - 【請求項3】 ソース電極(5)およびゲート電極(7)に対するトレンチ
は、ドレイン電極(6)に対するトレンチを取り囲んでいる、請求項1または2
記載の炭化ケイ素接合型電界効果トランジスタ。 - 【請求項4】 n導電性とp導電性の炭化ケイ素層(3,4)は、イオン打
ち込みとエピタキシャルデポジットにより炭化ケイ素基体(1)の上に形成され
る、請求項1から3までのいずれか1項記載の炭化ケイ素接合型電界効果トラン
ジスタ。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE19839969A DE19839969C2 (de) | 1998-09-02 | 1998-09-02 | Siliziumcarbid-Junction-Feldeffekttransistor |
DE19839969.3 | 1998-09-02 | ||
PCT/DE1999/002755 WO2000014810A1 (de) | 1998-09-02 | 1999-09-01 | Siliziumcarbid-junction-feldeffekttransistor |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2002524881A true JP2002524881A (ja) | 2002-08-06 |
JP4049998B2 JP4049998B2 (ja) | 2008-02-20 |
Family
ID=7879549
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2000569455A Expired - Fee Related JP4049998B2 (ja) | 1998-09-02 | 1999-09-01 | 炭化ケイ素−電界効果トランジスタ |
Country Status (5)
Country | Link |
---|---|
US (1) | US6365919B1 (ja) |
EP (1) | EP1027735B1 (ja) |
JP (1) | JP4049998B2 (ja) |
DE (2) | DE19839969C2 (ja) |
WO (1) | WO2000014810A1 (ja) |
Families Citing this family (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6936849B1 (en) * | 1997-07-29 | 2005-08-30 | Micron Technology, Inc. | Silicon carbide gate transistor |
US7196929B1 (en) * | 1997-07-29 | 2007-03-27 | Micron Technology Inc | Method for operating a memory device having an amorphous silicon carbide gate insulator |
US6746893B1 (en) | 1997-07-29 | 2004-06-08 | Micron Technology, Inc. | Transistor with variable electron affinity gate and methods of fabrication and use |
US7154153B1 (en) * | 1997-07-29 | 2006-12-26 | Micron Technology, Inc. | Memory device |
US6794255B1 (en) | 1997-07-29 | 2004-09-21 | Micron Technology, Inc. | Carburized silicon gate insulators for integrated circuits |
US6031263A (en) * | 1997-07-29 | 2000-02-29 | Micron Technology, Inc. | DEAPROM and transistor with gallium nitride or gallium aluminum nitride gate |
WO2003006893A2 (en) | 2001-07-09 | 2003-01-23 | Elan Pharmaceuticals, Inc. | Methods of inhibiting amyloid toxicity |
DE10212863B4 (de) * | 2002-03-22 | 2006-06-08 | Siemens Ag | Ansteuerschaltung für einen Sperrschicht-Feldeffekttransistor |
DE10212869A1 (de) * | 2002-03-22 | 2003-09-18 | Siemens Ag | Ansteuerschaltung für einen Sperrschicht-Feldeffekttransistor |
TWI320571B (en) | 2002-09-12 | 2010-02-11 | Qs Semiconductor Australia Pty Ltd | Dynamic nonvolatile random access memory ne transistor cell and random access memory array |
DE10325748B4 (de) * | 2003-06-06 | 2008-10-02 | Infineon Technologies Ag | Sperrschicht-Feldeffekttransistor (JFET) mit Kompensationsstruktur und Feldstoppzone |
US20050012143A1 (en) * | 2003-06-24 | 2005-01-20 | Hideaki Tanaka | Semiconductor device and method of manufacturing the same |
US7138292B2 (en) * | 2003-09-10 | 2006-11-21 | Lsi Logic Corporation | Apparatus and method of manufacture for integrated circuit and CMOS device including epitaxially grown dielectric on silicon carbide |
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US3254280A (en) * | 1963-05-29 | 1966-05-31 | Westinghouse Electric Corp | Silicon carbide unipolar transistor |
US5465249A (en) * | 1991-11-26 | 1995-11-07 | Cree Research, Inc. | Nonvolatile random access memory device having transistor and capacitor made in silicon carbide substrate |
US5378642A (en) * | 1993-04-19 | 1995-01-03 | General Electric Company | Method of making a silicon carbide junction field effect transistor device for high temperature applications |
US5679966A (en) * | 1995-10-05 | 1997-10-21 | North Carolina State University | Depleted base transistor with high forward voltage blocking capability |
DE19644821C1 (de) * | 1996-10-29 | 1998-02-12 | Daimler Benz Ag | Steuerbare Halbleiterstruktur mit verbesserten Schalteigenschaften |
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- 1999-09-01 JP JP2000569455A patent/JP4049998B2/ja not_active Expired - Fee Related
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Also Published As
Publication number | Publication date |
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US6365919B1 (en) | 2002-04-02 |
DE19839969A1 (de) | 2000-03-16 |
WO2000014810A1 (de) | 2000-03-16 |
DE59913522D1 (de) | 2006-07-20 |
DE19839969C2 (de) | 2003-02-27 |
EP1027735A1 (de) | 2000-08-16 |
JP4049998B2 (ja) | 2008-02-20 |
EP1027735B1 (de) | 2006-06-07 |
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