JP2002523854A - 集積回路のビルトイン自己試験方法及びその装置 - Google Patents
集積回路のビルトイン自己試験方法及びその装置Info
- Publication number
- JP2002523854A JP2002523854A JP2000566851A JP2000566851A JP2002523854A JP 2002523854 A JP2002523854 A JP 2002523854A JP 2000566851 A JP2000566851 A JP 2000566851A JP 2000566851 A JP2000566851 A JP 2000566851A JP 2002523854 A JP2002523854 A JP 2002523854A
- Authority
- JP
- Japan
- Prior art keywords
- memory
- test signal
- semiconductor device
- input circuit
- row
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010998 test method Methods 0.000 title claims description 5
- 230000015654 memory Effects 0.000 claims abstract description 218
- 238000012360 testing method Methods 0.000 claims abstract description 80
- 238000000034 method Methods 0.000 claims description 35
- 239000004065 semiconductor Substances 0.000 claims description 23
- 239000011159 matrix material Substances 0.000 claims description 8
- 230000008569 process Effects 0.000 claims description 4
- 230000006870 function Effects 0.000 abstract description 16
- 230000007704 transition Effects 0.000 abstract description 10
- 238000003672 processing method Methods 0.000 description 14
- 238000010586 diagram Methods 0.000 description 9
- 238000012937 correction Methods 0.000 description 7
- 238000005259 measurement Methods 0.000 description 5
- 238000013461 design Methods 0.000 description 3
- 238000001914 filtration Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000012546 transfer Methods 0.000 description 3
- 230000009471 action Effects 0.000 description 2
- 238000003491 array Methods 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 102200091804 rs104894738 Human genes 0.000 description 2
- 230000001360 synchronised effect Effects 0.000 description 2
- 239000013598 vector Substances 0.000 description 2
- 238000004458 analytical method Methods 0.000 description 1
- 238000013481 data capture Methods 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 238000010348 incorporation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000010899 nucleation Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000012552 review Methods 0.000 description 1
- 230000011218 segmentation Effects 0.000 description 1
- 238000007493 shaping process Methods 0.000 description 1
- 238000013519 translation Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
Landscapes
- For Increasing The Reliability Of Semiconductor Memories (AREA)
- Tests Of Electronic Circuits (AREA)
- Dram (AREA)
- Static Random-Access Memory (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/US1998/017298 WO2000011674A1 (en) | 1998-08-21 | 1998-08-21 | Method and apparatus for built-in self test of integrated circuits |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2002523854A true JP2002523854A (ja) | 2002-07-30 |
| JP2002523854A5 JP2002523854A5 (https=) | 2006-01-05 |
Family
ID=22267708
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2000566851A Pending JP2002523854A (ja) | 1998-08-21 | 1998-08-21 | 集積回路のビルトイン自己試験方法及びその装置 |
Country Status (4)
| Country | Link |
|---|---|
| EP (1) | EP1105876A4 (https=) |
| JP (1) | JP2002523854A (https=) |
| KR (1) | KR100589532B1 (https=) |
| WO (1) | WO2000011674A1 (https=) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006252702A (ja) * | 2005-03-11 | 2006-09-21 | Nec Electronics Corp | 半導体集積回路装置及びその検査方法 |
| JP2008065862A (ja) * | 2006-09-04 | 2008-03-21 | System Fabrication Technologies Inc | 半導体記憶装置 |
| JP2010033564A (ja) * | 2008-07-25 | 2010-02-12 | Internatl Business Mach Corp <Ibm> | キャッシュ・ディレクトリ内の実ページ番号ビットのテスト方法、装置、およびコンピュータ記録可能な媒体 |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6550034B1 (en) | 2000-02-17 | 2003-04-15 | Hewlett Packard Development Company, L.P. | Built-in self test for content addressable memory |
| US6658610B1 (en) * | 2000-09-25 | 2003-12-02 | International Business Machines Corporation | Compilable address magnitude comparator for memory array self-testing |
| KR101232195B1 (ko) * | 2011-02-25 | 2013-02-12 | 연세대학교 산학협력단 | 반도체 메모리 장치 테스트 방법 및 테스트 장치 |
Family Cites Families (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4817093A (en) * | 1987-06-18 | 1989-03-28 | International Business Machines Corporation | Method of partitioning, testing and diagnosing a VLSI multichip package and associated structure |
| US4965717A (en) * | 1988-12-09 | 1990-10-23 | Tandem Computers Incorporated | Multiple processor system having shared memory with private-write capability |
| US5258986A (en) * | 1990-09-19 | 1993-11-02 | Vlsi Technology, Inc. | Tightly coupled, low overhead RAM built-in self-test logic with particular applications for embedded memories |
| JPH0770240B2 (ja) * | 1990-12-27 | 1995-07-31 | 株式会社東芝 | 半導体集積回路 |
| JP3269117B2 (ja) * | 1992-05-26 | 2002-03-25 | 安藤電気株式会社 | 半導体メモリ用試験パターン発生器 |
| KR0141432B1 (ko) * | 1993-10-01 | 1998-07-15 | 기다오까 다까시 | 반도체 기억장치 |
| US5617531A (en) * | 1993-11-02 | 1997-04-01 | Motorola, Inc. | Data Processor having a built-in internal self test controller for testing a plurality of memories internal to the data processor |
| US5661732A (en) * | 1995-05-31 | 1997-08-26 | International Business Machines Corporation | Programmable ABIST microprocessor for testing arrays with two logical views |
| US5659551A (en) * | 1995-05-31 | 1997-08-19 | International Business Machines Corporation | Programmable computer system element with built-in self test method and apparatus for repair during power-on |
| US5615159A (en) * | 1995-11-28 | 1997-03-25 | Micron Quantum Devices, Inc. | Memory system with non-volatile data storage unit and method of initializing same |
| US5805789A (en) * | 1995-12-14 | 1998-09-08 | International Business Machines Corporation | Programmable computer system element with built-in self test method and apparatus for repair during power-on |
-
1998
- 1998-08-21 JP JP2000566851A patent/JP2002523854A/ja active Pending
- 1998-08-21 EP EP98945762A patent/EP1105876A4/en not_active Withdrawn
- 1998-08-21 WO PCT/US1998/017298 patent/WO2000011674A1/en not_active Ceased
- 1998-08-21 KR KR1020007014379A patent/KR100589532B1/ko not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006252702A (ja) * | 2005-03-11 | 2006-09-21 | Nec Electronics Corp | 半導体集積回路装置及びその検査方法 |
| JP2008065862A (ja) * | 2006-09-04 | 2008-03-21 | System Fabrication Technologies Inc | 半導体記憶装置 |
| JP2010033564A (ja) * | 2008-07-25 | 2010-02-12 | Internatl Business Mach Corp <Ibm> | キャッシュ・ディレクトリ内の実ページ番号ビットのテスト方法、装置、およびコンピュータ記録可能な媒体 |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20010052985A (ko) | 2001-06-25 |
| EP1105876A4 (en) | 2003-09-17 |
| KR100589532B1 (ko) | 2006-06-13 |
| WO2000011674A1 (en) | 2000-03-02 |
| EP1105876A1 (en) | 2001-06-13 |
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| KR100771263B1 (ko) | 메모리 어레이 테스트 방법과 이를 구현하기 위해 배열된메모리 기반 디바이스 |
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Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20050721 |
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