JP2002517080A5 - - Google Patents
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- Publication number
- JP2002517080A5 JP2002517080A5 JP2000531862A JP2000531862A JP2002517080A5 JP 2002517080 A5 JP2002517080 A5 JP 2002517080A5 JP 2000531862 A JP2000531862 A JP 2000531862A JP 2000531862 A JP2000531862 A JP 2000531862A JP 2002517080 A5 JP2002517080 A5 JP 2002517080A5
- Authority
- JP
- Japan
- Prior art keywords
- connection point
- layout
- same
- connection
- joining
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000758 substrate Substances 0.000 description 4
- 238000000034 method Methods 0.000 description 1
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US09/023,388 US6118669A (en) | 1998-02-13 | 1998-02-13 | Routing topology for identical connector point layouts on primary and secondary sides of a substrate |
| US09/023,388 | 1998-02-13 | ||
| PCT/US1999/001555 WO1999041770A2 (en) | 1998-02-13 | 1999-01-25 | Routing topology for identical connector point layouts on primary and secondary sides of a substrate |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2002517080A JP2002517080A (ja) | 2002-06-11 |
| JP2002517080A5 true JP2002517080A5 (enExample) | 2006-03-09 |
| JP4344088B2 JP4344088B2 (ja) | 2009-10-14 |
Family
ID=21814799
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2000531862A Expired - Fee Related JP4344088B2 (ja) | 1998-02-13 | 1999-01-25 | 基板の一次側と二次側における同一の接続点レイアウトのためのルーティングトポロジー |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US6118669A (enExample) |
| JP (1) | JP4344088B2 (enExample) |
| KR (1) | KR100347444B1 (enExample) |
| AU (1) | AU2342199A (enExample) |
| TW (1) | TW418420B (enExample) |
| WO (1) | WO1999041770A2 (enExample) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6347041B1 (en) * | 2000-01-21 | 2002-02-12 | Dell Usa, L.P. | Incremental phase correcting mechanisms for differential signals to decrease electromagnetic emissions |
| CN1211723C (zh) * | 2000-04-04 | 2005-07-20 | 胜开科技股份有限公司 | 计算机卡制作方法 |
| US6875930B2 (en) * | 2002-04-18 | 2005-04-05 | Hewlett-Packard Development Company, L.P. | Optimized conductor routing for multiple components on a printed circuit board |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0249463A (ja) * | 1988-05-27 | 1990-02-19 | Matsushita Electron Corp | 半導体装置 |
| JP2793378B2 (ja) * | 1991-03-28 | 1998-09-03 | 株式会社東芝 | セミカスタム半導体集積回路マクロセル設計法 |
| US5604710A (en) * | 1994-05-20 | 1997-02-18 | Mitsubishi Denki Kabushiki Kaisha | Arrangement of power supply and data input/output pads in semiconductor memory device |
| US5841686A (en) * | 1996-11-22 | 1998-11-24 | Ma Laboratories, Inc. | Dual-bank memory module with shared capacitors and R-C elements integrated into the module substrate |
| US5831890A (en) * | 1996-12-16 | 1998-11-03 | Sun Microsystems, Inc. | Single in-line memory module having on-board regulation circuits |
-
1998
- 1998-02-13 US US09/023,388 patent/US6118669A/en not_active Expired - Lifetime
-
1999
- 1999-01-25 JP JP2000531862A patent/JP4344088B2/ja not_active Expired - Fee Related
- 1999-01-25 WO PCT/US1999/001555 patent/WO1999041770A2/en not_active Ceased
- 1999-01-25 AU AU23421/99A patent/AU2342199A/en not_active Abandoned
- 1999-01-25 KR KR1020007008853A patent/KR100347444B1/ko not_active Expired - Fee Related
- 1999-04-03 TW TW088102277A patent/TW418420B/zh not_active IP Right Cessation
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