Classifications

• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K1/00—Printed circuits
  • H05K1/02—Details
  • H05K1/14—Structural association of two or more printed circuits
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C5/00—Details of stores covered by group G11C11/00
  • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
  • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K1/00—Printed circuits
  • H05K1/18—Printed circuits structurally associated with non-printed electric components
  • H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
  • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
  • H05K2201/10007—Types of components
  • H05K2201/10159—Memory
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
  • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
  • H05K2201/10431—Details of mounted components
  • H05K2201/10507—Involving several components
  • H05K2201/10545—Related components mounted on both sides of the PCB

Definitions

• the present invention relates to trace routing topologies and, more particularly, to topologies that allow for identical connection point layouts on primary and secondary sides of a substrate.
• processors such as microprocessors
• an off-chip cache chips sometimes called L2 caches
• the cache chip is mounted on a substrate such as a printed circuit board and is connected to processor core chip through a high speed bus.
• the Pentium® II processor manufactured by Intel Corporation includes a substrate to which a processor chip and a cache chip are connected.
• the substrate includes connector points that are mated with connector points on the processor chip and cache chip to connect the processor chip and cache chip to the substrate.
• the substrate includes multiple layers. Traces are connected to the connector points of the substrate to couple various ones of connectors points of one chip to various ones of connectors points of other chips. To avoid the traces coming into connector with each, the traces are routed in particular configurations. Traces can be routed through various layers, which are connected through vias, in order to avoid having traces contact each other.
• the substrate is connected to a connector, which may be attached to a motherboard, through goldfmgers on a single edge connector.
• a connector point on a single chip has been coupled to a connector point on more than one chip in the same relative layout position on the same side of a substrate through multiple branch traces, including those of substantially equal length from an intermediate connector point.
• a substrate such used in the Pentium®II processor includes multiple layers. Each layer adds complexity and expense. Further, the addition of vias adds complexity (for example by blocking trace routing channels) and expense.
• the invention includes a multilayered substrate.
• the substrate includes a primary side having a first group of connection points, including a first connection point, having a first layout to interface with a first chip.
• the substrate also includes a secondary side having a second group of connection points, including a second connection point, having a layout identical to the first layout, to interface with a second chip.
• the substrate also includes an intermediate connection point coupled to the first and second connection points through first and second branch traces each having substantially the same electrical length.
• FIG. 1 is a front view of a substrate including connection points.
• FIG. 2 is a back view of the substrate of FIG. 1.
• FIG. 3 is a schematic representation of trace connections between connections points of the substrate of FIG. 1.
• FIG. 4 is a simplified representation of a side view of the substrate of FIG. 1.
• FIG. 5 is a schematic representation of trace connections between connections points of the substrate of FIG. 1.
• FIG. 6 is a bottom view of a chip to be connected to connection points of FIG. 1 or FIG. 2.
• FIG. 7 is a side view of the chip of FIG. 6.
• a substrate 10 which may be a printed circuit board, includes a primary side 12 and a secondary side 14.
• Substrate 10 includes five groups of connection points: a group of connection points 18 and groups of connection point 22-1, 22-2, 22-3, and 22-4.
• the connection points may be pads on vias or other conductors.
• substrate 10 may be part of a processor that includes a processor chip that is connected to the group of connection points 18.
• the processor also includes four cache chips, each of which are connected to one of four groups of connection points 22-1, 22-2, 22-3, and 22-4.
• Each group of connection points has a layout.
• Chips also have a connection point layout.
• the connection points of chips may be pins, pads, or other conductors.
• connection point 30 of the group of connection points 18 connection points CPA-1 and CPB-1 of the group of connection points 22-1; connection points CPA-2 and CPB-2 of the group of connection points 22-2; connection points CPA-3 and CPB-3 of the group of connection points 22-3; connection points CPA-4 and CPB-4 of the group of connection points 22-4; and a connection point 32.
• Substrate 10 may include, for example, six groups of gold finger connections: 16A, 16B, 16C, 16D, 16E, and 16F.
• connection point 32 may be one of the gold finger connections or connected to one or more of the gold finger connections.
• Substrate 10 includes vias 34, 36, 44, and 46.
• the vias pass through each layer of substrate 10. In other embodiments, the vias do not extend through each layer.
• Vias 34, 36, 44, and 46 may be considered intermediate connection points. However, in the illustrated embodiment, vias 34, 36, 44, and 46 do not directly interface with chips, whereas connection points CPA-1, CPA-2, etc., do.
• a root trace 40 is coupled between connection point 30 and via 34.
• a root trace 42 is coupled between connection point 30 and via 36.
• Root trace 40 and 42 should have substantially same electrical length. Electrical length is the flight time. An equal physical length may provide an equal electrical length. A purpose for having substantially the same electrical length is to reduce timing tolerances for signals between chips. The extent to which the electrical lengths must be substantially the same depends at least in part on the tolerances, which vary with implementation. The extent may also depend on how closely other traces (described below) have substantially the same electrical length. Because connection point 30 is closer to via 34 than it is to via 36, root trace 40 may have a bend (e.g., a serpentine configuration, not illustrated in FIG. 3) to add extra physical length originating trace 40 to match the electrical length of root trace 42. Root trace 42 may also have bends. The various traces mentioned herein do not necessarily have to have a constant width.
• a branch trace BA1 is coupled between connection point CPA-1 and via 34.
• a branch trace BA2 is coupled between connection point CPA-2 and via 34.
• Branch traces BA1 and BA2 have substantially the same electrical length.
• a branch trace BA3 is coupled between connection point CPA-3 and via 36.
• a branch trace BA4 is coupled between connection point CPA-4 and via 36.
• Branch traces BA3 and BA4 have substantially the same electrical length.
• the vias do not have to extend completely through all layers.
• One or more of the traces may have a shape that is not straight (e.g., serpentine). Also, the width of the traces does not have to be uniform.
• substrate 10 includes N layers (not all of which are shown).
• FIG. 4 illustrates that root trace 40 may pass through an internal layer and connect to via 34 in an internal layer.
• root trace 40 may be replaced by multiple root traces or root/brand traces that pass through different layers and connect to different vias.
• Connector points CPA-1 and CPA-2 are displaced as suggested by FIGS. 1, 2, and 3 (i.e., one is not on top of the other).
• Connector points CPA-1 and CPA-2 could be pads connected to vias that extend through all layers (similar to via 34).
• FIG. 5 illustrates another type of trace routing topology which differs from that illustrated in FIG. 4.
• the trace routing topology includes a root trace 50 connected to root/branch traces 54 and 56. Root trace 50 may be connected to root/branch trace 54 and 56 through a via 52, which is a form of connection point.
• Branches BBl and BB2 are connected to via 44 and connection points CPB-1 and CPB-2, respectively.
• Branches BB3 and BB4 are connected to via 46 and connection points CPB-3 and CPB-4.
• Branches BBl and BB2 have substantially equal electrical lengths.
• Branches BB3 and BB4 have substantially equal electrical lengths.
• the trace routing topology of FIG. 4 includes a V topology, whereas the trace routing topology of FIG. 5 includes a Y topology.
• a root trace may be connected to more than two branch traces or root/branch traces.
• FIG. 6 illustrates a bottom view of a chip 70 and two connection points 74 and 76 which may be connected to connections points CPA-1 and CPB-1, or CPA-2 and CPB-2, or CPA-3 and CPB-3, or CPA-4 or CPB-4.
• FIG. 7 shows a side view of chip 70. Because of the trace topology, only one type of chip 70 is needed.
• Connection points to interface with chips may be a driving and/or receiving points.
• a substrate would be far simpler than substrate 10 if mirror image chips where used on each side. Indeed, the internal layer, traces and intermediate connections (34, 36, 44, and 46) illustrated in FIGS. 3, 4, and 5 of substrate 10 add complexity and expense to substrate 10. Accordingly, the invention is counter-intuitive.
• Substrate 10 may include well known materials and circuits, and materials and circuits that are not well known. Substrate 10 may be constructed according to well known techniques and processes, and also according to techniques and processes that are not well known. In a commercial implementation, there would be other connection points and groups of connection points which are not illustrated herein because they do not further add to the understanding of the invention and would clutter of the figures, tending to obscure the invention. The invention is not restricted to use in a processor, but may be used in connection with various other substrates, circuit boards, and chips.
• connection points do not have to be circular or spherical.
• borders of the boxes in the figures are for illustrative purposes and do not restrict the boundaries of the components, which may overlap.
• the relative size of the illustrative components does not to suggest actual relative sizes.
• the term "conductor” is intended to be interpreted broadly and includes devices that conduct although they also have some insulating properties. There may be intermediate components or conductors between the illustrated components and conductors.

Landscapes

• Engineering & Computer Science (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Production Of Multi-Layered Print Wiring Board (AREA)
• Combinations Of Printed Boards (AREA)
• Parts Printed On Printed Circuit Boards (AREA)
• Design And Manufacture Of Integrated Circuits (AREA)

Priority Applications (3)

Applications Claiming Priority (2)

Publications (2)

Family

ID=21814799

Family Applications (1)

Country Status (6)

Cited By (1)

Families Citing this family (2)

Family Cites Families (5)

• 1998
  • 1998-02-13 US US09/023,388 patent/US6118669A/en not_active Expired - Lifetime
• 1999
  • 1999-01-25 KR KR1020007008853A patent/KR100347444B1/ko not_active Expired - Fee Related
  • 1999-01-25 AU AU23421/99A patent/AU2342199A/en not_active Abandoned
  • 1999-01-25 JP JP2000531862A patent/JP4344088B2/ja not_active Expired - Fee Related
  • 1999-01-25 WO PCT/US1999/001555 patent/WO1999041770A2/en not_active Ceased
  • 1999-04-03 TW TW088102277A patent/TW418420B/zh not_active IP Right Cessation

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