JP2002508123A - マルチレイヤ・ネットワーク要素用のシステムおよび方法 - Google Patents
マルチレイヤ・ネットワーク要素用のシステムおよび方法Info
- Publication number
- JP2002508123A JP2002508123A JP50569999A JP50569999A JP2002508123A JP 2002508123 A JP2002508123 A JP 2002508123A JP 50569999 A JP50569999 A JP 50569999A JP 50569999 A JP50569999 A JP 50569999A JP 2002508123 A JP2002508123 A JP 2002508123A
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- packet
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Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L45/00—Routing or path finding of packets in data switching networks
- H04L45/74—Address processing for routing
- H04L45/742—Route cache; Operation thereof
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/60—Software-defined switches
- H04L49/602—Multilayer or multiprotocol switching, e.g. IP switching
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/20—Support for services
- H04L49/205—Quality of Service based
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/30—Peripheral units, e.g. input or output ports
- H04L49/3027—Output queuing
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/35—Switches specially adapted for specific applications
- H04L49/354—Switches specially adapted for specific applications for supporting virtual local area networks [VLAN]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Crystals, And After-Treatments Of Crystals (AREA)
Abstract
Description
Claims (1)
- 【特許請求の範囲】 1.少なくとも1つの入力ポートと少なくとも1つの出力ポートとを有するネッ トワーク要素において、入力ポートに入ったパケットを中継する方法であって、 (a)ヘッダを有するパケットをネットワークから入力ポートで受け取るステ ップと、 (b)ヘッダの第1の部分から第1のパケット情報を判定するステップと、 (c)ヘッダの第2の部分から第2のパケット情報を判定するステップと、 (d)第1のパケット情報と一致するエントリについてメモリ内のエントリを 同時にサーチするステップと、 (e)ステップ(d)で見つかった少なくとも1つのエントリがあれば、その エントリを使用して、第1のポート結果を決定するステップと、 (f)第2のパケット情報に関連するエントリについてメモリ内のエントリを 同時にサーチするステップと、 (g)第2のパケット情報に関連するエントリから1つのエントリを選択する ステップと、 (h)ステップ(g)の結果を使用して、第2のパケット情報中継情報を決定 するステップと、 (i)ステップ(e)およびステップ(h)の結果に基づいて、適切な出力ポ ートがもしあれば、その出力ポートを決定するステップと、 (j)パケットを適切な出力ポートへ中継するステップと を含む方法。 2.ステップ(g)が、最も適切であると判定された所定の重要性基準に基づく 層3情報に基づいてメモリ内のエントリを選択することを含む請求項1に記載の 方法。 3.ステップ(g)で一致するエントリがない場合、ステップ(i)が適切な出 力ポートを第1のポート結果として指定することを含む請求項2に記載の方法。 4.ステップ(i)が、ステップ(e)の結果を適切な出力ポートとして選択す るステップを含む請求項1に記載の方法。 5.ステップ(j)が、ステップ(h)の結果の一部を使用するステップを含む 請求項1に記載の方法。 6.メモリが第1のメモリおよび第2のメモリを備え、第1のメモリ内の少なく とも1つのエントリが、第2のメモリ内の対応するエントリを指し示すようにな される請求項1に記載のネットワーク要素。 7.第1のメモリが連想メモリである請求項6に記載のネットワーク要素。 8.ステップ(j)が、ステップ(h)の結果に従ってパケット・ヘッダを修正 することを含む請求項1に記載の方法。 9.ネットワーク上でパケットを中継するネットワーク要素であって、 (a)パケットを受け取る少なくとも1つの入力ポートと、 (b)パケットを調べ、第1のパケット情報および第2のパケット情報を判定 する処理論理と、 (c)内容の少なくとも一部が同時にサーチされ、サーチに基づく結果を出力 するメモリと、 (d)第1のパケット情報を使用してメモリをサーチし、メモリに第1のパケ ット情報結果を出力させる第1のパケット情報サーチ論理と、 (d)第2のパケット情報を使用してメモリをサーチし、メモリに第2のパケ ット情報結果を出力させる第2のパケット情報サーチ論理と、 (e)少なくとも1つの出力ポートと、 (f)第1のパケット情報結果および第2のパケット情報結果に基づく少なく とも1つの出力ポートがもしあれば、そのうちの適切な出力ポートへパケットを 中継するようにメモリに接続されたマージ論理と を備えるネットワーク要素。 10.メモリが第1のメモリおよび第2のメモリを備え、第1のメモリ内の少な くとも1つのエントリが、第2のメモリ内の対応するエントリを指し示し、第2 のメモリから結果を出力させる請求項9に記載のネットワーク要素。 11.第1のメモリが、その内容の少なくとも一部を同時にサーチされる請求項 10に記載のネットワーク要素。 12.第1のメモリが連想メモリである請求項11に記載のネットワーク要素。 13.ネットワーク上でパケットを中継するネットワーク要素であって、 (a)パケット・ヘッダを含むパケットを受け取るように構成された少なくと も1つの入力ポートと、 (b)パケット・ヘッダを調べ、第1のパケット情報および第2のパケット情 報を判定するように構成されたヘッダ処理論理と、 (c)メモリと、 (d)メモリに第1のパケット情報に基づいて第1のパケット情報結果を出力 させるように構成された第1のパケット情報サーチ論理と、 (d)メモリに第2のパケット情報に基づいて第2のパケット情報結果を出力 させるように構成された第2のパケット情報サーチ論理と、 (e)少なくとも1つの出力ポートと、 (f)第1のパケット情報結果および第2のパケット情報結果に基づく少なく とも1つの出力ポートがもしあれば、そのうちの適切な出力ポートへパケットを 中継するように構成された、メモリに接続されたマージ論理と を備えるネットワーク要素。 14.メモリが、その内容の少なくとも一部を同時にサーチされる請求項13に 記載のネットワーク要素。 15.第1のメモリが連想メモリである請求項14に記載のネットワーク要素。 16.メモリが第1のメモリおよび第2のメモリを備え、第1のメモリ内の各エ ントリが、第2のメモリ内の対応するエントリを指し示し、第2のメモリから結 果を出力させるようになされる請求項13に記載のネットワーク要素。 17.第1のメモリが、その内容の少なくとも一部を同時にサーチされる請求項 15に記載のネットワーク要素。 18.第1のメモリが連想メモリである請求項17に記載のネットワーク要素。 19.ネットワーク上でパケットを中継するネットワーク要素であって、 (a)パケット・ヘッダを含むパケットを受け取るように構成された少なくと も1つの入力ポートと、 (b)パケット・ヘッダから第1のパケット情報および第2のパケット情報を 判定するように構成された処理と、 (c)メモリと、 (d)第1のパケット情報結果を生成するために第1のパケット情報の関数と して求められた第1のアドレスと、第2のパケット情報結果を生成するために第 2のパケット情報の関数として求められた第2のアドレスとを使用してメモリに アクセスするように構成されたメモリ・アクセス論理と、 (e)少なくとも1つの出力ポートと、 (f)第1のパケット情報結果および第2のパケット情報結果に基づく少なく とも1つの出力ポートのうちの適切な出力ポートへパケットを中継するように構 成された、メモリに接続されたマージ論理と を備えるネットワーク要素。 20.メモリ・アクセス論理が連想メモリである請求項19に記載のネットワー ク要素。 21.メモリ・アクセス論理がハッシュ関数に基づく論理である請求項19に記 載のネットワーク要素。 22.少なくとも1つの入力ポートと少なくとも1つの出力ポートとを有するネ ットワーク要素に入るヘッダを有するパケットに関する中継決定を下す装置であ って、そのパケットはネットワーク要素の入力ポートに入り、ネットワーク要素 の適切な出力ポートから出る装置において、 ヘッダに基づいて、第1のサーチキー、第2のサーチキー、およびデフォルト 結果を出力するように構成されたヘッダ論理と、 ヘッダ論理から第1のサーチキーを受け取ったことに応答して第1の中継結果 を出力し、第2のサーチキーを受け取ったことに応答して第2の中継結果を出力 するように構成されたメモリと、 デフォルト結果、第1の中継結果、および第2の中継結果に応答して、適切な 出力ポートに関する情報を出力するように構成されたマージ論理と、 適切な出力ポートに関する情報に基づいて入力ポートからのパケットを適切な 出力ポートに向けて送るように構成された中継論理と を備える装置。 23.さらに、 パケット・メモリと、 パケットの一部を記憶するために使用できるメモリ内の位置を入力ポートに示 し、入力ポートからパケットを受け付け前記位置に記憶し、適切な出力ポートか ら要求があったときにその出力ポートへパケットを送るように構成されたパケッ ト・メモリ・マネージャとを備え、 中継論理が、前記位置を入力ポートから適切な出力ポートに渡すように構成さ れたポインタ・パッシング論理を含む請求項22に記載の装置。 24.入力ポートおよび出力ポートがパケット・ヘッダの内容を修正するように 構成される請求項22に記載の装置。 25.第1のパケット情報にVLAN情報が含まれ、ステップ(e)が、VLA N情報のみに一致するエントリを使用することを含む請求項1に記載の方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/885,559 US6081522A (en) | 1997-06-30 | 1997-06-30 | System and method for a multi-layer network element |
US08/885,559 | 1997-06-30 | ||
PCT/US1998/013177 WO1999000935A1 (en) | 1997-06-30 | 1998-06-24 | A system and method for a multi-layer network element |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2002508123A true JP2002508123A (ja) | 2002-03-12 |
JP4076586B2 JP4076586B2 (ja) | 2008-04-16 |
Family
ID=25387189
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP50569999A Expired - Lifetime JP4076586B2 (ja) | 1997-06-30 | 1998-06-24 | マルチレイヤ・ネットワーク要素用のシステムおよび方法 |
Country Status (6)
Country | Link |
---|---|
US (1) | US6081522A (ja) |
EP (1) | EP1021889B1 (ja) |
JP (1) | JP4076586B2 (ja) |
AT (1) | ATE403301T1 (ja) |
DE (1) | DE69839811D1 (ja) |
WO (1) | WO1999000935A1 (ja) |
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EP1021889A4 (en) | 2006-03-22 |
JP4076586B2 (ja) | 2008-04-16 |
ATE403301T1 (de) | 2008-08-15 |
DE69839811D1 (de) | 2008-09-11 |
WO1999000935A1 (en) | 1999-01-07 |
EP1021889A1 (en) | 2000-07-26 |
US6081522A (en) | 2000-06-27 |
EP1021889B1 (en) | 2008-07-30 |
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