JP2002343978A - Silicon carbide semiconductor device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce on-state resistance in a silicon carbide semiconductor device provided with a planar-type J-FET. SOLUTION: In a surface region of an n<-> type epitaxial layer 2, a p<+> type region 4a is formed at a specified distance away from a first gate region 3. On the surface of a channel layer 5, a p<+> type epitaxial layer 4b is formed, and a p<+> type contact region 4c is so extended as to connect the p<+> type epitaxial layer 4b and the p<+> type region 4a. The p<+> type contact region 4a, the p<+> type epitaxial layer 4b, and the p<+> type contact region 4c constitute a second gate region 4. Due to this structure, the channel layer 5 and a part of the n<-> type epitaxial layer 2 which is located between the first and second gate regions 3 and 4 serve for a channel, making the total distance L of the length of the channel layer 5 and that of the part of the n<-> type epitaxial layer 2 which is located between the first and second gate regions 3 and 4 nearly equal to a channel length of a conventional J-FET. Consequently, a J-FET resistance component can be eliminated, thus reducing the on-state resistance.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a silicon carbide (hereinafter referred to as "silicon carbide").
The present invention relates to a semiconductor device (referred to as SiC) and a method of manufacturing the same, and is particularly suitably applied to a J-FET.

[0002]

2. Description of the Related Art FIG.
A cross-sectional configuration of a planar J-FET is shown as an example of an iC semiconductor device. As shown in FIG. 9, the n-channel type J-FET is formed using a substrate obtained by growing an n ⁻ -type epi layer J2 on an n ⁺ -type substrate J1 made of SiC. A p-type first gate region J3 is formed in a surface portion of the n ⁻ -type epi layer J2. Then, the first base region J3
Including the upper part, a channel layer J4 is formed on the n ⁻ -type epi layer J2. The first of the channel layers J4
An n ⁺ type source region J5 is formed in a region located above the base region J3. Also, the first gate region J
3 so as to overlap with a portion extending so as to protrude beyond the n ⁺ type source region J5.
On the surface of No. 4, a p-type second gate region J6 is formed. Then, first and second gate electrodes J7 and J8 are formed so as to be in contact with the first and second gate regions J3 and J6, and a source electrode J9 is formed so as to be in contact with the n ⁺ type source region J5. Further, a drain electrode J10 is formed so as to be in contact with the n ⁺ type substrate J1, and the drain electrode J10 shown in FIG.
An FET is configured.

In the case of a J-FET having such a configuration, the channel layer J4 between the first and second gate electrodes J7 and J8 is set as a channel, and the channel layer J4 is connected to the first and second gate regions J3 and J6. The channel width is controlled by the depletion layer extending toward
It operates by passing a current between the drains.

[0004]

In the case of a planar type J-FET having the above structure, a J-FET having a trench structure is used.
This has the advantage that a higher breakdown voltage can be obtained and the manufacturing process can be simplified.

However, in the case of a planar type J-FET, there is a problem that the resistance is increased by the J-FET resistance component because the J-FET resistance component is present as compared with the trench structure J-FET. The ratio of the J-FET resistance component to the on-resistance is very high, for example, about 1/4.

In view of the above, the present invention provides a planar type J
In a silicon carbide semiconductor device including an FET, an object is to provide a structure capable of reducing on-resistance and a manufacturing method thereof.

[0007]

According to the present invention, the second gate region (4) has a depth of the channel layer (5) and the depth of the semiconductor layer (2). Part (4) extending in the depth direction.
a, 4c) and the first gate region (3), wherein a channel is formed by a semiconductor layer sandwiched between the first gate region (3) and the first gate region (3).

As described above, by using the portion of the channel layer and the semiconductor layer located between the first and second gate regions as a channel, the J-FET resistance component can be eliminated, and the on-resistance can be reduced. Can be planned.

For example, as set forth in claim 2, in the surface portion of the semiconductor layer, the first region (4a) of the second conductivity type formed at a position different from the first gate region, and the upper portion of the channel layer. Alternatively, in the surface layer portion of the channel layer, a second conductive type second layer formed so as to include a portion facing the first gate region.
The second gate region can be configured to include the region (4b) and the third region (4c) of the second conductivity type formed to connect the first region and the second region.

[0010] The third aspect of the invention is characterized in that the first region or the third region is made deeper than the first gate region. With this configuration, breakdown can occur at the bottom of the first region or the third region. As a result, the surge withstand capability can be improved.

According to a fifth aspect of the present invention, the first region (4b) of the second conductivity type is formed on the channel layer or in the surface layer of the channel layer so as to include a portion facing the first gate region. ) And a second region (4c) extending from the first region toward the semiconductor layer to form a second gate region. In this case, as described in claim 6, if the second region is made deeper than the first gate region, the same effect as in claim 3 can be obtained.

According to the present invention, a portion of the surface layer portion of the semiconductor layer (2) located below the second gate region (4) is provided from the first gate region (3) to the semiconductor substrate (1). ) Of the second conductivity type at a predetermined interval in the planar direction of the third conductivity type.
A gate region (15) is formed. In this manner, by forming the third gate region, a portion of the channel layer and the semiconductor layer located between the second and third gate regions can function as a channel. Thereby, the J-FET resistance component can be eliminated, and the on-resistance can be reduced.

Also in this case, the third gate region is made deeper than the first gate region, as described in claim 8.
The same effect as the third aspect can be obtained.

The invention according to claims 9 to 17 relates to a method for manufacturing a silicon carbide semiconductor device according to claims 1 to 8. By these manufacturing methods, the silicon carbide semiconductor device according to claims 1 to 8 can be manufactured.

In this case, if the step of forming the first region (4a) and the step of forming the first gate region (3) are performed simultaneously, the manufacturing process can be simplified. Can be achieved.

The reference numerals in parentheses of the above means indicate the correspondence with specific means described in the embodiments described later.

[0017]

(First Embodiment) FIG. 1 shows a cross-sectional structure of a double gate drive type n-channel J-FET as a silicon carbide semiconductor device according to a first embodiment of the present invention. Hereinafter, the configuration of the J-FET will be described with reference to FIG.

FIG. 1 shows a cross-sectional structure of one cell of a J-FET. N ⁺ type substrate 1 made of silicon carbide has an upper surface as a main surface and a lower surface opposite to the main surface as a back surface. Dopant concentration of the n ⁺ -type substrate 1, for example, a 1 × 10 ¹⁹ cm ^-3, on the on the main surface of the n ⁺ -type substrate 1, a lower dopant concentration than the substrate 1 (e.g. 2
An n ⁻ -type epi layer 2 made of silicon carbide having a ^{density of} × 10 ¹⁶ cm ⁻³ ) is epitaxially grown.

N^-Region in the surface layer portion of the mold epi layer 2
Has a dopant concentration of 1 × 10¹⁸cm^-3Composed of
Done p⁺The first gate region 3 made of a mold layer⁺Type area
(First region) 4a and n⁺A predetermined distance in the plane direction of the mold substrate 1
The first gate regions 3 and
And p⁺N on the mold region 4a^-N on the surface of the
^-Channel layer 5 composed of a mold layer is epitaxially grown
Have been. The dopant concentration of this channel layer 5 is, for example,
For example, 1 × 10¹⁶cm^-3It has become.

An n ⁺ -type source region 6 is formed in a region of the surface layer of the channel layer 5 located above the first gate region 3. Further, on the surface of the channel layer 5, the first
A p ⁺ -type epi layer (second region) 4b is formed in a portion located above the gate region 3 and the p ⁺ -type region 4a, and connects the p ⁺ -type epi layer 4b and the p ⁺ -type region 4a. Thus, p ⁺ -type contact region (third region) 4c extending from p ⁺ -type epi layer 4b toward n ⁻ -type epi layer 2 is formed. The p ⁺ -type region 4 and the p ⁺ -type epi layer 4b
And the p ⁺ -type contact region 4c constitutes the second gate region 4.

In the channel layer 5, a recess 8 reaching the surface of the n ⁺ type source region 6 and the surface of the first gate region 3 is formed. In the recess 8, a source electrode 9 electrically connected to the n ⁺ type source region 6 is formed, and a first gate electrode 10 electrically connected to the first gate region 3 is formed. It is the configuration that was done.
A second gate electrode 11 for controlling the potential of the second gate region 4 is formed on the surface of the second gate region 4, and the source electrode 9, the first and second gate electrodes 10, 11 are each passivated. It is in a state of being insulated and separated by the film 12.

Furthermore, on the back side of the n ⁺ -type substrate 1, n ⁺ -type substrate 1 and electrically connected to the drain electrode 13 are formed. In this manner, JF in the present embodiment is used.
ET is configured, in such a configuration, the channel layer 5 and the n ^- first out type epitaxial layer 2, the distance L plus a portion located between the second gate region 3 and 4, the conventional Is set substantially equal to the channel length of the J-FET.

The J-FET configured as described above is configured to operate in a normally-off type. That is, first, when no voltage is applied to the second gate electrode 10 and 11, the channel layer 5 and the n ^- first out type epitaxial layer 2, the portion located between the second gate regions 3 and 4 The pinch is pinched off by the depletion layer extending from the first gate region 3 and the depletion layer extending from the second gate region 4. And
When a desired voltage is applied to the first and second gate electrodes 10 and 11, the amount of extension of the depletion layer from the first and second gate regions 3 and 4 decreases, a channel is formed, and the source electrode 9
→ n ⁺ type source region 6 → channel layer 5 → n ⁻ type epi layer 2 →
The current flows in the order of the n ⁺ type substrate 1 → the drain electrode 13.

In such a J-FET, a portion of the channel layer 5 and the n ⁻ -type epi layer 2 located between the first and second gate regions 3 and 4 functions as a channel, and the channel layer 5 and the n − ^The distance L, which is the sum of the -type epitaxial layer 2 and the portion located between the first and second gate regions 3 and 4, is made substantially equal to the channel length of the conventional J-FET. That is, a channel is formed in the vertical direction and the horizontal direction (the substrate vertical direction and the horizontal direction) on the paper surface, and a region serving as a J-FET resistor functions substantially as a channel.

Therefore, the J-FET resistance component can be almost eliminated without increasing the channel length as compared with the conventional J-FET, and the on-resistance can be reduced.
The breakdown voltage of the J-FET is determined by the state of the depletion layer in the region serving as a channel.
^- first out type epitaxial layer 2, both the portion located between the second gate region 3 and 4, is pinched off by the depletion layer extending from the depletion layer and the second gate region 4 which extends from the first gate region 3 As a result, it is possible to ensure a sufficient withstand voltage.

As described above, the channel layer 5 and n ⁻
By making the portion of the type epitaxial layer 2 located between the first and second gate regions 3 and 4 work as a channel, the J-FE
The T resistance component can be eliminated, and the on-resistance can be reduced.

Next, a manufacturing process of the J-FET shown in FIG. 1 will be described with reference to FIGS.

[Step shown in FIG. 2A] First, the n-type 4
H, 6H, 3C or 15R-SiC substrate, ie n ⁺
A mold substrate 1 is prepared. For example, the n ⁺ type substrate 1 has a thickness of 400 μm and a main surface of a (0001) Si surface, or
A (112-0) surface is prepared. Then, an n ⁻ -type epi layer 2 having a thickness of 5 μm is epitaxially grown on the main surface of the substrate 1. In this case, the same crystal as that of the underlying substrate 1 is obtained as the n ⁻ -type epi layer 2, which becomes an n-type 4H, 6H, 3C or 15R-SiC layer.

[Step shown in FIG. 2B] n ^- type epi layer 2
(Low Temperature Oxide) film 20 is arranged in a predetermined region above the
A predetermined region is opened by patterning the O film 20. Then, ion implantation is performed using the LTO film 20 as a mask.
Specifically, boron is ion-implanted as a p-type impurity at a position where the first gate region 3 and the p ⁺ -type region 4a are to be formed. At this time, if necessary, the first gate region 3
Alternatively, aluminum may be ion-implanted into the surface at the position where the p ⁺ -type region 4a is to be formed for contact.

Thereafter, a heat treatment is performed to activate the implanted ions, and the first gate region 3 and the p ⁺ -type region 4 are activated.
a is formed. Thus, the first gate region 3 and p ⁺
By simultaneously forming the mold regions 4a, the manufacturing process can be simplified as compared with the case where these are separately manufactured.

In forming the first gate region 3 and the p ⁺ -type region 4a, if it is not desired to thermally diffuse the p-type impurity, use Al which is difficult to thermally diffuse, or remove carbon from boron. Is preferably implanted at a fixed ratio (preferably, boron: carbon = 1: 10) to make the heat diffusion difficult.

[Step shown in FIG. 2C] After the LTO film 20 is removed, the channel layer 5 composed of an n ⁻ -type layer is epitaxially grown on the n ⁻ -type epi layer 2 including the first gate region 3. To form At this time, it is preferable that the impurity concentration of the channel layer 5 be lower than that of the n ⁻ -type epi layer 2 in order to make the J-FET of a normally-off type easier.

[Step shown in FIG. 3A] After an LTO film 21 serving as a first mask material is formed on the surface of the channel layer 5, the LTO film 21 is patterned by photolithography to form an n ⁺ type source region. An opening is formed in the LTO film 21 at a position facing the position where the 6 is to be formed. Thereafter, ion implantation is performed using the LTO film 21 as a mask. Specifically, nitrogen or phosphorus as an n-type impurity is ion-implanted. Thereby, an n-type impurity is implanted at a position where the n ⁺ -type source region 6 is to be formed. Thereafter, n by activating the n-type impurity by annealing ⁺ -type source region 6
To form

[Step shown in FIG. 3B] After the LTO film 21 is removed, epitaxial growth is performed under the condition that p-type impurities are doped at a high concentration, so that the n ⁺ source region 6 is included. A p ⁺ -type epi layer 4b is formed on the surface of the channel layer 5.

[Step shown in FIG. 3C] p ⁺ -type epi layer 4
after forming the LTO layer 22 on the b surface of the LTO layer 22 is patterned by photolithography, at a site facing the formation planned location of the p ⁺ -type diffusion region 4b L
An opening is formed in the TO film 22. After that, the LTO film 22
Is implanted using the mask as a mask. Specifically, boron is ion-implanted as a p-type impurity at a position where the p ⁺ -type contact region 4c is to be formed.

Thereafter, the implanted ions are activated by performing a heat treatment to form ap ⁺ -type contact region 4c. Thereby, the p ⁺ type region 4, the p ⁺ type epi layer 4b and the p ⁺ type
The second gate region 4 is formed by the ⁺ type contact region 4c. When the p ⁺ -type contact region 4c is formed, if it is not desired to diffuse the p-type impurity by heat,
Either Al which is difficult to thermally diffuse is used, or a certain ratio of carbon to boron (preferably, boron: carbon = 1: 1)
0) It is desirable to make thermal diffusion difficult by implantation.

[Step shown in FIG. 4 (a)] After the LTO film 23 is formed on the surface of the second gate region 4, the LTO film 23 is patterned by photolithography, so that the LTO film 23 is formed on the n ⁺ type source region 6. An opening is formed in the LTO film 23. Thereafter, the surface of the n ⁺ -type source region 6 is exposed by performing etching using the LTO film 23 as a mask, for example, reactive ion etching (RIE).

[Step shown in FIG. 4B] After removing the LTO film 23, an LTO film 24 is formed again, and the LTO film 24 is patterned by photolithography. As a result, in a predetermined region on n ⁺ type source region 6, L
An opening is formed in the TO film 24. After that, the LTO film 24
By performing etching using the mask as a mask, for example, reactive ion etching, the n ⁺ -type source region 6 is penetrated and the first
A recess 8 reaching the gate region 3 is formed.

[Step shown in FIG. 5C] After the LTO film 24 is removed, the interlayer insulating film 1 is formed on the substrate surface side including the inside of the concave portion 8.
Form 2 Then, after patterning the interlayer insulating film 12 to form a contact hole communicating with the first and second gate regions 3 and 7 and the n ⁺ -type source region 6, an electrode layer is formed on the interlayer insulating film 12. The source electrode 9 and the first and second gate electrodes 10 and 11 are formed by patterning the electrode layer. Finally, a drain electrode 13 is formed on the back side of the substrate to form a J-FET shown in FIG.
Is completed.

[0040] Here, to form the p ⁺ -type contact region 4c after forming the p ⁺ -type epitaxial layer 4b is, p ⁺
P ⁺ -type contact region 4c before forming the type epi layer 4b
It is also possible to form

(Second Embodiment) FIG. 5 shows a cross-sectional structure of a J-FET according to a second embodiment of the present invention. As shown in FIG. 5, in the present embodiment, a trench 14 is formed from the p ⁺ -type epi layer 4b to the p ⁺ -type region 4a, and a p ⁺ -type contact region 4c is formed on the inner wall surface of the trench 14. I have. Note that other parts are the same as those in the first embodiment, and a description thereof will not be repeated.

The J-FET having such a structure has the first
Instead of the step shown in FIG.
At the time of the steps shown in FIGS. 3A and 3B, the trenches 14 are simultaneously formed, and then the arrangement of the mask material, the patterning of the mask material by photolithography, and the ion implantation of p-type impurities from above the mask material are sequentially performed. It is manufactured by performing.

As described above, even when the p ⁺ -type contact region 4c is formed using the trench 14, the same operation as that of the J-FET shown in the first embodiment is performed, and the same effect as above is obtained. It is possible.

(Third Embodiment) FIG. 6 shows a cross-sectional structure of a J-FET according to a third embodiment of the present invention. As shown in FIG. 6, in the present embodiment, by deepening the p ⁺ -type diffusion region junction depth of the p ⁺ -type contact region extending from the (first region) 4b (second region) 4c, p ^{The +} type contact region 4c plays the role of the p ⁺ type region 4a shown in FIG. The p ⁺ -type contact region 4c is made deeper than the first gate region 3. Further, the first gate region 3 is electrically connected to the source electrode 9 so as to have the same potential as that of the n ⁺ -type source region 6 so as to be of a single gate drive type. Note that other parts are the same as those in the first embodiment, and a description thereof will not be repeated.

Such a J-FET has a configuration in which the p ⁺ -type contact region 4c is formed to a deep position like the trench type. Therefore, similarly to the first embodiment, J-FE
The T resistance component can be eliminated, and the same effect as in the first embodiment can be obtained. Furthermore, since the p ⁺ -type contact region 4c is made deeper than the first gate region 3, breakdown can occur at the bottom of the p ⁺ -type contact region 4c. As a result, the surge withstand capability can be improved. The J-FET having such a structure is manufactured by adjusting the ion implantation conditions for forming the p ⁺ -type contact region 4c in the step shown in FIG. 3C of the first embodiment. .

In this case, the p ⁺ type contact region 4c
Is formed to a position deeper than the first gate region 3, but the p ⁺ -type region 4a is formed in a step different from that of the first gate region 3, and the p ⁺ -type region 4a is The same effect as described above can be obtained even if it is formed to a deeper position.

(Fourth Embodiment) FIG. 7 shows a sectional configuration of a J-FET according to a fourth embodiment of the present invention. As shown in FIG. 7, in the present embodiment, p ⁺
The mold region 4 a is made deeper than the first gate region 3. The other parts are the same as in the second embodiment, and the description is omitted here.

As described above, by making the p ⁺ type region 4a deeper than the first gate region 3, breakdown can occur at the bottom of the p ⁺ type region 4a. As a result, the surge withstand capability can be improved. Note that the J-FET of such a structure, the p ⁺ -type region 4a is formed in the first gate region 3 in the step shown in FIG. 2 (b) of the first embodiment further step, the p ⁺ type region 4a Is formed to a position deeper than the first gate region 3,
Others are manufactured by using the same method as the second embodiment.

(Fifth Embodiment) FIG. 8 shows a cross-sectional structure of a J-FET according to a fifth embodiment of the present invention. In this embodiment, a case in which one embodiment of the present invention is applied to a J-FET having a triple gate structure will be described.

As shown in FIG. 8, in the present embodiment, the first
Unlike the embodiment, the p ⁺ -type contact region 4c is eliminated, and a third gate made of a p ⁺ -type layer is provided at a position below the p ⁺ -type epi layer 4b instead of the p ⁺ -type region 4a shown in FIG. The third gate region 15
Is made deeper than the first gate region 3. The third gate region 15 may be set to the same potential as the second gate region 4, but the third gate region 15 is controlled to the same potential as the first gate region 3. Any of a state where the potential is independently controlled, a floating state, a state having the same potential as the source electrode 9, and a ground state may be employed. Other parts are the same as in the first embodiment,
Here, the description is omitted.

In the J-FET thus configured, the same operation as that of the J-FET shown in the first embodiment is performed, and the same effect as that of the first embodiment can be obtained. Further, since the third gate region 15 is configured to be deep, when the third gate region 15 is set to the same potential as the second gate region 4 or the ground state, the third gate region 1
Breakdown can occur at the bottom of the fifth embodiment, and the same effects as in the third and fourth embodiments can be obtained.

In the J-FET having such a structure, the third gate region 15 is formed in a step different from that of the first gate region 3 in the step shown in FIG.
The gate region 15 may be formed to a position deeper than the first gate region 3, and the step shown in FIG.

(Other Embodiments) In each of the above embodiments, the p + type epi layer 4b constituting the second gate region 4 is formed by epitaxial growth. This region is ion-implanted into the surface layer of the channel layer 5. It is also possible to form by.

In the first, second, and fourth embodiments, the J-FET having the double gate structure capable of controlling both the potentials in the first and second gate regions 3 and 4 has been described.
Each of the above embodiments can be applied to a J-FET having a single gate structure in which the potential of only one of the first and second gate regions 3 and 4 can be controlled. In that case,
One of the first and second gate electrodes 10 and 11 is connected to the source electrode 9.

Although the above embodiment has been described with reference to an n-channel type J-FET, the present invention can, of course, be applied to a J-FET in which the conductivity type of each component is reversed.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a cross-sectional configuration of a J-FET according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a manufacturing process of the J-FET shown in FIG.

FIG. 3 is a view illustrating a manufacturing step of the J-FET following FIG. 2;

FIG. 4 is a view illustrating a manufacturing step of the J-FET following FIG. 3;

FIG. 5 is a diagram illustrating a cross-sectional configuration of a J-FET according to a second embodiment of the present invention.

FIG. 6 is a diagram illustrating a cross-sectional configuration of a J-FET according to a third embodiment of the present invention.

FIG. 7 is a diagram illustrating a cross-sectional configuration of a J-FET according to a fourth embodiment of the present invention.

FIG. 8 is a diagram illustrating a cross-sectional configuration of a J-FET according to a fifth embodiment of the present invention.

FIG. 9 is a diagram showing a cross-sectional configuration of a conventional J-FET.

[Explanation of symbols]

1 ... n ⁺ -type substrate, 2 ... n ^-- type epi layer, 3, 4 ... first, second
Gate regions, 4a ... p ⁺ -type region, 4b ... p ⁺ -type epitaxial layer, 4
c ... p ⁺ type contact region, 5 ... channel layer, 6 ... n ⁺ type source region, 8 ... concave portion, 9 ... source electrode, 10, 11 ...
First and second gate electrodes, 13... Drain electrodes, 14.

Continued on the front page F term (reference) 5F102 FA03 GB04 GC05 GC07 GC08 GJ02 GR00 GR07 GR11 HC01 HC07 HC16

Claims (17)

[Claims] 1. A semiconductor substrate (1) of a first conductivity type made of silicon carbide; and silicon carbide formed on a main surface of the semiconductor substrate (1) and having higher resistance than the semiconductor substrate (1). A semiconductor layer of a first conductivity type, a first gate region of a second conductivity type formed in a predetermined region of a surface portion of the semiconductor layer and having a predetermined depth; (2) and a first conductivity type channel layer (5) formed on the first gate region (3); and the first gate region (3) of the channel layer (5).
A first conductivity type source region (6) formed in a portion located above the first gate region (3), on the channel layer (5) or in a surface layer portion of the channel layer (5). A second gate region (4) of a second conductivity type formed so as to include a portion opposed to the first region, a source electrode (9) electrically connected to the source region (6), and the first gate region. A first gate electrode (10) electrically connected to (3), a second gate electrode (11) electrically connected to the second gate region (4), and a semiconductor substrate (1). A drain electrode (13) formed on the back surface side, wherein the second gate region (4) extends in a depth direction of the channel layer (5) and the semiconductor layer (2), and Between the portions (4a, 4c) extending in the vertical direction and the first gate region (3). Silicon carbide semiconductor device characterized by being configured to Mareta said semiconductor layer (2) in the channel is formed. 2. The semiconductor device according to claim 1, wherein the second gate region is a first gate region of a surface layer of the semiconductor layer.
The first region of the second conductivity type (4
a) and a second conductive type second formed on the channel layer (5) or in a surface layer portion of the channel layer (5) so as to include a portion facing the first gate region (3).
A region (4b) and a third region (4c) of the second conductivity type formed so as to connect the first region (4a) and the second region (4b). The silicon carbide semiconductor device according to claim 1, wherein: 3. The silicon carbide semiconductor device according to claim 2, wherein said first region (4a) or said third region (4c) is deeper than said first gate region (3). 4. A recess (1) penetrating through the second region (4b) and the channel layer (5) and reaching the first region.
4), wherein the third region (4c) is provided with the concave portion (14).
3. The method according to claim 2, wherein the inner wall surface is formed on the inner wall surface.
Or the silicon carbide semiconductor device according to 3. 5. The second gate region (4) includes a portion facing the first gate region (3) on the channel layer (5) or in a surface layer of the channel layer (5). A first region (4b) of the second conductivity type formed in
2. The silicon carbide semiconductor device according to claim 1, further comprising a second region extending from the first region toward the semiconductor layer. 3. 6. The silicon carbide semiconductor device according to claim 5, wherein said second region (4c) is deeper than said first gate region (3). 7. A semiconductor substrate (1) of a first conductivity type made of silicon carbide; and silicon carbide formed on a main surface of the semiconductor substrate (1) and having a higher resistance than the semiconductor substrate (1). A semiconductor layer of a first conductivity type, a first gate region of a second conductivity type formed in a predetermined region of a surface portion of the semiconductor layer and having a predetermined depth; (2) and a first conductivity type channel layer (5) formed on the first gate region (3); and the first gate region (3) of the channel layer (5).
A first conductivity type source region (6) formed in a portion located above the first gate region (3), on the channel layer (5) or in a surface layer portion of the channel layer (5). A second gate region (4) of a second conductivity type formed so as to include a portion opposed to the first region, a source electrode (9) electrically connected to the source region (6), and the first gate region. A first gate electrode (10) electrically connected to (3), a second gate electrode (11) electrically connected to the second gate region (4), and a semiconductor substrate (1). A drain electrode (13) formed on the back surface side, and a portion of the surface layer of the semiconductor layer (2) located below the second gate region (4) is provided with the first gate region (13). 3) a predetermined distance from the second conductivity type in the planar direction of the semiconductor substrate (1). Silicon carbide wherein the third gate region (15) is formed the semiconductor device. 8. The silicon carbide semiconductor device according to claim 7, wherein said third gate region (15) is deeper than said first gate region (3). 9. A first conductivity type semiconductor layer (2) made of silicon carbide having a higher resistance than the semiconductor substrate (1) on a main surface of the first conductivity type semiconductor substrate (1) made of silicon carbide. Forming a first gate region (3) of a second conductivity type having a predetermined depth in a predetermined region of a surface layer portion of the semiconductor layer (2); and forming the first gate region (3). Forming a first conductivity type channel layer (5) on the semiconductor layer (2); and the first gate region (3) in the channel layer (5).
A first conductivity type source region (6)
Forming a second conductive type second region of the second conductivity type on the channel layer (5) or on the surface layer of the channel layer (5) so as to include a portion facing the first gate region (3). Gate area (4)
Forming a source electrode (9) electrically connected to the source region (5); a first gate electrode (10) electrically connected to the first gate region (3); 2 gate area (4)
Forming a second gate electrode (11) electrically connected to the semiconductor substrate (1); and forming a drain electrode (13) on the back side of the semiconductor substrate (1).
Forming a second gate region, wherein the step of forming the second gate region includes the step of forming the second gate region in the surface layer portion of the semiconductor layer (2). Forming a first region (4a) of a second conductivity type, which is separated from the first gate region (3) by a predetermined distance, in a different portion; and on the channel layer (5) or in the channel layer (5). Forming a second region (4b) of the second conductivity type so as to include a portion facing the first gate region (3) in the surface layer portion; and the second region (4b) and the first region. Forming a third region (4c) of the second conductivity type connecting the second gate region (4a) with the first, second, and third regions (4a to 4c). ) Forming a silicon carbide semiconductor device. . 10. The step of forming the third region (4c), wherein the third region (4c) is formed by ion-implanting a second conductivity type impurity into the channel layer (5). The method for manufacturing a silicon carbide semiconductor device according to claim 9. 11. The step of forming the third region (4c) includes forming a recess (14) penetrating through the second region (4b) and the channel layer (5) and reaching the first region (4a). The silicon carbide semiconductor device according to claim 9, wherein after the formation, the third region (4c) is formed by ion-implanting a second conductivity type impurity into the inner wall surface of the concave portion (14). Manufacturing method. 12. The method according to claim 9, wherein the step of forming the first region and the step of forming the first gate region are performed simultaneously. Of manufacturing a silicon carbide semiconductor device. 13. In the step of forming the first region (4a) or the third region (4c), the first region (4a)
Alternatively, the third region (4c) is the first gate region (3).
The method of manufacturing a silicon carbide semiconductor device according to claim 9, wherein the depth is made deeper. 14. A first conductivity type semiconductor layer (2) made of silicon carbide having a higher resistance than the semiconductor substrate (1) on a main surface of the first conductivity type semiconductor substrate (1) made of silicon carbide.
Forming a first gate region (3) of a second conductivity type having a predetermined depth in a predetermined region of a surface layer portion of the semiconductor layer (2); and forming the first gate region (3). Forming a first conductivity type channel layer (5) on the semiconductor layer (2); and the first gate region (3) in the channel layer (5).
A first conductivity type source region (6)
Forming a second conductive type second region of the second conductivity type on the channel layer (5) or on the surface layer of the channel layer (5) so as to include a portion facing the first gate region (3). Gate area (4)
Forming a source electrode (9) electrically connected to the source region (5); a first gate electrode (10) electrically connected to the first gate region (3); 2 gate area (4)
Forming a second gate electrode (11) electrically connected to the semiconductor substrate (1); and forming a drain electrode (13) on the back side of the semiconductor substrate (1).
Forming the second gate region, wherein the step of forming the second gate region is performed on the channel layer (5) or a surface layer portion of the channel layer (5). Forming a first region (4b) of the second conductivity type so as to include a portion facing the first gate region (3); and forming the semiconductor layer (2) from the first region (4b). Extending a second region (4c) toward
The second gate region (4) in the second region (4b, 4c)
Forming a silicon carbide semiconductor device. 15. The method according to claim 14, wherein in the step of forming the second region (4c), the second region (4c) is made deeper than the first gate region (3). The manufacturing method of the silicon carbide semiconductor device described in the above. 16. A first conductivity type semiconductor layer (2) made of silicon carbide having a higher resistance than the semiconductor substrate (1) on a main surface of the first conductivity type semiconductor substrate (1) made of silicon carbide.
Forming a first gate region (3) of a second conductivity type having a predetermined depth in a predetermined region of a surface layer portion of the semiconductor layer (2); and forming the first gate region (3). Forming a first conductivity type channel layer (5) on the semiconductor layer (2); and the first gate region (3) in the channel layer (5).
A first conductivity type source region (6)
Forming a second conductive type second region of the second conductivity type on the channel layer (5) or on the surface layer of the channel layer (5) so as to include a portion facing the first gate region (3). Gate area (4)
Forming a source electrode (9) electrically connected to the source region (5); a first gate electrode (10) electrically connected to the first gate region (3); 2 gate area (4)
Forming a second gate electrode (11) electrically connected to the semiconductor substrate (1); and forming a drain electrode (13) on the back side of the semiconductor substrate (1).
Forming a silicon carbide semiconductor device, the method comprising: forming a portion of the surface layer portion of the semiconductor layer (2) below the second gate region (4); A step of forming a third gate region (15) of the second conductivity type at a predetermined distance from one gate region (3) in the planar direction of the semiconductor substrate (1). A method for manufacturing a semiconductor device. 17. In the step of forming the third gate region (15), the thirty-second gate region (15) includes the first gate region (15).
17. The method of manufacturing a silicon carbide semiconductor device according to claim 16, wherein the depth is made deeper than the gate region (3).