JP2002329785A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device having dummy patterns which can protect analog use poly silicon capacitors adequately. SOLUTION: Dummy patterns 8, 9 for protecting an analog use poly silicon capacitor are formed in a two-layer structure consisting of a gate electrode layer and a lower electrode layer, or in a three-layer structure consisting of the gate electrode layer, a dielectric layer, and the lower electrode layer.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor device, and more particularly to a structure of a dummy pattern disposed around a polysilicon capacitor used as an analog semiconductor element.

[0002]

2. Description of the Related Art A semiconductor logic device and a logic circuit and a DRAM / SRAM / flash memory etc.
An embedded device (hereinafter referred to as eRAM) embedded in the chip
) Uses a polysilicon capacitor as an analog semiconductor element.

Hereinafter, an example of a manufacturing method for forming a polysilicon capacitor on a semiconductor substrate will be briefly described with reference to FIG. (1) An isolation region 2 and an active region 3 are formed on a semiconductor substrate 1 (FIG. 4A). (2) Next, a polysilicon capacitor silicon film or an amorphous silicon film is formed for the capacitor lower electrode, and a photoresist pattern for forming the lower electrode is formed (FIG. 4B). (3) After the lower electrode is patterned by a dry etching method or the like, a silicon oxide film, a silicon nitride film, or a laminated film thereof is formed for a dielectric layer of the capacitor. After the formation of the dielectric layer, the dielectric layer is formed through photolithography and etching steps (FIG. 4C). (4) After forming the dielectric layer, a gate oxide film is formed on the active region of the semiconductor substrate by a thermal oxidation method on the active region [FIG.
(D)]. (5) After forming the gate oxide film, a polysilicon capacitor silicon film or an amorphous silicon film is formed for the gate electrode and the capacitor upper electrode [FIG. 4 (e)]. (6) After forming a photoresist pattern for the gate electrode and the capacitor upper electrode, the gate electrode and the capacitor upper electrode are patterned by using a dry etching method or the like (FIG. 4F). (7) Further, a TEOS oxide film or the like is deposited by a CVD method as an interlayer insulating film.

At this time, after forming the interlayer insulating film in the step (7), the surface of the insulating film is flattened in order to secure a margin in the subsequent patterning. CM in this flattening
When the P method is used, since the step portion is easily polished in the polishing, the thickness of the insulating film on the capacitor after polishing is large at the center of the capacitor and thin at the capacitor end as shown in FIG. Furthermore, when over-polishing due to CMP occurs,
At the end of the capacitor, the upper electrode of the capacitor is exposed, and the probability of damaging the capacitor is high. Further, since the dummy for protecting the gate electrode is usually formed of a single layer of the gate electrode, the effect of preventing shoulder drop is small (FIG. 6). Analog semiconductor devices require high reliability to handle continuously changing information in various states, unlike digital semiconductor devices that handle low- and high-level two-level information. This is a major problem for some polysilicon capacitors.

[0005]

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device having a dummy pattern capable of accurately protecting an analog polysilicon capacitor.

[0006]

In the semiconductor device according to the first invention, a dummy pattern for protecting an analog polysilicon capacitor is formed in a two-layer structure of a gate electrode layer and a lower electrode layer.

In the semiconductor device according to the second invention, a dummy pattern for protecting the analog polysilicon capacitor is formed in a three-layer structure of a gate electrode layer, a dielectric layer, and a lower electrode layer.

In the semiconductor device according to the third invention, the gate electrode layer is shared with the polysilicon capacitor body.

In the semiconductor device according to a fourth aspect of the present invention, the lower electrode layer is shared with the polysilicon capacitor body.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 Embodiment 1 of the present invention will be described with reference to FIG. FIG. 1 is a cross-sectional view showing a manufacturing process according to the first embodiment. In the figure,
1 is a semiconductor substrate, 2 is an isolation region, 3 is an active region, 4 is an isolation oxide film, 5 is a polysilicon film, 6 is a photoresist,
7 is a gate oxide film. 8 is a dummy pattern,
It has a three-layer structure of lower electrode / dielectric layer / gate electrode layer. Reference numeral 9 denotes a dummy pattern, which has a three-layer structure of a lower electrode / gate electrode layer. 10 is a gate electrode layer, 1
1 is a lower electrode layer shared by the dummy patterns 8, 9 and the polysilicon capacitor, and 12 is an upper electrode layer shared by the dummy patterns 8, 9 and the polysilicon capacitor.

FIG. 1 shows a first embodiment according to the present invention. (1) An isolation region 2 and an active region 3 are formed on a semiconductor substrate 1 (FIG. 1A). (2) Next, a polysilicon capacitor silicon film 5 or an amorphous silicon film is formed for the capacitor lower electrode, and a photoresist pattern for forming the lower electrode is formed (FIG. 1B). (3) After the lower electrode is patterned by a dry etching method or the like, a silicon oxide film, a silicon nitride film, or a laminated film thereof is formed for a dielectric layer of the capacitor. After the formation of the dielectric layer, the dielectric layer is formed through the steps of photolithography and etching [FIG. 1 (c)]. (4) After forming the dielectric layer, a gate oxide film is formed on the active region of the semiconductor substrate by a thermal oxidation method on the active region [FIG.
(D)]. (5) After forming the gate oxide film, a polysilicon film or an amorphous silicon film is formed for the gate electrode and the capacitor upper electrode [FIG. 1 (e)]. (6) After forming a photoresist pattern of a gate electrode, a capacitor upper electrode and a dummy pattern, patterning is performed using a dry etching method or the like [FIG.
(F)].

As described above, the dummy patterns 8 and 9 formed around the analog polysilicon capacitor are formed by a two-layer structure of a lower electrode / gate electrode or a three-layer structure of a lower electrode / dielectric layer / gate electrode layer. By forming with
The CMP flattening performed after the formation of the interlayer film can suppress shoulder drop occurring at the end of the polysilicon capacitor.

According to the first embodiment of the present invention, the dummy pattern 9 for protecting the analog polysilicon capacitor has a two-layer structure of a gate electrode layer and a lower electrode layer, and the dummy pattern 8 is formed of a gate electrode layer and a dielectric layer. Since it has a three-layer structure of a body layer and a lower electrode layer, it has a two-layer structure of a gate electrode layer and a lower electrode layer, or a gate electrode layer, a dielectric layer,
Dummy patterns 8, 9 formed in a three-layer structure of a lower electrode layer
Accordingly, a semiconductor device having a dummy pattern that can accurately protect the analog polysilicon capacitor can be obtained.

Embodiment 2 FIG. A second embodiment according to the present invention will be described with reference to FIGS. FIG. 2 is a cross-sectional view showing a configuration according to the second embodiment. FIG. 3 is a sectional view showing another configuration according to the second embodiment. In the second embodiment, the configuration and operation other than the specific configuration described here have the same configuration as the above-described first embodiment and exert the same operation. The same or corresponding parts are denoted by the same reference numerals as in the first embodiment.

In the dummy pattern and the polysilicon capacitor body of the first embodiment, the lower electrode layer 11 is shared by the dummy patterns 8 and 9 and the polysilicon capacitor (FIG. 2), or the upper electrode layer as the gate electrode layer 12 may be shared by the dummy pattern and the polysilicon capacitor (FIG. 3).

According to the second embodiment of the present invention, upper electrode layer 12 or lower electrode layer 1 as a gate electrode layer
1 is shared between the dummy patterns 8 and 9 and the polysilicon capacitor body, and therefore, the dummy patterns 8 and 9 having the gate electrode layer or the lower electrode layer shared with the polysilicon capacitor body A semiconductor device capable of accurately protecting an analog polysilicon capacitor with a simple configuration can be obtained.

[0017]

According to the first aspect of the present invention, the dummy pattern for protecting the analog polysilicon capacitor is formed in the two-layer structure of the gate electrode layer and the lower electrode layer. With the dummy pattern formed in the two-layer structure, a semiconductor device capable of accurately protecting the analog polysilicon capacitor can be obtained.

According to the second aspect, the dummy pattern for protecting the analog polysilicon capacitor is formed in the three-layer structure of the gate electrode layer, the dielectric layer, and the lower electrode layer. With the dummy pattern formed with the three-layer structure of the layer and the lower electrode layer, it is possible to obtain a semiconductor device capable of properly protecting the analog polysilicon capacitor.

According to the third invention, in the first or second invention, since the gate electrode layer is shared with the polysilicon capacitor body, the gate electrode layer is shared with the polysilicon capacitor body. With the dummy pattern, it is possible to obtain a semiconductor device capable of accurately protecting the analog polysilicon capacitor with a simple configuration.

According to the fourth invention, in the first to third inventions, the lower electrode layer is shared with the polysilicon capacitor body, so that the lower electrode layer is shared with the polysilicon capacitor body. With the dummy pattern, it is possible to obtain a semiconductor device capable of accurately protecting the analog polysilicon capacitor with a simple configuration.

[Brief description of the drawings]

FIG. 1 is a sectional view illustrating a manufacturing process of a semiconductor device according to a first embodiment of the present invention;

FIG. 2 is a sectional view showing a configuration of a semiconductor device according to a second embodiment of the present invention;

FIG. 3 is a sectional view showing another configuration according to the second embodiment of the present invention.

FIG. 4 is a cross-sectional view showing a manufacturing process in a conventional technique.

FIG. 5 is a cross-sectional view illustrating an example of a configuration according to the related art.

FIG. 6 is a cross-sectional view showing another example of the configuration according to the related art.

[Description of Signs] 1 semiconductor substrate, 2 isolation region, 3 active region, 4 isolation oxide film, 5 polysilicon film, 6 photoresist,
7 gate oxide film, 8, 9 dummy pattern, 10 is a gate electrode layer, 11 lower electrode layer, 12 upper electrode layer.

Claims (4)

[Claims] 1. A semiconductor device wherein a dummy pattern for protecting an analog polysilicon capacitor is formed in a two-layer structure of a gate electrode layer and a lower electrode layer. 2. A semiconductor device wherein a dummy pattern for protecting an analog polysilicon capacitor is formed in a three-layer structure of a gate electrode layer, a dielectric layer, and a lower electrode layer. 3. The semiconductor device according to claim 1, wherein the gate electrode layer is shared with the polysilicon capacitor body. 4. The semiconductor device according to claim 1, wherein the lower electrode layer is shared with the polysilicon capacitor body.