JP2001267318A - Method of manufacturing semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a technology for reducing dishing quantity on metallic wiring and securing its planarity. SOLUTION: A first mask pattern Fra is formed of a photoresist film in a region except for a wiring region on a silicon oxide film 15 and a second mask pattern FRb into an almost rectangular shape is formed in a wiring region 3Mb. The silicon oxide film is etched with the patterns as masks. Poles 15b, constituted of the silicon oxide films, are formed in the wiring region, and a Cu film 16 is formed. Then, the Cu film 16 is ground until the silicon oxide films 15a and 15b are exposed, so that a metal wiring is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for manufacturing a semiconductor integrated circuit device, and more particularly, to a technique for chemical mechanical polishing.
The present invention relates to a technique which is effective when applied to formation of a buried metal wiring using a mechanical polishing (CMP) method.

[0002]

2. Description of the Related Art In recent years, a chemical mechanical polishing (CM) has been proposed as a new fine processing technology accompanying high integration and high performance of LSI.
P) method is being introduced.

On the other hand, with miniaturization, an increase in resistance of conventional Al (aluminum) wiring has become a problem.
Introduction of Cu (copper) wiring having a lower electric resistance than that of copper wiring has been promoted.

For example, after a wiring groove is formed in an insulating film deposited on a silicon substrate and a Cu film is deposited, an unnecessary Cu film outside the groove is removed by a CMP method to bury Cu inside the groove. , Cu wiring. This is the formation of a Cu wiring by a so-called Damascene method.

[0005]

In the above-described method for forming a Cu wiring, an unnecessary Cu film outside the trench is removed by CM.
When the metal film is removed by the P method, a part of the metal film remains in a depression on the surface of the insulating film due to the step of the base. Since this metal residue causes a short circuit between the embedded wirings, it is necessary to remove it by overpolishing.

However, when this overpolishing is performed, a phenomenon (dishing) occurs in which the central portion of the surface of the embedded wiring is polished more excessively than the peripheral portion and recedes.
When such a phenomenon occurs, it becomes difficult to secure flatness, which affects subsequent steps. Further, since the cross-sectional area of the embedded wiring is reduced, the wiring resistance is increased.

An object of the present invention is to provide a technique capable of reducing the amount of dishing and securing flatness by providing a pillar made of an insulating film called a slit or an island inside a buried wiring.

Another object of the present invention is to provide a technique for reducing a dishing amount and preventing an increase in wiring resistance.

The above objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0010]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

The method of manufacturing a semiconductor integrated circuit device according to the present invention includes: (a) forming an element on a main surface of a semiconductor substrate; and (b) forming an insulating film on the element.
(C) forming a first mask pattern in a region other than the wiring formation region on the insulating film, and forming a second mask pattern in the wiring formation region; and (d) forming the first and second mask patterns. Forming a column made of the insulating film in the wiring formation region by etching the insulating film using the mask pattern as a mask; and (e) forming the first and second columns.
(F) forming a metal layer on the insulating film and the wiring formation region;
(G) chemically and mechanically polishing the metal layer until the insulating film is exposed.

According to the above means, after forming the pillar made of the insulating film in the wiring forming region, a metal layer is formed thereon and polished chemically and mechanically, so that the apparent metal wiring width is small. Thus, the dishing amount in the polishing step of the metal layer can be reduced.

[0013]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, members having the same functions are denoted by the same reference numerals, and the repeated description thereof will be omitted.

(First Embodiment) FIG. 1 is a plan view showing a shape of a metal wiring of a semiconductor integrated circuit device according to a first embodiment. FIG. 1 shows a state in which the wide wiring 16a and the normal wiring 16b are formed in parallel. A silicon oxide film 15a is formed between the wide wiring 16a and the normal wiring 16b. Further, a pillar 15b (hereinafter, referred to as a silicon oxide pillar) made of a silicon oxide film is provided in the wide wiring 16a.
The surface of is exposed.

The wide wiring 16a, the normal wiring 16b, and the lower layers of these wirings will be described with reference to FIGS. FIG. 2A is a cross-sectional view taken along line AA of FIG. 1, and FIG.
1 is a sectional view taken along the line BB of FIG. 1, and FIG. 3 is a sectional view taken along the line CC of FIG. As shown in FIG. 2B, the wide wiring 16a and the normal wiring 16b are buried inside the silicon oxide film 15a, and as shown in FIGS. Has a substantially square pillar-shaped silicon oxide pillar 15b
Are formed. Reference numeral 1 denotes a silicon substrate, and 14 denotes an insulating film. As will be described later, a semiconductor element is formed on the main surface of the silicon substrate 1. Wirings and plugs for connecting to the wiring 16b and the like are formed.

Next, with reference to FIG. 4, a description will be given of a manufacturing process until the wide wiring 16a and the normal wiring 16b are formed. First, as shown in FIG.
The silicon substrate 1 on which is formed is prepared.

Although not shown in FIG. 4A,
On the main surface of the silicon substrate 1, a MISFET (Metal Insulator Semiconductor) constituting a memory or a microcomputer is provided.
r Field Effect Transistor) and other semiconductor devices (devices)
Are connected to the wide wiring 16a or the normal wiring 16b via a plurality of metal wirings and plugs.

FIG. 10 shows an example. As shown in FIG. 10, the active region of the silicon substrate 1 where the diffusion layer 2 is formed, that is, the region where the field oxide film 3 is not formed, is subjected to the MIS by a normal MOS device process.
The FET Q is formed. After the silicon oxide film 4 is formed on the MISFETQ, the silicon oxide film 4 on the source and drain regions of the MISFETQ is removed, and a contact hole 5 is formed. Further, after a W (tungsten) film 6 is deposited on the contact hole 5 and the silicon oxide film 4 by a sputtering method, the W film 6 is patterned by dry etching to form a first layer wiring made of the W film 6. I do.

Further, a silicon oxide film 7 is formed on the W film 6, a contact hole 8 is formed on the W film 6,
A u film 9 is formed on the contact hole 8 and the silicon oxide film 7 by a sputtering method, and is polished by a CMP method to form a plug made of a Cu film 9 in the contact hole 8. Next, a silicon oxide film 10 is formed on the Cu film 9 (plug) and the silicon oxide film 7, and the silicon oxide film 10 in the second-layer wiring formation region is removed by etching. A Cu film 11 is formed on the opening formed by the etching and on the silicon oxide film 10 and polished by a CMP method to form a second-layer wiring made of the Cu film 11 in the opening.

Further, the silicon oxide film 1 is formed on the Cu film 11.
After forming a contact hole on the Cu film 11, a Cu film 13 is formed on the contact hole and the silicon oxide film 12 by a sputtering method, and polished by a CMP method to form a Cu film 13 in the contact hole. In addition to forming a plug made of a Cu film 9 and then forming a Cu film 10 serving as a second layer wiring (single damascene), forming a contact hole 8 and the opening, It is also possible to form the second layer wiring by so-called dual damascene in which a film is formed in the contact hole 8 and the opening. Also, the first
Although the layer wiring is a W film, it may be a Cu film like the second layer wiring.

Therefore, the insulating film 14 shown in FIG. 4 includes the silicon oxide films 4, 7, 10, and 12 as described above, and has a surface on the surface of the insulating film 14 for connection with the third layer wiring. An embedded plug (for example, an embedded plug made of the Cu film 13 in FIG. 10) and the like are exposed.

Next, as shown in FIG.
4, a silicon oxide film 15 (insulating film) is formed, and then a photoresist film FR is formed on the silicon oxide film 15. Next, a third-layer wiring formation region (3Ma, 3Mb)
Is removed, and the third-layer wiring formation region (3Ma, 3Mb) is opened.
a (first mask pattern) is formed. At this time, the third
Without removing all the photoresist film FR in the layer wiring formation region (3Ma, 3Mb), a plurality of substantially rectangular patterns FRb (the second mask Pattern) (Fig. 4)
(C)). Thereafter, using the photoresist films FRa and FRb as a mask, the silicon oxide film 15 is etched to remove the photoresist films FRa and FRb. As a result, of the third-layer wiring formation region, the wide wiring formation region 3
A substantially square pillar-shaped silicon oxide pillar 15b (a pillar made of an insulating film) is formed in Mb.

Next, the third portion including the silicon oxide pillar 15b
A Cu film 16 (metal layer) is formed on the layer wiring formation region (3Ma, 3Mb) and the silicon oxide film 15a (FIG. 4).
(D)).

Thereafter, the Cu film 16 is polished by the CMP method until the silicon oxide pillars 15b and the silicon oxide film 15a are exposed, and the Cu film 16 is formed in the silicon oxide film 15a.
The wiring (16a, 16b) is formed by embedding (third layer wiring) (see FIGS. 1 to 3).

As described above, according to the present embodiment, the third
After the silicon oxide pillar 15b is formed in the wide wiring formation area 3Mb in the layer wiring formation area, the silicon oxide pillar 15b is formed.
b, a Cu film 16a is formed, and the Cu film 1 is formed by the CMP method.
Since the third layer wiring is formed by polishing the substrate 6, the dishing amount of the Cu film 16a can be reduced, and the flatness can be ensured.

More specifically, the cross-sectional shape after the Cu film 16 is formed will be described in detail. As shown in FIG. 5A, a plurality of silicon oxide pillars 15b are formed in the wide wiring forming region 3Mb. Therefore, the apparent wiring width is reduced, and the dishing amount is reduced. On the other hand, as shown in FIG. 5B, when the silicon oxide pillar is not formed in the wide wiring forming region of the silicon oxide film 55, the center of the wide wiring 56a among the third layer wirings 56a and 56b is formed. A dishing phenomenon occurs in which the wiring cross section is reduced, which leads to an increase in wiring resistance. In addition, the dishing phenomenon impairs flatness. On the other hand, in order to reduce the dishing amount, it is necessary to finely control the polishing amount by the CMP method.

Accordingly, as in the present embodiment, the Cu film 16
If the dishing amount a can be reduced, it is possible to prevent an increase in wiring resistance due to dishing. Further, flatness can be improved. Further, the necessity of controlling the polishing amount is reduced, and the process margin can be increased.

In this embodiment, the wiring layer on which the silicon oxide pillars 15b are provided is the third-layer wiring, but the silicon oxide pillars 15b may be provided on wirings of other layers. The wiring layer on which the silicon oxide pillars 15b are provided is not limited to one layer, and may be provided on a plurality of wiring layers.

In particular, since the power supply wiring provided in the uppermost layer and the lower layer has a large wiring width of usually 4 μm or more, it is effective to apply this embodiment. Note that this embodiment is desirably applied to a wiring having a wiring width of 1 μm or more without being limited to the power supply wiring.

The size and the number of the silicon oxide pillars 15b may be appropriately set within a range that does not hinder the resistance increase due to the silicon oxide pillars. In addition, it is effective to form the wiring at substantially equal intervals in the wiring length direction in consideration of the wiring width and the wiring length. Further, the shape of the silicon oxide pillar 15b is not limited to a shape having a substantially rectangular upper surface as shown in FIG. 1, but may be a shape having a substantially square upper surface described below.

(Embodiment 2) FIG. 6 is a plan view showing the shape of metal wiring of a semiconductor integrated circuit device according to Embodiment 2. FIG. 6 shows a state in which the wide wiring 26a and the normal wiring 16b are formed in parallel. A silicon oxide film 15a is formed between the wide wiring 26a and the normal wiring 16b. Further, the surface of a pillar 25b (hereinafter referred to as a silicon oxide pillar 25b) made of a silicon oxide film is exposed in the wide wiring 26a.

The wide wiring 26a, the normal wiring 16b, and the lower layers of these wirings will be described with reference to FIGS. FIG. 7A is a sectional view taken along the line AA in FIG. 6, and FIG.
6 is a sectional view taken along line BB of FIG. 6, and FIG. 8 is a sectional view taken along line CC of FIG. As shown in FIG. 7B, the wide wiring 26a and the normal wiring 16b are buried in the silicon oxide film 15a, and as shown in FIGS. Has a substantially square pillar-shaped silicon oxide pillar 25
b is formed. Reference numeral 1 denotes a silicon substrate, and 14 denotes an insulating film. As described in the first embodiment, a semiconductor element is formed on the main surface of the silicon substrate 1 and the insulating film 1 is formed.
In 4, wirings and plugs for connecting these semiconductor elements to the wide wiring 26 a or the normal wiring 16 b are formed.

The wide wiring 26a and the normal wiring 16
The manufacturing process until b is formed is the same as that of the first embodiment except that the shape of the plurality of patterns FRb (the second mask pattern) in the first embodiment is substantially square, and thus the description is omitted.

As described above, according to the present embodiment, similarly to the first embodiment, after forming the silicon oxide pillar 25b, a Cu film is formed on the silicon oxide pillar 25b.
The third layer wirings (26a, 16b) were formed by polishing the Cu film by the CMP method.
The dishing amount of 6a can be reduced and flatness can be ensured. Further, an increase in wiring resistance due to dishing can be prevented, and a process margin can be increased.

In the first and second embodiments, only the silicon oxide pillars (15b, 25b)
Was formed, but as shown in FIG.
Can be provided not only in the region where the wide wiring (36a) is formed, but also in the region where the normal wiring (36b) is formed. By providing the same silicon oxide pillar in the normal wiring forming area as in the wide wiring forming area, the DA operation processing at the time of masking can be simplified.

(Embodiment 3) In the above embodiment, a silicon oxide pillar is formed in a wiring forming region to reduce the dishing amount of a wiring made of a Cu film.
As shown in FIG. 13, a pillar made of a silicon substrate (hereinafter referred to as a silicon pillar) is formed in the element isolation region F of the silicon substrate 1.
31b, the dishing amount of the silicon oxide film 33 buried in the element isolation region F can be reduced.

FIG. 11 is a plan view showing the shape of the element isolation region (33) of the semiconductor integrated circuit device according to the third embodiment. FIG. 12A is a cross-sectional view taken along the line AA of FIG. 11, and FIG.
FIG. 12 is a sectional view taken along line BB of FIG. 11. FIG. 13 is a sectional view taken along the line CC of FIG.

FIG. 11 shows a state in which a plurality of element formation regions A1 to A4 are formed on the silicon substrate 1. A silicon oxide film 33 is provided between these element formation regions (A1 to A4).
(Element isolation region F) is formed. Further, the surface of the silicon pillar 31b is exposed in the element isolation region F.

As shown in FIG. 12A, a trench for device isolation is formed around the device forming regions A1 to A4 in FIG. 11, and a silicon oxide film 33 is buried in the trench. I have. The trench for element isolation is formed by etching the silicon substrate 1 using the silicon nitride film formed on the element formation regions (A1 to A4) of the silicon substrate 1 as a mask. The silicon oxide film 33 is embedded in the groove by polishing the silicon oxide film 33 formed on the element isolation groove and the element formation regions A1 to A4 by a CMP method.

However, FIGS. 12B and 13
As shown in FIG. 7, since a substantially square pillar-shaped silicon pillar 1b is formed in the element isolation region F, a silicon oxide film 33 is formed on the silicon pillar 31b during element isolation, and is polished by a CMP method. Therefore, the dishing amount of the silicon oxide film 33 can be reduced, and flatness can be ensured.

Further, the necessity of controlling the polishing amount is reduced,
The process margin can be expanded.

Although the invention made by the inventor has been specifically described based on the embodiment, the invention is not limited to the embodiment, and various modifications can be made without departing from the gist of the invention. Needless to say,

[0043]

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

In the method of manufacturing a semiconductor integrated circuit device according to the present invention, after a column made of an insulating film is formed in a wiring formation region, a metal layer is formed on the column, and the metal layer is polished chemically and mechanically. The metal wiring width can be reduced, and the dishing amount in the polishing step of the metal layer can be reduced. Therefore, as a result, flatness can be ensured. Further, an increase in wiring resistance due to dishing can be prevented, and a process margin can be increased.

[Brief description of the drawings]

FIG. 1 is a plan view showing a shape of a metal wiring of a semiconductor integrated circuit device according to a first embodiment of the present invention.

2A is a cross-sectional view taken along the line AA of FIG. 1, and FIG. 2B is a cross-sectional view taken along the line BB of FIG.

FIG. 3 is a sectional view taken along line CC of FIG. 1;

FIG. 4 is a fragmentary cross-sectional view of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device of the first embodiment.

5A is a cross-sectional view for explaining in detail a cross-sectional shape after forming a wiring, and FIG. 5B is a cross-sectional view for explaining an effect of the present invention.

FIG. 6 is a plan view showing a shape of a metal wiring of a semiconductor integrated circuit device according to a second embodiment of the present invention.

7A is a sectional view taken along the line AA in FIG. 6, and FIG. 7B is a sectional view taken along the line BB in FIG.

FIG. 8 is a sectional view taken along line CC of FIG. 6;

FIG. 9 is a plan view showing a shape of a metal wiring in a case where a silicon oxide pillar is formed also in a normal wiring of the semiconductor integrated circuit device.

FIG. 10 is a diagram illustrating an element and a wiring formed on a silicon substrate.

FIG. 11 is a plan view showing a shape of an element isolation region of a semiconductor integrated circuit device according to a third embodiment of the present invention.

12A is a cross-sectional view taken along the line AA in FIG. 11, FIG.
FIG. 12 is a sectional view taken along line BB of FIG. 11.

FIG. 13 is a sectional view taken along line CC of FIG. 11;

[Explanation of symbols]

 Reference Signs List 1 silicon substrate 2 diffusion layer 3 field oxide film 4 silicon oxide film 5 contact hole 6 W film 7 silicon oxide film 8 contact hole 9 Cu film 10 silicon oxide film 11 Cu film 12 silicon oxide film 13 Cu film 14 insulating film 15 silicon oxide Film 15a Silicon oxide film 15b Silicon oxide pillar 16 Cu film 16a Wide wiring 16b Normal wiring FR Photoresist film FRa Photoresist film FRb Substantially rectangular pattern 3Ma Normal wiring forming area 3Mb Wide wiring forming area Q MISFET 26a Wide wiring 25b Silicon oxide pillar 36a Wide wiring 36b Normal wiring 31b Silicon pillar 33 Silicon oxide film A1 to A4 Element formation area F Element isolation area 56a Wide wiring 56b Normal wiring

Continued on the front page (72) Inventor Hideo Aoki 3-16-6 Shinmachi, Ome-shi, Tokyo F-term in the Device Development Center, Hitachi, Ltd. (Reference) 5F033 HH11 HH19 JJ01 JJ11 JJ19 KK01 KK19 MM01 MM02 MM21 PP15 QQ09 QQ37 QQ48 RR04 TT02 XX01

Claims (1)

[Claims] (A) forming an element on a main surface of a semiconductor substrate; (b) forming an insulating film on the element; and (c) excluding a wiring formation region on the insulating film. Forming a first mask pattern in a region and forming a second mask pattern in the wiring formation region; and (d) etching the insulating film using the first and second mask patterns as a mask. (E) removing the first and second mask patterns in the wiring formation region, (f) removing the first and second mask patterns, and (f) forming the column on the insulation film and the wiring formation region. A method for manufacturing a semiconductor integrated circuit device, comprising: a step of forming a metal layer; and (g) a step of chemically and mechanically polishing the metal layer until the insulating film is exposed.