JP3002665B2 - Method for Crown Type Capacitor of Dynamic Random Access Memory - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to a DR in a broad sense.
The present invention relates to the fabrication of capacitors in AM devices, and more particularly to a method for fabricating a capacitor on a bit line having a large capacitance, and more particularly to a method for a crown cylinder capacitor.

[0002]

2. Description of the Related Art Very large scale integrated circuit (VLSI) semiconductor technology has significantly increased the degree of circuit integration on a chip. Miniaturized devices are mounted in close proximity on or on a semiconductor substrate, and the degree of integration has become extremely high. More recent advances in photolithography techniques, such as phase shift masks and self-alignment processing steps, have resulted in smaller devices and higher circuit integration. This has advanced to ultra large scale integrated circuits (ULSI), where the minimum size of the device is less than 1 micrometer and the transistors on the chip exceed one million. As the degree of integration has increased, some circuit elements have been electrically restricted due to their smaller size. One such electrical limitation is an array of storage elements in a dynamic random access memory (DRAM) chip. An individual DRAM storage element is generally a single metal oxide semiconductor field effect transistor (MOS-FE).
T), a single capacitor is widely used in the electronics industry for data storage. A single DRAM device stores one bit of data on a capacitor when current flows. The decrease in element capacity caused by the decrease in storage element area is caused by dynamic random access memory (DR).
A serious obstacle to increasing the degree of integration of AMs).
When the element capacity decreases, not only is excessive power consumption during low-voltage operation due to imminent device operation, but also the read performance deteriorates and the rate of soft errors in the memory element increases. Is a problem that must be solved in order to further increase the degree of integration. Therefore, in order to improve the element capacity, an integrated capacitor having a three-dimensional structure is desirable. The integrated capacitor includes, for example, a capacitor having a double integration, a fin structure, a cylindrical body, an enlarged integration, and a box-shaped structure.

The following US patents show related processes and capacitor structures: That is, US 5,543,345 (Liao et al.), US 5,550,076 (Cheng), US 5,604,146 (Zen), US 5,491,103 (Ann et al.), US 5,545,584 (Wu et al.) Show a unified contact plug process. However, many of the prior art approaches require substantially more processing steps and / or planar structures, which makes the manufacturing process more complicated and leads to increased costs. Developing a method of manufacturing a capacitor that minimizes manufacturing costs and maximizes device output is a challenge. In particular, developing a method to minimize the number of photoresist masking operations and providing maximum processing tolerances to maximize productivity is a challenge. Another challenge is to develop a capacitor that is not subject to size limitations due to photolithography technology.

[0004]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a method for manufacturing a capacitor having high integration and large capacitance. An object of the present invention is to provide a method for easily manufacturing a DRAM and a capacitor having a high degree of integration and a large capacity at a low cost. SUMMARY OF THE INVENTION It is an object of the present invention to provide a method for manufacturing a capacitor that exceeds the limits of photographic technology and that can reduce the number of masking steps. SUMMARY OF THE INVENTION An object of the present invention is to provide a method for easily manufacturing a dynamic random access memory (DRAM) having a capacitor having a high degree of integration and a large capacity at a low cost.

[0005] It is an object of the present invention to provide a method for manufacturing a crown capacitor that can deposit hemispherical grains (HSG) in the crown to avoid the problem of HSG grain pieces inducing leakage. It is in. In order to achieve the above object, the present invention, which aims to provide a method of manufacturing a crown capacitor for a memory device, comprises the steps of (a) FIG.
Where the device area is about to be left, an isolated area 12 is selectively formed on the surface of the substrate 10, and (b) device structures 20, 22, 24, 2 within the substrate device area.
6, 28, 29 are formed and the device structure is
FIG. 1 shows a structure including a capacitor contact point contact zone 18 (eg, a drain zone).
A first insulating layer 30 is formed thereon, (d) FIG. 2-An etching sealing layer 34 is formed on the first insulating layer, and (e) an etching sealing layer is exposed to expose a capacitor contact point contact zone on the substrate. A connection point contact hole 40 penetrating the stop layer 34 and the first insulating layer 30 is formed, and (f) FIG. 2-a plug filling the connection point contact hole 40 while making electrical and mechanical contact with the capacitor connection point contact zone 18. 42, and (g) FIG. 3—a planarization layer 44 is formed on the etching sealing layer 34 and the plug 42;
A crown hole 46 is formed in the planarization layer 44 while exposing the peripheral portions of the plug 42 and the etching sealing layer 34, and the crown hole is defined so as to be defined by the remaining portion 44A of the planarization layer. FIG. 4) While partially filling the crown hole, the etching sealing layer, the plug 42,
Then, a first polysilicon layer 50 is deposited on the first flattening layer remaining portion 44A, and (j) an optical treatment—an HSG layer 52 is formed on the first polysilicon layer 50, and (k) FIG. A sacrificial layer 54 made of borophosphosilicate glass is formed on one polysilicon layer 50 so that a crown hole 46 is formed.
And (l) removing the upper portion of the sacrificial layer 54 to expose the first polysilicon layer on the remaining portion 44A of the planarization layer, but the upper portion of the sacrificial layer 54 is etched back and chemically mechanically polished. (M) to remove the exposed portion of the first polysilicon layer 50 on top of the remaining planarization layer 44A, and (n) to selectively remove the remaining portion of the sacrificial layer 54 planarization layer 44A. The crown-shaped storage electrode rods 42 and 50 are formed, and (o) the capacitor dielectric layer 56 and the upper electrode rod 58 are formed on the crown-shaped storage electrode rods 42 and 50.
Is formed.

The first insulating layer is made of silicon oxide, BPSG
And a material selected from the group consisting of silicon oxide formed by a sub-air oxidation process. The etching sealing layer is made of silicon nitride, silicon oxynitride, or TEOS oxide, and the thickness of the etching sealing layer 34 ideally ranges from about 50 to 200A. The contact point contact hole 40 preferably has an opening size in the range of about 0.18 to 0.35 μm. Ideally, the plug 42 is made of doped polysilicon, which deposits a doped polysilicon layer having a thickness in the range of about 3,000 to 4,500 A and etches back the doped polysilicon layer. It is formed by doing.

The planarization layer 44 is formed from borophosphosilicate glass, silicon oxide or spin-on glass,
Desirably, the thickness ranges from about 7,000 to 13,000 A. The opening size of the crown hole 46 is preferably in the range of about 0.3 to 0.8 μm. The first polysilicon layer 50 is made of doped polysilicon and has a thickness of about 300 to 5
Ideally, it should be in the range of 00A. Hemispherical grains (H
SG) preferably has a thickness in the range of about 300 to 700A. The sacrificial layer 54 is formed of borophosphosilicate glass, silicon oxide, polymer or photoresist material and preferably has a thickness in the range of about 4,500 to 10,000A.

[0008] The present invention achieves these advantages in relation to known processing techniques. However, by referring to the following specification and accompanying drawings, the nature and advantages of the present invention will be better understood. The invention has the following advantages: (1) The etching sealing layer protects the underlying first insulating layer 30 from selective etching to form the plug 42 (see FIG. 2) and the sacrificial layer 44A etching back (see FIGS. 6 and 7). . Further, it is preferable that the etching sealing layer 34 is made of silicon oxynitride which reduces stress and improves productivity. Also, the etching sealing layer 34
Has a higher etching selectivity than an oxidizing substance such as TEOS oxide. (2) The polysilicon plug 42 process improves photolithographic accuracy, especially in processes of 0.25 μM and smaller, by reducing the asperities and obtaining a depth of focus (DOF) margin. Conventional plug holes are defined after the crown hole 46 etch (see FIG. 4). The polysilicon plug 42 process (see FIG. 2) consists of forming a polysilicon layer on the etch sealing layer 34 and etching back the polysilicon layer.

(3) Hemispherical grains (H
The crown cylindrical electrode rod 50 with the SG 52 removes any HSG grains that may fall from the outer crown wall. Additional objects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or
It will be understood if the present invention is embodied. The objects and advantages of the invention will be realized and attained by means of the instrumentalities and combinations particularly pointed out in the appended claims.

[0010]

BRIEF DESCRIPTION OF THE DRAWINGS The invention is explained in more detail by means of the accompanying figures. The present invention provides a method for forming a crown capacitor on a bit line. An important feature is the etching sealing layer 34 and the early plug 42 formation process. In the following description, numerous specific details are set forth, such as flow rates, pressure settings, thicknesses, etc., in order to provide a more thorough understanding of the present invention. But,
It will be apparent to one skilled in the art that the present invention may be embodied without these details. In other instances, well known processes have not been described in detail so as not to unnecessarily obscure the present invention. It should be readily understood by those skilled in the art that other types of devices may be provided on the DRAM chip, including additional process steps not described in this embodiment. For example, P in the P substrate
Wells and CMOS circuits will now be formed. It should also be understood that the drawings depict only one DRAM storage element of the group of elements simultaneously fabricated on the substrate. The capacitor can be used not only in a DRAM chip but also in another type of chip.
The figure shows an N-MOS device, but a P-MO
It should also be understood that an S device or a combination of N and P-MOS devices can be simultaneously formed on the substrate.

The method of fabricating a crown capacitor involving a memory device begins with selectively forming an isolation area 12 on the surface of a substrate 10 as it leaves a device area for semiconductor device fabrication. The substrate 10 includes a semiconductor wafer, active and passive devices formed in the wafer, and layers formed on the surface of the wafer. "substrate"
Includes a device formed in a semiconductor wafer and a layer covering the wafer. FIG. 1 shows a device structure 20, 22, 24, 26 formed in a device area of a substrate.
The device structure includes a capacitor contact point contact zone 18 (eg, a source zone). The device comprises a gate structure 20, a spacer 22, a source zone 18, a drain zone 16, a first insulating layer 24 and a second insulating layer 26.

The gate structure 20 preferably comprises a gate oxide layer, a polysilicon / polysite layer, and an upper gate isolation layer (all shown as layer 20). Source zone 18 and drain zone 16 are formed in the substrate using conventional processes. One of these doped zones is the capacitor junction contact zone where the bottom electrode rod of the capacitor contacts. The gate structure is formed by the M
It is a part of the OS memory device. The spacer 22 is preferably formed on the side wall of the gate structure. The first isolation layer 24 is preferably made of tetraethylorthosilane (T
EOS) silicon oxide produced by the process,
Ideally, the thickness is in the range of about 300 to 2,000A.

The second isolation layer 26 is preferably formed from an oxide, borophosphosilicate glass (BPSG), phosphite glass, borosilicate glass, and has a thickness of about 2,000 to 4,500 A. Ideally, the range is The present invention takes the form of a capacitor on bit line (COB) structure. The bit line contact hole 28 (FIG. 9)
The top view is preferably formed through the first isolation layer 30 and the second isolation layer exposing the underlying bit lines. Next, bit line contact holes 28 are filled with polysilicon from the second polysilicon layer to form bit line plugs and bit lines 29. This allows
A capacitor on bit line (COB) DRAM structure is completed. This structure can have a higher degree of integration, a larger capacitor area.

As shown in FIG. 1, the first insulating layer 30
Is formed on the second isolation layer 26, the device structure, the bit lines, and the substrate 10. The first insulating layer is preferably made of silicon oxide, BPSG, silicon oxide made by an SA-oxidation process, but most ideally consists of borophosphosilicate glass (BPSG). is there. Preferably, the first insulating layer has a thickness in the range of about 4,500 to 6,000A. As shown in FIG. 2, the etching sealing layer 34 is formed on the first insulating layer 30. The etch sealing layer 34 is preferably made of silicon nitride (SiN), silicon oxynitride, phosphite silicate glass, and TEOS oxide, but SiN or silicon oxide is more ideal and SiN Most ideally consists of Preferably, the etch sealing layer 34 of SiN or silicon oxide has a thickness in the range of about 55 to 200A. Preferably, the etch sealing layer 34 of TEOS or PSG has a thickness in the range of about 100 to 300A. Connection point contact hole 40 and poly plug 42 before crown 50B
As an important step, a connection point contact hole 40 is formed through the etching sealing layer 34 and the first insulating layer 30 to expose the capacitor connection point contact area 18 on the substrate 10.
The connection point contact hole 40 has an opening size of about 0.18 to 0.35 μm.
Is desirably within the range. Forming contact point contact holes so early in the process is that the planarization layer 44
The photo process is improved compared to the inventor's previous process of forming a contact point contact hole after the formation of the crown hole 46, and is therefore significantly advantageous. FIG.
See In addition, the etching sealing layer 34 is a very important photosensitive process for products of 0.25 μm and below.

Referring to FIG. 2, a plug 42 is formed to fill the contact point contact hole 40 while making electrical and mechanical contact with the capacitor contact point contact zone 18. Ideally, plug 42 is comprised of doped polysilicon. The plug is preferably formed by depositing a doped polysilicon layer having a thickness in the range of about 3,000 to 4,000 A, and etching back or chemically and mechanically polishing the doped polysilicon layer. The processing of the polysilicon plug 42 of the present invention can obtain a deeper depth of focus (DOF) margin in the 0.25 μM photo process. The polysilicon plug 42 process (see FIG. 2) is formed by forming a polysilicon layer on the etching sealing layer 34 and etching back the polysilicon layer. In contrast, the conventional method of forming a contact point contact is to etch through layers 30 and 44 simultaneously.

Referring to FIG. 3, a planarization layer 44 is formed on the etching sealing layer 34 and the plug 42. Planarization layer 44 is preferably comprised of borophosphosilicate glass (BPSG), silicon oxide, and spin-on glass (SOG), is most preferably formed of BPSG, and ideally has a thickness of It should be in the range of about 7,000 to 13,000A. FIG. 4 shows a state in which a crown hole 46 is formed on the planarization layer 44 so as to expose the peripheral portions of the plug 42 and the etching sealing layer 34. The crown hole 46 is contoured by the remaining portion 44A of the planarization layer. The crown hole 46 preferably has an opening size in the range of about 0.3 to 0.8 μm. FIG. 4 also illustrates a first conductive layer (eg, a first polysilicon layer) formed over the etch seal layer 34, the plug 42, and the remaining portion 44A of the first planarization layer while partially filling the crown hole 46. Layer) 5
Represents 0. The first conductive layer (eg, first polysilicon layer) 50 comprises doped polysilicon and may have a thickness in the range of about 300 to 500A. Later in the process, HSG grains are formed on the first conductive layer of polysilicon. Alternatively, the first conductive layer 50 is comprised of two layers, a first tungsten (W) layer and an overlying layer of titanium nitride (TiN).

FIG. 4 shows a preferred embodiment of the present invention. Polysilicon layer 50 doped with first conductive layer and HS
The G layer 52 includes two layers. The HSG layer 52 is an optional process. FIG. 8 shows a capacitor of the present invention formed without the HSG layer 52. In this optional process, a hemispherical grain (HSG) layer 52 is formed on the first polysilicon layer 50 to increase the surface area of the bottom electrode bar. The HSG layer preferably has a thickness (size) in the range of 300 to 700A. FIG.
As shown in FIG.
0, thereby filling the crown hole 46. The sacrificial layer 54 is preferably comprised of borophosphosilicate glass, silicon oxide, or a photoresist polymer, of which the photoresist polymer is most ideal. The sacrificial layer 54 has a thickness of about 4,500 to 10,000 A
Is preferably within the range.

Still referring to FIG. 5, the sacrificial layer 54A is then exposed to expose the first polysilicon layer 50 (and the HSG layer 52, if present) on the top surface of the remaining portion 44A of the planarization layer. Etched back. The etching back is ideally dry etching. Alternatively, the sacrificial layer may be subjected to chemical mechanical polishing. FIG. 6 shows etching back or chemical mechanical polishing (CM).
P) indicates a state where it is continuing. Rest 4 of the planarization layer
From above 4A, the top of first polysilicon layer 50 (and HSG layer 52, if present) is removed. The remaining layer 50 forms the top cylinder of the crown of the bottom electrode rod.
The top 50B of the first conductive layer is exposed as shown. In addition, refer to the diagram viewed from above in FIG. FIG.
As can be seen, the sacrificial layer 54 and the remaining portion 44A of the first planarization layer are selectively removed, thereby forming the crown-shaped storage electrode rods 42,50. Layer 54,
44A is preferably removed using HF dip etching. To remove photoresist residues, use H ₂
Preferably used SO ₄ and H ₂ O ₂ and NH ₄ OH.

One of the important features of the present invention is that silicon oxynitride (SixOyNz) protects the underlying first insulating layer 30 from selective etching (eg, dilute HF etching—vapor HF without water vapor). It is the etching sealing layer 34 desirably formed from. Further, the etching sealing layer is preferably made of silicon oxynitride, which greatly reduces stress and improves productivity. With continued reference to FIG. 7, a capacitor dielectric layer 56 and an upper electrode rod 58 are formed on the crown-shaped storage electrode rods 42, 50, thereby completing the manufacture of a dynamic random access memory (DRAM) device. The capacitor dielectric layer is typically silicon nitride and silicon oxide (NO) or ON
It is composed of an O layer. In making the ONO dielectric, the first or bottom silicon oxide (O) layer is typically a pure oxide grown to a thickness of about 15A. The silicon nitride layer (N) has a thickness in the range of about 80 to 200A.
It is formed by PCVD. The upper silicon oxide (O) layer can also be made in an oxidation furnace. The overall thickness of the ONO is
It is desirable to be about 100 to 250A.

The top surface electrode rod 58 is preferably formed by depositing an in-situ doped polysilicon layer by LPCVD (Low Pressure Chemical Vapor Deposition). Preferably, the thickness of the top surface electrode rod is in the range of about 1,000 to 2,000A. Alternatively, the top surface electrode rod may be composed of TiN and W layers. FIG. 9 shows a top view of the crown capacitor of the present invention. The present invention offers significant advantages over the prior art with respect to forming a 0.25 μm underlayer process capacitor. (1) The etching sealing layer protects the underlying first insulating layer 30 from selective etching to form the plug 42 (see FIG. 2) and the sacrificial layer 44A etching back (see FIGS. 6 and 7). Further, it is preferable that the etching sealing layer 34 is made of silicon oxynitride which reduces stress and improves productivity. Also, the etching sealing layer 34
Has a higher etching selectivity than an oxidizing substance such as TEOS oxide.

(2) The processing of the polysilicon plug 42 is particularly effective for
Improve photolithography accuracy by reducing irregularities and obtaining depth of focus (DOF) margins at 25 μM and smaller processes. The polysilicon plug 42 process (see FIG. 2) consists of forming a polysilicon layer on the etching encapsulation layer 34 and etching back the polysilicon layer. Forming the contact point so early in the process is that the photo process is not as efficient as the inventor's earlier process of forming the contact point contact hole after forming the crown hole 46 in the planarization layer 44. Improved, and thus significantly advantageous.
See FIG. If the connection point contact hole 40 is formed after the planarization layer 44 is formed, the depth of focus (DO
F) will reduce the exposure accuracy. in addition,
The etching sealing layer 34 is a very important photosensitive process for products of 0.25 μm and below.

(3) The hemispherical grains (H
The crowned cylindrical electrode rod 50 having SG) removes HSG grains that may fall from the outer crown wall. (4) The sacrificial layer 54 can be formed from a polymer that is a photoresist material, or borophosphosilicate glass. The general techniques used in the manufacture of integrated circuit components are well described in numerous publications. See, for example, "ULSI Technology", McGraw-Hill Company, Inc., 1997, by C.Y.Chang, S.M.S. These techniques can be widely used for manufacturing a structure in the present invention. In addition, individual steps in such a process can be accomplished using commercially available integrated circuit manufacturing machines. Representative technical data will be described based on the current technology as particularly indispensable for understanding the present invention. Those skilled in the art will appreciate that future developments in the art will require appropriate rework.

Although the present invention has been described in terms of a particularly preferred embodiment, those skilled in the art will recognize that various changes may be made in form and detail without altering the spirit and scope of the invention. I can understand. The features and advantages of the semiconductor device of the present invention, and the more detailed manufacturing process of the semiconductor device of the present invention, will be more clearly understood from the following description of the accompanying drawings, in which like or corresponding elements, zones and parts are indicated by reference numerals. Understood.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a method for manufacturing a crown capacitor according to the present invention.

FIG. 2 is a sectional view showing a method for manufacturing a crown capacitor according to the present invention.

FIG. 3 is a sectional view showing a method for manufacturing a crown capacitor according to the present invention.

FIG. 4 is a cross-sectional view illustrating a method for manufacturing a crown capacitor according to the present invention.

FIG. 5 is a sectional view showing a method for manufacturing a crown capacitor according to the present invention.

FIG. 6 is a sectional view showing a method for manufacturing a crown capacitor according to the present invention.

FIG. 7 is a cross-sectional view illustrating a method for manufacturing a crown capacitor according to the present invention.

FIG. 8 shows a hemispherical grain (HSG) layer 5 according to the present invention.
2 is a cross-sectional view depicting an embodiment of the invention relating to the manufacture of a crown capacitor without 2; FIG.

FIG. 9 is a top plan view depicting a method involved in fabricating a crown capacitor in a semiconductor memory device according to the present invention.

[Explanation of symbols]

 Reference Signs List 10 substrate 16 drain zone 18 source zone 20 gate structure 22 spacer 24 insulating layer 26 insulating layer 28 bit line contact hole 29 bit line 30 insulating layer 34 etching sealing layer 40 connection point contact hole 42 plug 44 planarization layer 46 crown hole Reference Signs List 50 polysilicon layer 52 HSG layer 54 sacrificial layer 56 capacitor dielectric layer 58 electrode rod

──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-6-112430 (JP, A) International Electron Devices Meetings (IEDM) '92 p. 259-262 (58) Fields surveyed (Int. Cl. ⁷ , DB name) H01L 27/108 H01L 21/8242

Claims (12)

(57) [Claims] 1. A method for manufacturing a crown capacitor for a memory device, comprising the steps of: (a) selectively separating an element isolation region on a surface of a substrate where an element formation region for manufacturing a semiconductor device is to be separated; (B) forming the device structure in the substrate element forming region, the device structure including a capacitor contact region on the substrate; and (c) forming the device structure. Forming a first insulating layer on the body and the substrate; (d) forming an etching stop layer on the first insulating layer; and (e) exposing the capacitor contact region on the substrate. and forming a connecting point contact hole through the etch stop layer and the first insulating layer, it is filled with (f) the connection point contact holes, the capacitor contact region and collector And exposing and forming a plug that mechanical contact, forming a planarizing layer (g) the etching blocking layer and on the plug, the peripheral portion of the (h) the plug and the etching stopper layer Forming a crown hole in the flattening layer while causing the crown hole to be contoured by the remaining portion of the flattening layer; and (i) performing the etching while partially filling the crown hole. Depositing a first polysilicon layer on the blocking layer, the plug, and the remaining portion of the first planarization layer; and (j) forming a sacrificial layer on the first polysilicon layer, thereby forming the crown hole. Filling; (k) removing an upper portion of the sacrificial layer to expose the first polysilicon layer on the remaining portion of the planarization layer, wherein the upper portion of the sacrificial layer is etched back and etched. Removing by a process selected from the group consisting of mechanical polishing; (l) removing an exposed portion of the first polysilicon layer on top of the remaining portion of the planarization layer; Selectively removing the remaining portion of the sacrificial layer and the planarization layer, thereby forming a crown-shaped storage electrode rod; and (n) forming a capacitor dielectric layer and an upper electrode rod on the crown-shaped storage electrode rod. A method comprising the steps of: 2. The method of claim 1 wherein said first polysilicon layer comprises two layers: a doped polysilicon layer and a hemispherical grain (HSG) layer. 3. The device as claimed in claim 1, wherein the device comprises a gate structure, a spacer, a first isolation layer of silicon oxide, ideally made of tetraethylorthrasin (TEOS), preferably silicon oxide, borophosphosilicate glass and The method of claim 1, comprising a second isolation layer of borosilicate glass (BSG), and bit line contacts and bit lines. 4. The method according to claim 1, wherein the first insulating layer is formed of a material selected from the group consisting of silicon oxide, borophosphosilicate glass, and silicon oxide formed by low- pressure oxidation. The method according to claim 1, wherein 5. The method according to claim 1, wherein the opening size of the connection point contact hole is in a range of about 0.18 to 0.35 μm . 6. are made of polysilicon the plug is doped, the plug is about 3000 thick 4,500 Å
Depositing a doped polysilicon layer in the range of
The method of claim 1, wherein the method is formed by etching the doped polysilicon layer. 7. The method of claim 1, wherein the planarizing layer comprises a material selected from the group consisting of borophosphosilicate glass, silicon oxide, and spin-on glass, and has a thickness of about 7,000 to 1
The method of claim 1, wherein the range is 3,000 square meters . 8. The method of claim 1, wherein the size of the opening in the crown hole is in the range of about 0.3 to 0.8 μm . 9. The method of claim 1 wherein said first polysilicon layer comprises doped polysilicon and has a thickness in the range of about 300 to 500 degrees . 10. The method of claim 1, wherein said HSG layer has a thickness in the range of about 300 to 700 degrees . 11. The sacrificial layer is formed from a material selected from the group consisting of BPSG, silicon oxide, a polymer, and a photoresist material, and the thickness of the sacrificial layer ranges from about 4,500 to 10,000 mm. The method of claim 1, wherein: 12. A method for manufacturing a crown capacitor for a memory device, comprising: (a) selectively separating an element isolation region on a surface of a substrate where an element formation region for manufacturing a semiconductor device is to be separated; Forming a gate structure, a spacer, a first isolation layer made of silicon oxide made of tetraethylorthosilane (TEOS), and a second isolation made of silicon oxide in the substrate element formation region. layer, and is composed of a bit line contact and the bit line, the capacitor contact territory on the substrate
Forming a device structure comprising a band, it is selected from the group consisting of silicon oxide formed (c) to the devices structures and the substrate, a silicon oxide, BPSG, and under reduced oxidation consisting of material
Forming a first insulating layer, (d) the first insulating layer, a silicon nitride, silicon oxynitride, and made from selected materials from the group consisting of TEOS oxide, a thickness of about 50 Forming an etch stop layer in the range of 200 ° ; and (e) opening a hole size of about 0.18 to 0.35 through the etch stop layer and the first insulating layer to expose the capacitor contact area on the substrate. μm range
Forming a contact point contact hole; and (f) depositing a doped polysilicon layer having a thickness in the range of about 3,000 to 4,500 ° on the contact point contact hole, and etching the doped polysilicon layer. By
Filling the connection point contact hole with the capacitor contact
A step forming a plug in electrical and mechanical contact with the area
And floors, in (g) the etching blocking layer and on the plug, HouA phosphosilicate glass, silicon oxide, and consists substances selected from the group consisting of spin-on glass, its thickness is from about 7,000 13000 A planarization layer in the range of
(H) forming an opening having a size of about 0.3 in the planarizing layer while exposing the peripheral portions of the plug and the etching stopper layer;
Forming a crown hole which is in the range of 0.8 μm and is contour- constrained by the remaining portion of the flattening layer ; (i) the etching stopper layer, the plug, while partially filling the crown hole; and on to the rest of the first planarization layer, depositing a first polysilicon layer thickness made of doped polysilicon is located about 300 in the range of 500Å
A step of, (j) the thickness of the first polysilicon layer is 700Å to about 300
Forming a hemispherical grain (HSG) layer in the range of, (k) to the first polysilicon layer, forming BPSG, silicon oxide, polymer, or from a material selected from the group consisting of photoresist material And the thickness is about 4,
Form a sacrificial layer in the range of 500 to 10,000
Filling the round holes; (l) removing an upper portion of the sacrificial layer to expose the first polysilicon layer on the remaining portion of the planarization layer, wherein the upper portion of the sacrificial layer is etched. Removing by a process selected from the group consisting of backing and chemical mechanical polishing; (m) removing the exposed portion of the first polysilicon layer on top of the remaining portion of the planarization layer; (n) selectively removing the remaining portion of the sacrificial layer and the planarization layer, thereby forming a crown-shaped storage electrode rod; and (o) a capacitor dielectric layer and an upper electrode on the crown-shaped storage electrode rod. Forming a bar.