KR20030094622A - A Method for fabricating semiconductor device having inner capacitor - Google Patents

Abstract

PURPOSE: A method for fabricating a semiconductor device with an inner capacitor is provided to improve yield and reliability of the semiconductor device by guaranteeing the margin of a process for etching a metal contact hole. CONSTITUTION: The inner capacitor is formed on the first interlayer dielectric covering a predetermined conductive structure. The second interlayer dielectric is formed on the resultant structure including the inner capacitor. The first photoresist(29) having a thickness corresponding to the metal contact hole etching target is formed on the second dielectric layer. A hard mask layer is formed on the first photoresist. The second photoresist(31) thinner than the first photoresist is formed on the hard mask layer. The second photoresist is patterned through a photolithography process using a metal contact hole mask. The hard mask layer is etched by using the patterned second photoresist as an etch mask. The first photoresist is etched by using the etched hard mask layer as an etch mask. The first and second interlayer dielectrics are etched to form the metal contact hole exposing the conductive structure by using at least the etched photoresist as an etch mask.

Description

A method for fabricating semiconductor device having inner capacitor

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly, to a metal contact process in a semiconductor device manufacturing process including an inner capacitor.

Since inner capacitors are structurally stable, relatively large cell capacitances can be secured, and thus, they are attracting attention as capacitors of ultra-high density semiconductor memory devices.

Meanwhile, as the design rule continues to decrease, the height of the capacitor structure is inevitably increased to secure sufficient cell capacitance (about 30 fF), and the increase in the height of the capacitor structure makes it difficult to etch the capacitor oxide film (sacrifice film). Rather, it is increasing the difficulty of the subsequent metal contact hole etching process.

Currently, a memory device having a design rule of 0.16 μm maintains at least 28000 μm of an interlayer insulating layer etch target when etching a metal contact hole, and the etching target is 35000 μm or more considering the process margin such as excessive etching.

1A to 1C are diagrams illustrating a metal contact hole forming process according to the prior art.

FIG. 1A shows a state where an inner capacitor (not shown) forming process is completed and flattened with the interlayer insulating film 18. A brief description will be made of a process for forming the illustrated structure, first forming an isolation region 11 on a silicon substrate 10 to define an active region, and then forming a gate oxide layer 12 and a word line 13 on the active region. And the bit line 15a is formed. When the bit line 15a is formed, the interlayer insulating layer 14 on the word line 13 is etched to simultaneously form the contact pads 15b. Subsequently, the interlayer insulating film 16 and the etch stop nitride film 17 are deposited, and a contact hole is formed through a mask process and an etching process using a charge storage electrode contact mask, and a charge storage electrode contact plug (not shown) is formed in the contact hole. ). Subsequently, a PSG (phosphosilicate glass) film, which is a sacrificial film, is deposited on the entire structure, the PSG film is selectively etched through a mask and an etching process using a charge storage electrode mask, and then a polysilicon film for a charge storage electrode is formed along the entire structure surface. (Not shown) is deposited, and the polysilicon film is polished through the CMP process to define the unit charge storage electrode. Thereafter, the PSG film is removed, the dielectric thin film and the plate electrode are sequentially deposited, and then the interlayer insulating film 18 is deposited to planarize the entire structure.

Next, as shown in FIG. 1B, a photoresist is applied on the interlayer insulating layer 18 and a photoresist pattern 19 is formed through an exposure and development process using a metal contact mask.

Subsequently, as shown in FIG. 1C, using the photoresist pattern 19 as an etch mask, the interlayer insulating film 18, the etch stop nitride film 17, and the interlayer insulating film 16 are sequentially dry-etched to form the bit line 15a and The metal contact hole exposing the contact pad 15b is formed, and then the residual photoresist pattern 19 is removed.

However, as described above, in consideration of securing cell capacitance, an etch target of an interlayer insulating layer is increasing during metal contact hole etching, causing an interlayer insulating layer loss (A) due to photoresist loss during etching, and such an interlayer insulating layer loss (A ) Is a factor that causes the bridge between the metallization, and there is a problem that drops the margin of the subsequent metallization etching process.

On the other hand, in order to prevent the interlayer dielectric loss A, the thickness of the photoresist used as an etching mask may be increased, but considering the optical margin such as the depth of focus (DOF), it is difficult to secure the thickness of 1.0 μm or more.

The present invention has been proposed to solve the above problems of the prior art, and an object of the present invention is to provide a method for manufacturing a semiconductor device that can prevent the loss of the interlayer dielectric layer during metal contact hole etching due to the height of the inner capacitor.

1a to 1c is a process diagram of forming a metal contact hole according to the prior art.

2a to 2d are metal contact hole forming process diagrams according to one embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

28: interlayer insulating film

29: first photoresist

30: plasma oxide film

31: second photoresist

According to an aspect of the present invention for achieving the above technical problem, forming an inner capacitor on the first interlayer insulating film covering a predetermined conductive structure; Forming a second interlayer insulating film on the entire structure where the inner capacitor is formed; Applying a first photoresist having a thickness corresponding to the metal contact hole etching target on the second interlayer insulating layer; Forming a hard mask layer on the first photoresist; Applying a second photoresist thinner than the first photoresist on the hard mask layer; Patterning the second photoresist through a photolithography process using a metal contact hole mask; Etching the hard mask layer using the patterned second photoresist as an etch mask; Etching the first photoresist using the etched hard mask layer as an etch mask; And etching the first and second interlayer insulating layers using at least the etched photoresist as an etch mask to form metal contact holes exposing the conductive structure.

In the present invention, in order to increase the margin of the metal contact hole etching process according to the height of the inner capacitor, an etch mask structure having a triple structure of photoresist / hard mask layer / photoresist is used. That is, since the hard mask layer is patterned using a thin photoresist to secure an optical margin, the patterned hard mask layer is patterned using a etch mask to pattern a thick photoresist and used as an etch mask when etching the interlayer insulating film. Process margins can be secured.

Hereinafter, preferred embodiments of the present invention will be introduced in order to enable those skilled in the art to more easily carry out the present invention.

2A through 2D are diagrams illustrating a metal contact hole forming process according to an embodiment of the present invention.

FIG. 2A shows a state where an inner capacitor (not shown) forming process is completed and flattened with the interlayer insulating film 28. A brief description will be made of a process for forming the illustrated structure, first, forming an isolation layer 21 on a silicon substrate 20 to define an active region, and then forming a gate oxide layer 22 and a word line 23 on the active region. And the bit line 25a is formed. When the bit line 25a is formed, the interlayer insulating layer 24 on the word line 23 is etched to simultaneously form the contact pads 25b. Subsequently, an interlayer insulating layer 26 and an etch stop nitride film 27 are deposited, and a contact hole is formed through a mask process and an etching process using a charge storage electrode contact mask, and a charge storage electrode contact plug (not shown) is formed in the contact hole. ). Subsequently, a PSG (phosphosilicate glass) film, which is a sacrificial film, is deposited on the entire structure, the PSG film is selectively etched through a mask and an etching process using a charge storage electrode mask, and then a polysilicon film for a charge storage electrode is formed along the entire structure surface. (Not shown) is deposited, and the polysilicon film is polished through the CMP process to define the unit charge storage electrode. Thereafter, the PSG film is removed, the dielectric thin film and the plate electrode are sequentially deposited, and then the interlayer insulating film 28 is formed to planarize the entire structure.

Next, as shown in FIG. 2B, the first photoresist 29 is coated on the interlayer insulating film 28 to a thickness of 1.0 μm or more, and a plasma oxide film (PE-oxide) 30 having a thickness of 500 to 1500 Å is formed thereon. ), The second photoresist 31 is applied to the upper portion with a thickness of 0.6 μm or less, and the second photoresist 31 is patterned by performing exposure and development processes using a metal contact mask. At this time, it is preferable that the second photoresist 31 is a photoresist of HOPJ series, SE series, I-line series series.

Next, as shown in FIG. 2C, the plasma oxide layer 30 is etched using the patterned second photoresist 31 as an etch mask, and the lower first first portion is etched using the etched plasma oxide layer 30 as an etch mask. The photoresist 29 is patterned.

Subsequently, as shown in FIG. 2D, the interlayer insulating film 28, the etch stop nitride film 27, and the interlayer insulating film 26 are sequentially dried using the plasma oxide film 30 and the first photoresist 29 as an etching mask. Etching is performed to form a metal contact hole exposing the bit line 25a and the contact pad 25b, and then the remaining first photoresist 29 is removed.

In the present invention, since it is possible to perform metal contact hole etching using a photoresist having a thickness of 1.0 μm or more, an etching target of about 30000 μs can be etched without loss of an interlayer insulating film.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

For example, in the above-described embodiment, the case where the plasma oxide film is used as the hard mask layer used for the photoresist patterning has been described as an example. Instead, another material film (eg, nitride film) having an etching selectivity with the photoresist is substituted. The present invention also applies to use as a sacrificial film.

The present invention described above can increase the yield and reliability of the semiconductor device by securing the margin of the metal contact hole etching process.

Claims (5)

Forming an inner capacitor on the first interlayer insulating film covering the predetermined conductive structure; Forming a second interlayer insulating film on the entire structure where the inner capacitor is formed; Applying a first photoresist having a thickness corresponding to the metal contact hole etching target on the second interlayer insulating layer; Forming a hard mask layer on the first photoresist; Applying a second photoresist thinner than the first photoresist on the hard mask layer; Patterning the second photoresist through a photolithography process using a metal contact hole mask; Etching the hard mask layer using the patterned second photoresist as an etch mask; Etching the first photoresist using the etched hard mask layer as an etch mask; And Etching the first and second interlayer insulating layers using at least the etched photoresist as an etch mask to form a metal contact hole exposing the conductive structure Semiconductor device manufacturing method comprising a. The method of claim 1, Wherein the first photoresist is applied to a thickness of at least 1.0 μm. The method of claim 2, The second photoresist is a semiconductor device manufacturing method, characterized in that for coating to a thickness of not more than 0.6㎛. The method according to any one of claims 1 to 3, The hard mask layer is a semiconductor device manufacturing method, characterized in that the plasma oxide film. The method of claim 4, wherein The hard mask layer is a semiconductor device manufacturing method, characterized in that formed to a thickness of 500 ~ 1500Å.