KR19980048867A - How to form a storage electrode of a capacitor - Google Patents

Abstract

The present invention again discloses a method of forming a storage electrode of a capacitor. This includes forming an interlayer insulating layer on a semiconductor substrate; Forming a contact hole by etching the interlayer insulating layer to expose a predetermined region of the semiconductor substrate; Forming a first conductive layer in the contact hole by depositing a conductive material on the entire surface of the semiconductor substrate on which the contact hole is formed and then etching back; Forming an insulating film on the semiconductor substrate on which the first conductive layer is formed; Patterning the insulating film to expose a predetermined region including the first conductive layer using a photolithography process; Depositing a conductive material on the semiconductor substrate to form a second conductive layer; Etching back so that some of the second conductive layer remains; And removing the insulating film. As a result, the effective area of the storage electrode is increased within the limited area, thereby increasing the capacity of the capacitor.

Description

How to form a storage electrode of a capacitor

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a storage electrode of a capacitor for increasing the effective area of the storage electrode.

With the development of semiconductor manufacturing technology and the expansion of application fields, development of large-capacity memory devices is progressing.

Therefore, the area of the unit memory cell decreases with the higher integration of the circuit, but the cell capacitance must have a specific value or more.

Particularly, in a DRAM (dynamic random access memory) device including a capacitor as a means for storing information and a switching transistor as a means for controlling signal transmission, a decrease in cell capacitance caused by a decrease in the area of a unit memory cell is achieved. Since the readability is lowered and the soft error rate is increased, a cell capacitance of a specific value or more must be secured for high integration of the semiconductor memory device.

1A to 1D are cross-sectional views illustrating a method of forming a storage electrode of a capacitor according to the prior art.

Reference numeral 1 is a semiconductor substrate, 3 is an interlayer insulating layer, 5 is a first insulating film, 7 · 7a is a second insulating film, 8 · 10 is a contact hole, 9 is a spacer, 11 is a conductive layer, 11a represents a storage electrode and 13 占 a represents a photosensitive film pattern, respectively.

Referring to FIG. 1A, a step of forming an interlayer insulating layer (patterned as 3 in a subsequent step) on a semiconductor substrate 1 on which a transistor (not shown) is formed, and a first insulating film (following step) on the interlayer insulating layer Patterned to 5 at < RTI ID = 0.0 > and then < / RTI > a second insulating film (patterned to 7 at a subsequent process), followed by etching the second insulating film / first insulating film / interlayer insulating layer so as to expose the source region of the transistor. (8) and the second insulating film (7) / the first insulating film (5) / the interlayer insulating layer (3) and the step of depositing an insulating material on the semiconductor substrate (1) formed with the contact hole (8) Etching is performed to sequentially form a spacer 9 on the sidewall of the contact hole 8.

The first insulating film 5 and the spacer 9 are formed using SiON.

The second insulating layer 7 is formed using high temperature oxide (HTO).

Referring to FIG. 1B, a process of forming a conductive layer 11 by depositing a conductive material on the entire surface of the resultant material to sufficiently fill the contact hole 10 and a photoresist film on the conductive layer 11 (13 in a subsequent process) The photoresist is etched to form a photoresist pattern 13 so that the portion where the storage electrode is to be formed is exposed.

Referring to FIG. 1C, the conductive layer 11 is etched using the photoresist pattern 13 as a mask to form a storage electrode 11a.

At this time, in the etching process, a dry etching process is performed first to generate a polymer to form a slope-type storage electrode 11a, and then a wet etching process is performed to undercut the lower portion of the storage electrode 11a. An undercut second insulating film 7a is formed.

Referring to FIG. 1D, the storage electrode of the capacitor is completed by removing the photoresist pattern 13.

According to the storage electrode forming method as described above, if the area of the unit memory cell is reduced, the area of the storage electrode is also reduced, thereby reducing the capacitance of the capacitor. Therefore, increasing the height of the storage electrode in order to increase the capacity of the capacitor increases the step between the cell array portion and the peripheral circuit portion, and when the etching process using the polymer excessively causes a bridge between the storage electrodes. have.

An object of the present invention is to provide a method for forming a storage electrode of a capacitor for increasing the effective area of the storage electrode.

1A to 1D are cross-sectional views illustrating a method of forming a storage electrode of a capacitor according to the prior art.

2A through 2E are cross-sectional views illustrating a method of forming a storage electrode of a capacitor according to the present invention.

The present invention to achieve the above object, forming an interlayer insulating layer on a semiconductor substrate; Forming a contact hole by etching the interlayer insulating layer to expose a predetermined region of the semiconductor substrate; Forming a first conductive layer in the contact hole by depositing a conductive material on the entire surface of the semiconductor substrate on which the contact hole is formed and then etching back; Forming an insulating film on the semiconductor substrate on which the first conductive layer is formed; Patterning the insulating film to expose a predetermined region including the first conductive layer using a photolithography process; Depositing a conductive material on the semiconductor substrate to form a second conductive layer; Etching back so that some of the second conductive layer remains; And removing the insulating layer.

The insulating layer may be formed using any one of BPSG (Boron-Phosphorus Silicate Glass), PSG (Phosphorus Silicate Glass), and High Temperature Oxide (HTO), or an oxide film may be formed by plasma chemical vapor deposition (PE-CVD; Plasma Enhenced). Chemical Vapor Deposition) is preferable.

The insulating film is preferably formed to a thickness of 6000 to 10000 kPa in consideration of the height of the storage electrode to be formed.

The second conductive layer is preferably formed to a thickness of 6000 to 10000 kPa in consideration of the thickness remaining on the first conductive layer during the subsequent etch back process.

Therefore, the method of forming a storage electrode of a capacitor according to the present invention has the advantage that the effective area of the storage electrode is increased within a limited area, thereby increasing the capacity of the capacitor.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

2A through 2E are cross-sectional views illustrating a method of forming a storage electrode of a capacitor according to the present invention.

Reference numeral 21 is a semiconductor substrate, 23 is an interlayer insulating layer, 25 is a first insulating film, 26 is a contact hole, 27 is a spacer, 29 is a first conductive layer, 31.31a is a second insulating film, 33 represents a photosensitive film pattern, 35 占 a represents a second conductive layer, and 36 represents a storage electrode.

Referring to FIG. 2A, a step of forming an interlayer insulating layer (patterned as 23 in a subsequent step) on a semiconductor substrate 21 on which a transistor (not shown) is formed, and a first insulating film (following step) on the interlayer insulating layer Patterning the second insulating film / interlayer insulating layer to expose the source region of the transistor, thereby forming the contact hole 26 and the second insulating film 25 / interlayer insulating layer 23. Forming a spacer 27 on the sidewalls of the contact hole 26 by depositing an insulating material on the semiconductor substrate 21 on which the contact hole 26 is formed and then etching the same. After the conductive material is deposited on the entire surface of the resultant to sufficiently fill the etch, the first conductive layer 29 is formed in the contact hole 26 by etching back until the second insulating layer 25 is exposed. .

The first insulating layer 25 and the spacer 29 are formed using SiON, and the first conductive layer 29 is formed using polycrystalline silicon doped with impurities.

Referring to FIG. 2B, a process of forming a second insulating film 31 on the semiconductor substrate 21 on which the contact hole 26 is formed, and a photosensitive film on the second insulating film 31 (patterned as 33 in a subsequent process) ), And then forming the photoresist pattern 33 by etching the photoresist so that the portion where the storage electrode is to be formed is exposed.

The second insulating layer 31 is formed using an insulating material, for example, any one of BPSG (Boron-Phosphorus Silicate Glass), PSG (Phosphorus Silicate Glass), and High Temperature Oxide (HTO), or the oxide film is formed using a plasma chemical vapor phase. It is formed by deposition (PE-CVD; Plasma Enhenced Chemical Vapor Deposition). At this time, the thickness is the height of the storage electrode to be formed, that is, 6000 to 10000 kPa.

Referring to FIG. 2C, a process of forming the second insulating film 31a by etching the second insulating film 31 using the photosensitive film pattern 33 as a mask, removing the photosensitive film pattern 33, and the semiconductor A conductive material is deposited on the entire surface of the substrate 21 to form the second conductive layer 35.

The second conductive layer 35 is 6000 to 10000 kPa in consideration of the thickness remaining on the first conductive layer 29 during the subsequent etch back process.

Referring to FIG. 2D, the second conductive layer 35a is formed by etching back a portion of the second conductive layer 35 to remain on the first insulating film 25 and the sidewall of the second insulating film 31a. .

In this case, the thickness of the second conductive layer 35a may be adjusted by adjusting the etching rate and the etching gas.

Referring to FIG. 2E, the storage electrode 36a including the second conductive layer 35a and the first conductive layer 29 is completed by removing the second insulating layer 31a.

The removal process of the second insulating layer 31a is performed by a dry etching method using an etching selectivity of polycrystalline silicon and an insulating material.

As a result, it can be seen that the effective area is increased by the portion indicated by the solid line as compared with the related art.

The present invention is not limited to this, and it is apparent that many modifications are possible by those skilled in the art within the technical idea of the present invention.

As described above, the method of forming the storage electrode of the capacitor according to the present invention has the advantage that the effective area of the storage electrode is increased within the limited area, thereby increasing the capacity of the capacitor.

Claims (7)

Forming an interlayer insulating layer on the semiconductor substrate; Forming a contact hole by etching the interlayer insulating layer to expose a predetermined region of the semiconductor substrate; Forming a first conductive layer in the contact hole by depositing a conductive material on the entire surface of the semiconductor substrate on which the contact hole is formed and then etching back; Forming an insulating film on the semiconductor substrate on which the first conductive layer is formed; Patterning the insulating film to expose a predetermined region including the first conductive layer using a photolithography process; Depositing a conductive material on the semiconductor substrate to form a second conductive layer; Etching back to leave some of the second conductive layer; and And removing the insulating film. The storage electrode of claim 1, wherein the insulating layer is formed using any one of boron-phosphorus silicate glass (BPSG), phosphorus silicate glass (PSG), and high temperature oxide (HTO). Forming method. The method of claim 1, wherein the insulating layer is formed by plasma-enhanced chemical vapor deposition (PE-CVD). The method of claim 1, wherein the insulating layer is formed in consideration of a height of a storage electrode to be formed. The method for forming a storage electrode of a capacitor according to claim 1, wherein the insulating film has a thickness of 6000 to 10000 GPa. The method of claim 1, wherein the second conductive layer is formed in consideration of a thickness remaining on the first conductive layer during a subsequent etch back process. The method for forming a storage electrode of a capacitor according to claim 1, wherein the second conductive layer has a thickness of 6000 to 10000 GPa.