JP2002299486A - Package for storing optical semiconductor element - Google Patents

Package for storing optical semiconductor element

Info

Publication number
JP2002299486A
JP2002299486A JP2001096110A JP2001096110A JP2002299486A JP 2002299486 A JP2002299486 A JP 2002299486A JP 2001096110 A JP2001096110 A JP 2001096110A JP 2001096110 A JP2001096110 A JP 2001096110A JP 2002299486 A JP2002299486 A JP 2002299486A
Authority
JP
Japan
Prior art keywords
optical semiconductor
semiconductor element
package
thermal expansion
insulating substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001096110A
Other languages
Japanese (ja)
Inventor
Masanobu Ishida
政信 石田
Mitsuo Yanagisawa
美津夫 柳沢
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP2001096110A priority Critical patent/JP2002299486A/en
Publication of JP2002299486A publication Critical patent/JP2002299486A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/1615Shape
    • H01L2924/16195Flat cap [not enclosing an internal cavity]

Landscapes

  • Optical Couplings Of Light Guides (AREA)

Abstract

PROBLEM TO BE SOLVED: To enhance mounting reliability for an external circuit board having a relatively large coefficient of thermal expansion and for the package of an optical semiconductor element. SOLUTION: The package for storing an optical semiconductor element comprises an insulating board and a wiring conductor layer, a ceramic wiring board having an optical semiconductor element mounting part on the upper surface of the insulating board, a frame fixed onto the wiring board while surrounding the optical semiconductor element mounting part and provided with a part for introducing an optical signal, a cover member fixed to the upper surface of the frame and sealing the optical semiconductor element, and a terminal for connection with an external circuit board provided on the side of the insulating board opposite to the optical semiconductor element mounting part wherein the coefficient of thermal expansion on the side of the insulating board provided with the connection terminal is set larger than that on the optical semiconductor element mounting side.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、内部に光半導体素
子を収納するための光半導体素子収納用パッケージに関
するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an optical semiconductor element housing package for housing an optical semiconductor element therein.

【0002】[0002]

【従来技術】従来、光半導体素子を収納する光半導体素
子収納用パッケージは、一般にFe/Ni/Co合金や
Cu/W合金等の凹状の金属製容器と、その容器の開口
部を封止するための金属製の蓋体から構成されており、
この金属製容器内の底部中央に光半導体素子を搭載固定
するための搭載部が設けられている。また、この金属製
容器の側壁部には、アルミナなどのセラミックスからな
る絶縁基板の表面に配線導体層を設けた配線基板および
光ファイバーを導入する導入部が側壁部を貫通して設け
られ、例えば、光ファイバーから送られた信号を光半導
体素子で電気信号に変換し、配線基板を通じて外部回路
に伝達する構造からなる。
2. Description of the Related Art Conventionally, an optical semiconductor element housing package for housing an optical semiconductor element generally seals a concave metal container such as an Fe / Ni / Co alloy or a Cu / W alloy and an opening of the container. It consists of a metal lid for
A mounting portion for mounting and fixing the optical semiconductor element is provided at the center of the bottom of the metal container. In addition, on the side wall portion of the metal container, a wiring board provided with a wiring conductor layer on the surface of an insulating substrate made of ceramics such as alumina and an introduction portion for introducing an optical fiber are provided through the side wall portion. It has a structure in which a signal sent from an optical fiber is converted into an electric signal by an optical semiconductor element and transmitted to an external circuit through a wiring board.

【0003】また、最近では、部品の軽薄化に伴い光半
導体素子収納用パッケージを所定の外部回路基板に実装
する形態が要求されている。この要求に対して最近で
は、従来から周知の多層セラミック加工手法を用いて、
アルミナなどのセラミック絶縁基板の表面や内部にタン
グステンからなる配線導体層を形成し、その表面に、光
半導体素子搭載部を形成し、この搭載部を囲むようにし
て枠体を取り付けてキャビティを形成し、これを蓋体に
よって封止したパッケージも提案されている。このパッ
ケージでは、配線基板の側面や底面にリード端子を取着
し半田によって実装したり、底面にピン端子を取着して
外部回路基板に、ピンを垂直挿入することによって外部
回路基板に実装することも提案されている。
In recent years, with the reduction in the weight of components, a form in which an optical semiconductor element housing package is mounted on a predetermined external circuit board has been required. In response to this demand, recently, using a conventionally known multilayer ceramic processing method,
Forming a wiring conductor layer made of tungsten on the surface or inside of a ceramic insulating substrate such as alumina, forming an optical semiconductor element mounting part on the surface, attaching a frame so as to surround this mounting part, forming a cavity, A package in which this is sealed with a lid has also been proposed. In this package, lead terminals are attached to the side and bottom of the wiring board and mounted by soldering, or pin terminals are attached to the bottom and mounted on the external circuit board by vertically inserting pins into the external circuit board It has also been suggested.

【0004】[0004]

【発明が解決しようとする課題】近年の光通信の拡大に
伴い、前記光半導体素子収納用パッケージの外部回路基
板への実装を自動化すること要求されているが、従来の
リード端子やピン端子を用いたパッケージの場合、リー
ド端子は通常、パッケージと外部回路基板基板との実装
における応力の発生を緩和する為に長めに設定されてい
るために、実装時にずれが発生しやすく、また実装時の
半田量を一定にできないなどの問題から、高周波信号の
伝達がずれによって変動するという問題があった。ま
た、ピン端子を用いた場合では、挿入したピンが前記外
部回路基板基板から突出し、これによって高周波信号の
反射損失が大きくなるという問題があった。
With the recent expansion of optical communication, it has been required to automate the mounting of the optical semiconductor element housing package on an external circuit board. In the case of the package used, the lead terminals are usually set to be long to reduce the generation of stress in the mounting of the package and the external circuit board. There is a problem that the transmission of the high-frequency signal fluctuates due to a shift due to a problem that the amount of solder cannot be made constant. Further, in the case where the pin terminal is used, there is a problem that the inserted pin protrudes from the external circuit board, thereby increasing the reflection loss of the high-frequency signal.

【0005】これらの問題に対して、リード端子やピン
端子に代えて、ボール状などの半田によって直接実装す
ることも考えられる。
In order to solve these problems, it is conceivable to mount directly by soldering in a ball shape or the like instead of the lead terminal or the pin terminal.

【0006】一方、外部回路基板は、有機樹脂を絶縁材
料と一般に、光半導体素子は熱膨張係数が5〜7×10
-6/℃程度であり、一方、外部回路基板は、有機樹脂を
絶縁材料として含有しており、熱膨張係数が10〜15
×10-6/℃のいわゆるプリント配線基板からなる。そ
こで、パッケージをアルミナなどのセラミックスによっ
て形成した場合、アルミナセラミックスは熱膨張係数が
6〜7×10-6/℃と光半導体素子と近似しているため
に、光半導体素子に対する実装信頼性は高いものの、外
部回路基板との熱膨張差が大きいことから外部回路基板
への実装信頼性の点で問題があった。
On the other hand, an external circuit board is generally made of an organic resin as an insulating material, and an optical semiconductor element has a thermal expansion coefficient of 5 to 7 × 10
−6 / ° C., while the external circuit board contains an organic resin as an insulating material and has a coefficient of thermal expansion of 10 to 15
It consists of a so-called printed wiring board of × 10 -6 / ° C. Therefore, when the package is formed of ceramics such as alumina, the alumina ceramics has a thermal expansion coefficient of 6 to 7 × 10 −6 / ° C., which is close to that of the optical semiconductor element, so that the mounting reliability for the optical semiconductor element is high. However, since the thermal expansion difference between the external circuit board and the external circuit board is large, there is a problem in reliability of mounting on the external circuit board.

【0007】この問題に対して、パッケージを高熱膨張
のセラミックスによって形成すると、パッケージの外部
回路基板への実装信頼性は向上するものの、パッケージ
と光半導体素子との熱膨張差が大きくなるために、実装
信頼性が低下し、特に熱膨張差によってパッケージ上に
搭載された光半導体素子に応力が発生し、この応力によ
って光ファイバとの位置ずれが発生し、これによる光半
導体素子と光ファイバ間での信号の変換効率が低下する
という問題があった。
To solve this problem, if the package is formed of ceramics having a high thermal expansion, the reliability of mounting the package on an external circuit board is improved, but the difference in thermal expansion between the package and the optical semiconductor element is increased. The mounting reliability is reduced, and a stress is generated in the optical semiconductor device mounted on the package due to a difference in thermal expansion, and the stress causes a displacement between the optical semiconductor device and the optical semiconductor device. However, there is a problem in that the conversion efficiency of the signal is reduced.

【0008】従って、本発明の目的は、熱膨張係数の比
較的大きい外部回路基板に対する実装信頼性および光半
導体素子のパッケージに対する実装信頼性を改良した光
半導体素子収納用パッケージを提供することを目的とす
るものである。
SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide an optical semiconductor device housing package having improved mounting reliability for an external circuit board having a relatively large coefficient of thermal expansion and mounting reliability for an optical semiconductor device package. It is assumed that.

【0009】[0009]

【課題を解決するための手段】本発明者らは、上記の課
題に対して検討を重ねた結果、パッケージ内の光半導体
素子の実装にあたって、セラミック配線基板における光
半導体素子を取着するセラミック絶縁基板において、接
続端子を設ける面を外部回路基板の熱膨張に整合させ、
光半導体素子を搭載する面を光半導体素子の熱膨張に整
合させ、その絶縁基板内を段階的あるいは連続的に熱膨
張係数を変化させることによって、セラミック配線基板
の熱膨張を高めて外部回路基板の熱膨張に近似させた場
合においても、光半導体素子の実装に対して何ら影響を
及ぼすことなく、信号の変換効率の劣化のない高信頼性
の光半導体素子収納用パッケージが得られることを見い
だし、本発明に至った。
Means for Solving the Problems As a result of repeated studies on the above-mentioned problems, the present inventors have found that when mounting an optical semiconductor element in a package, a ceramic insulating member for mounting the optical semiconductor element on a ceramic wiring board is used. On the board, the surface on which the connection terminals are provided is matched to the thermal expansion of the external circuit board,
The surface on which the optical semiconductor element is mounted is matched to the thermal expansion of the optical semiconductor element, and the thermal expansion coefficient of the ceramic wiring board is increased by changing the coefficient of thermal expansion in the insulating substrate stepwise or continuously. It is found that even when the thermal expansion of the optical semiconductor device is approximated, a highly reliable package for storing the optical semiconductor device can be obtained without deteriorating the signal conversion efficiency without affecting the mounting of the optical semiconductor device. This has led to the present invention.

【0010】即ち、本発明の光半導体素子収納用パッケ
ージは、絶縁基板と配線導体層とを具備し、絶縁基板上
面に光半導体素子搭載部を有するセラミック配線基板
と、該光半導体素子搭載部を取り囲むように前記配線基
板上に取り付けられ、且つ光信号を導入するため導入部
が設けられた枠体と、前記枠体の上面に取着され、前記
光半導体素子を封止するための蓋部材と、を具備すると
ともに、前記絶縁基板の前記光半導体素子搭載部とは反
対側の面に、外部回路基板に接続するための接続端子を
設けてなるものであって、前記絶縁基板の前記接続端子
を設けた面の熱膨張係数が光半導体素子搭載面における
熱膨張係数よりも大きいことを特徴とするものであり、
これによってパッケージの光半導体素子の配線基板への
一次実装信頼性を、またパッケージの外部回路基板への
2次し実装信頼性をも改善することができる。
That is, a package for storing an optical semiconductor element according to the present invention comprises a ceramic wiring board having an insulating substrate and a wiring conductor layer, and having an optical semiconductor element mounting portion on the upper surface of the insulating substrate; A frame body mounted on the wiring board so as to surround and provided with an introduction portion for introducing an optical signal; and a lid member attached to an upper surface of the frame body for sealing the optical semiconductor element. And a connection terminal for connecting to an external circuit board is provided on a surface of the insulating substrate opposite to the optical semiconductor element mounting portion, and the connection of the insulating substrate is provided. The coefficient of thermal expansion of the surface on which the terminals are provided is larger than the coefficient of thermal expansion of the optical semiconductor element mounting surface,
As a result, the primary mounting reliability of the optical semiconductor element of the package on the wiring board and the secondary mounting reliability of the package on the external circuit board can be improved.

【0011】なお、1次実装信頼性を高める上で、配線
基板における絶縁基板の光半導体素子搭載面の光半導体
素子との25〜200℃における熱膨張係数差が3×1
-6/℃以下であることが、また前記配線基板における
絶縁基板の光半導体素子搭載面の25〜200℃におけ
る熱膨張係数が9×10-6/℃以下であることが望まし
い。
In order to improve the primary mounting reliability, the difference in thermal expansion coefficient between 25 and 200.degree.
It is 0 -6 / ° C. or less, and it is desirable thermal expansion coefficient at 25 to 200 ° C. of the optical semiconductor element mounting surface of the insulating substrate in the wiring substrate is 9 × 10 -6 / ℃ or less.

【0012】さらに、2次実装信頼性を高める上で、前
記配線基板における接続端子を設けた面の外部回路基板
との25〜200℃における熱膨張係数差が3×10-6
/℃以下であること、特に絶縁基板の接続端子を設ける
面の25〜200℃における熱膨張係数が9×10-6
℃よりも大きいことが望ましい。
In order to enhance the reliability of the secondary mounting, the difference in the coefficient of thermal expansion between 25 and 200 ° C. between the surface of the wiring board on which the connection terminals are provided and the external circuit board is 3 × 10 −6.
/ ° C or less, and particularly, the coefficient of thermal expansion at 25 to 200 ° C of the surface of the insulating substrate on which the connection terminals are provided is 9 × 10 −6 /
Desirably, it is higher than ° C.

【0013】また、前記絶縁基板の熱膨張係数は、光半
導体素子搭載面から接続端子を設けた面にかけて段階的
あるいは連続的に変化していることが望ましい。
Preferably, the coefficient of thermal expansion of the insulating substrate changes stepwise or continuously from the surface on which the optical semiconductor element is mounted to the surface on which the connection terminals are provided.

【0014】さらに、配線基板の絶縁基板を、1000
℃以下で焼成可能な低温焼成セラミック材料によって形
成することによって、配線導体層を銅、銀などの低抵抗
金属によって形成することができるために、高周波信号
の取り扱いに好適である。
Further, the insulating substrate of the wiring board is
Since the wiring conductor layer can be formed of a low-resistance metal such as copper or silver by being formed of a low-temperature fired ceramic material that can be fired at a temperature of not more than 0 ° C., it is suitable for handling high-frequency signals.

【0015】本発明の光半導体素子収納用パッケージに
よれば、上記のように、配線基板における絶縁基板内で
光半導体素子搭載面側と、接続端子を設ける面側の熱膨
張を変化させることによって、外部回路基板とパッケー
ジとの熱膨張差と、光半導体素子とパッケージとの熱膨
張差を小さくすることができるために、熱膨張差に起因
する応力の発生を抑制し、パッケージへの光半導体素子
の一次実装信頼性とパッケージの外部回路基板への2次
実装信頼性を同時に達成することができる。
According to the package for housing an optical semiconductor element of the present invention, as described above, the thermal expansion on the side on which the optical semiconductor element is mounted and the side on which the connection terminals are provided in the insulating substrate of the wiring board are changed. Since the difference in thermal expansion between the external circuit board and the package and the difference in thermal expansion between the optical semiconductor element and the package can be reduced, the generation of stress due to the difference in thermal expansion is suppressed, and the optical semiconductor Primary mounting reliability of the element and secondary mounting reliability of the package on the external circuit board can be achieved at the same time.

【0016】[0016]

【発明の実施の形態】次に本発明を添付の図面に基づき
詳細に説明する。図1は本発明の光半導体素子収納用パ
ッケージAの一例を説明するための概略断面図である。
図中、1はセラミック配線基板、2は枠体、3は蓋部材
である。この配線基板1と枠体2と蓋部材3によってキ
ャビティが形成され、このキャビティ内に光半導体素子
4が収納される。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail with reference to the accompanying drawings. FIG. 1 is a schematic cross-sectional view for explaining an example of an optical semiconductor element housing package A of the present invention.
In the figure, 1 is a ceramic wiring board, 2 is a frame, and 3 is a lid member. A cavity is formed by the wiring board 1, the frame 2, and the lid member 3, and the optical semiconductor element 4 is housed in the cavity.

【0017】配線基板1は、絶縁基板5と配線導体層6
とを具備しており、配線基板1のキャビティ側の上面の
略中央部には、光半導体素子4を載置する為の載置部が
形成されている。その載置部には、光半導体素子4を接
着固定するための導体層7が形成されており、例えばシ
リコンなどからなる光半導体素子基板4aの上に光電変
換素子部4bが形成された光半導体素子4が、金−ゲル
マニウム等の半田材(図示せず)により導体層7に接着
固定される。
The wiring board 1 includes an insulating substrate 5 and a wiring conductor layer 6.
A mounting portion for mounting the optical semiconductor element 4 is formed substantially at the center of the upper surface of the wiring substrate 1 on the cavity side. A conductor layer 7 for bonding and fixing the optical semiconductor element 4 is formed on the mounting portion. For example, an optical semiconductor in which a photoelectric conversion element section 4b is formed on an optical semiconductor element substrate 4a made of silicon or the like. The element 4 is bonded and fixed to the conductor layer 7 with a solder material (not shown) such as gold-germanium.

【0018】また、枠体2は、セラミックスあるいは金
属から構成され、光ファイバ8による光信号を光電変換
素子4bに到達させるために、枠体2には、光ファイバ
ー8を導入するための導入部9が形成されている。この
導入部9には、例えば、枠体2を貫通する貫通孔10が
形成されており、この貫通孔10には、光ファイバー8
を固定する筒状の固定部材11が貫通孔10の外面にロ
ウ材によって取着されている。この枠体2における固定
部材11の取着面には、予め導体層(図示せず)が形成
されており、その導体層表面にニッケルメッキ層や金メ
ッキ層が施され、固定部材11のロウ付け性を高め固定
部材11が枠体2に強固に固定されている。
The frame 2 is made of ceramics or metal. In order for the optical signal from the optical fiber 8 to reach the photoelectric conversion element 4b, the frame 2 has an introduction section 9 for introducing the optical fiber 8. Are formed. For example, a through hole 10 that penetrates the frame 2 is formed in the introduction portion 9, and the optical fiber 8 is formed in the through hole 10.
Is fixed to the outer surface of the through hole 10 with a brazing material. A conductor layer (not shown) is previously formed on the attachment surface of the fixing member 11 of the frame 2, and a nickel plating layer or a gold plating layer is applied to the surface of the conductor layer, and the fixing member 11 is brazed. The fixing member 11 is firmly fixed to the frame body 2 with enhanced properties.

【0019】そして、光ファイバー8が筒状の固定部材
11を貫通して支持され、貫通孔10を経由してキャビ
ティ内に導入され、光半導体素子4の間で光信号の授受
ができるように配置されている。なお、筒状固定部材1
1と光ファイバ8とは、半田材や樹脂封止等によって固
定される。
The optical fiber 8 is supported so as to pass through the cylindrical fixing member 11, is introduced into the cavity through the through hole 10, and is arranged so that an optical signal can be transmitted and received between the optical semiconductor elements 4. Have been. In addition, the cylindrical fixing member 1
The optical fiber 1 and the optical fiber 8 are fixed by a solder material, resin sealing or the like.

【0020】また、枠体2の上面には、例えばFe−N
i−Co合金やFe−Ni合金等の金属材料からなる蓋
部材3がシームウェルド法等の溶接によって接合され、
キャビティ内を気密に封止している。
On the upper surface of the frame 2, for example, Fe-N
A cover member 3 made of a metal material such as an i-Co alloy or an Fe-Ni alloy is joined by welding such as a seam welding method,
The inside of the cavity is hermetically sealed.

【0021】さらに、配線基板1の下面には、接続パッ
ド12を介して接続端子13が取着形成されている。こ
の例では、接続端子13として、ボール状半田が取着さ
れている。
Further, connection terminals 13 are attached to the lower surface of the wiring board 1 via connection pads 12. In this example, a ball-shaped solder is attached as the connection terminal 13.

【0022】また、このパッケージAは、外部回路基板
Bに実装されている。外部回路基板Bは、絶縁基体14
の表面にパッケージAを実装するための接続パッド15
が形成されており、図1に示すように、パッケージA
は、パッケージA側の接続パッド12が外部回路基板B
の接続パッド15とボール状半田からなる接続端子13
によって接続固定される。
The package A is mounted on an external circuit board B. The external circuit board B includes an insulating base 14.
Pad 15 for mounting package A on the surface of
Are formed, and as shown in FIG.
Means that the connection pads 12 on the package A side are connected to the external circuit board B
Connection pad 15 and connection terminal 13 made of ball-shaped solder
The connection is fixed.

【0023】本発明によれば、光半導体素子収納用パッ
ケージの接続端子13を上記のようなボール状半田など
の半田によって形成し、パッケージA側の接続パッド1
2と外部回路基板基板B側の接続パッド15とを半田に
よって直接接続する場合、パッケージAと外部回路基板
Bとの接続パッド間の高さが非常に低いことから、両者
の熱膨張差に起因する応力が半田によって吸収できず、
接続端子13となる半田や接続パッドの周囲にクラック
などが発生し、接続抵抗が増大し実装信頼性が損なわれ
てしまう。
According to the present invention, the connection terminals 13 of the package for housing an optical semiconductor element are formed by soldering such as ball solder as described above, and the connection pads 1 on the package A side are formed.
2 and the connection pads 15 on the external circuit board B side are directly connected by soldering, because the height between the connection pads between the package A and the external circuit board B is very low, the difference is caused by the difference in thermal expansion between the two. Stress cannot be absorbed by the solder,
Cracks and the like are generated around the solder and the connection pad serving as the connection terminal 13, so that the connection resistance is increased and the mounting reliability is impaired.

【0024】そのために、上記のような半田からなる接
続端子13からなる場合、パッケージAの外部回路基板
Bへの実装信頼性を高めるために、外部回路基板を構成
する絶縁基体14の熱膨張係数と光半導体素子収納用パ
ッケージにおける絶縁基板5との熱膨張係数を近似させ
ることが望ましい。
In order to improve the reliability of mounting the package A on the external circuit board B when the connection terminals 13 are made of solder as described above, the coefficient of thermal expansion of the insulating base 14 constituting the external circuit board is increased. It is desirable to approximate the thermal expansion coefficient between the substrate and the insulating substrate 5 in the optical semiconductor element housing package.

【0025】本発明の光半導体素子4を搭載するパッケ
ージAにおいては、光ファイバ8と光電変換素子4aと
の位置ずれの発生を防止することが信号の変換効率を高
める上で非常に重要である。この位置ずれは、光半導体
素子4が直接搭載されるパッケージAにおける絶縁基板
5への導体層7への実装の信頼性によって定められる。
In the package A on which the optical semiconductor element 4 according to the present invention is mounted, it is very important to prevent the occurrence of displacement between the optical fiber 8 and the photoelectric conversion element 4a in order to increase the signal conversion efficiency. . This displacement is determined by the reliability of the mounting on the conductor layer 7 on the insulating substrate 5 in the package A on which the optical semiconductor element 4 is directly mounted.

【0026】パッケージAの外部回路基板Bへの2次実
装信頼性を高めるために、絶縁基板5の熱膨張係数が大
きくなる傾向にあり、そのために光半導体素子4との熱
膨張差による実装信頼性が低下し、光半導体素子の搭載
部で歪が生じ、光半導体素子の光ファイバとの位置ずれ
によって信号の変換効率が劣化してしまう。
In order to increase the reliability of the secondary mounting of the package A on the external circuit board B, the thermal expansion coefficient of the insulating substrate 5 tends to increase. Therefore, distortion occurs in the mounting portion of the optical semiconductor element, and the optical semiconductor element is displaced from the optical fiber, thereby deteriorating the signal conversion efficiency.

【0027】そこで、本発明によれば、絶縁基板の接続
端子を設けた面(以下、接続端子設置面という。)の熱
膨張係数が光半導体素子搭載面における熱膨張係数より
も大きくなるように調整することによって、接続端子設
置面を外部回路基板の熱膨張に整合させ、光半導体素子
搭載面を光半導体素子の熱膨張に整合させることができ
る。
Therefore, according to the present invention, the thermal expansion coefficient of the surface of the insulating substrate on which the connection terminals are provided (hereinafter referred to as the connection terminal installation surface) is set to be larger than the thermal expansion coefficient of the optical semiconductor element mounting surface. By adjusting, the connection terminal installation surface can be matched to the thermal expansion of the external circuit board, and the optical semiconductor element mounting surface can be matched to the thermal expansion of the optical semiconductor element.

【0028】特に、熱膨張の整合性の点では、絶縁基板
の光半導体素子搭載面側と光半導体素子との熱膨張係数
差、および絶縁基板の接続端子設置面側と外部回路基板
との熱膨張係数差がいずれも3×10-6/℃以下、特に
2×10-6/℃以下であることが望ましい。
In particular, in terms of the matching of the thermal expansion, the difference in the thermal expansion coefficient between the optical semiconductor element mounting surface side of the insulating substrate and the optical semiconductor element, and the thermal expansion coefficient between the connecting terminal installation surface side of the insulating substrate and the external circuit substrate. The expansion coefficient difference is desirably 3 × 10 −6 / ° C. or less, particularly 2 × 10 −6 / ° C. or less.

【0029】また、絶縁基板の光半導体素子搭載面の熱
膨張係数は9×10-6/℃以下、特に8×10-6/℃以
下であることが適当である。
The thermal expansion coefficient of the optical semiconductor element mounting surface of the insulating substrate is preferably 9 × 10 −6 / ° C. or less, particularly preferably 8 × 10 −6 / ° C. or less.

【0030】一方、外部回路基板Bは、FR−4の名称
で呼ばれるような、ガラスなどの織布や不織布にエポキ
シ樹脂などの熱硬化性樹脂を含浸させたような有機樹脂
を含む絶縁基板に、金属箔によって配線回路層が形成さ
れたものが使用される。このような外部回路基板は、通
常、20〜200℃における熱膨張係数は10〜15×
10-6/℃である。従って、本発明の光半導体素子収納
用パッケージAにおける絶縁基板5の接続端子設置側の
25〜200℃における熱膨張係数が9×10 -6/℃を
超える、特に10×10-6/℃以上であることが望まし
い。
On the other hand, the external circuit board B has a name of FR-4.
Epoxy on woven or non-woven fabric such as glass
Organic resin impregnated with thermosetting resin such as resin
The wiring circuit layer is formed by metal foil on the insulating substrate containing
Is used. Such an external circuit board is commonly used.
Usually, the coefficient of thermal expansion at 20 to 200 ° C. is 10 to 15 ×.
10-6/ ° C. Therefore, the optical semiconductor device housing of the present invention
On the connection terminal installation side of the insulating substrate 5 in the package A
The coefficient of thermal expansion at 25 to 200 ° C. is 9 × 10 -6/ ℃
Greater than, especially 10 × 10-6/ ° C or higher
No.

【0031】また、セラミック絶縁基板5内において、
光半導体素子搭載面と、接続端子設置面とは熱膨張係数
が異なるものであって、絶縁基板5内では熱膨張係数が
段階的または連続的に熱膨張係数が変化していることが
望ましい。
In the ceramic insulating substrate 5,
The optical semiconductor element mounting surface and the connection terminal installation surface have different thermal expansion coefficients, and it is desirable that the thermal expansion coefficient in the insulating substrate 5 changes stepwise or continuously.

【0032】従って、セラミック絶縁基板5は、図2
(a)に示すように、熱膨張係数の異なる2層の絶縁層
5a、5bによって形成した場合、この絶縁層5a、5
bを同時焼成して形成すると、その界面に自ずと、絶縁
層5a、5bの中間的な組成からなる中間層が形成さ
れ、熱膨張係数の段階的あるいは連続的な傾斜構造が形
成される。また、絶縁層5a、5bの熱膨張係数差が大
きい場合には、図2(b)に示すように、絶縁層5a、
5bとの間に、絶縁層5a、5bの中間的な熱膨張特性
を有する中間層5cを設けることが望ましく、これによ
って絶縁層5a、5bの熱膨張差に起因する応力の発生
を抑制することができる。この中間絶縁層は1層のみな
らず、2層以上あってもよい。 (絶縁基板)本発明のパッケージによれば、配線基板1
におけるセラミック絶縁基板5は、従来から周知のセラ
ミック絶縁基板材料が採用され、アルミナ、ムライト、
フォルステライト、窒化アルミニウム、窒化珪素、ガラ
スセラミックスの群から選ばれる少なくとも1種によっ
て形成することができる。
Accordingly, the ceramic insulating substrate 5 is formed as shown in FIG.
As shown in (a), when formed by two insulating layers 5a and 5b having different thermal expansion coefficients, the insulating layers 5a and 5b
When b is formed by simultaneous firing, an intermediate layer having an intermediate composition of the insulating layers 5a and 5b is naturally formed at the interface, and a graded or continuous gradient structure with a thermal expansion coefficient is formed. When the difference between the thermal expansion coefficients of the insulating layers 5a and 5b is large, as shown in FIG.
It is desirable to provide an intermediate layer 5c having an intermediate thermal expansion characteristic between the insulating layers 5a and 5b between the insulating layers 5a and 5b, thereby suppressing generation of stress due to a difference in thermal expansion between the insulating layers 5a and 5b. Can be. This intermediate insulating layer is not limited to one layer, and may have two or more layers. (Insulating substrate) According to the package of the present invention, the wiring substrate 1
The ceramic insulating substrate 5 is made of a conventionally known ceramic insulating substrate material, and is made of alumina, mullite,
It can be formed of at least one selected from the group consisting of forsterite, aluminum nitride, silicon nitride, and glass ceramics.

【0033】本発明によれば、絶縁基板5内で熱膨張を
変化させる必要がある。この絶縁基板5の光半導体素子
搭載面と接続端子設置面とで熱膨張係数を変化させるた
めには、熱膨張係数の異なる絶縁層をそれぞれ作製した
後、これらを接合することもできるが、この絶縁基板5
内には配線導体層6によって回路形成する必要があり、
しかも熱膨張係数が絶縁基板内に段階的あるいは連続的
に変化することが望ましいことから、これらは絶縁基板
5はすべて同時焼成によって形成されることが望まし
い。
According to the present invention, it is necessary to change the thermal expansion in the insulating substrate 5. In order to change the thermal expansion coefficient between the optical semiconductor element mounting surface of the insulating substrate 5 and the connection terminal mounting surface, insulating layers having different thermal expansion coefficients can be formed and then joined. Insulating substrate 5
It is necessary to form a circuit in the wiring conductor layer 6 inside,
Moreover, since it is desirable that the coefficient of thermal expansion changes stepwise or continuously in the insulating substrate, it is desirable that all of these are formed by simultaneous firing.

【0034】同時焼成が可能であって、しかも熱膨張係
数を広い範囲で制御できるセラミック材料としては、前
記CuやAgとの同時焼成が可能なように1000℃以
下の低温で焼成可能なセラミックスが好適に使用され、
特にガラスセラミックスは、概して低誘電損失であり、
誘電率を低誘電率から高い誘電率まで任意に制御でき、
さらには熱膨張係数も任意に制御できる点で本発明のパ
ッケージに特に有用である。
As a ceramic material which can be co-fired and whose thermal expansion coefficient can be controlled in a wide range, ceramics which can be fired at a low temperature of 1000 ° C. or lower so as to be able to co-fire with the above-mentioned Cu or Ag are used. Preferably used,
In particular, glass ceramics generally have low dielectric loss,
Dielectric constant can be arbitrarily controlled from low dielectric constant to high dielectric constant,
Furthermore, it is particularly useful for the package of the present invention in that the coefficient of thermal expansion can be arbitrarily controlled.

【0035】このガラスセラミックスは、ガラス成分、
あるいはガラス成分とフィラー成分との混合物を焼成し
たものであり、特に配線基板における強度を高める上
で、フィラー成分を、ガラス:フィラーを5:95〜9
5:5の体積比率で混合してなる組成物を焼成したもの
が好適に使用される。
This glass ceramic has a glass component,
Alternatively, it is obtained by firing a mixture of a glass component and a filler component. In particular, in order to enhance the strength of the wiring board, the filler component is used in the form of glass: filler of 5:95 to 9: 9.
A composition obtained by calcining a composition mixed at a volume ratio of 5: 5 is suitably used.

【0036】用いられるガラス成分としては、少なくと
もSiO2を含み、Al23、B2 3、ZnO、Pb
O、アルカリ土類金属酸化物、アルカリ金属酸化物のう
ち少なくとも1種以上を含有し、焼成処理することによ
っても非晶質であるもの、また焼成処理によってコージ
ェライト、ムライト、アノーサイト、セルジアン、スピ
ネル、ガーナイト、ウィレマイト、ドロマイト、ペタラ
イトやその置換誘導体の結晶を少なくとも1種を析出す
る結晶化ガラスが用いられる。
As the glass component used, at least
Also SiOTwoContaining, AlTwoOThree, BTwoO Three, ZnO, Pb
O, alkaline earth metal oxide, alkali metal oxide
At least one or more of them, and
Even if it is amorphous,
Cellite, mullite, anorthite, Sergien, spi
Flannel, garnite, willemite, dolomite, petara
Precipitates at least one type of crystal of a site or its substituted derivative
Crystallized glass is used.

【0037】フィラー成分としては、ジルコン酸カルシ
ウム、珪酸ストロンチウム、チタン酸カルシウム、チタ
ン酸ストロンチウム、チタン酸バリウム、アルミナ、ク
オーツ、クリストバライト、石英ガラス、ムライト、フ
ォルステライト、ジルコニア、スピネル、コージェライ
ト、アノーサイト、セルジアン、ガーナイト、ウィレマ
イト、ドロマイト、ペタライトやその置換誘導体の結晶
を少なくとも1種を析出する結晶化ガラスを用いること
が良好な電気特性を示すと共に、強度向上の点からも好
適である。
As the filler component, calcium zirconate, strontium silicate, calcium titanate, strontium titanate, barium titanate, alumina, quartz, cristobalite, quartz glass, mullite, forsterite, zirconia, spinel, cordierite, anorthite It is preferable to use crystallized glass that precipitates at least one kind of crystal of Celsian, garnite, willemite, dolomite, petalite or a substituted derivative thereof, from the viewpoint of exhibiting good electric characteristics and improving strength.

【0038】9×10-6/℃未満のセラミックスとして
は、ホウ珪酸ガラスなどにアルミナ、ムライト、窒化ア
ルミニウムなどのフィラーを添加混合することによって
形成することができる。
The ceramics having a density of less than 9 × 10 −6 / ° C. can be formed by adding a filler such as alumina, mullite, aluminum nitride or the like to borosilicate glass or the like.

【0039】熱膨張係数が9×10-6/℃を超えるセラ
ミックスとしては、例えば、BaOを5乃至60重量%
の割合で含有する低軟化点、高熱膨張のBaO系ガラ
ス、その他、特願平8−322038号の明細書中に記
載されているような、例えば、リチウム珪酸系ガラス、
PbO系ガラス、ZnO系ガラスをはじめとする高熱膨
張系のガラス成分に対して、SiO2(クオーツ)、エ
ンスタタイト、フォルステライト、MgO、ZrO2
ペタライト等の各種高熱膨張性のセラミックフィラー成
分を混合したものを焼成することによってその比率を制
御することによって容易に作製することができる。
As ceramics having a coefficient of thermal expansion exceeding 9 × 10 −6 / ° C., for example, BaO is 5 to 60% by weight.
A low-softening point, high thermal expansion BaO-based glass, and others, such as lithium silicate-based glass described in the specification of Japanese Patent Application No. 8-322038.
For high thermal expansion glass components such as PbO-based glass and ZnO-based glass, SiO 2 (quartz), enstatite, forsterite, MgO, ZrO 2 ,
It can be easily produced by baking a mixture of various high thermal expansion ceramic filler components such as petalite and controlling the ratio thereof.

【0040】また、本発明によれば、枠体2をセラミッ
クスによって形成する場合、配線基板1と同じ焼成温度
で焼成可能なセラミックスによって形成すれば、配線基
板1と枠体2とを焼成によって一体化することができ
る。 (導体材料)また、上記光半導体素子4を固定する導体
層7や、配線基板1内の配線導体層6および接続パッド
12などは、従来より周知の導体材料であるW、Mo、
Mn、Cu、Agの群から選ばれる少なくとも1種を主
とする導体材料によって形成されるが、特に上記の10
00℃以下で焼成可能なセラミックスを選択し、高周波
信号の伝送性を高めるためにCuやAgの低抵抗金属を
主成分とする導体材料によって形成することができる。
また、この導体層7や接続パッド12には、耐蝕性に優
れ、且つロウ材に対し濡れ性が良い金属、具体的には厚
さ1.5〜6μmのNi層および厚さ0.2〜5μmの
Au層を順次、メッキ法により被着させておくと、配線
基板1が酸化腐食するのを有効に防止出来るとともに配
線基板1上面の光半導体素子4をロウ材によって強固に
接着固定させることができる。
According to the present invention, when the frame 2 is formed of ceramics, if the frame 2 is formed of ceramics that can be fired at the same firing temperature as the wiring board 1, the wiring board 1 and the frame 2 are integrally fired. Can be (Conductor Material) The conductor layer 7 for fixing the optical semiconductor element 4 and the wiring conductor layer 6 and the connection pads 12 in the wiring board 1 are made of W, Mo, a conventionally known conductor material.
It is formed of a conductor material mainly containing at least one selected from the group consisting of Mn, Cu, and Ag.
Ceramics that can be fired at a temperature of 00 ° C. or less are selected, and can be formed of a conductive material mainly composed of a low-resistance metal such as Cu or Ag in order to enhance the transmission of high-frequency signals.
The conductor layer 7 and the connection pad 12 are made of a metal having excellent corrosion resistance and good wettability to a brazing material, specifically, a Ni layer having a thickness of 1.5 to 6 μm and a thickness of 0.2 to If a 5 μm Au layer is sequentially applied by a plating method, the oxidative corrosion of the wiring substrate 1 can be effectively prevented, and the optical semiconductor element 4 on the upper surface of the wiring substrate 1 is firmly adhered and fixed with a brazing material. Can be.

【0041】[0041]

【実施例】以下に、本発明の効果を確認するために以下
の実験を行った。パッケージにおける配線基板を形成す
るための絶縁基板材料として、表1に示すような25〜
200℃における熱膨張係数が8〜12×10-6/℃の
ガラスセラミック材料を用いた。配線基板内の配線導体
層や光半導体素子を搭載するための導体層を銅メタライ
ズを用いて絶縁基板と950℃で同時焼成して形成し
た。
EXAMPLES The following experiments were conducted to confirm the effects of the present invention. As an insulating substrate material for forming a wiring board in a package, 25-
A glass ceramic material having a thermal expansion coefficient at 200 ° C. of 8 to 12 × 10 −6 / ° C. was used. The wiring conductor layer in the wiring substrate and the conductor layer for mounting the optical semiconductor element were formed by simultaneous firing at 950 ° C. with the insulating substrate using copper metallization.

【0042】また、配線基板の底面には、接続パッドに
共晶半田からなるボール半田の端子を取り付けた。そし
て、この導体層上に共晶半田を用いて、熱膨張係数がシ
リコン基板上に光電変換素子(α=6×10-6)が形成
された光半導体素子を接着させた。
A ball solder terminal made of eutectic solder was attached to the connection pad on the bottom surface of the wiring board. Then, an optical semiconductor element having a photoelectric conversion element (α = 6 × 10 −6 ) formed on a silicon substrate with a coefficient of thermal expansion was bonded using eutectic solder on the conductor layer.

【0043】このパッケージをガラス織布にエポキシ樹
脂を含浸させた絶縁基板(FR−4、α=14×10-6
/℃)表面に銅箔からなる接続パッドが形成されたプリ
ント配線基板の表面に上記パッケージを載置して共晶半
田を用いて表面実装した。
An insulating substrate (FR-4, α = 14 × 10 −6) obtained by impregnating this package with a glass woven fabric and an epoxy resin.
(/ ° C.) The above package was mounted on the surface of a printed wiring board having connection pads made of copper foil formed on the surface, and was surface-mounted using eutectic solder.

【0044】作製した光半導体素子パッケージにおい
て、光結合損失を光パワーメータにて測定した。なお、
光結合損失は発光源と光ファイバの位置をあらかじめ設
定しておき、ファイバ出力0.2mWで安定させて測定
した。また、上記パッケージをプリント配線基板に実装
したものを−40℃と85℃の熱サイクルを繰り返し印
加して、100サイクル毎に接続端子を介した接続パッ
ド間の抵抗を測定し初期値に対して10%以上劣化した
時のサイクル数を限界値として表1に示した。
The optical coupling loss of the manufactured optical semiconductor device package was measured with an optical power meter. In addition,
The optical coupling loss was measured by setting the positions of the light emitting source and the optical fiber in advance and stabilizing the fiber output at 0.2 mW. The package mounted on a printed wiring board was subjected to a thermal cycle of −40 ° C. and 85 ° C. repeatedly, and the resistance between the connection pads via the connection terminals was measured every 100 cycles. Table 1 shows the number of cycles at the time of deterioration of 10% or more as a limit value.

【0045】[0045]

【表1】 [Table 1]

【0046】[0046]

【表2】 [Table 2]

【0047】表1に示されるように、本発明に従い、光
半導体素子搭載面と接続端子設置面との熱膨張係数を制
御することによって、光結合損失を0.2dB以下にで
きるとともに、2次実装信頼性においても500サイク
ル後であっても何ら変化のない信頼性の高いものであっ
た。
As shown in Table 1, by controlling the thermal expansion coefficient between the optical semiconductor element mounting surface and the connection terminal mounting surface according to the present invention, the optical coupling loss can be reduced to 0.2 dB or less and the secondary coupling loss can be reduced. The mounting reliability was high without any change even after 500 cycles.

【0048】これに対して、絶縁基板を光半導体素子に
整合させた単一のセラミックスによって形成した試料N
o.1では、光結合損失は良好であったが、2次実装信
頼性の劣るものであった。逆に外部回路基板に整合させ
た単一のセラミックスによって形成した試料No.2で
は、熱サイクル試験では良好であったが、光結合損失が
低いものであった。
On the other hand, a sample N formed of a single ceramic having an insulating substrate aligned with an optical semiconductor element was used.
o. In No. 1, the optical coupling loss was good, but the secondary mounting reliability was poor. Conversely, the sample No. formed by a single ceramic matched to the external circuit board. In No. 2, the heat cycle test was good, but the optical coupling loss was low.

【0049】[0049]

【発明の効果】以上詳述した通り、本発明の光半導体素
子収納用パッケージによれば、光ファイバから光半導体
素子および電気信号を円滑に伝達でき、光半導体素子の
一次実装信頼性および2次実装信頼性を向上することが
できる。
As described above in detail, according to the package for housing an optical semiconductor device of the present invention, the optical semiconductor device and the electric signal can be smoothly transmitted from the optical fiber, and the primary mounting reliability and the secondary The mounting reliability can be improved.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の光半導体素子収納用パッケージの実施
例を示す展開図である。
FIG. 1 is a development view showing an embodiment of an optical semiconductor element housing package of the present invention.

【図2】本発明における絶縁基板の構造を説明するため
の概略断面図であり、(a)はその一例、(b)は他の
例を説明するものである。
FIGS. 2A and 2B are schematic cross-sectional views illustrating the structure of an insulating substrate according to the present invention, wherein FIG. 2A illustrates one example and FIG. 2B illustrates another example.

【符号の説明】[Explanation of symbols]

1 セラミック配線基板 2 枠体 3 蓋部材 4 光半導体素子 4a 光半導体素子基板 4b 光電変換素子 5 絶縁基板 6 配線導体層 7 導体層 8 光ファイバ 9 導入部 10 貫通孔 11 固定部材 DESCRIPTION OF SYMBOLS 1 Ceramic wiring board 2 Frame 3 Cover member 4 Optical semiconductor element 4a Optical semiconductor element substrate 4b Photoelectric conversion element 5 Insulating substrate 6 Wiring conductor layer 7 Conductor layer 8 Optical fiber 9 Introducing part 10 Through hole 11 Fixing member

Claims (8)

【特許請求の範囲】[Claims] 【請求項1】絶縁基板と配線導体層とを具備し、絶縁基
板上面に光半導体素子搭載部を有するセラミック配線基
板と、該光半導体素子搭載部を取り囲むように前記配線
基板上に取り付けられ、且つ光信号を導入するための導
入部が設けられた枠体と、前記枠体の上面に取着され、
前記光半導体素子を封止するための蓋部材と、を具備す
るとともに、前記絶縁基板の前記光半導体素子搭載部と
は反対側の面に、外部回路基板に接続するための接続端
子を設けてなる光半導体素子収納用パッケージにおい
て、前記絶縁基板の前記接続端子を設けた面の熱膨張係
数が光半導体素子搭載面における熱膨張係数よりも大き
いことを特徴とする光半導体素子収納用パッケージ。
A ceramic wiring board comprising an insulating substrate and a wiring conductor layer, wherein the ceramic wiring board has an optical semiconductor element mounting portion on the upper surface of the insulating substrate, and is mounted on the wiring substrate so as to surround the optical semiconductor element mounting portion; And a frame provided with an introduction portion for introducing an optical signal, attached to the upper surface of the frame,
A cover member for sealing the optical semiconductor element, and a connection terminal for connecting to an external circuit board is provided on a surface of the insulating substrate opposite to the optical semiconductor element mounting portion. An optical semiconductor element housing package according to claim 1, wherein a thermal expansion coefficient of a surface of said insulating substrate on which said connection terminal is provided is larger than a thermal expansion coefficient of an optical semiconductor element mounting surface.
【請求項2】前記絶縁基板の光半導体素子搭載面の光半
導体素子との25〜200℃における熱膨張係数差が3
×10-6/℃以下であることを特徴とする請求項1記載
の光半導体素子収納用パッケージ。
2. A thermal expansion coefficient difference between the optical semiconductor element mounting surface of the insulating substrate and the optical semiconductor element at 25 to 200.degree.
2. The package for housing an optical semiconductor element according to claim 1, wherein the temperature is not higher than × 10 −6 / ° C.
【請求項3】前記絶縁基板の光半導体素子搭載面の25
〜200℃における熱膨張係数が9×10-6/℃以下で
あることを特徴とする請求項1または請求項2記載の光
半導体素子収納用パッケージ。
3. An optical semiconductor device mounting surface of the insulating substrate.
3. The package for housing an optical semiconductor element according to claim 1, wherein a thermal expansion coefficient at a temperature of from 200 to 200 [deg.] C. is 9 * 10 < -6 > / [deg.] C. or less.
【請求項4】前記絶縁基板の接続端子を設けた面の外部
回路基板との25〜200℃における熱膨張係数差が3
×10-6/℃以下であることを特徴とする請求項1乃至
請求項3のいずれか記載の光半導体素子収納用パッケー
ジ。
4. A thermal expansion coefficient difference between the surface of the insulating substrate on which the connection terminals are provided and the external circuit substrate at 25 to 200.degree.
4. The package for accommodating an optical semiconductor element according to claim 1, wherein the temperature is not higher than × 10 −6 / ° C.
【請求項5】前記絶縁基板の接続端子を設ける面の25
〜200℃における熱膨張係数が9×10-6/℃よりも
大きいことを特徴とする請求項1乃至請求項4のいずれ
か記載の光半導体素子収納用パッケージ。
5. A semiconductor device according to claim 5, wherein said insulating substrate has connection terminals on a surface on which connection terminals are provided.
The package for housing an optical semiconductor element according to any one of claims 1 to 4, wherein a thermal expansion coefficient at -200 ° C is larger than 9 × 10 -6 / ° C.
【請求項6】前記絶縁基板の熱膨張係数が、光半導体素
子搭載面から接続端子を設けた面にかけて段階的あるい
は連続的に変化していることを特徴とする請求項1記載
の光半導体素子収納用パッケージ。
6. The optical semiconductor device according to claim 1, wherein the thermal expansion coefficient of the insulating substrate changes stepwise or continuously from the surface on which the optical semiconductor device is mounted to the surface on which the connection terminals are provided. Package for storage.
【請求項7】前記接続端子が、半田からなる請求項1記
載の光半導体素子収納用パッケージ。
7. The package for housing an optical semiconductor device according to claim 1, wherein said connection terminals are made of solder.
【請求項8】前記絶縁基板が、1000℃以下で焼成さ
れた低温焼成セラミック材料からなることを特徴とする
請求項1記載の光半導体素子収納用パッケージ。
8. The package according to claim 1, wherein said insulating substrate is made of a low-temperature fired ceramic material fired at 1000 ° C. or lower.
JP2001096110A 2001-03-29 2001-03-29 Package for storing optical semiconductor element Pending JP2002299486A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2001096110A JP2002299486A (en) 2001-03-29 2001-03-29 Package for storing optical semiconductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001096110A JP2002299486A (en) 2001-03-29 2001-03-29 Package for storing optical semiconductor element

Publications (1)

Publication Number Publication Date
JP2002299486A true JP2002299486A (en) 2002-10-11

Family

ID=18950064

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001096110A Pending JP2002299486A (en) 2001-03-29 2001-03-29 Package for storing optical semiconductor element

Country Status (1)

Country Link
JP (1) JP2002299486A (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011119615A (en) * 2009-12-07 2011-06-16 Shinko Electric Ind Co Ltd Wiring board, method of manufacturing the same, and semiconductor package
JP2011155149A (en) * 2010-01-27 2011-08-11 Shinko Electric Ind Co Ltd Wiring board and method of manufacturing the same, and semiconductor package
US8686548B2 (en) 2010-01-12 2014-04-01 Shinko Electric Industries Co., Ltd. Wiring substrate, method for manufacturing wiring substrate, and semiconductor package including wiring substrate
US9155212B2 (en) 2012-04-27 2015-10-06 Canon Kabushiki Kaisha Electronic component, mounting member, electronic apparatus, and their manufacturing methods
US9220172B2 (en) 2012-04-27 2015-12-22 Canon Kabushiki Kaisha Electronic component, electronic module, their manufacturing methods, mounting member, and electronic apparatus
US9253922B2 (en) 2012-04-27 2016-02-02 Canon Kabushiki Kaisha Electronic component and electronic apparatus
KR20180014697A (en) * 2015-06-01 2018-02-09 후루카와 덴키 고교 가부시키가이샤 CONSTRUCTION MATERIAL AND PREPARATION METHOD
JP2020086389A (en) * 2018-11-30 2020-06-04 富士通株式会社 Optical component, and optical module using the same

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011119615A (en) * 2009-12-07 2011-06-16 Shinko Electric Ind Co Ltd Wiring board, method of manufacturing the same, and semiconductor package
US8674514B2 (en) 2009-12-07 2014-03-18 Shinko Electric Industries Co., Ltd. Wiring board, manufacturing method of the wiring board, and semiconductor package
US8686548B2 (en) 2010-01-12 2014-04-01 Shinko Electric Industries Co., Ltd. Wiring substrate, method for manufacturing wiring substrate, and semiconductor package including wiring substrate
JP2011155149A (en) * 2010-01-27 2011-08-11 Shinko Electric Ind Co Ltd Wiring board and method of manufacturing the same, and semiconductor package
US9155212B2 (en) 2012-04-27 2015-10-06 Canon Kabushiki Kaisha Electronic component, mounting member, electronic apparatus, and their manufacturing methods
US9220172B2 (en) 2012-04-27 2015-12-22 Canon Kabushiki Kaisha Electronic component, electronic module, their manufacturing methods, mounting member, and electronic apparatus
US9253922B2 (en) 2012-04-27 2016-02-02 Canon Kabushiki Kaisha Electronic component and electronic apparatus
KR20180014697A (en) * 2015-06-01 2018-02-09 후루카와 덴키 고교 가부시키가이샤 CONSTRUCTION MATERIAL AND PREPARATION METHOD
KR102521145B1 (en) * 2015-06-01 2023-04-13 후루카와 덴키 고교 가부시키가이샤 Conductive material and its manufacturing method
JP2020086389A (en) * 2018-11-30 2020-06-04 富士通株式会社 Optical component, and optical module using the same
JP7147517B2 (en) 2018-11-30 2022-10-05 富士通オプティカルコンポーネンツ株式会社 Optical component and optical module using the same

Similar Documents

Publication Publication Date Title
JP2002299486A (en) Package for storing optical semiconductor element
JP2007043073A (en) Package for storing optical semiconductor element and optical semiconductor device
JPH09307122A (en) Photocell module
US5134246A (en) Ceramic-glass integrated circuit package with integral ground and power planes
JP2001060635A (en) Optical semiconductor element housing package
JP3631638B2 (en) Mounting structure of semiconductor device package
JP2001102469A (en) Package for semiconductor element
JP2002289957A (en) Package for housing optical semiconductor element
JPH10189815A (en) Mounting structure for semiconductor element mounting substrate
JP2001160598A (en) Substrate for mounting semiconductor device and package for housing optical semiconductor device
JP3426827B2 (en) Semiconductor device
JP3732923B2 (en) Wiring board
JP2002076193A (en) Semiconductor element storing package and package mounting board
JP3740225B2 (en) Wiring board mounting structure
JP2002255636A (en) Porcelain fired at low temperature and method of producing the same
JP2001244390A (en) Package for semiconductor device and mounting structure
US11264293B2 (en) Wiring board, electronic device package, and electronic device
JP3420447B2 (en) Wiring board mounting structure
JP2001102492A (en) Wiring board and mounting structure thereof
JP3610239B2 (en) Wiring board for mounting semiconductor device and mounting structure thereof
JP3677468B2 (en) Package and its mounting structure
JP2002324876A (en) Wiring board and its mounting method
JP3914764B2 (en) Optical semiconductor device
JP3847237B2 (en) Semiconductor element storage package and semiconductor device using the same
JP2005012032A (en) Package for housing optical semiconductor element, and optical semiconductor device

Legal Events

Date Code Title Description
A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20040930

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20050111

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20050314

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20050314

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20050621