JP2002246608A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve a problem that variation of output is significant in a conventional analog buffer circuit comprising a polycrystalline semiconductor TFT and a countermeasure of providing a correction circuit causes complication of circuitry and driving operation. SOLUTION: Gate length and gate width of a TFT constituting the analog buffer circuit are increased and a multi-gate structure is employed. In addition, arrangement of a channel part is contrived. Consequently, an analog buffer circuit having insignificant variation can be obtained without using a correction circuit and a semiconductor device having insignificant variation can be provided.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a semiconductor device. In particular, the present invention relates to a semiconductor device having an analog buffer circuit including a TFT (thin film transistor) having a polycrystalline semiconductor layer. Further, the present invention relates to a semiconductor device as an image display device.

[0002]

2. Description of the Related Art In recent years, the demand for information communication equipment has been increased due to the activation of information communication. Here, a display device for displaying an image is indispensable for these information communication devices. As the display device, a liquid crystal display device using a liquid crystal, E
There are EL display devices and the like using an L (electroluminescence) element, but with the enlargement and high definition of the display unit,
Active matrix display devices in which a TFT is arranged for each pixel are becoming mainstream.

FIG. 8 is a block diagram of an active matrix type display device. A source signal line driver circuit and a gate signal line driver circuit are arranged around the pixel portion. The pixel portion, the source signal line driver circuit, and the gate signal line driver circuit are formed over a substrate. A signal output from the source signal line driving circuit is input to a source signal line and transmitted to each pixel. Further, a signal output from the gate signal line driving circuit is input to the gate signal line and transmitted to each pixel. As a structure of the pixel portion, there are a structure using liquid crystal, a structure using an EL element, and the like. Here, FIG. 15 illustrates an example of a structure of a pixel using an EL element.

[0004] In this specification, an EL element is
It includes both one that emits light from a singlet state (fluorescence) and one that emits light from a triplet state (phosphorescence).

The gate electrode of the switching TFT is connected to a gate signal line, one of a source region and a drain region is connected to a source signal line, and the other is connected to one electrode of a capacitor and the gate electrode of an EL driving TFT. It is connected. T for switching with capacitor electrode
The side not connected to the FT is connected to a power supply line. One of a source region and a drain region of the EL driving TFT is connected to a power supply line, and the other is connected to an EL element.

A method of driving the pixel having the above configuration will be briefly described.

In the pixel where the gate signal line is selected,
The analog signal voltage input from the source signal line is applied to the capacitor and the gate electrode of the EL driving TFT via the switching TFT which is turned on. With this applied voltage, a current flows from the power supply line to the EL element via the EL driving TFT or in the reverse direction. The EL element emits light with luminance according to the flowing current.

In order to reduce the size of the display device and to reduce the manufacturing cost, an attempt has been made to manufacture a pixel portion and a driver circuit portion (a source signal line driver circuit and a gate signal line driver circuit) on one substrate. ing. At this time, TFTs forming a pixel portion and a driver circuit portion are manufactured using the polycrystalline semiconductor layer.

Here, a configuration of a source signal line driving circuit for outputting an analog signal to the source signal line will be described. Note that x
It is assumed that a source signal line driving circuit outputs an analog signal to (x is a natural number) source signal lines. As a driving method of the source signal line driving circuit, there are a dot sequential driving and a line sequential driving.

First, the dot sequential driving will be described. In the dot sequential driving, signals are sequentially input to each of the source signal lines. FIG. 9 is a block diagram of a source signal line driving circuit for dot sequential driving.

The source signal line driving circuit includes a shift register 901, an analog signal input line 903, and a switching circuit 904 (SW.1 to SW.x), and outputs signals to the source signal lines S1 to Sx.

The sampling signal from the shift register 901 causes the analog signal voltage input from the analog signal input line 903 to change into the switching circuit 904 (S
W. 1 to SW. x), the source signal lines S1 to S1
Output to Sx.

At this time, the length of the effective horizontal scanning period is set to H1.
Assuming that the number of source signal lines (the number of pixels in the horizontal direction) is N as (about 80% of the horizontal scanning period), the period that can be used to input a signal per source signal line is H1 / N.

This driving method has an advantage that the configuration of the driving circuit can be simplified. However, the period H1 / N of signal output per pixel is short in a display device having a large display portion or a high-definition display device because N is large, and cannot be set sufficiently. Therefore, line-sequential driving, which will be described next, is mainly used.

FIG. 10 is a block diagram of a source signal line driving circuit for line sequential driving.

The source signal line driving circuit shown in FIG. 10 includes a shift register 101, an analog signal input line 103, a signal transfer line 106, holding capacitors 105 and 108, first switching circuits (SW1.1 to SW1.x) 104, A second switching circuit (SW 2. 1 to SW 2 .x) 107 and an analog buffer circuit (AB. 1 to AB. X) 109 are provided. An analog signal input from the analog signal input line 103 is sampled by a sampling signal from the shift register 101 and stored in the storage capacitor 105 via the first switching circuit 104. After holding the signal for one line, the signal transfer line 106
The second switching circuit 10
7 and is stored in the next storage capacitor 108. Here, the held signals are simultaneously transmitted by one line for the source signal lines S1 to S1.
Output to Sx. Here, while the signals are being output to the source signal lines S1 to Sx, that is, immediately after the signals are output to the second switching circuit 107, the signals for the next one horizontal line are output from the analog signal input lines to the first signal lines. The data is sequentially stored in the storage capacitor 105 via one switching circuit 104.

According to this driving method, the source signal line driving circuit holds output signals for one horizontal line and then outputs the signals to the source signal lines all at once. Therefore, even in a display device having a large number of pixels, a period during which a signal is output to a source signal line can be sufficiently set.

Here, when the panel is large, the load applied to one source signal line increases. In order to reduce the influence of signal dullness due to the load, a signal amplifier circuit is required. Therefore, in the block diagram of FIG. 10, before outputting a signal to the source signal line, an analog buffer circuit (AB.1 to AB.x) 109 is arranged as a signal amplifier circuit. FIG. 5 shows an example of this analog buffer circuit.

In FIG. 5, the analog buffer circuit comprises:
It comprises a differential circuit 5501, a current mirror circuit 5502, and a constant current source 5503. Differential circuit 55
01 is composed of TFT5505 and TFT5506. The current mirror circuit 5502 includes a TFT
5507 and a TFT 5508.
The constant current source 5503 includes a TFT 5504.

The gate electrodes of the TFT 5507 and the TFT 5508 are connected to each other. TFT5507 and T
One of a source region and a drain region of the FT 5508 is connected to the power supply line Vdd, and the other is connected to the TFT 550.
5 and one of the source region and the drain region of the TFT 5506. TFT
The power supply line V in the source or drain region of 5507
The side not connected to dd is connected to the gate electrode of the TFT 5507. One of the source region and the drain region of the TFT 5506 that is connected to the TFT 5508 is connected to a gate electrode of the TFT 5506, and is connected to an output terminal. A gate electrode of the TFT 5505 is connected to an input terminal to which an input signal is input. One of a source region and a drain region of the TFT 5504 is a source region or a drain region of the TFT 5505 and the TFT 5506, and the TFT 5507 and the TF
It is connected to the side not connected to T5508, and the other is grounded. A bias voltage is input to a gate electrode of the TFT 5504.

The analog signal voltage input to the input terminal is impedance-converted to increase the current capability and is output from the output terminal. Thus, even when the load on the source signal line for outputting a signal is large, the influence of rounding can be suppressed and the signal can be transmitted.

FIGS. 9 and 10 show an example of a source signal line driving circuit which receives an analog signal and outputs the analog signal. On the other hand, a source signal line driving circuit that inputs a digital signal, converts the signal into an analog signal by a digital / analog converter (D / A converter), and outputs the signal to a source signal line is also similarly used in a large panel. An analog buffer circuit is provided by applying sequential driving. FIG. 18 shows an example of this source signal line driving circuit.

FIG. 18 shows an example of a source signal line drive circuit configured to input and sample 4-bit digital signals in parallel.

In FIG. 18, a source signal line driving circuit includes a shift register, a digital signal input line VD, a latch 1 (LAT1, 1 to LAT1, x), and a latch 2 (LAT
2, LAT2, x), latch pulse lines, D / A converters (DAC1 to DACx), and analog buffer circuits (AB.1 to AB.x).

In response to the timing signal of the shift register, a signal is sampled from the digital signal input line VD to the latch 1, and a signal for one line period is held in the latch 1.

In FIG. 18, the digital signal input line VD is represented by four wires. The four wirings correspond to signals of the first to fourth bits.
According to the timing signal of the shift register, the first to fourth bit signals are simultaneously sampled by the latch 1 for each signal corresponding to each source signal line.

Thereafter, a signal for one line period is transferred to the latch 2 by the latch pulse input to the latch pulse line. The signal of the latch 2 is analog-converted by the D / A converter. The converted analog signals are simultaneously sent to a source signal line S1 via an analog buffer circuit.
To Sx. Thus, an image is displayed by line-sequential driving.

[0028]

It is assumed that the analog buffer circuit shown in FIG. 5 is configured using a TFT whose channel region is formed by a polycrystalline semiconductor layer. In this specification, the channel region is formed of a polycrystalline semiconductor layer.
The FT is called a polycrystalline TFT.

Here, in order for this analog buffer circuit to operate normally, two (one pair) constituting a differential circuit are required.
The characteristics of the TFTs must be the same, and the characteristics of the two (one pair) TFTs forming the current mirror circuit must be the same. Here, the two TFTs have the same characteristics when the same gate voltage is applied to the two TFTs.
This indicates that the same drain current flows. However, the characteristics of these TFTs vary greatly in practice. This is because the characteristics of the TFT greatly depend on the crystal state and the like of the polycrystalline semiconductor layer in the channel region.

Therefore, an offset voltage is generated in the analog buffer circuit with respect to the input voltage, and the output voltage varies by the amount of the offset voltage by each analog buffer circuit. Therefore, an attempt has been made to provide a correction circuit to reduce variation in the output voltage of the analog buffer circuit. These methods are disclosed in Japanese Patent Laid-Open No. 2-189.
No. 3 and JP-A-7-162788.

An example of a correction circuit proposed so far is shown below.
The operation will be described.

When the reference voltage V ₀ is input to the analog buffer circuit, the output voltage of the analog buffer circuit becomes (V
₀ + ΔV), and a difference in offset voltage ΔV is assumed to occur. A correction circuit is added to this analog buffer circuit. The correction circuit detects a difference between the output voltage (V ₀ + ΔV) when the reference potential V ₀ is first input to the analog buffer circuit and the reference voltage V ₀ as an offset voltage ΔV. Thereafter, a voltage (V−ΔV) obtained by subtracting the offset voltage ΔV from the input signal voltage V is input to the analog buffer circuit. As a result, the output voltage of the analog buffer circuit becomes
The offset voltage ΔV is canceled and the voltage V is output.

A specific example of such a correction circuit will be described. Here, a correction circuit described in JP-A-7-162788 will be described as an example.

FIG. 6 is an example of a circuit diagram of an analog buffer circuit 61 provided with a correction circuit 62. The correction circuit 62
It is composed of a capacitor 63 and switching TFTs 64 to 68.

Input terminal 61 of analog buffer circuit 61
“a” is connected to the power supply line V ₀ via the switching TFT 64 and at the same time is connected to one electrode of the capacitor 63 via the switching TFT 65.
On the side of the electrode of the capacitor 63 connected to the switching TFT 65,
It is connected to the input terminal 71a of the analog buffer circuit with the correction circuit.

The other electrode of the capacitor 63 is connected to the power supply line V ₀ via the switching TFT 68 and, at the same time, to the output terminal 61 b of the analog buffer circuit 61 via the switching TFT 67. The output terminal 61b of the analog buffer circuit 61 corresponds to the output terminal 71b of the analog buffer circuit with a correction circuit.

It is _assumed that signals of V _{g64 to} V _g68 are input to the gate electrodes of the switching TFTs 64 to 68, respectively.

The operation of FIG. 6 will be described with reference to the timing chart of FIG. The timing chart of FIG. 7 corresponds to a case where n-channel TFTs are used as the switching TFTs 64 to 68. However, there is no problem if p-channel TFTs are used as the switching TFTs 64 to 68. At this time, the signals V _{g64 to} V _g68 are
The phase is opposite to the case where the n-channel TFT is used.

First, at time t ₁ , the signals V _g64 and V _g64
to _g65, V _g67, Hi-level signal voltage is inputted. On the other hand, the signals V _g66 and V _g68 are Lo level signals. Thereby, the switching TFTs 64, 6
5, 67 are in a conductive state, and the switching TFT 66,
68 is non-conductive.

[0040] At this time, the voltage V ₀ which supply line V ₀ through the switching TFT 64, the analog buffer circuit 61
Input terminal 61a, and the switching T
The voltage is applied to the capacitor 63 via the FT 65.

[0041] Then, at time t _2, the left V _G64 and V _G67 is the Hi level, V _G68 is remains Lo level, changing the V _G65 to Lo level, changing the V _G66 to Hi level. Then, the switching TFTs 64, 66,
67 becomes conductive, and the switching TFTs 65 and 68
Becomes non-conductive. Thereby, the input voltage V is input to the capacitor 63 via the switching TFT 66.

Thereafter, at time t ₃ , the signal V _g66 becomes Lo while the switching TFTs 64 and 67 remain conductive.
Level, and the switching TFT 66 is turned off.

Next, at time t ₄ , V _g64 , V _g65 , V _g65
The signal voltage of _g66 does not change, V _g67 changes to Lo level, and V _g68 changes to Hi level. Then, the switching TFTs 64 and 68 are conducting, and the switching TF
T65, 66, and 67 are turned off.

Thus, the voltage V ₀ of the power supply line V ₀ is applied to the electrode of the capacitor 63 via the switching TFT 68.

[0045] Thereafter, at time _{t 5,} V g66 ~V g68
_Remains unchanged, V _g64 goes to Lo level, and V _g65 goes Hi.
Become a level. Then, the switching TFTs 65 and 68 are turned on, and the switching TFTs 64, 66 and 67 are turned off.

Thus, the voltage between the electrodes of the capacitor 63 is input to the input terminal 61 a of the analog buffer circuit 61 via the switching TFT 65.

Here, since the voltage between the electrodes of the capacitor 63 is (V−ΔV), when this voltage is input, the output of the analog buffer circuit 61 becomes V.

By providing the correction circuit 62 as described above,
A voltage excluding the offset voltage ΔV can be output from the analog buffer circuit 61.

However, it takes (t ₅ −t ₁ ) to correct the offset voltage ΔV. In addition, in _order to apply a signal voltage of V _{g64 to} V _g68, a new dedicated signal must be created. However, there is a problem that the signal system becomes complicated and the number of elements increases.

It is to be noted that not only an analog buffer circuit provided with a correction circuit having the configuration shown in FIG. 6 but also a circuit provided with a correction circuit having another configuration has been proposed. After the holding, the input voltage of the analog buffer circuit is changed based on the output voltage to remove the offset voltage from the output of the analog buffer circuit.

[0051]

In an analog buffer circuit including a differential circuit, a current mirror circuit and a constant current source, the characteristics and characteristics of individual TFTs are improved by devising the structure and arrangement of polycrystalline TFTs. So that the difference between them is reduced. In addition, a plurality of TFTs are used, and a circuit operates using an average characteristic thereof. These provide an analog buffer circuit with little variation.

The configuration of the present invention will be described below.

According to the present invention, in a semiconductor device having an analog buffer circuit constituted by a thin film transistor having a channel region formed of a polycrystalline semiconductor, the analog buffer circuit is at least one of a differential circuit and a current mirror circuit. And the gate length (or channel length) of the thin film transistor constituting the differential circuit or the current mirror circuit is 7 μm
As described above, the gate width (or channel width) is 50 μm.
m or more.

According to the present invention, in a semiconductor device having an analog buffer circuit constituted by a thin film transistor having a channel region formed of a polycrystalline semiconductor, the analog buffer circuit is at least one of a differential circuit and a current mirror circuit. And the thin film transistor forming the differential circuit or the current mirror circuit has a multi-gate structure.

According to the present invention, in a semiconductor device having an analog buffer circuit constituted by a thin film transistor having a channel region formed of a polycrystalline semiconductor, the analog buffer circuit is at least one of a differential circuit and a current mirror circuit. And the thin film transistor forming the differential circuit or the current mirror circuit is configured by connecting a plurality of thin film transistors in parallel.

[0056] The semiconductor device may be characterized in that the plurality of thin film transistors are arranged at an angle.

According to the present invention, in a semiconductor device having an analog buffer circuit constituted by a thin film transistor having a channel region formed of a polycrystalline semiconductor, the analog buffer circuit is constituted by a source follower, and constitutes the source follower. The gate length (or channel length) of the thin film transistor is 7 μm
m and the gate width (or channel width) is 50
There is provided a semiconductor device having a thickness of not less than μm.

According to the present invention, in a semiconductor device having an analog buffer circuit constituted by a thin film transistor having a channel region formed of a polycrystalline semiconductor, the analog buffer circuit is constituted by a source follower, and constitutes the source follower. A semiconductor device is provided in which the thin film transistor has a multi-gate structure.

[0059]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The structure of an analog buffer circuit according to the present invention will be described.

A polycrystalline TFT is used as an element constituting the analog buffer circuit. The crystallinity of the polycrystalline semiconductor layer in the channel portion of the TFT is a major factor that determines the characteristics of the TFT.

Here, when the channel region is formed by a polycrystalline semiconductor layer, a boundary (crystal grain boundary) between polycrystalline grains (crystal grains) becomes a problem. The crystal grain boundaries are disturbed in crystallinity unlike the inside of the crystal grains.
Since there is a problem such as segregation of impurities, it acts as a barrier to hinder carrier movement. Therefore, depending on how many crystal grain boundaries exist in the channel portion of the TFT, the T
FT characteristics are significantly different.

In recent years, TFTs have been miniaturized, and TFTs having a channel region width equivalent to the size of crystal grains have come to be formed. Therefore, the characteristics of the TFT change drastically depending on whether or not the crystal grain boundary exists in the channel region.

FIG. 16 schematically shows the relationship between the arrangement of the crystal grain boundaries of the polycrystalline semiconductor layer and the channel region.

In FIG. 16A, since the crystal grain boundary exists so as to cross the channel region, the carrier is affected by the crystal grain boundary and the mobility is reduced. On the other hand, FIG.
In (B), the channel region is located exactly inside the crystal grain, and there is no crystal grain boundary. In this case, since the carriers almost move inside the single crystal, FIG.
The mobility is higher than (A).

As described above, the characteristics of the TFT greatly change depending on whether or not the crystal grain boundary exists in the channel region. Further, even when the crystal grain boundaries exist in the channel region, the variation in the characteristics of each TFT increases depending on the number thereof.

It is preferable that the variation in the number of crystal grain boundaries, which becomes an obstacle when carriers propagate through the channel portion, between the TFTs is reduced.

Therefore, as a first embodiment, in the analog buffer circuit, by increasing the gate length (or channel length) and gate width (or channel width) of the TFT, the number of crystal grains contained in the channel portion is increased. I do. This schematic diagram is shown in FIG. Thus, a TFT having relatively uniform characteristics can be obtained.

FIG. 19 shows the variation of the threshold value (Vth) between the TFT having a gate width of 8 μm and the TFT having a gate width of 200 μm. FIG. 19A shows the variation in the threshold value of a TFT having a gate width of 8 μm, and FIG.
This is a variation in the threshold value of a TFT having a gate width of 200 μm. Here, the gate oxide film (GI) is 950 ° and 1
The measurement results in two cases of 150 ° are shown.

FIG. 19 shows that the larger the gate width is, the larger the TF is.
It can be seen that the variation in the threshold value of T is reduced.

The gate width (or channel width) is 50 μm.
m or more.

The gate length of the TFT and the drain current I
_D and the drain-source voltage V _DS have a relationship as shown in the graph of FIG.

Generally, an FET (Field Effect Transistor)
r: field-effect transistor), the length of the depletion layer changes depending on the drain voltage, so that the effective channel length changes. This has a greater relative effect as the channel length is shorter.

S ₂ is a curve showing the characteristics of the drain current _ID to the drain-source voltage V _{DS of} a TFT having a relatively short gate length L.

On the other hand, S ₁ has a gate length L of T
It is a curve showing the characteristics of drain current I _D with respect to the drain-source voltage V _DS of the FT. According to this graph, in the region A, as compared with a TFT having a short gate length, a longer T
If the FT it can be seen that the change in the drain current I _D is small relative to the change in the voltage V _DS between the drain and source. Therefore, by increasing the gate length L, a TFT with less characteristic variation can be obtained.

For this purpose, it is desirable to set the gate length (or channel length) to 7 μm or more.

As a second embodiment, a TFT is a multi-gate type in order to suppress variations in TFT characteristics. As a result, the TFT characteristics are averaged due to the presence of a plurality of channel regions, and TFTs with little variation
Is obtained. In a multi-gate type TFT,
Since the high electric field around the drain can be reduced and the generation of hot carriers can be suppressed, deterioration of the TFT can be prevented. Further, it also provides a measure against the depletion layer.

In the third embodiment, a plurality of TFTs are connected in parallel, and each TFT has a common gate electrode potential, so that the TFTs are used as one element. As a result, an element having averaged characteristics is obtained.

Here, a plurality of TFTs having the same gate electrode potential and connected in parallel are referred to as a set of TFTs in this specification.
Let's call it FT. That is, each of the differential circuit and the current mirror circuit is composed of two sets (one pair) of TFTs. That is, these two pairs (one pair) of T
If the average characteristics of the FT are the same, the problem of the offset voltage of the analog buffer circuit can be solved.

As a fourth embodiment, a method will be described in which the arrangement of a plurality of TFTs constituting one set of TFTs is devised to make the average characteristics of the two sets of TFTs uniform.

First, a film formation technique, which is an important factor in determining the crystallinity of a polycrystalline semiconductor thin film, will be described. First, a method using a laser, which is generally widely used, will be described.

This is a method in which an amorphous semiconductor thin film is irradiated with a laser to be crystallized.

Here, it becomes more difficult to polycrystallize one panel at a time as the panel becomes larger. This is because it is difficult to uniformly irradiate the entire surface of the panel with the laser, and uneven irradiation may occur depending on the location in the panel. This is because the characteristics of the polycrystalline semiconductor film are greatly different.

Therefore, the following laser irradiation methods have been proposed as the size of the panel increases. For example,
By using a linear laser and sequentially shifting the position of the linear laser, a device for obtaining a polycrystalline thin film having uniform characteristics has been devised. However, it is still difficult to obtain a polycrystalline semiconductor film having uniform characteristics over the entire surface due to the degree of overlap when the linear lasers are sequentially moved and the variation in irradiation energy of the lasers themselves.

Therefore, the TF is set perpendicular to the scanning direction of the linear laser, that is, at a position very close to the line irradiated at a time.
By manufacturing a T channel region, TFTs having relatively similar characteristics can be obtained.

As another crystallization method, there is a method in which crystallization is performed by using a metal catalyst and applying heat.

In this method, a metal catalyst is added to the amorphous semiconductor layer, and the metal catalyst is diffused and moved by applying heat, and crystallization of the amorphous semiconductor layer proceeds along the path of the movement.

Therefore, the crystallization proceeds around the region where the metal catalyst is added, and the characteristics of the polycrystallized semiconductor layer also vary with the distance from the region where the metal catalyst is added. Therefore, at a position where the distance from the metal catalyst added region is equal, the TFT
By arranging the channel portion, a TFT having relatively uniform characteristics can be obtained.

The technique of crystallization using a laser and the technique of crystallization using a metal catalyst can be used in combination.

In the analog buffer circuit of the present invention, TFTs are arranged in consideration of the above. FIG. 11 is a schematic diagram showing this arrangement.

In FIG. 11, two TFTs having the same gate electrode potential are connected in parallel, and as a set of TFTs,
An example of a differential circuit that operates using its average characteristics will be described.
Can be arranged.

FIG. 11A is a schematic top view showing the arrangement of TFTs. Further, FIG.
It is a circuit diagram of (A). FIG. 11A and FIG. 11B are compared.

In FIG. 11A, the TFTs 1111 to 1114 forming the differential circuit are the same as the TFT 1111 and the TF.
T1112 forms one set of TFTs, and TFT1113 and TFT1114 form another set of TFTs. Here, in FIG. 11B, the TFT 1111 and the TFT
The channel portion of 1112 is disposed at a geometrically symmetric position, the channel portions of TFT 1113 and TFT 1114 are disposed at a geometrically symmetric position, and the positions of the two sets of object centers coincide with each other. I have. With this configuration,
Variations in crystallinity depending on positions and other variations in manufacturing can be averaged by the arrangement of the channel regions of the plurality of TFTs. Therefore, two sets of TFTs having relatively uniform characteristics can be obtained, and an analog buffer circuit with little variation can be obtained.

As shown in FIG. 11A, the so-called crossing arrangement can reduce the variation in crystallinity depending on the position and other manufacturing variations.

The arrangement of the TFT channel regions is not limited to the point-symmetric arrangement as shown in FIG. 11 as long as the variation in crystallinity can be averaged by the arrangement of the channel regions of a plurality of TFTs. .

Further, one set of TFTs does not need to be composed of two TFTs, but may be composed of two or more TFTs. If more TFTs are connected in parallel and the circuit is driven using the average property, a circuit with less variation can be obtained.

According to the above-described first to fourth embodiments, variation in TFT characteristics can be suppressed, and TF
By reducing the influence of the characteristic variation of T,
An analog buffer circuit with a reduced offset voltage can be obtained.

The first to fourth embodiments can be implemented in any combination.

For example, a configuration in which the first embodiment is combined with the second embodiment, that is, a multi-gate TF
A configuration in which the gate width (or channel width) is 50 μm or more and the gate length (or channel length) is 7 μm or more corresponding to each of the plurality of gate electrodes included in T is effective.

Further, the configuration in which the first embodiment and the third embodiment are combined, that is, the gate width (or channel width) of each of a plurality of TFTs connected in parallel with a common gate electrode potential is set. A configuration in which the gate length (or channel length) is 50 μm or more and the gate length (or channel length) is 7 μm or more is effective.

[0100]

Embodiments of the present invention will be described below.

Embodiment 1 FIG. 1 shows an example of an analog buffer circuit according to the present invention.

The differential circuit 11 is composed of TFT1 and TFT2, and the current mirror circuit 12 is
And the TFT 4, and the constant current source 13 is a TFT
5. In contrast to the configuration of the conventional analog buffer circuit shown in FIG. 5, in FIG. 1, each TFT of the differential circuit 11, the current mirror circuit 12, and the constant current source 13 is formed by a double-gate TFT.

The gate electrodes of TFT3 and TFT4 are connected. One of a source region and a drain region of the TFT3 and the TFT4 is connected to a power supply line Vdd, and the other is connected to one of a source region and a drain region of the TFT1 and the TFT2. The side of the source region or the drain region of the TFT 3 that is not connected to the power supply line Vdd is connected to the gate electrode of the TFT 3. One of the source region and the drain region of the TFT 2 connected to the TFT 4 is connected to the gate electrode of the TFT 2 and connected to an output terminal from which an output is taken out. The gate electrode of the TFT 1 is connected to an input terminal to which an input signal is input. T
One of the source region and the drain region of FT5 is T
The source region or the drain region of FT1 and TFT2 is connected to the side not connected to TFT3 and TFT4, and the other is grounded. A bias voltage is input to the gate electrode of the TFT 5.

Note that the TFTs 1 to 5 are not limited to the double gate type, but are multi-gate type TFTs having a larger number of gates.
FT is acceptable.

By using such a double-gate type or multi-gate type TFT having a larger number of gates, the characteristics of the channel region are averaged, and an element with less characteristic variation can be obtained. Further, deterioration of the TFT due to hot carriers can be suppressed.

In the figure, an n-channel TFT is used as an element forming the differential circuit 11 and a p-channel TFT is used as an element forming the current mirror circuit 12. The present invention can also be applied to a case where a p-channel TFT is used as an element to be used and an n-channel TFT is used as an element constituting the current mirror circuit 12.

The gate length and gate width of the TFT constituting the analog buffer circuit shown in FIG. 1 are the same as those of another TFT constituting the source signal line drive circuit incorporating the analog buffer circuit (this TFT is referred to as a logic portion TFT). ) Is set to be at least twice as large.

More specifically, the gate length is set to 7 μm or more, and the gate width is set to 50 μm or more.

With the above configuration, an analog buffer circuit with little variation can be obtained.

(Embodiment 2) In this embodiment, an example of an analog buffer circuit having a configuration different from that of Embodiment 1 is shown in FIG. The same parts as those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted.

The analog buffer circuit shown in FIG. 2 is obtained by adding a first amplifier circuit 14 and a second amplifier circuit 15 to the analog buffer shown in FIG.

The first amplifier circuit 14 includes a TFT 20, a TF
It is composed of T22, TFT23 and TFT24, and capacitor 21. The second amplifier circuit 15 includes a TFT
25 and a TFT 26.

The gate electrodes of TFT3 and TFT4 are connected. One of a source region and a drain region of the TFT3 and the TFT4 is connected to a power supply line Vdd, and the other is connected to one of a source region and a drain region of the TFT1 and the TFT2. The side of the TFT 4 that is not connected to the power supply line Vdd in the source or drain region is connected to the gate electrode of the TFT 4. The side of the source region or the drain region of the TFT 3 that is not connected to the power supply line Vdd is TF
It is connected to the gate electrode of T20 and the capacitor 21. The gate electrode of TFT2, TFT25 and TFT2
Either the source region or the drain region of No. 6 is connected and connected to an output terminal from which an output is taken out. The gate electrode of the TFT 1 is connected to an input terminal to which an input signal is input. One of the source region and the drain region of the TFT 5 is connected to the side of the source region or the drain region of the TFT 1 and the TFT 2 that is not connected to the TFT 3 and the TFT 4, and the other is grounded. A bias voltage is input to the gate electrode of the TFT 5. One of the source region and the drain region of the TFT 20 is connected to the power supply line Vdd, and the other is connected to the side of the capacitor 21 that is not connected to the TFT1 and the TFT3, and to the source or drain region of the TFT 22 and the gate electrode. Have been. The gate electrode of the TFT 22 is connected to the gate electrode of the TFT 25. T
TFT2 of source region or drain region of FT22
The side not connected to 0 is connected to either the source region or the drain region of the TFT 23.
TFT of source region or drain region of TFT23
The side not connected to 22 is connected to the gate electrode of the TFT 23, one of the source region or the drain region of the TFT 24, and the gate electrode of the TFT 26. The side of the TFT 24 that is not connected to the TFT 23 in the source region or the drain region is grounded.
A bias voltage is input to the gate electrode of the TFT 24. The side of the TFT 25 connected to the source region or the drain region of the TFT 25 is connected to either the source region or the drain region of the TFT 26. T of the source region or the drain region of the TFT 25
The side not connected to FT2 is connected to power supply line Vdd. The side of the TFT 26 that is not connected to the source region or the drain region of the TFT 26 is grounded.

The TFT constituting the circuit is partly of a double gate type. Note that a multi-gate type having a larger number of gates may be used.

By using such a double-gate type or multi-gate type TFT having a larger number of gates, the characteristics of the channel region are averaged, and an element with less characteristic variation can be obtained. Further, deterioration of the TFT due to hot carriers can be suppressed.

In the figure, an n-channel TFT is used as an element forming the differential circuit 11 and a p-channel TFT is used as an element forming the current mirror circuit 12. The present invention can also be applied to a case where a p-channel TFT is used as an element to be used and an n-channel TFT is used as an element constituting the current mirror circuit 12.

The gate length and gate width of the TFT constituting the analog buffer circuit shown in FIG. 2 are the same as those of another TFT constituting the source signal line driving circuit incorporating the analog buffer circuit (this TFT is referred to as a logic portion TFT). ) Is set to be at least twice as large.

More specifically, the gate length is set to 7 μm or more, and the gate width is set to 50 μm or more.

With the above configuration, an analog buffer circuit with little variation can be obtained.

(Embodiment 3) In this embodiment, an example of an analog buffer having a configuration different from those of Embodiments 1 and 2 will be described with reference to FIG.

The analog buffer circuit shown in FIG.
It is a source follower type configured by T3301 and a constant current source 3302. The constant current source 3302 is
It is configured by FT3303.

A signal is input to the gate electrode of the amplification TFT 3301. One of a source region and a drain region of the amplifying TFT 3301 is connected to a power supply line Vdd, and the other is connected to a source region or a drain region of the TFT 3303 to take an output. T of TFT3303
The side not connected to the FT 3301 is grounded. A bias voltage is input to a gate electrode of the TFT 3303.

Amplifying TFT 3301 and constant current source 3302
Has a double gate type structure. It should be noted that the present invention is not limited to the double gate structure, but may be a multi-gate structure having a larger number of gates.

By using such a double-gate type or multi-gate type TFT having a larger number of gates, the characteristics of the channel region are averaged, and an element with less characteristic variation can be obtained. Further, deterioration of the TFT due to hot carriers can be suppressed.

The gate length and gate width of the TFT constituting the analog buffer circuit shown in FIG. 3 are twice as large as those of the other TFTs (TFTs in the logic portion) constituting the source signal line driving circuit incorporating the analog buffer circuit. The above is set to be large.

More specifically, the gate length is set to 7 μm or more, and the gate width is set to 50 μm or more.

With the above configuration, an analog buffer circuit with less variation can be obtained.

In this embodiment, a plurality of source followers may be connected in parallel.

(Embodiment 4) In this embodiment, an analog buffer circuit having a configuration different from that shown in Embodiments 1 to 3 will be described with reference to FIG.

The analog buffer circuit includes the differential circuit 12
1 and 123, current mirror circuits 122 and 124, and a constant current source 125.

In FIG. 12, TFTs constituting a circuit
Is a double gate type. It should be noted that the present invention is not limited to the double gate structure, but may be a multi-gate structure having a larger number of gates.

By using such a double-gate type or multi-gate type TFT having a larger number of gates, the characteristics of the channel region are averaged, and an element with less characteristic variation can be obtained. Further, deterioration of the TFT due to hot carriers can be suppressed.

The gate length and the gate width of the TFT constituting the analog buffer circuit shown in FIG. 12 are twice as large as those of the other TFTs constituting the source signal line drive circuit incorporating the analog buffer circuit (TFTs in the logic part). The above is set to be large.

More specifically, the gate length is set to 7 μm or more, and the gate width is set to 50 μm or more.

In the differential circuits 121 and 123 and the current mirror circuits 122 and 124, two TFTs 1201, TFT 1202 and TFT 1203 are respectively provided.
TFT 1204, TFT 1205 and TFT 1206,
TFT1207 and TFT1208, TFT1209 and T
FT1210, TFT1211 and TFT1212, TF
T1213 and TFT1214, TFT1215 and TFT
1216 are connected in parallel, and one set of TFT 12
21, 1222, 1225, 1226, 1223, 12
24, 1227 and 1228.

With the above structure, the circuit can be driven using the average characteristics of the two TFTs, so that a circuit with little variation can be obtained as a whole.

In addition, two sets (126 and 127) of one differential circuit and one current mirror circuit are used in parallel. As a result, variation in the analog buffer circuit can be further reduced.

FIG. 13 shows an example of the arrangement of TFTs when the circuit shown in FIG. 12 is actually manufactured.

This is an example in which the substrate on which the polycrystalline semiconductor layer is formed is observed from above.

In FIG. 13, as described in the embodiment, a plurality of TFTs each requiring the same characteristics are provided.
FTs are configured as connected in parallel, the arrangement of the channel regions of the plurality of TFTs is devised, and variation in TFT characteristics due to the positional dependence of the crystallinity of the polycrystalline semiconductor film is reduced.

Here, for the sake of simplicity, FIG.
FIG. 17 shows the arrangement of the TFTs in FIG.

FIG. 12 is compared with FIG. Here, FIG.
2, two sets of TFTs 122 that require the same characteristics
A description will be given focusing on 1 and 1222.

TFT 1 forming one set of TFT 1221
201 and the TFT 1202 are arranged point-symmetrically with respect to a certain target center. On the other hand, another set of TFT122
The TFTs 1203 and 1204 that constitute the second pixel 2 are also arranged pointwise with respect to a certain target center. The object centers of the two sets of TFTs coincide. As a result, two sets of TFTs having similar characteristics can be obtained. Other two sets of TFT1
223 and 1224, 1225 and 1226, 1227 and 1
228 has the same arrangement.

Although the two sets of TFTs forming the differential circuit have been described, the two sets of TFTs forming the current mirror circuit have been described.
The same applies to.

As described above, the so-called TFT
By arranging the channel regions described above, an analog buffer circuit with little variation can be obtained.

FIG. 20 shows the characteristics of the analog buffer circuit having the above configuration.

[0147] Figure 20 (A) is a graph showing characteristics of output voltage V _{ou t} for the input voltage V _in of the analog buffer circuit.

[0148] FIG. 20 (B) is a graph input voltage V _in of the analog buffer circuits are at the level of the output voltage V _out relative to 4.0V. The results for 40 measurement points are shown.

[0149] FIG. 20 (C) are graphs input voltage V _in of the analog buffer circuits are at the level of the output voltage V _out for 8.0 V. The results for 40 measurement points are shown.

[0150] FIG. 20 (D) is a graph input voltage V _in of the analog buffer circuits are at the level of the output voltage V _out for 12.0 V. The results for 40 measurement points are shown.

In the analog buffer circuit using the polycrystalline TFT, the variation of the output voltage could be reduced to 50 mV or less.

With the above configuration, an analog buffer circuit with little variation can be obtained.

Embodiment 5 In this embodiment, a case where an EL display device is manufactured as a semiconductor device having the analog buffer circuit of the present invention will be described. In this EL display device, a method for simultaneously manufacturing a pixel portion and a TFT of a driver circuit provided around the pixel portion (typically, an n-channel TFT and a p-channel TFT) on the same substrate is described with reference to FIGS. This will be described in detail with reference to FIG.

First, in this embodiment, Corning # 70
A substrate 300 made of glass such as barium borosilicate glass represented by 59 glass or # 1737 glass, or aluminoborosilicate glass is used. Note that the substrate 300 is not limited as long as it is a light-transmitting substrate, and a quartz substrate may be used. Further, a plastic substrate having heat resistance enough to withstand the processing temperature of this embodiment may be used.

Next, a base film 301 made of an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is formed over the substrate 300. Although a two-layer structure is used as the base film 301 in this embodiment, a single-layer film of the insulating film or a structure in which two or more layers are stacked may be used. As the first layer of the base film 301, a plasma CVD method is used, and SiH ₄ , N
The silicon oxynitride film 301a formed by using H ₃ and N ₂ O as reaction gases is formed to a thickness of 10 to 200 nm (preferably 50 to 1 nm).
00 nm). In this embodiment, a 50-nm-thick silicon oxynitride film 301a (composition ratio Si = 32%, O = 27
%, N = 24%, H = 17%). Next, as the second layer of the base film 301, a silicon oxynitride film 301b formed using SiH ₄ and N ₂ O as a reaction gas is formed to a thickness of 50 to 200 nm (preferably 100 to 150 nm) by a plasma CVD method. The layers are formed to a thickness. In this embodiment, a 100-nm-thick silicon oxynitride film 301b (composition ratio: Si = 32%, O = 59%, N = 7%, H = 2%) was formed.

Next, the semiconductor layers 302 to 30 are formed on the underlying film.
5, 381 are formed. Semiconductor layers 302 to 305, 38
1 is to form a semiconductor film having an amorphous structure by a known means (sputtering method, LPCVD method, plasma CVD method, or the like) and then perform a known crystallization treatment (laser crystallization method, thermal crystallization method, Alternatively, a crystalline semiconductor film obtained by performing a thermal crystallization method using a catalyst such as nickel) is patterned and formed into a desired shape. This semiconductor layer 302
305 and 381 have a thickness of 25 to 80 nm (preferably 30 to 60 nm). The material of the crystalline semiconductor film is not limited, but is preferably silicon (silicon) or silicon germanium (Si _x Ge _1-x (X = 0.00
01-0.02)) It is good to form with an alloy etc. In this embodiment, after a 55 nm amorphous silicon film is formed by using the plasma CVD method, a solution containing nickel is held on the amorphous silicon film. Dehydrogenation (500
(1 ° C., 1 hour), thermal crystallization (550 ° C., 4 hours), and a laser annealing treatment for improving crystallization were performed to form a crystalline silicon film. And
The crystalline silicon film is patterned by photolithography to form semiconductor layers 302 to 305 and 38.
1 was formed.

After the formation of the semiconductor layers 302 to 305 and 381, a small amount of impurity element (boron or phosphorus) may be doped in order to control the threshold voltage of the TFT.

In the case of manufacturing a crystalline semiconductor film by a laser crystallization method, a pulse oscillation type or continuous emission type excimer laser, a YAG laser, or a YVO ₄ laser can be used. In the case of using these lasers, it is preferable to use a method in which laser light emitted from a laser oscillator is linearly condensed by an optical system and irradiated on a semiconductor film. The crystallization conditions are appropriately selected by the practitioner. When an excimer laser is used, the pulse oscillation frequency is 30 Hz, and the laser energy density is 100 to 40.
(Typically ^{200~300mJ / cm 2) 0mJ / cm} 2 to. When a YAG laser is used, the second
It is preferable that the pulse oscillation frequency is 1 to 10 kHz using a harmonic and the laser energy density is 300 to 600 mJ / cm ² (typically 350 to 500 mJ / cm ² ). Then, a laser beam condensed linearly with a width of 100 to 1000 μm, for example, 400 μm, is irradiated over the entire surface of the substrate, and the superposition rate (overlap rate) of the linear laser light at this time is set to 50 to 90%. Good.

Next, the semiconductor layers 302 to 305, 381
Is formed to cover the gate insulating film 306. Gate insulating film 3
Reference numeral 06 denotes an insulating film containing silicon having a thickness of 40 to 150 nm by using a plasma CVD method or a sputtering method. In this embodiment, 110 nm is formed by a plasma CVD method.
Silicon oxynitride film (composition ratio Si = 32%, O = 5
9%, N = 7%, H = 2%). Needless to say, the gate insulating film is not limited to the silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a stacked structure.

When a silicon oxide film is used, TEOS (Tetraethyl Orthosilicate) is formed by a plasma CVD method.
And O ₂ , a reaction pressure of 40 Pa and a substrate temperature of 300
It can be formed by discharging at a high frequency (13.56 MHz) and a power density of 0.5 to 0.8 W / cm ² . The silicon oxide film thus manufactured can obtain favorable characteristics as a gate insulating film by subsequent thermal annealing at 400 to 500 ° C.

Next, as shown in FIG. 21A, a first conductive film 307 having a thickness of 20 to 100 nm and a second conductive film 3 having a thickness of 100 to 400 nm are formed on the gate insulating film 306.
08 are laminated. In this embodiment, a first conductive film 307 made of a TaN film having a thickness of 30 nm and a
A second conductive film 308 made of a W film having a thickness of m was laminated.
The TaN film was formed by a sputtering method, and was sputtered using a Ta target in an atmosphere containing nitrogen. The W film was formed by a sputtering method using a W target. In addition, thermal CV using tungsten hexafluoride (WF ₆ )
It can also be formed by Method D. In any case, it is necessary to lower the resistance in order to use it as a gate electrode,
It is desirable that the resistivity of the W film be 20 μΩcm or less. The resistivity of the W film can be reduced by enlarging the crystal grains. However, when the W film contains many impurity elements such as oxygen, the crystallization is inhibited and the resistance is increased. Therefore, in this embodiment, the W film is formed by a sputtering method using a high-purity W (purity of 99.9999%) target, and further taking care not to mix impurities from the gas phase during film formation. By forming, a resistivity of 9 to 20 μΩcm could be realized.

In this embodiment, the first conductive film 307 is used.
Is TaN, and the second conductive film 308 is W. However, the present invention is not particularly limited, and any of Ta, W, Ti, Mo, Al, Cu,
It may be formed of an element selected from Cr and Nd, or an alloy material or a compound material containing the element as a main component.
Alternatively, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus may be used. Also, Ag,
An alloy made of Pd and Cu may be used. The first conductive film is formed of a tantalum (Ta) film, the second conductive film is formed of a W film, and the first conductive film is formed of titanium nitride (T
iN) film, the second conductive film is a W film, the first conductive film is a tantalum nitride (TaN) film, and the second conductive film is an Al film. The conductive film may be formed using a tantalum nitride (TaN) film and the second conductive film may be formed using a Cu film.

Next, as shown in FIG.
A mask 309 to be made of a resist by using a lithography method
313 and a first for forming electrodes and wirings.
Perform an etching process. In the first etching process, the first
And under the second etching condition. In this embodiment, the first
Etching conditions are ICP (Inductively Coupled).
Plasma: Inductively coupled plasma) etching method
CF for gas for etching _FourAnd Cl_TwoAnd O_TwoAnd use
The gas flow ratio is 25/25/10 (sccm),
At a pressure of 1 Pa, a 500 W RF (1
3.56 MHz) power is applied to generate plasma and
Was performed. Here, Matsushita Electric Industrial Co., Ltd.
Dry etching equipment using ICP (Model E64
5- □ ICP) was used. Also on the substrate side (sample stage)
Apply 150W RF (13.56MHz) power,
A qualitatively negative self-bias voltage is applied. This first d
Etching the W film according to the etching conditions to form a first conductive layer
Are tapered. Under the first etching condition
Is 200.39 nm / mi for W.
n, the etching rate for TaN is 80.32 nm /
min and the selectivity ratio of W to TaN is about 2.5.
is there. In addition, the first etching condition allows the W
The taper angle is about 26 °.

Thereafter, as shown in FIG. 21B, the masks 309 to 313 made of resist are not removed and the second etching condition is changed, and CF ₄ and Cl ₂ are used as etching gases.
And the respective gas flow ratios are set to 30/30 (scc
m), a 500 W RF (13.56 MHz) power was applied to the coil-type electrode at a pressure of 1 Pa to generate plasma, and etching was performed for about 30 seconds. A 20 W RF (13.56 MHz) power is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. Under the second etching condition in which CF ₄ and Cl ₂ are mixed, the W film and the TaN film are etched to the same extent. Second
The etching rate for W under the etching conditions of
The etching rate for 8.97 nm / min and TaN is 66.43 nm / min. Note that in order to perform etching without leaving a residue on the gate insulating film, 10
It is preferable to increase the etching time by about 20%.

In the first etching process, by making the shape of the mask made of resist suitable,
The ends of the first conductive layer and the second conductive layer are tapered due to the effect of the bias voltage applied to the substrate side. The angle of the tapered portion may be 15 to 45 degrees. In this manner, the first shape conductive layers 314 to 318 (the first conductive layers 314 a to 318 a and the second conductive layer 314 b) including the first conductive layer and the second conductive layer are formed by the first etching process.
To 318b). Reference numeral 319 denotes a gate insulating film. A region which is not covered with the first shape conductive layers 314 to 318 is etched by about 20 to 50 nm to form a thinned region.

Then, a first doping process is performed without removing the resist mask to add an impurity element imparting n-type to the semiconductor layer (FIG. 21B). The doping treatment may be performed by an ion doping method or an ion implantation method. The condition of the ion doping method is that the dose amount is 1 × 10
^{13 to} 5 × 10 ¹⁵ atoms / cm ³ and an acceleration voltage of 60
It is performed as １００100 keV. In this embodiment, the dose is 1.5 × 10 ¹⁵ atoms / cm ³ , and the acceleration voltage is 80
It was performed as keV. As the impurity element imparting n-type, an element belonging to Group 15 of the periodic table, typically phosphorus (P) or arsenic (As) is used. Here, phosphorus (P) is used. In this case, the conductive layers 314 to 318 serve as a mask for the impurity element imparting n-type, and the high-concentration impurity regions 320 to 323 and 382 are formed in a self-aligned manner. The high-concentration impurity regions 320 to 323 and 382 have 1 × 10 ²⁰ to 1 × 1
An impurity element for imparting n-type is added in a concentration range of 0 ²¹ atoms / cm ³ .

Next, as shown in FIG. 21C, a second etching process is performed without removing the resist mask. Here, CF ₄ , Cl _2, and O are used as etching gases.
₂ and the respective gas flow ratios are 20/20/20
(Sccm) and a pressure of 1 Pa applies 5
An RF (13.56 MHz) power of 00 W was applied to generate plasma to perform etching. A 20 W RF (13.56 MHz) power is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. Second
The etching rate for W in the etching process is 12
The etching rate for 4.62 nm / min and TaN is 20.67 nm / min, and the selectivity ratio of W to TaN is 6.05. Therefore, the W film is selectively etched. The taper angle of W became 70 ° by the second etching. By this second etching process, second conductive layers 324b to 328b are formed. on the other hand,
Since the first conductive layers 314a to 318a are hardly etched, the shapes of the first conductive layers 324a to 328a are almost the same as those of the first conductive layers 314a to 318a.

Next, a second doping process is performed as shown in FIG. Doping is performed on the second conductive layer 32
Using the masks 4b to 328b as masks for the impurity elements, the semiconductor layers below the tapered portions of the first conductive layers 324a to 328a are doped so that the impurity elements are added. In this embodiment, P (phosphorus) was used as an impurity element, and plasma doping was performed at a dose of 1.5 × 10 ¹⁴ atoms / cm ³ , a current density of 0.5 μA, and an acceleration voltage of 90 keV. Thus, low-concentration impurity regions 329 to 332 overlapping with the first conductive layer are formed in a self-aligned manner. The concentration of phosphorus (P) added to these low concentration impurity regions 329 to 332 is 1 × 10 ^{17 to} 5 × 10 ¹⁸ atoms /
cm ³ , and has a gentle concentration gradient according to the thickness of the tapered portion of the first conductive layer. Note that in the semiconductor layer overlapping with the tapered portion of the first conductive layer, the impurity concentration is slightly reduced from the end of the tapered portion of the first conductive layer toward the inside, but is approximately the same. . In addition, high-concentration impurity regions 320 to 323 and 382
To the high concentration impurity region 333-
337 is formed.

Next, as shown in FIG. 22B, the mask made of resist is removed, and then a third etching process is performed by using photolithography. This third etching treatment is performed in order to partially etch the tapered portion of the first conductive layer so that the tapered portion overlaps with the second conductive layer. However, in a region where the third etching is not performed, as shown in FIG.
38, 339) are formed.

Etching in Third Etching Process
The conditions are Cl as an etching gas. _TwoAnd SF₆Using
Each gas flow ratio is 10/50 (sccm)
ICP etching method as well as first and second etching
This is performed using The TaN in the third etching process
Is 111.2 nm / min.
The etching rate for the gate insulating film is 12.8.
nm / min.

In this example, etching was performed by applying a 500 W RF (13.56 MHz) power to the coil-type electrode at a pressure of 1.3 Pa to generate plasma. 10 W RF (13.56 MH) also on the substrate side (sample stage)
z) Turn on the power and apply a substantially negative self-bias voltage. As described above, the first conductive layers 340a to 342a
Is formed.

By the third etching, impurity regions (LD which do not overlap with first conductive layers 340a to 342a)
D regions) 343 to 345 are formed. Note that impurity regions (GOLD regions) 346 and 347 remain overlapping first conductive layers 324a and 326a.

Further, an electrode formed by the first conductive layer 324a and the second conductive layer 324b ultimately becomes a gate electrode of an n-channel TFT of a driver circuit. The electrode formed with the second conductive layer 340b finally becomes the gate electrode of the p-channel TFT of the driver circuit.

Similarly, the electrode formed by the first conductive layer 341a and the second conductive layer 341b finally becomes the gate electrode of the n-channel TFT in the pixel portion, and the first conductive layer 342a and the second The electrode formed by the second conductive layer 342b finally becomes a gate electrode of a p-channel TFT in the pixel portion. Further, the first conductive layer 326a and the second conductive layer 3
26b finally becomes one electrode of a capacitor (holding capacity) of the pixel portion.

As described above, in this embodiment, the impurity regions (LDDs) which do not overlap with the first conductive layers 340a to 342a are formed.
Regions) 343 to 345 and impurity regions (GOLD regions) 346 and 347 overlapping with the first conductive layers 324a and 326a can be formed at the same time, and can be separately formed according to TFT characteristics.

Next, masks 338 and 33 made of resist are used.
After removing 9, the gate insulating film 319 is etched.
I do. Here, the etching process is performed by adding C to the etching gas.
HF _ThreeUsing reactive ion etching (RIE)
This is performed using In this embodiment, the chamber pressure is 6.7P
a, RF power 800W, CHF_ThreeGas flow rate 35sccm
A third etching process was performed.

Thus, high concentration impurity regions 333-3
A part of 37 is exposed, and insulating films 356a to 356e are formed.

Next, a mask 3 made of a new resist
48 and 349 are formed and a third doping process is performed.
By this third doping process, a p-channel TFT
In the semiconductor layer to be an active layer, impurity regions 350 to 355 to which an impurity element imparting a conductivity type (p type) opposite to the one conductivity type (n type) is added are formed. (FIG. 22 (C))
Using the first conductive layers 340a, 326a, and 342a as a mask for the impurity element, an impurity element imparting p-type is added to form an impurity region in a self-aligned manner.

In this embodiment, the impurity regions 350 to 355
Is formed by an ion doping method using diborane (B ₂ H ₆ ). During the third doping process, the semiconductor layers forming the n-channel TFT are covered with resist masks 348 and 349. By the first doping process and the second doping process, the impurity region 3
Phosphorus is added at different concentrations to 50 to 355, but the concentration of the impurity element imparting p-type is 2 × 10 ²⁰ to 2 × 10 ²¹ atoms in any of the regions.
/ cm ³ , doping
There is no problem because it functions as the source and drain regions of the channel type TFT.

Through the above steps, impurity regions are formed in the respective semiconductor layers.

In this embodiment, the method of doping the impurity (boron) after etching the gate insulating film has been described. However, the impurity may be doped without etching the gate insulating film.

Next, a mask 348 made of resist is used.
349 is removed, and a first interlayer insulating film 357 is formed as shown in FIG. This first interlayer insulating film 357
As, using a plasma CVD method or a sputtering method,
The insulating film containing silicon is formed with a thickness of 100 to 200 nm. In this embodiment, the film thickness is 1 by the plasma CVD method.
A 50 nm silicon oxynitride film was formed. Needless to say, the first interlayer insulating film 357 is not limited to a silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a stacked structure.

Next, a step of activating the impurity element added to each semiconductor layer is performed. This activation step is performed by a thermal annealing method using a furnace annealing furnace. As a thermal annealing method, the oxygen concentration is 1 ppm or less,
400 to 400 ppm in a nitrogen atmosphere of preferably 0.1 ppm or less.
700 ° C., typically at 500-550 ° C.
In this embodiment, the activation treatment is performed by heat treatment at 550 ° C. for 4 hours. Note that, other than the thermal annealing method, a laser annealing method or a rapid thermal annealing method (RTA method) can be applied.

In this embodiment, at the same time as the activation treatment, the nickel used as a catalyst at the time of crystallization contains impurity regions (350, 351 and 352) containing a high concentration of phosphorus.
And the nickel concentration in the semiconductor layer which mainly becomes a channel formation region is reduced. A TFT having a channel formation region manufactured in this manner has a low off-current value and high crystallinity, so that a high field-effect mobility can be obtained and favorable characteristics can be achieved.

An activation process may be performed before forming the first interlayer insulating film. However, when the wiring material used is weak to heat, after forming an interlayer insulating film (an insulating film containing silicon as a main component, for example, a silicon nitride film) for protecting the wiring and the like as in this embodiment, the active material is activated. It is preferable to carry out a chemical treatment.

In addition, after the activation process, the first interlayer insulating film 357 may be formed by performing a doping process.

Further, a heat treatment is performed at 300 to 550 ° C. for 1 to 12 hours in an atmosphere containing 3 to 100% of hydrogen to hydrogenate the semiconductor layer. In this embodiment, heat treatment was performed at 410 ° C. for one hour in a nitrogen atmosphere containing about 3% of hydrogen. In this step, dangling bonds in the semiconductor layer are terminated by hydrogen contained in the interlayer insulating film. As another means of hydrogenation, plasma hydrogenation (using hydrogen excited by plasma) may be performed.

When a laser annealing method is used as the activation treatment, it is desirable to irradiate a laser beam such as an excimer laser or a YAG laser after the above-mentioned hydrogenation.

Next, as shown in FIG. 23B, a second interlayer insulating film 358 made of an organic insulating material is formed on the first interlayer insulating film 357. In this embodiment, the film thickness is 1.6 μm.
m of the acrylic resin film was formed. Next, patterning for forming a contact hole reaching each of the impurity regions 333, 336, 350, and 352 is performed.

As second interlayer insulating film 358, a film made of an insulating material containing silicon or an organic resin is used. As the insulating material containing silicon, silicon oxide, silicon nitride, or silicon oxynitride can be used. As the organic resin, polyimide, polyamide, acrylic, BCB (benzocyclobutene), or the like can be used.

In this embodiment, a silicon oxynitride film formed by a plasma CVD method was formed. Note that the thickness of the silicon oxynitride film is preferably 1 to 5 μm (more preferably 2 to 4 μm). A silicon oxynitride film is effective in suppressing deterioration of an EL element because moisture contained in the film itself is small.

Although dry etching or wet etching can be used for forming the contact hole, it is preferable to use a wet etching method in consideration of the problem of electrostatic breakdown at the time of etching.

Further, in forming the contact hole here, the first interlayer insulating film 357 and the second interlayer insulating film 3 are formed.
58 are simultaneously etched, and considering the shape of the contact hole, the material for forming the second interlayer insulating film is the first material.
It is preferable to use a material having an etching rate higher than that of the material for forming the interlayer insulating film 357.

Then, each of the impurity regions 333, 336, 3
Wirings 359 to 359 to be electrically connected to 50 and 352, respectively.
366 are formed. And a 50 nm thick Ti film;
Although a laminated film of a 500-nm-thick alloy film (an alloy film of Al and Ti) is formed by patterning, another conductive film may be used.

Next, a transparent conductive film is further formed on the transparent conductive film.
The transparent electrode 367 is formed by forming a pattern with a thickness of 0 nm and patterning. (FIG. 23 (B))

In this embodiment, an indium tin oxide (ITO) film or indium oxide is used as a transparent electrode.
A transparent conductive film mixed with 20% of zinc oxide (ZnO) is used.

The transparent electrode 367 is connected to the drain wiring 3
The EL driving T
An electrical connection is formed with the drain region of the FT.

Next, as shown in FIG. 24A, an insulating film containing silicon (a silicon oxide film in this embodiment) is formed to a thickness of 500 nm, and an opening is formed at a position corresponding to the transparent electrode 367. Third interlayer insulating film 3 formed and functioning as a bank
68 are formed. When the opening is formed, a tapered side wall can be easily formed by using a wet etching method. Care must be taken because if the side wall of the opening is not sufficiently smooth, deterioration of the EL layer due to the step will become a significant problem.

In this embodiment, a film made of silicon oxide is used as the third interlayer insulating film. However, depending on the case, polyimide, polyamide, acryl, BCB may be used.
An organic resin film such as (benzocyclobutene) can also be used.

Next, an EL layer 369 is formed by an evaporation method, and a cathode (MgAg electrode) 370 and a protection electrode 371 are formed by an evaporation method. At this time, it is preferable that heat treatment be performed on the transparent electrode 367 before the EL layer 369 and the cathode 370 are formed to completely remove moisture. In this embodiment, Mg is used as the cathode of the EL element.
Although an Ag electrode is used, other known materials may be used.

It is to be noted that a known material can be used for the EL layer 369. In this embodiment, the hole transport layer (Hole
transporting layer) and emitting layer (Emitting layer)
The EL layer has a two-layer structure of, but any of a hole injection layer, an electron injection layer, and an electron transport layer may be provided. As described above, various examples of the combination have already been reported, and any of the configurations may be used.

In this embodiment, polyphenylene vinylene is formed as a hole transport layer by an evaporation method. The light emitting layer is formed by vapor deposition of a 30% to 40% molecular dispersion of PBD of a 1,3,4-oxadiazole derivative in polyvinyl carbazole, and about 1% of coumarin 6 is used as a green light emitting center. Has been added.

Although the protection layer 371 can protect the EL layer 369 from moisture and oxygen, a passivation film 372 is more preferably provided. In this embodiment, the passivation film 372 has a thickness of 300 nm.
A thick silicon nitride film is provided. This passivation film may be formed continuously after the protection electrode 371 without being exposed to the atmosphere.

The protection electrode 371 is provided to prevent the deterioration of the cathode 370, and is typically a metal film containing aluminum as a main component. Of course, other materials may be used. Also,
Since the EL layer 369 and the cathode 370 are very sensitive to moisture, the layers up to the protective electrode 371 are continuously formed without being exposed to the atmosphere.
It is desirable to protect the EL layer from outside air.

The thickness of the EL layer 369 is 10 to 400.
nm (typically 60-150 nm), and the thickness of the cathode 370 is 80-200 nm (typically 100-150 nm).
m).

Thus, an EL module having a structure as shown in FIG. 24A is completed. Note that E in the present embodiment is
In the manufacturing process of the L module, the material forming the gate electrode, T,
Although the source signal line is formed by a and W, and the gate signal line is formed by Al which is a wiring material forming the source and drain electrodes, different materials may be used.

[0207] A driver circuit 506 having an n-channel TFT 501 and a p-channel TFT 502 and a pixel portion 507 having a switching TFT 503, an EL driving TFT 504, and a capacitor 505 can be formed over the same substrate.

In this embodiment, the switching TFT 503 includes an n-channel TFT and an EL driving TF.
Although a configuration in which a p-channel TFT is used for T504 and bottom emission is performed from the element configuration of the EL element has been described, in this embodiment,
It is only a preferred form and need not be limited to this.

The n-channel TFT 50 of the driving circuit 506
Reference numeral 1 denotes a low-concentration impurity region 3 overlapping with a channel formation region 391 and a first conductive layer 324a forming a part of a gate electrode.
29 (GOLD region) and a high-concentration impurity region 333 functioning as a source region or a drain region.
The channel forming region 39 is provided in the p-channel TFT 502.
2. It has impurity regions 350 and 353 functioning as a source region or a drain region.

The switching TFT 50 of the pixel portion 507
Numeral 3 does not overlap with the channel formation region 394 and the first conductive layer 341a which forms the gate electrode, and a low concentration impurity region 344 (LDD region) formed outside the gate electrode and a high concentration which functions as a source region or a drain region. It has a concentration impurity region 336.

[0211] The EL driving TFT 504 in the pixel portion 507 includes a channel formation region 395, high-concentration impurity regions 352 and 35 functioning as source or drain regions.
Five. The capacitor 505 is formed so that the first conductive layer 326a and the second conductive layer 326b function as one electrode.

In this embodiment, the structure in which the EL layer is formed on the pixel electrode (anode) and then the cathode is formed has been described. However, the EL layer and the anode are formed on the pixel electrode (cathode). It is good also as a structure. However, in this case, unlike the bottom emission described above, a top emission form is adopted. At this time, it is desirable that the switching TFT and the EL driving TFT are formed of an n-channel TFT.

This embodiment can be implemented by freely combining with Embodiments 1 to 4.

(Embodiment 6) In the semiconductor device of the present invention, an active matrix display device can be used as a display portion of an electric appliance. Examples of such appliances include a video camera, a digital camera, a projector, a projection TV, a goggle-type display (head-mounted display), a navigation system, a sound reproducing device, a notebook personal computer, a game device, and a portable information terminal (mobile computer, mobile phone,
A portable game machine or an electronic book), and an image reproducing device provided with a recording medium. FIG. 25 shows specific examples of these electric appliances.

FIG. 25A shows a mobile phone, and the main body 30 is shown.
01, audio output unit 3002, audio input unit 3003, display unit 3004, operation switch 3005, antenna 3006
It consists of. The semiconductor device of the present invention can be used for the display portion 3004.

FIG. 25B shows a video camera, which includes a main body 3101, a display portion 3102, an audio input portion 3103, operation switches 3104, a battery 3105, and an image receiving portion 310.
6. The semiconductor device of the present invention has a display portion 3102.
Can be used.

FIG. 25C shows a mobile computer (mobile computer), which comprises a main body 3201, a camera section 3202, an image receiving section 3203, operation switches 3204, and a display section 3205. The semiconductor device of the present invention can be used for the display portion 3205.

FIG. 25D shows a goggle type display having a main body 3331, a display portion 3332, and an arm portion 333.
3 The semiconductor device of the present invention has a display portion 3332
Can be used.

FIG. 25E shows a rear projector (projection TV), which includes a main body 3401 and a light source 340.
2, display portion 3403, polarizing beam splitter 3404,
Reflector 3405, 3406, screen 3407
It consists of. The semiconductor device of the present invention can be used for the display portion 3403.

FIG. 25F shows a front projector, which includes a main body 3501, a light source 3502, a display portion 3503,
It comprises an optical system 3504 and a screen 3505. The semiconductor device of the present invention can be used for the display portion 3503.

As described above, the applicable range of the present invention is extremely wide, and the present invention can be applied to electric appliances in various fields.

This embodiment can be implemented by freely combining with Embodiments 1 to 5.

The present invention is applicable not only to a TFT in which a channel region is formed in a self-aligned manner corresponding to a gate electrode, but also to a TFT in which a channel region is not formed in a self-aligned manner corresponding to a gate electrode. It is possible to apply.

Further, the differential circuit, the current mirror circuit, the source follower circuit, and the like having the structure shown in this specification may be used in circuits other than the analog buffer circuit of the driving circuit.

As described above, there has been a problem that the analog buffer circuit composed of the polycrystalline TFTs varies. Although the variation can be corrected by using the correction circuit, there has been a problem that the circuit and the driving operation are complicated by the correction circuit.

In the present invention, the gate length and gate width of the TFT are set large. A plurality of TFTs having a common gate electrode potential are connected in parallel and used. In addition, the arrangement of the channel portions of the plurality of TFTs connected in parallel is devised. This makes it possible to obtain an analog buffer circuit with less variation as a whole without using a correction circuit, and to provide a semiconductor device with less variation.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of an analog buffer circuit according to the present invention.

FIG. 2 is a circuit diagram of an analog buffer circuit according to the present invention.

FIG. 3 is a circuit diagram of an analog buffer circuit according to the present invention.

FIG. 4 shows the relationship between the drain current and the source
FIG. 4 is a diagram illustrating a relationship between drain voltages.

FIG. 5 is a circuit diagram of a conventional analog buffer circuit.

FIG. 6 is a circuit diagram of a conventional analog buffer circuit with a correction circuit.

FIG. 7 is a diagram showing a timing chart of a conventional analog buffer circuit with a correction circuit.

FIG. 8 is a block diagram of an active matrix display device.

FIG. 9 is a diagram illustrating a configuration of a source signal line driver circuit for dot sequential driving.

FIG. 10 is a diagram illustrating a configuration of a source signal line driver circuit for line-sequential driving.

11A and 11B are a plan view and a circuit diagram illustrating an arrangement of a TFT.

FIG. 12 is a circuit diagram of an analog buffer circuit according to the present invention.

FIG. 13 is a plan view of an analog buffer circuit according to the present invention.

FIG. 14 illustrates a relationship between a crystal grain boundary of a polycrystalline semiconductor and a channel region.

FIG. 15 illustrates a structure of a pixel in an EL display device.

FIG. 16 illustrates a relationship between a crystal grain boundary of a polycrystalline semiconductor and a channel region.

FIG. 17 is a plan view showing an arrangement of TFTs in the analog buffer circuit of the present invention.

FIG. 18 is a diagram illustrating a configuration of a source signal line driver circuit for line-sequential driving.

FIG. 19 is a diagram showing the relationship between the gate width of a TFT and variation in threshold characteristics.

FIG. 20 is a diagram showing characteristics of the analog buffer circuit according to the present invention.

FIG. 21 illustrates a method for manufacturing an EL display device of the present invention.

FIG. 22 illustrates a method for manufacturing an EL display device of the present invention.

FIG. 23 illustrates a method for manufacturing an EL display device of the present invention.

FIG. 24 illustrates a method for manufacturing an EL display device of the present invention.

FIG. 25 illustrates an application example to an electronic device.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 21/28 H01L 27/08 331E 5F052 27/08 331 29/78 618C 5F110 612B 617N 614F Term (Reference) 2H092 GA59 JA24 JA31 JA32. JJ04 JJ05 JJ06 KK43 5F048 AC04 5F052 AA02 AA12 BA07 BB02 BB07 DA02 EA16 FA06 HA01 JA01 5F110 AA26 AA30 BB02 BB04 CC02 DD01 DD02 DD03 DD13 DD14 DD15 DD17 EE01 EE02 EE03 EE28 FF23 FF23 FF23 GG02 GG13 GG25 GG28 GG29 GG32 GG43 GG45 GG47 HJ01 HJ04 HJ12 HJ13 HJ23 HL04 HL06 HL07 HM13 HM15 NN03 NN04 NN22 NN23 NN24 NN27 NN35 NN72 NN73 NN77 NN78 PP03 PP05 PP06 PP10 PP29 PP34 PP35 QQ04 QQ11 QQ24 QQ25 QQ28

Claims (22)

[Claims] 1. A semiconductor device comprising an analog buffer having at least one of a differential circuit and a current mirror circuit, wherein the differential circuit or the current mirror circuit has a channel region formed of a polycrystalline semiconductor layer. A semiconductor device comprising: a plurality of thin film transistors; and a gate length of the plurality of thin film transistors is 7 μm or more. 2. A semiconductor device comprising an analog buffer having at least one of a differential circuit and a current mirror circuit, wherein the differential circuit or the current mirror circuit has a channel region formed by a polycrystalline semiconductor layer. A semiconductor device, comprising: a plurality of thin film transistors; and a gate width of each of the plurality of thin film transistors is 50 μm or more. 3. A semiconductor device comprising an analog buffer having at least one of a differential circuit and a current mirror circuit, wherein the differential circuit or the current mirror circuit has a channel region formed of a polycrystalline semiconductor layer. A semiconductor device, comprising: a plurality of thin film transistors; and a gate length of the plurality of thin film transistors of 7 μm or more and a gate width of 50 μm or more. 4. A semiconductor device comprising an analog buffer having at least one of a differential circuit and a current mirror circuit, wherein the differential circuit or the current mirror circuit has a channel region formed of a polycrystalline semiconductor layer. A plurality of thin film transistors, wherein the plurality of thin film transistors have a multi-gate structure. 5. A semiconductor device comprising an analog buffer having at least one of a differential circuit and a current mirror circuit, wherein the differential circuit or the current mirror circuit has a channel region formed of a polycrystalline semiconductor layer. Wherein the plurality of thin film transistors have a multi-gate structure, and a gate length corresponding to each of a plurality of gate electrodes of the plurality of thin film transistors is 7 μm or more. Semiconductor device. 6. A semiconductor device comprising an analog buffer having at least one of a differential circuit and a current mirror circuit, wherein the differential circuit or the current mirror circuit has a channel region formed of a polycrystalline semiconductor layer. Wherein the plurality of thin film transistors have a multi-gate structure, and a gate width corresponding to each of a plurality of gate electrodes of each of the plurality of thin film transistors is 50 μm or more. Semiconductor device. 7. A semiconductor device provided with an analog buffer having at least one of a differential circuit and a current mirror circuit, wherein the differential circuit or the current mirror circuit has a channel region formed of a polycrystalline semiconductor layer. A plurality of thin film transistors, wherein the plurality of thin film transistors have a multi-gate type structure, a gate length corresponding to each of a plurality of gate electrodes of each of the plurality of thin film transistors is 7μm or more,
A semiconductor device having a gate width of 50 μm or more. 8. A semiconductor device comprising an analog buffer having at least one of a differential circuit and a current mirror circuit, wherein the differential circuit or the current mirror circuit has a pair of configurations, Each of the pair of configurations has the same gate electrode potential,
And a plurality of thin film transistors connected in parallel, and a channel region of each of the plurality of thin film transistors connected in parallel is formed of a polycrystalline semiconductor layer. 9. A semiconductor device comprising an analog buffer having at least one of a differential circuit and a current mirror circuit, wherein the differential circuit or the current mirror circuit has a pair of configurations, Each of the pair of configurations has the same gate electrode potential,
And a plurality of thin film transistors connected in parallel, a channel region of each of the plurality of thin film transistors connected in parallel is formed by a polycrystalline semiconductor layer,
And a semiconductor device which is arranged at a crossing. 10. The semiconductor device according to claim 8, wherein a gate length of the plurality of thin film transistors is 7 μm or more. 11. The semiconductor device according to claim 8, wherein the plurality of thin film transistors have a gate width of 50 μm or more. 12. The semiconductor device according to claim 8, wherein the plurality of thin film transistors have a gate length of 7 μm or more and a gate width of 50 μm or more. 13. The method according to claim 8, wherein the plurality of thin film transistors have a multi-gate structure, and a gate length corresponding to each of a plurality of gate electrodes of each of the plurality of thin film transistors is 7 μm or more. Characteristic semiconductor device. 14. The semiconductor device according to claim 8, wherein the plurality of thin film transistors have a multi-gate structure, and a gate width corresponding to each of the plurality of gate electrodes of each of the plurality of thin film transistors is 50 μm or more. Characteristic semiconductor device. 15. The plurality of thin film transistors according to claim 8, wherein the plurality of thin film transistors have a multi-gate structure, and a gate length corresponding to each of the plurality of gate electrodes of each of the plurality of thin film transistors is 7 μm or more;
A semiconductor device having a gate width of 50 μm or more. 16. A semiconductor device provided with an analog buffer constituted by a source follower, wherein the source follower is constituted by a thin film transistor having a channel region formed by a polycrystalline semiconductor layer, and the gate length of the thin film transistor is 7 μm. A semiconductor device characterized by the above. 17. A semiconductor device provided with an analog buffer constituted by a source follower, wherein the source follower is constituted by a thin film transistor in which a channel region is formed by a polycrystalline semiconductor layer, and the gate width of the thin film transistor is 50 μm. A semiconductor device characterized by the above. 18. A semiconductor device having an analog buffer constituted by a source follower, wherein the source follower is constituted by a thin film transistor having a channel region formed by a polycrystalline semiconductor layer, and the gate length of the thin film transistor is 7 μm. That ’s it,
A semiconductor device having a gate width of 50 μm or more. 19. A semiconductor device provided with an analog buffer constituted by a source follower, wherein the source follower is constituted by a thin film transistor in which a channel region is formed by a polycrystalline semiconductor layer; A semiconductor device having a structure. 20. A semiconductor device provided with an analog buffer constituted by a source follower, wherein the source follower is constituted by a thin film transistor in which a channel region is formed by a polycrystalline semiconductor layer; A semiconductor device having a structure, wherein a gate length corresponding to each of a plurality of gate electrodes of the thin film transistor is 7 μm or more. 21. A semiconductor device provided with an analog buffer constituted by a source follower, wherein the source follower is constituted by a thin film transistor in which a channel region is formed by a polycrystalline semiconductor layer; A semiconductor device having a structure, wherein a gate width corresponding to each of a plurality of gate electrodes of the thin film transistor is 50 μm or more. 22. A semiconductor device provided with an analog buffer constituted by a source follower, wherein the source follower is constituted by a thin film transistor in which a channel region is formed by a polycrystalline semiconductor layer; A gate length corresponding to each of the plurality of gate electrodes of the thin film transistor is 7 μm or more, and a gate width is 50 μm.
m or more.