JP2002182980A5 - - Google Patents

Download PDF

Info

Publication number
JP2002182980A5
JP2002182980A5 JP2001327071A JP2001327071A JP2002182980A5 JP 2002182980 A5 JP2002182980 A5 JP 2002182980A5 JP 2001327071 A JP2001327071 A JP 2001327071A JP 2001327071 A JP2001327071 A JP 2001327071A JP 2002182980 A5 JP2002182980 A5 JP 2002182980A5
Authority
JP
Japan
Prior art keywords
cache
cache line
memory
power
lines
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2001327071A
Other languages
English (en)
Japanese (ja)
Other versions
JP2002182980A (ja
JP4038786B2 (ja
Filing date
Publication date
Priority claimed from US09/865,847 external-priority patent/US6983388B2/en
Application filed filed Critical
Publication of JP2002182980A publication Critical patent/JP2002182980A/ja
Publication of JP2002182980A5 publication Critical patent/JP2002182980A5/ja
Application granted granted Critical
Publication of JP4038786B2 publication Critical patent/JP4038786B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

JP2001327071A 2000-10-25 2001-10-25 キャッシュメモリにおける漏洩電力の低減方法及び装置 Expired - Fee Related JP4038786B2 (ja)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US24317300P 2000-10-25 2000-10-25
US09/865,847 US6983388B2 (en) 2000-10-25 2001-05-25 Method and apparatus for reducing leakage power in a cache memory by using a timer control signal that removes power to associated cache lines
US60/243173 2001-05-25
US09/865847 2001-05-25

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2007181585A Division JP2007317213A (ja) 2000-10-25 2007-07-11 キャッシュメモリにおける漏洩電力の低減方法及び装置

Publications (3)

Publication Number Publication Date
JP2002182980A JP2002182980A (ja) 2002-06-28
JP2002182980A5 true JP2002182980A5 (enExample) 2004-10-14
JP4038786B2 JP4038786B2 (ja) 2008-01-30

Family

ID=26935640

Family Applications (2)

Application Number Title Priority Date Filing Date
JP2001327071A Expired - Fee Related JP4038786B2 (ja) 2000-10-25 2001-10-25 キャッシュメモリにおける漏洩電力の低減方法及び装置
JP2007181585A Ceased JP2007317213A (ja) 2000-10-25 2007-07-11 キャッシュメモリにおける漏洩電力の低減方法及び装置

Family Applications After (1)

Application Number Title Priority Date Filing Date
JP2007181585A Ceased JP2007317213A (ja) 2000-10-25 2007-07-11 キャッシュメモリにおける漏洩電力の低減方法及び装置

Country Status (3)

Country Link
US (2) US6983388B2 (enExample)
EP (1) EP1202287B1 (enExample)
JP (2) JP4038786B2 (enExample)

Families Citing this family (44)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7865747B2 (en) * 2000-10-31 2011-01-04 International Business Machines Corporation Adaptive issue queue for reduced power at high performance
TWI223526B (en) * 2001-03-23 2004-11-01 Foma Feng Asynchronous serial data transmission method
US6907534B2 (en) * 2001-06-29 2005-06-14 Hewlett-Packard Development Company, L.P. Minimizing power consumption in pipelined circuit by shutting down pipelined circuit in response to predetermined period of time having expired
US6993571B2 (en) * 2001-08-16 2006-01-31 International Business Machines Corporation Power conservation in a server cluster
US6996678B1 (en) * 2002-07-31 2006-02-07 Cisco Technology, Inc. Method and apparatus for randomized cache entry replacement
US20040064657A1 (en) * 2002-09-27 2004-04-01 Muraleedhara Navada Memory structure including information storage elements and associated validity storage elements
JP3806131B2 (ja) * 2003-05-21 2006-08-09 富士通株式会社 アドレス変換バッファの電力制御方法及びその装置
JP4591657B2 (ja) * 2003-12-22 2010-12-01 キヤノン株式会社 動画像符号化装置及びその制御方法、プログラム
JP3834323B2 (ja) 2004-04-30 2006-10-18 日本電気株式会社 キャッシュメモリおよびキャッシュ制御方法
JP4421390B2 (ja) * 2004-06-21 2010-02-24 富士通マイクロエレクトロニクス株式会社 半導体集積回路
US7257678B2 (en) * 2004-10-01 2007-08-14 Advanced Micro Devices, Inc. Dynamic reconfiguration of cache memory
US7472224B1 (en) * 2004-10-01 2008-12-30 Advanced Micro Devices, Inc. Reconfigurable processing node including first and second processor cores
WO2006120507A1 (en) * 2005-05-11 2006-11-16 Freescale Semiconductor, Inc. Method for power reduction and a device having power reduction capabilities
US7451353B2 (en) * 2005-12-23 2008-11-11 Intel Corporation Cache disassociation detection
US20070288776A1 (en) * 2006-06-09 2007-12-13 Dement Jonathan James Method and apparatus for power management in a data processing system
US7401185B2 (en) * 2006-07-06 2008-07-15 International Business Machines Corporation Buffered indexing to manage hierarchical tables
US7900018B2 (en) * 2006-12-05 2011-03-01 Electronics And Telecommunications Research Institute Embedded system and page relocation method therefor
JP2009252165A (ja) * 2008-04-10 2009-10-29 Toshiba Corp マルチプロセッサシステム
EP2319043B1 (en) 2008-07-21 2018-08-15 Sato Holdings Corporation A device having data storage
US8135941B2 (en) * 2008-09-19 2012-03-13 International Business Machines Corporation Vector morphing mechanism for multiple processor cores
US8799587B2 (en) * 2009-01-26 2014-08-05 International Business Machines Corporation Region coherence array for a mult-processor system having subregions and subregion prefetching
US8285942B2 (en) * 2009-01-27 2012-10-09 International Business Machines Corporation Region coherence array having hint bits for a clustered shared-memory multiprocessor system
US8495300B2 (en) * 2010-03-03 2013-07-23 Ati Technologies Ulc Cache with reload capability after power restoration
JP5534912B2 (ja) * 2010-04-13 2014-07-02 三菱電機株式会社 データ記憶装置
US8645730B2 (en) 2010-09-21 2014-02-04 International Business Machines Corporation Systems and methods to improve power efficiency in hybrid storage clusters
JPWO2013080426A1 (ja) 2011-12-01 2015-04-27 パナソニックIpマネジメント株式会社 熱を考慮した構造を持つ集積回路装置、三次元集積回路、三次元プロセッサ装置、及びプロセススケジューラ
JP5565425B2 (ja) * 2012-02-29 2014-08-06 富士通株式会社 演算装置、情報処理装置および演算方法
US9703704B2 (en) * 2012-05-01 2017-07-11 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US9135182B2 (en) * 2012-06-01 2015-09-15 Semiconductor Energy Laboratory Co., Ltd. Central processing unit and driving method thereof
US9218040B2 (en) 2012-09-27 2015-12-22 Apple Inc. System cache with coarse grain power management
US9317102B2 (en) 2013-01-03 2016-04-19 Apple Inc. Power control for cache structures
US9165650B2 (en) 2013-02-07 2015-10-20 Qualcomm Incorporated Hybrid dynamic-static encoder with optional hit and/or multi-hit detection
US8984227B2 (en) 2013-04-02 2015-03-17 Apple Inc. Advanced coarse-grained cache power management
US9400544B2 (en) 2013-04-02 2016-07-26 Apple Inc. Advanced fine-grained cache power management
US9396122B2 (en) 2013-04-19 2016-07-19 Apple Inc. Cache allocation scheme optimized for browsing applications
JP6130750B2 (ja) * 2013-07-16 2017-05-17 株式会社東芝 メモリ制御回路およびプロセッサ
GB2547939B (en) * 2016-03-04 2020-04-22 Advanced Risc Mach Ltd Cache power management
US9727488B1 (en) 2016-10-07 2017-08-08 International Business Machines Corporation Counter-based victim selection in a cache memory
US9940239B1 (en) 2016-10-07 2018-04-10 International Business Machines Corporation Counter-based victim selection in a cache memory
US9727489B1 (en) 2016-10-07 2017-08-08 International Business Machines Corporation Counter-based victim selection in a cache memory
US9940246B1 (en) 2016-10-07 2018-04-10 International Business Machines Corporation Counter-based victim selection in a cache memory
US9753862B1 (en) 2016-10-25 2017-09-05 International Business Machines Corporation Hybrid replacement policy in a multilevel cache memory hierarchy
WO2019165272A1 (en) * 2018-02-23 2019-08-29 Octavo Systems Llc Analog memory cells with valid flag
US11493986B2 (en) * 2019-12-22 2022-11-08 Qualcomm Incorporated Method and system for improving rock bottom sleep current of processor memories

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4420807A (en) * 1981-08-31 1983-12-13 International Business Machines Corporation Selectively holding data in a buffer for defective backing store tracks
JP2641819B2 (ja) * 1990-11-05 1997-08-20 三菱電機株式会社 キャッシュ・コントローラ並びにフォールト・トレラント・コンピュータ及びそのデータ転送方式
US5813028A (en) * 1993-10-12 1998-09-22 Texas Instruments Incorporated Cache read miss request invalidation prevention method
US5632038A (en) * 1994-02-22 1997-05-20 Dell Usa, L.P. Secondary cache system for portable computer
US5430683A (en) 1994-03-15 1995-07-04 Intel Corporation Method and apparatus for reducing power in on-chip tag SRAM
AU3313795A (en) * 1994-10-14 1996-04-26 Compaq Computer Corporation Circuit for placing a cache memory into low power mode in response to special bus cycles
US5835949A (en) * 1994-12-27 1998-11-10 National Semiconductor Corporation Method of identifying and self-modifying code
US6138213A (en) * 1997-06-27 2000-10-24 Advanced Micro Devices, Inc. Cache including a prefetch way for storing prefetch cache lines and configured to move a prefetched cache line to a non-prefetch way upon access to the prefetched cache line
US6535961B2 (en) * 1997-11-21 2003-03-18 Intel Corporation Spatial footprint prediction
US5835435A (en) * 1997-12-02 1998-11-10 Intel Corporation Method and apparatus for dynamically placing portions of a memory in a reduced power consumtion state
US6490654B2 (en) * 1998-07-31 2002-12-03 Hewlett-Packard Company Method and apparatus for replacing cache lines in a cache memory
US6157977A (en) * 1998-11-24 2000-12-05 Hewlett Packard Company Bus bridge and method for ordering read and write operations in a write posting system
TW451132B (en) * 1998-12-15 2001-08-21 Nippon Electric Co System and method for cache processing
JP3798563B2 (ja) * 1999-01-06 2006-07-19 株式会社東芝 命令キャッシュメモリ
US6141283A (en) * 1999-04-01 2000-10-31 Intel Corporation Method and apparatus for dynamically placing portions of a memory in a reduced power consumption state
US6473814B1 (en) * 1999-05-03 2002-10-29 International Business Machines Corporation System for optimally tuning a burst length by setting a maximum burst length based on a latency timer value and adjusting the maximum burst length based on a cache line size
US6510494B1 (en) * 1999-06-30 2003-01-21 International Business Machines Corporation Time based mechanism for cached speculative data deallocation
US6408364B1 (en) * 2000-03-17 2002-06-18 Advanced Micro Devices, Inc. Apparatus and method for implementing a least recently used cache replacement algorithm
US6795896B1 (en) * 2000-09-29 2004-09-21 Intel Corporation Methods and apparatuses for reducing leakage power consumption in a processor

Similar Documents

Publication Publication Date Title
JP2002182980A5 (enExample)
US6956782B2 (en) Selective bank refresh
JP4056173B2 (ja) 半導体記憶装置および該半導体記憶装置のリフレッシュ方法
WO2000019445B1 (en) Read/write buffers for complete hiding of the refresh of a semiconductor memory and method of operating same
JP2000353382A5 (enExample)
WO2006019624A3 (en) Method and system for controlling refresh to avoid memory cell data losses
KR20070086472A (ko) 부분 메모리 리프레시를 위한 방법, 장치 및 시스템
JP2002150771A (ja) Dramキャッシュ・メモリ中のデータをリフレッシュする方法および装置
WO2002005281A3 (en) A high speed dram architecture with uniform access latency
KR102501651B1 (ko) 리프레쉬 제어 장치
AU2001283568A1 (en) Method and system for hiding refreshes in a dynamic random access memory
KR20020003032A (ko) 리프레시 동작에서의 전력소모를 줄이기 위한반도체메모리장치
JPH08138374A (ja) 半導体メモリ装置およびそのリフレッシュ方法
WO2002089140A3 (en) Method and apparatus for completely hiding refresh operations in a dram device using multiple clock division
JP2002008371A (ja) 半導体記憶装置
US6862238B1 (en) Memory system with reduced refresh current
US6967886B2 (en) Pseudo static random access memory and data refresh method thereof
TW200513067A (en) Method of storing data access records in network communication device
JPS6157097A (ja) ダイナミツク半導体メモリ
JP2004220697A (ja) 半導体メモリ装置のリフレッシュ制御
US20050024924A1 (en) 1t1c sram
WO2024148730A1 (zh) 刷新控制电路及其存储器
CN103823762A (zh) 存储器随机查表方法、装置和系统
JP3962850B2 (ja) Sdramの制御装置
US20050088894A1 (en) Auto-refresh multiple row activation