JP4038786B2 - キャッシュメモリにおける漏洩電力の低減方法及び装置 - Google Patents

キャッシュメモリにおける漏洩電力の低減方法及び装置 Download PDF

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Publication number
JP4038786B2
JP4038786B2 JP2001327071A JP2001327071A JP4038786B2 JP 4038786 B2 JP4038786 B2 JP 4038786B2 JP 2001327071 A JP2001327071 A JP 2001327071A JP 2001327071 A JP2001327071 A JP 2001327071A JP 4038786 B2 JP4038786 B2 JP 4038786B2
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cache
cache line
memory
power
line
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JP2002182980A (ja
JP2002182980A5 (enExample
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カクシラス ステファノス
ダブリュ. ディオデトー フィリップ
ラエ マックレラン,ジュニヤ ハーバート
ナーリカー ギリジャ
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Agere Systems LLC
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Agere Systems LLC
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    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C5/00Details of stores covered by group G11C11/00
    • G11C5/14Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/143Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels ; Switching between alternative supplies
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Dram (AREA)
JP2001327071A 2000-10-25 2001-10-25 キャッシュメモリにおける漏洩電力の低減方法及び装置 Expired - Fee Related JP4038786B2 (ja)

Applications Claiming Priority (4)

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US24317300P 2000-10-25 2000-10-25
US09/865,847 US6983388B2 (en) 2000-10-25 2001-05-25 Method and apparatus for reducing leakage power in a cache memory by using a timer control signal that removes power to associated cache lines
US60/243173 2001-05-25
US09/865847 2001-05-25

Related Child Applications (1)

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JP2007181585A Division JP2007317213A (ja) 2000-10-25 2007-07-11 キャッシュメモリにおける漏洩電力の低減方法及び装置

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JP2002182980A JP2002182980A (ja) 2002-06-28
JP2002182980A5 JP2002182980A5 (enExample) 2004-10-14
JP4038786B2 true JP4038786B2 (ja) 2008-01-30

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JP2001327071A Expired - Fee Related JP4038786B2 (ja) 2000-10-25 2001-10-25 キャッシュメモリにおける漏洩電力の低減方法及び装置
JP2007181585A Ceased JP2007317213A (ja) 2000-10-25 2007-07-11 キャッシュメモリにおける漏洩電力の低減方法及び装置

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JP2007181585A Ceased JP2007317213A (ja) 2000-10-25 2007-07-11 キャッシュメモリにおける漏洩電力の低減方法及び装置

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US (2) US6983388B2 (enExample)
EP (1) EP1202287B1 (enExample)
JP (2) JP4038786B2 (enExample)

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Publication number Publication date
US20060041769A1 (en) 2006-02-23
JP2002182980A (ja) 2002-06-28
EP1202287A2 (en) 2002-05-02
US20020049918A1 (en) 2002-04-25
US7472302B2 (en) 2008-12-30
US6983388B2 (en) 2006-01-03
EP1202287A3 (en) 2004-04-21
JP2007317213A (ja) 2007-12-06
EP1202287B1 (en) 2012-05-09

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