JP2002171030A - Wiring board and manufacturing method - Google Patents

Wiring board and manufacturing method

Info

Publication number
JP2002171030A
JP2002171030A JP2000364762A JP2000364762A JP2002171030A JP 2002171030 A JP2002171030 A JP 2002171030A JP 2000364762 A JP2000364762 A JP 2000364762A JP 2000364762 A JP2000364762 A JP 2000364762A JP 2002171030 A JP2002171030 A JP 2002171030A
Authority
JP
Japan
Prior art keywords
wiring board
wiring
insulating substrate
circuit layer
via hole
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2000364762A
Other languages
Japanese (ja)
Other versions
JP4646386B2 (en
Inventor
Katsura Hayashi
桂 林
Kazunori Koga
和憲 古賀
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP2000364762A priority Critical patent/JP4646386B2/en
Publication of JP2002171030A publication Critical patent/JP2002171030A/en
Application granted granted Critical
Publication of JP4646386B2 publication Critical patent/JP4646386B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Structure Of Printed Boards (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a wiring board with advantages in small size, small thickness, highly minute pattern, and adaptation for all shape of electronic equipment, such as a portable information terminal or a mobile computer while high rigidity is realized even when the wiring board is small in thickness. SOLUTION: In a wiring board 15, a wiring circuit layer 3 is formed in the surface and/or the inside of an insulating substrate 2 containing thermosetting resin in an uncured or semi-cured state, and at the same time, there is a via hole conductor 4 made up of conductive paste in the via hole in the inside of the insulating substrate 2. The wiring substrate 15 is put between dies 17a and 17b with an uneven or three-dimensional formation structure is provided and heated under pressure, so that the thermosetting type resin is made to harden completely. As a result, a wiring board having an uneven part 5, made up of a projected part 5a on one front side and a recessed part 5b the other front side or a three-dimensional formation structure with a curved face or a bent part, can be obtained.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、例えば、多層配線
基板及び半導体素子収納用パッケージ等の電子部品、パ
ソコン、移動体通信用電話機、ビデオカメラ等の各種電
子機器などに適した多層配線基板とその製造方法に関す
るものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer wiring board suitable for electronic parts such as a multilayer wiring board and a package for accommodating a semiconductor element, a personal computer, a mobile communication telephone, and a video camera. The present invention relates to the manufacturing method.

【0002】[0002]

【従来技術】近年、携帯電話を初めとする携帯情報端末
の発達やコンピューターを持ち運んで操作するいわゆる
モバイルコンピューティングの普及によって、電子機器
の小型化がますます進んでいる。このような電子機器に
使用される配線基板は小型、薄型且つ高精細であること
が求められる傾向にある。
2. Description of the Related Art In recent years, with the development of mobile information terminals such as mobile phones and the spread of so-called mobile computing that carries and operates a computer, electronic devices have been increasingly reduced in size. Wiring boards used in such electronic devices tend to be required to be small, thin and high definition.

【0003】基板を小型にするためには、配線密度を高
くすれば良いが、基板を薄くすると基板の剛性がなくな
るために、変形や反りなどが発生しやすくなるために多
層配線板では厚さ0.5mm程度が実用上の限界であ
り、これ以上薄くすると基板の反りやうねりが大きくな
ってしまう。従って、反りや変形の低減と軽量化とは相
反する性質として捉えられていた。
In order to reduce the size of the substrate, it is necessary to increase the wiring density. However, when the substrate is made thinner, the rigidity of the substrate is lost, so that deformation and warping are likely to occur. About 0.5 mm is a practical limit, and if it is thinner than this, warpage and undulation of the substrate will increase. Therefore, the reduction in warpage and deformation and the reduction in weight have been regarded as contradictory properties.

【0004】また、携帯情報端末の発達と普及につれ、
その性能とともに、デザインが重視されている。特に3
次元的な曲面を多用したデザインも求められる傾向があ
るが、この様な曲面デザインの電子機器には従来の平ら
な配線基板は組み込むことが困難であった。このため、
曲面を多用した情報機器のデザインに合わせて曲面を持
った配線基板が求められている。
[0004] Further, with the development and spread of portable information terminals,
Along with its performance, design is emphasized. Especially 3
There is also a demand for designs that make extensive use of dimensional curved surfaces, but it has been difficult to incorporate conventional flat wiring boards into electronic devices having such curved surface designs. For this reason,
There is a demand for a wiring board having a curved surface in accordance with the design of an information device that uses many curved surfaces.

【0005】[0005]

【発明が解決しようとする課題】しかしながら、従来の
プリント配線基板は、通常、熱硬化性樹脂を硬化させた
後に表面に配線回路層の形成を施すもので、配線回路層
の形成は、被形成面が平坦であることが必要であるため
に、事実上、配線基板に凹凸や3次元的な造形を形成す
ることは不可能であった。
However, a conventional printed wiring board is usually formed by forming a wiring circuit layer on the surface after curing a thermosetting resin. Since the surface needs to be flat, it has been virtually impossible to form irregularities or three-dimensional modeling on the wiring substrate.

【0006】そのために、配線基板の平面形状であるこ
とから、携帯情報端末などの電気機器のデザインも配線
基板の形状に束縛されることが多かった。
For this reason, since the wiring board has a planar shape, the design of electric equipment such as a portable information terminal is often restricted by the shape of the wiring board.

【0007】本発明は、このような課題に対して、配線
基板の厚みが薄い場合においても高い剛性を付与でき、
また、携帯情報端末やモバイルコンピュータなどのあら
ゆる電子機器形状に適用可能で、小型、軽量、薄型、高
精細化が可能な配線基板とそれを作製するための製造方
法を提供することを目的とするものである。
The present invention can provide high rigidity to such a problem even when the thickness of the wiring board is small.
It is another object of the present invention to provide a wiring board that can be applied to all electronic device shapes such as a personal digital assistant and a mobile computer, and that can be made small, light, thin, and high-definition, and a manufacturing method for manufacturing the same. Things.

【0008】[0008]

【課題を解決するための手段】本発明者らは、上記のよ
うな課題について鋭意検討した結果、未硬化または半硬
化状態の熱硬化性樹脂を含有する絶縁基板の表面および
/または内部に配線回路層を形成し、且つ絶縁基板の内
部に、ビアホール内に導体ペーストを充填して形成され
てなる未硬化の配線基板に対して所定形状の型を用いて
加圧加熱することによって型形状を配線基板に転写する
ことができるために、任意の形状の配線基板を作製でき
るという知見を得た。
Means for Solving the Problems As a result of intensive studies on the above-mentioned problems, the present inventors have found that wiring is provided on the surface and / or inside of an insulating substrate containing an uncured or semi-cured thermosetting resin. A circuit layer is formed, and an uncured wiring board formed by filling a conductive paste in a via hole inside an insulating substrate is pressed and heated using a mold having a predetermined shape to form a mold. It has been found that since it can be transferred to a wiring board, a wiring board of an arbitrary shape can be manufactured.

【0009】即ち、本発明の配線基板は、完全硬化され
た熱硬化性樹脂を含有する絶縁基板の表面および/また
は内部に配線回路層を形成し、且つ絶縁基板の内部に、
ビアホール内に導体ペーストを充填して形成されてなる
ビアホール導体を具備する配線基板であって、該配線基
板の一方の表面側が凸部、他方の表面側が凹部となる凹
凸部を有することを特徴とするものである。
That is, the wiring board of the present invention has a wiring circuit layer formed on the surface and / or inside of an insulating substrate containing a thermosetting resin which has been completely cured, and
A wiring board having a via-hole conductor formed by filling a conductive paste in a via-hole, wherein the wiring board has an uneven portion in which one surface side is a convex portion and the other surface side is a concave portion. Is what you do.

【0010】なお、かかる凹凸部を具備する配線基板に
おいては配線基板の全体厚みが0.5mm以下のように
剛性が低い薄い配線基板に好適であり、配線基板の剛性
を高めることができ、特に一方の表面側の凸部高さが
0.1mm以上であること、前記凹凸部における凸部が
長尺状に形成されていること、さらには長尺状の凸部が
互いに直交する方向に複数形成されていることが望まし
い。
[0010] A wiring board provided with such an uneven portion is suitable for a thin wiring board having low rigidity such that the total thickness of the wiring board is 0.5 mm or less, and can increase the rigidity of the wiring board. The height of the convex portion on one surface side is 0.1 mm or more, the convex portion in the concave / convex portion is formed in a long shape, and further, the plural long convex portions are arranged in a direction orthogonal to each other. Preferably, it is formed.

【0011】また、本発明の他の配線基板は、完全硬化
された熱硬化性樹脂を含有する絶縁基板の表面および/
または内部に配線回路層を形成し、且つ絶縁基板の内部
に、ビアホール内に導体ペーストを充填して形成されて
なるビアホール導体を具備する配線基板であって、該配
線基板が曲面あるいは屈曲部を有する3次元的な造形構
造を具備することを特徴とするものである。
Another wiring board according to the present invention comprises a surface of an insulating substrate containing a thermosetting resin which is completely cured and / or
Alternatively, a wiring board having a via hole conductor formed by filling a via paste with a conductive paste inside an insulating substrate, wherein a wiring circuit layer is formed inside, and the wiring board has a curved surface or a bent portion. Characterized by having a three-dimensional structure.

【0012】また、本発明の配線基板の製造方法は、未
硬化または半硬化状態の熱硬化性樹脂を含有する絶縁基
板の表面および/または内部に配線回路層を形成し、且
つ絶縁基板の内部に、ビアホール内に導体ペーストを充
填して形成されてなる配線基板を、凹凸または3次元的
な造形構造が形成された型間に配置して、加圧加熱処理
して、前記熱硬化性樹脂を完全硬化させることを特徴と
するものである。
Further, according to the method for manufacturing a wiring board of the present invention, a wiring circuit layer is formed on the surface and / or inside of an insulating substrate containing an uncured or semi-cured thermosetting resin, and A wiring board formed by filling a conductive paste in a via hole is placed between a mold having irregularities or a three-dimensional structure, and is subjected to a pressure and heat treatment so that the thermosetting resin is formed. Is completely cured.

【0013】従来の配線基板は、単純平面であることを
基本とし、平坦性を阻害する反りやうねりの発生は極力
避ける必要があるが、そのような変形を任意に制御でき
れば、配線基板をあらゆる形状に変形することが可能と
なる。そこで、本発明の配線基板によれば、例えば、配
線回路に対して、ほとんど影響のない配線基板の一部の
領域に凹凸を形成したり、あるいは、配線基板の周囲に
フランジ上の突起を設けることで、逆に配線基板の強度
を高め、予期せぬ反りやうねりの発生を防止することが
できる。その結果、配線基板の厚さを0.5mm以下ま
で薄くしても実用上問題がなくなり、基板の大幅な軽量
化が可能となる。
The conventional wiring board is basically a simple plane, and it is necessary to minimize the occurrence of warpage or undulation that hinders flatness. It becomes possible to transform into a shape. Therefore, according to the wiring board of the present invention, for example, unevenness is formed in a part of the wiring board that has little effect on the wiring circuit, or a protrusion on the flange is provided around the wiring board. Accordingly, the strength of the wiring board can be increased and unexpected warpage or undulation can be prevented. As a result, even if the thickness of the wiring board is reduced to 0.5 mm or less, there is no practical problem, and the board can be significantly reduced in weight.

【0014】また、従来の基板は単純平面であったた
め、曲面を多用したデザインの電子機器へ組み込むと、
無駄な空間が増加し、電子機器の小型化を阻害する大き
な要因であった。本発明の配線基板では、電子機器のデ
ザインに合わせて配線基板を例えば、曲面に形成できる
曲面を多用したデザインの電子機器への組み込みが可能
になる。
Further, since the conventional substrate is a simple flat surface, if it is incorporated into an electronic device having a design that makes extensive use of curved surfaces,
Useless space increases, which is a major factor that hinders miniaturization of electronic devices. According to the wiring board of the present invention, the wiring board can be formed into a curved surface, for example, in accordance with the design of the electronic device.

【0015】[0015]

【発明の実施の形態】本発明の配線基板の構造の一例を
示す図1および図2をもとに説明する。図1は、本発明
の配線基板の(a)概略平面図と、(b)そのx−x断
面図と、(c)凹凸部付近の拡大断面図である。配線基
板1は、熱硬化性樹脂を含有する絶縁基板2の表面や内
部に、配線回路層3が形成されており、また異なる層の
配線回路層3同士を接続するために、絶縁基板2内に
は、ビアホールに導体ペーストを充填して形成されたビ
アホール導体4が形成されている。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An example of the structure of a wiring board according to the present invention will be described with reference to FIGS. 1 and 2. FIG. 1A is a schematic plan view of a wiring board of the present invention, FIG. 1B is an xx cross-sectional view thereof, and FIG. 1C is an enlarged cross-sectional view of the vicinity of an uneven portion. The wiring board 1 has a wiring circuit layer 3 formed on the surface or inside of an insulating substrate 2 containing a thermosetting resin. In order to connect the wiring circuit layers 3 of different layers to each other, the inside of the insulating substrate 2 is formed. A via-hole conductor 4 formed by filling a via-hole with a conductive paste.

【0016】本発明の配線基板1は、上記のように配線
回路層3とビアホール導体4によって回路が形成されて
いるために、あらゆる回路を自在に形成できることか
ら、回路の高密度パターンを形成することができる。
In the wiring board 1 of the present invention, since the circuit is formed by the wiring circuit layer 3 and the via-hole conductor 4 as described above, any circuit can be formed freely, so that a high-density pattern of the circuit is formed. be able to.

【0017】そして、本発明によれば、このような配線
基板1の一部の表面には表面側が凸部5a、裏面側が凹
部5bとなる凹凸部5が形成されていることが大きな特
徴である。この凹凸部5は本質的には、配線基板におけ
る回路パターンに影響のないように形成されていること
が必要であり、かかる点から、凹凸部5には、実質的に
配線回路層3やビアホール導体4が形成されていないこ
とが望ましい。
According to the present invention, it is a great feature that such a wiring board 1 is formed on a part of the surface thereof with an uneven part 5 having a convex part 5a on the front side and a concave part 5b on the back side. . The uneven portion 5 must be formed essentially without affecting the circuit pattern on the wiring board. From this point, the uneven portion 5 substantially includes the wiring circuit layer 3 and the via hole. It is desirable that the conductor 4 is not formed.

【0018】このような凹凸部5の形状は、その必要に
応じてあらゆる形状を適用できるが、表面側の凸部5a
の高さが0.1mm以上、特に0.2mm以上,特に
0.3mm以上であることが基板の強度を高める上で望
ましい。また、前記凹凸部5における凸部5aが長尺状
(リブ状)に形成されていること、さらには長尺状の凸
部5aが図1に示すように互いに直交する方向に複数本
形成されていることが望ましい。
As the shape of the uneven portion 5, any shape can be applied as needed.
Is preferably 0.1 mm or more, particularly 0.2 mm or more, particularly 0.3 mm or more in order to increase the strength of the substrate. In addition, the protrusions 5a of the uneven portion 5 are formed in a long shape (rib shape), and a plurality of long protrusions 5a are formed in directions orthogonal to each other as shown in FIG. Is desirable.

【0019】なお、この凹凸部5の形成箇所は、配線基
板1の周囲または内側のいずれでもよいが、配線基板1
の全体の強度の向上を図る上では、少なくとも配線基板
1の周囲に形成することが望ましい。
It should be noted that the uneven portion 5 may be formed around or inside the wiring board 1.
In order to improve the overall strength of the wiring board, it is desirable to form it at least around the wiring board 1.

【0020】また、この凹凸部5は、例えば、図2に示
すように、配線基板を実装する電子機器内部への取付け
に伴い、取付け部6への適合を図るための凹凸部5であ
ったり、取付け位置への固定を図るために、機器側に設
けられた位置決め用孔7と整合するための凹凸部5であ
ってもよい。
Further, as shown in FIG. 2, for example, as shown in FIG. 2, the concave / convex portion 5 is a concave / convex portion 5 for adapting to the mounting portion 6 in accordance with the mounting inside the electronic device on which the wiring board is mounted. In order to fix to the mounting position, the concave / convex portion 5 may be used for alignment with the positioning hole 7 provided on the device side.

【0021】さらに、上記の図1、図2では、配線基板
1の部分的に凹凸部5が形成されたものであったが、例
えば、配線基板1を電子機器の内部に実装する場合に、
3次元的な複雑な空間内に配線基板1を取付ける必要が
ある場合、その空間形状に整合するように配線基板1が
3次元的な造形構造からなるものである。
Further, in FIGS. 1 and 2 described above, the uneven portion 5 is formed partially on the wiring board 1. For example, when the wiring board 1 is mounted inside an electronic device,
When it is necessary to mount the wiring board 1 in a complicated three-dimensional space, the wiring board 1 has a three-dimensional structure so as to match the space shape.

【0022】その一例を図3に示した。この図3(a)
によれば、配線基板1が、全体として、球曲面や曲面に
よって形成されたもの、(b)全体として波うった形状
からなものであってもよい。かかる3次元的な造形構造
においても、回路パターンに影響が及ばないように回路
設計することが必要である。例えば、図3(b)のよう
に、部分的に屈曲部aを有する場合、その屈曲部aには
パターンがないことが望ましいが、屈曲部aを挟んで両
側に形成された回路間を接続する場合には、屈曲部aの
凹側に、接続用の配線回路層を設けることが、配線回路
層の断線を防止する上で望ましい。つまり、凸部側に配
線回路層を形成すると屈曲部aの加工時に、配線回路層
に引っ張り応力が加わり、配線回路層が断線するおそれ
があるためである。
An example is shown in FIG. FIG. 3 (a)
According to this, the wiring substrate 1 may be formed as a whole by a spherical curved surface or a curved surface, or (b) may be formed into a wavy shape as a whole. Even in such a three-dimensional structure, it is necessary to design a circuit so that the circuit pattern is not affected. For example, as shown in FIG. 3 (b), when a part has a bent part a, it is desirable that the bent part a has no pattern. However, the circuit formed on both sides of the bent part a is connected. In this case, it is desirable to provide a wiring circuit layer for connection on the concave side of the bent portion a in order to prevent disconnection of the wiring circuit layer. That is, when the wiring circuit layer is formed on the protruding portion side, a tensile stress is applied to the wiring circuit layer when the bent portion a is processed, and the wiring circuit layer may be disconnected.

【0023】本発明の配線基板1において、絶縁基板2
は、少なくとも熱硬化性樹脂を含有するものであり、具
体的にはエポキシ系樹脂、トリアジン系樹脂、ポリブタ
ジエン系樹脂、フェノール系樹脂、フッ素系樹脂、ポリ
イミド系樹脂の群から選ばれる少なくとも1種など一般
に回路基板に使用される樹脂が用いられるが、特にPP
E(ポリフェニレンエーテル)、BTレジン(ビスマレ
イミドトリアジン)、エポキシ樹脂、ポリイミド樹脂、
フッ素樹脂、フェノール樹脂、ポリアミドビスマレイミ
ド樹脂の群から選ばれる少なくとも1種が望ましく、と
りわけ原料として室温でワニス状になる熱硬化性樹脂で
あることが望ましい。
In the wiring board 1 of the present invention, the insulating substrate 2
Is a resin containing at least a thermosetting resin, specifically, at least one selected from the group consisting of an epoxy resin, a triazine resin, a polybutadiene resin, a phenol resin, a fluorine resin, and a polyimide resin. Generally, a resin used for a circuit board is used.
E (polyphenylene ether), BT resin (bismaleimide triazine), epoxy resin, polyimide resin,
At least one selected from the group consisting of a fluororesin, a phenolic resin, and a polyamide-bismaleimide resin is desirable, and in particular, a thermosetting resin that becomes a varnish at room temperature as a raw material is desirable.

【0024】また、上記有機樹脂にガラス繊維を補強材
として含浸させた有機樹脂も好適に用いられる。この
時、ガラス繊維は織布または不織布として含有されるこ
とが望ましい。特に、均一なビアホール導体4を形成す
るために、織布の繊維の一部をほぐし織布の厚さを均一
にする解繊を施したものが望ましい。また、絶縁層中に
ガラス繊維が30〜70体積%の割合で含まれることが
望ましい。
An organic resin obtained by impregnating the above organic resin with glass fiber as a reinforcing material is also preferably used. At this time, the glass fiber is desirably contained as a woven or nonwoven fabric. In particular, in order to form a uniform via-hole conductor 4, it is desirable that the fiber be defibrated so as to loosen some of the fibers of the woven fabric and make the thickness of the woven fabric uniform. Further, it is desirable that glass fibers be contained in the insulating layer at a ratio of 30 to 70% by volume.

【0025】さらに、絶縁基板1の強度を高めるため
に、上記有機樹脂に無機質フィラーを添加することもで
きる。無機質フィラーとしては、SiO2、Al23
AlNなどが好適に用いられる。フィラーの形状は平均
粒径が20μm以下、特に10μm以下、最適には7μ
m以下の略球状の粉末が用いられる。また、場合によっ
ては、高誘電率のフィラーを用いることによって、絶縁
基板2の誘電率を高めることも可能である。さらに、有
機樹脂と無機質フィラーの体積比率を85:15〜1
5:85の比率で適宜配合することにより、絶縁基板2
の熱膨張係数を調整することができる。
Further, in order to increase the strength of the insulating substrate 1, an inorganic filler can be added to the organic resin. As the inorganic filler, SiO 2 , Al 2 O 3 ,
AlN or the like is preferably used. The filler has an average particle diameter of 20 μm or less, particularly 10 μm or less, and optimally 7 μm or less.
An approximately spherical powder of m or less is used. In some cases, the dielectric constant of the insulating substrate 2 can be increased by using a filler having a high dielectric constant. Furthermore, the volume ratio of the organic resin and the inorganic filler is set to 85:15 to 1
By appropriately blending at a ratio of 5:85, the insulating substrate 2
Can be adjusted.

【0026】また、配線回路層3は、銅、アルミニウム
などの低抵抗金属からなる金属箔や、銅、アルミニウ
ム、金、銀などの低抵抗金属粉末を含む導体から形成さ
れる。低抵抗化の上では、金属箔から構成されることが
望ましい。また、場合によっては、上記金属以外にも回
路の抵抗調整のためにNi−Cr合金などの高抵抗の金
属を混合または合金化したものを用いてもよい。さら
に、低抵抗化のために、前記低抵抗金属よりも低融点の
金属、例えば半田や錫などの低融点金属を導体組成物中
に含んでもよい。
The wiring circuit layer 3 is formed from a metal foil made of a low-resistance metal such as copper or aluminum, or a conductor containing a low-resistance metal powder such as copper, aluminum, gold or silver. From the viewpoint of lowering the resistance, it is desirable to use a metal foil. In some cases, in addition to the above-mentioned metals, a material obtained by mixing or alloying a high-resistance metal such as a Ni—Cr alloy for adjusting the resistance of the circuit may be used. Further, in order to reduce the resistance, the conductor composition may include a metal having a lower melting point than the low-resistance metal, for example, a low-melting metal such as solder or tin.

【0027】また、ビアホール導体4は、銅、アルミニ
ウム、金、銀の群から選ばれる少なくとも1種の導体粉
末を充填して形成されてなることが望ましい。また、ビ
アホール導体中には上記の低抵抗金属以外に、金属粉末
間の結合材あるいは金属粉末の充填性を向上させるため
に結合剤および溶剤が添加される。
The via-hole conductor 4 is desirably formed by filling at least one kind of conductor powder selected from the group consisting of copper, aluminum, gold and silver. In addition, a binder and a solvent are added to the via-hole conductor, in addition to the low-resistance metal described above, in order to improve a filling material between metal powders or metal powder.

【0028】また、配線基板1においては、配線基板1
の表面から裏面に達するスルーホールを形成して、その
スルーホール内壁に金属メッキを施したスルーホール導
体を具備してもよい。
In the wiring board 1, the wiring board 1
May be provided with a through hole extending from the front surface to the back surface, and a metal plated inner wall of the through hole.

【0029】次に、本発明の配線基板の製造方法につい
て図4をもとに説明する。まず、図4(a)に示すよう
に、未硬化または半硬化状態の絶縁シート11を作製す
る。この絶縁シート11は、前記絶縁材料をからなる絶
縁材料からなるスラリーをドクターブレード法等によっ
てシート状に成形したり、繊維体からなる織布または不
織布に樹脂を含浸させることによって作製される。
Next, a method of manufacturing a wiring board according to the present invention will be described with reference to FIG. First, as shown in FIG. 4A, an uncured or semi-cured insulating sheet 11 is prepared. The insulating sheet 11 is manufactured by forming a slurry made of the insulating material made of the insulating material into a sheet shape by a doctor blade method or the like, or impregnating a woven or nonwoven fabric made of a fibrous body with a resin.

【0030】次に、図4(b)に示すように、この絶縁
シート11に、レーザー加工により直径0.05〜0.
3mm程度のビアホール12を形成する。また、ビアホ
ール12の形成に使用されるレーザーは、炭酸ガスレー
ザー、YAGレーザ一あるいはエキシマレーザーなどの
公知のレーザーが使用できるが、特に炭酸ガスレーザー
が好適である。
Next, as shown in FIG. 4B, the insulating sheet 11 is laser-processed to have a diameter of 0.05-0.
A via hole 12 of about 3 mm is formed. As a laser used for forming the via hole 12, a known laser such as a carbon dioxide laser, a YAG laser, or an excimer laser can be used, and a carbon dioxide laser is particularly preferable.

【0031】次に、図4(c)に示すように、ビアホー
ル12に対して、導体ペーストを充填してビアホール導
体13を形成する。導体ペーストは、銅、アルミニウ
ム、金、銀から選ばれる少なくとも1種または2種以上
の合金を主体とする低抵抗金属粉末を含む平均粒径が
0.1〜10μmの導体粉末100重量部に対して、エ
ポキシ、セルロースなどの液状あるいは粉末状樹脂を
0.1〜10重量部添加し混合することが望ましい。ま
た、所望により酢酸ブチル、イソプロピルアルコール、
オクタノール、テルピネオール、トルエン、キシレンな
どの溶剤を添加しても良い。場合によっては、ビアホー
ル導体13形成後に、60〜140℃で加熱処理を行な
い、ペースト中の溶剤および樹脂分を分解、揮散除去す
ることもできる。
Next, as shown in FIG. 4C, the via hole 12 is filled with a conductive paste to form a via hole conductor 13. The conductor paste has a low resistance metal powder mainly composed of at least one or two or more alloys selected from copper, aluminum, gold and silver, and has an average particle size of 0.1 to 10 μm. It is desirable to add and mix 0.1 to 10 parts by weight of a liquid or powdery resin such as epoxy or cellulose. If desired, butyl acetate, isopropyl alcohol,
A solvent such as octanol, terpineol, toluene, or xylene may be added. In some cases, after the via-hole conductor 13 is formed, a heat treatment may be performed at 60 to 140 ° C. to decompose and volatilize and remove the solvent and the resin component in the paste.

【0032】次に、図4(d)に示すように、ビアホー
ル導体13が形成された絶縁シート11の表面に、配線
回路層14を形成する。配線回路層14の形成には、銅
などの金属箔を絶縁シート11に接着剤で貼り付けた後
に、回路パターンのレジストを形成して酸などによって
不要な部分の金属をエッチング除去するか、予め打ち抜
きした金属箔を貼りつけるなどの方法がある。他の方法
としては、絶縁シート11の表面に導体ペーストを回路
パターンにスクリーン印刷や、フォトレジスト法などに
よって形成して乾燥した後、加圧して配線回路層14を
絶縁シート11表面に埋め込み絶縁シート11に密着さ
せることで形成できる。特に、フィルム、金属板などの
転写フィルム15上にメッキあるいは金属箔のエッチン
グによって回路パターンを形成した後、絶縁シート11
に貼り合わせて加圧加熱して配線回路層14を絶縁シー
ト11表面に埋め込んだ後に転写フィルム15を剥離す
ることによって配線回路層14を転写形成することが望
ましい。このように、絶縁シート11表面に配線回路層
14を埋め込むことで、特に多層化時、積層時の配線回
路層による積層不良を防止できる。
Next, as shown in FIG. 4D, a wiring circuit layer 14 is formed on the surface of the insulating sheet 11 on which the via-hole conductors 13 are formed. To form the wiring circuit layer 14, after attaching a metal foil such as copper to the insulating sheet 11 with an adhesive, a resist of a circuit pattern is formed, and unnecessary metal is removed by etching with an acid or the like. There is a method such as attaching a punched metal foil. As another method, a conductive paste is formed on the surface of the insulating sheet 11 by screen printing or a photoresist method on a circuit pattern, dried, and then pressurized to bury the wiring circuit layer 14 on the surface of the insulating sheet 11. 11 can be formed. In particular, after a circuit pattern is formed on a transfer film 15 such as a film or a metal plate by plating or etching of a metal foil, the insulating sheet 11 is formed.
It is desirable to transfer and form the wiring circuit layer 14 by peeling off the transfer film 15 after embedding the wiring circuit layer 14 on the surface of the insulating sheet 11 by heating under pressure and heating. By embedding the wiring circuit layer 14 in the surface of the insulating sheet 11 as described above, lamination failure due to the wiring circuit layer at the time of laminating, particularly in the case of multilayering, can be prevented.

【0033】以上の工程によって、絶縁シート11に対
してビアホール導体13および配線回路層14を形成し
た図4(e)に示す単一の配線シートAを作製すること
ができる。
Through the above steps, a single wiring sheet A shown in FIG. 4E in which the via-hole conductor 13 and the wiring circuit layer 14 are formed on the insulating sheet 11 can be manufactured.

【0034】更に上記と同様な工程を経て、複数の配線
シートを作製し、これらを位置合わせして積層し、図5
(a)の積層体15を形成する。次に、図5(b)
(c)に示すように、この積層体15を、所定の凹部1
6aと凹部16bが施された一対の型17a、17b間
に設置し、上下から50〜500MPaの圧力を印加し
つつ、150〜300℃の硬化温度で加熱して絶縁シー
ト中の熱硬化性樹脂を完全に硬化させることによって、
本発明の配線基板を作製することができる。
Further, through the same steps as described above, a plurality of wiring sheets are produced, these are aligned and laminated, and
The laminated body 15 of (a) is formed. Next, FIG.
As shown in (c), the laminate 15 is inserted into a predetermined recess 1.
6a and a pair of dies 17a and 17b provided with the concave portions 16b, and heated at a curing temperature of 150 to 300 ° C. while applying a pressure of 50 to 500 MPa from above and below, thereby setting the thermosetting resin in the insulating sheet. By completely curing
The wiring board of the present invention can be manufactured.

【0035】なお、上記の加圧加熱処理にあたっては、
積層体15の表裏に離型フィルム18を配置して加圧加
熱処理することが望ましい。この離型フィルム18はフ
ッ素樹脂を含有するフィルムが良好に用いられる。ま
た、フッ素樹脂を金型にスプレーなどの方法で塗布する
ことにより、フイルムと同様の離型効果を得ることもで
きる。
It should be noted that, in the above-mentioned heating under pressure,
It is desirable that the release film 18 be disposed on the front and back of the laminate 15 and subjected to pressure and heat treatment. As the release film 18, a film containing a fluororesin is preferably used. Also, by applying a fluororesin to a mold by a method such as spraying, the same release effect as that of a film can be obtained.

【0036】[0036]

【実施例】PPE(ポリフェニレンエーテル)樹脂を含
むスラリーをガラス織布に含浸させた後、乾燥させ、プ
リプレグを準備した。なお、含有比率は、PPE樹脂5
0体積%、ガラスの織布50体積%とした。
EXAMPLE A glass woven fabric was impregnated with a slurry containing a PPE (polyphenylene ether) resin and then dried to prepare a prepreg. The content ratio is PPE resin 5
0% by volume and 50% by volume of glass woven fabric.

【0037】このプリプレグに炭酸ガスレーザーを用
い、70μmのビアホールを形成し、そのホール内に銀
をメッキした銅粉末を含む銅ペーストを充填してビアホ
ール導体を形成後、前記PETフィルムおよびアクリル
系粘着層を剥離した。
Using a carbon dioxide laser in this prepreg, a via hole of 70 μm was formed, and the hole was filled with a copper paste containing copper powder plated with silver to form a via hole conductor. The layers were peeled.

【0038】一方、ポリエチレンテレフタレート(PE
T)樹脂からなる転写フィルムの表面に接着剤を塗布し
て粘着性をもたせ、厚さ12μm、表面粗さ0.8μm
の銅箔を一面に接着した。その後、フォトレジストを塗
布し露光現像を行った後、これを塩化第二鉄溶液中に浸
漬して非パターン部をエッチング除去して配線回路層を
形成した。なお、作製した配線回路層は、線幅が30μ
m、配線と配線との間隔を30μmとした。
On the other hand, polyethylene terephthalate (PE)
T) An adhesive is applied to the surface of a transfer film made of a resin so as to have tackiness, and the thickness is 12 μm and the surface roughness is 0.8 μm.
Was adhered to one surface. Then, after applying a photoresist and performing exposure and development, it was immersed in a ferric chloride solution to remove non-pattern portions by etching to form a wiring circuit layer. The manufactured wiring circuit layer has a line width of 30 μm.
m, and the distance between the wirings was 30 μm.

【0039】そして、プリプレグの表面に配線回路層を
形成した転写フィルムを重ね合わせて圧着し、転写フィ
ルムのみを剥離して配線回路層を転写し、配線回路層を
プリプレグ表面に埋め込み、配線回路層およびビアホー
ル導体を有する配線シートを作製した。
Then, a transfer film having a wiring circuit layer formed on the surface of the prepreg is superposed and pressed, and only the transfer film is peeled off to transfer the wiring circuit layer. The wiring circuit layer is embedded in the prepreg surface. And a wiring sheet having via-hole conductors was produced.

【0040】その後、この配線シートを3層形成し、こ
れらを位置合わせして積層した。そしてこの積層体の両
表面にフッ素樹脂フィルムを貼り、200MPaの荷重
をかけた状態で200℃で1時間、加熱して完全硬化さ
せて、図1に示すような両面に凹凸部を有する配線基板
を作製することができた。なお、作製した配線基板の厚
みは0.4mmとした。
Thereafter, three layers of this wiring sheet were formed, and these were aligned and laminated. Then, a fluororesin film is applied to both surfaces of the laminate, and the laminate is heated and completely cured at 200 ° C. for 1 hour under a load of 200 MPa. Could be produced. The thickness of the manufactured wiring board was 0.4 mm.

【0041】得られた配線基板について、3次元測定器
を用いて基板寸法を測定し、変形や反りの有無の確認を
行った。
The dimensions of the obtained wiring board were measured using a three-dimensional measuring device, and the presence or absence of deformation and warpage was confirmed.

【0042】また、型の凹凸部の凸部高さを種々変え
て、配線基板の中央に300gの荷重を印加した時の配
線基板の撓み量を測定し、凹凸を全く形成しなかった場
合の撓み量を1とし、これに対する相対撓み量を測定し
た。その結果、凹凸を形成することによって配線基板の
撓み量を低減でき、配線基板の強度、剛性を高めること
ができることを確認した。
The amount of deflection of the wiring board when a load of 300 g was applied to the center of the wiring board was measured by changing the height of the projections of the projections and depressions of the mold. The amount of bending was set to 1, and the relative amount of bending was measured. As a result, it was confirmed that the amount of bending of the wiring board can be reduced by forming the unevenness, and the strength and rigidity of the wiring board can be increased.

【0043】 [0043]

【0044】[0044]

【発明の効果】以上詳述したとおり、本発明の配線基板
によれば、厚さ0.5mm以下の薄い配線基板であって
も、基板の一方の表面側が凸部、他方の表面側が凹部と
なる凹凸部を形成することによって、基板の強度、剛性
を高めることができる結果、配線基板の反りやうねりの
発生を防止することができる。また、曲面を多用したデ
ザインの電子機器に合わせて曲面を持った配線基板も簡
便な工程で作製することができる。
As described above in detail, according to the wiring board of the present invention, even if the wiring board is as thin as 0.5 mm or less, one surface side of the substrate has a convex portion and the other surface side has a concave portion. By forming the uneven portions, the strength and rigidity of the substrate can be increased, so that the occurrence of warpage and undulation of the wiring substrate can be prevented. In addition, a wiring board having a curved surface can be manufactured by a simple process in accordance with an electronic device having a design that uses many curved surfaces.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の配線基板の一例を説明するための
(a)概略平面図と、(b)そのx−x断面図と、
(c)凹凸部付近の拡大断面図である。
FIG. 1A is a schematic plan view for explaining an example of a wiring board according to the present invention, and FIG.
(C) It is an expanded sectional view near an uneven part.

【図2】本発明の配線基板の他の例を説明するための概
略断面図である。
FIG. 2 is a schematic sectional view for explaining another example of the wiring board of the present invention.

【図3】本発明の配線基板のさらに他の例を説明するた
めの概略図である。
FIG. 3 is a schematic diagram for explaining still another example of the wiring board of the present invention.

【図4】本発明の配線基板の製造方法の一例を説明する
ための工程図である。
FIG. 4 is a process diagram illustrating an example of a method for manufacturing a wiring board according to the present invention.

【図5】本発明の配線基板の製造方法における加圧加熱
工程を説明するための工程図である。
FIG. 5 is a process diagram for explaining a pressurizing and heating process in the method for manufacturing a wiring board of the present invention.

【符号の説明】[Explanation of symbols]

1 配線基板 2 絶縁基板 3 配線回路層 4 ビアホール導体 5 凹凸部 DESCRIPTION OF SYMBOLS 1 Wiring board 2 Insulating board 3 Wiring circuit layer 4 Via hole conductor 5 Uneven part

───────────────────────────────────────────────────── フロントページの続き Fターム(参考) 5E317 AA24 BB01 BB11 CC25 CD21 CD31 GG09 5E338 AA03 AA05 AA16 BB02 BB13 BB19 BB25 BB61 CC01 CD01 CD05 CD11 EE26 5E346 AA02 AA04 AA12 AA15 AA29 AA32 AA43 CC04 CC09 CC10 CC13 CC14 CC32 CC34 CC38 CC39 CC40 DD03 DD13 DD32 EE09 EE12 EE13 EE14 FF01 FF18 FF27 GG15 GG19 GG28 HH11 HH22 HH23 HH24  ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5E317 AA24 BB01 BB11 CC25 CD21 CD31 GG09 5E338 AA03 AA05 AA16 BB02 BB13 BB19 BB25 BB61 CC01 CD01 CD05 CD11 EE26 5E346 AA02 AA04 AA12 AA15 AA29 CC14 CC14 CC04 CC14 CC14 CC39 CC40 DD03 DD13 DD32 EE09 EE12 EE13 EE14 FF01 FF18 FF27 GG15 GG19 GG28 HH11 HH22 HH23 HH24

Claims (7)

【特許請求の範囲】[Claims] 【請求項1】完全硬化された熱硬化性樹脂を含有する絶
縁基板の表面および/または内部に配線回路層を形成
し、且つ絶縁基板の内部に、ビアホール内に導体ペース
トを充填して形成されてなるビアホール導体を具備する
配線基板であって、該配線基板の一方の表面側が凸部、
他方の表面側が凹部となる凹凸部を有することを特徴と
する配線基板。
A wiring circuit layer is formed on the surface and / or inside of an insulating substrate containing a thermosetting resin which has been completely cured, and a conductive paste is filled in a via hole inside the insulating substrate. A wiring board comprising a via-hole conductor, wherein one surface side of the wiring board has a convex portion,
A wiring substrate having an uneven portion on the other surface side of which is a concave portion.
【請求項2】前記配線基板の全体厚みが0.5mm以下
である請求項1記載の配線基板。
2. The wiring board according to claim 1, wherein the entire thickness of the wiring board is 0.5 mm or less.
【請求項3】前記一方の表面側の凸部高さが0.1mm
以上であることを特徴とする請求項1または請求項2記
載の配線基板。
3. The height of the projection on the one surface side is 0.1 mm.
The wiring board according to claim 1 or 2, wherein:
【請求項4】前記凹凸部における凸部が長尺状に形成さ
れてなる請求項1乃至請求項3のいずれか記載の配線基
板。
4. The wiring board according to claim 1, wherein the projections in the projections and depressions are formed in a long shape.
【請求項5】前記長尺状の凸部が互いに直交する方向に
複数形成されてなる請求項4記載の配線基板。
5. The wiring board according to claim 4, wherein a plurality of said elongated protrusions are formed in a direction orthogonal to each other.
【請求項6】完全硬化された熱硬化性樹脂を含有する絶
縁基板の表面および/または内部に配線回路層を形成
し、且つ絶縁基板の内部に、ビアホール内に導体ペース
トを充填して形成されてなるビアホール導体を具備する
配線基板であって、該配線基板が曲面あるいは屈曲部を
有する3次元的な造形構造を具備することを特徴とする
配線基板。
6. A wiring circuit layer is formed on the surface and / or inside of an insulating substrate containing a completely cured thermosetting resin, and a conductive paste is filled in a via hole inside the insulating substrate. A wiring board comprising a via-hole conductor comprising a three-dimensional structure having a curved surface or a bent portion.
【請求項7】未硬化または半硬化状態の熱硬化性樹脂を
含有する絶縁基板の表面および/または内部に配線回路
層を形成し、且つ絶縁基板の内部に、ビアホール内に導
体ペーストを充填して形成されてなる配線基板を、凹凸
または3次元的な造形構造が形成された型間に配置し
て、加圧加熱処理して、前記熱硬化性樹脂を完全硬化さ
せることを特徴とする配線基板の製造方法。
7. A wiring circuit layer is formed on the surface and / or inside of an insulating substrate containing an uncured or semi-cured thermosetting resin, and a conductive paste is filled in a via hole inside the insulating substrate. A wiring substrate formed between the molds having irregularities or a three-dimensional structure formed thereon, and subjected to a pressure and heat treatment to completely cure the thermosetting resin. Substrate manufacturing method.
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Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005236232A (en) * 2004-02-23 2005-09-02 Hitachi Chem Co Ltd Connection substrate, method for fixing in position, method for manufacturing solid-type multi-layer substrate, press apparatus, and multi-layer
EP1747704A1 (en) * 2004-05-17 2007-01-31 Aspocomp Oy Printed wiring board, manufacturing method and electronic device
JP2009288322A (en) * 2008-05-27 2009-12-10 Epson Imaging Devices Corp Electronic device and electronic equipment
JP2011014727A (en) * 2009-07-02 2011-01-20 Mitsui Mining & Smelting Co Ltd Copper foil with composite resin layer, method of manufacturing the same, and method of manufacturing flexible double-sided copper clad laminate and solid molding printed wiring board
WO2014125852A1 (en) * 2013-02-14 2014-08-21 株式会社村田製作所 Circuit substrate, and production method therefor
WO2014125851A1 (en) * 2013-02-14 2014-08-21 株式会社村田製作所 Circuit substrate, and production method therefor
JP2015032691A (en) * 2013-08-02 2015-02-16 株式会社村田製作所 Resin multilayer substrate and method for producing the same
KR20160033527A (en) * 2014-09-18 2016-03-28 삼성전기주식회사 Printed circuit board and method for manufacturing thereof
JP2017100401A (en) * 2015-12-03 2017-06-08 日立化成株式会社 Laminate film, laminate and method for producing the same, and method for manufacturing printed wiring board
JPWO2019230524A1 (en) * 2018-05-28 2021-04-22 株式会社村田製作所 Resin multilayer board and electronic equipment
US20230026151A1 (en) * 2021-07-23 2023-01-26 Innolux Corporation Composite layer circuit element and manufacturing method thereof

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5773989A (en) * 1980-10-25 1982-05-08 Tokyo Shibaura Electric Co Method of fabricating electric circuit substrate
JPH07106768A (en) * 1993-10-06 1995-04-21 Toshiba Corp Manufacture of three-dimensional printed wiring board
JPH10200217A (en) * 1997-01-07 1998-07-31 Ibiden Co Ltd Flexible substrate for printed wiring board manufacture

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5773989A (en) * 1980-10-25 1982-05-08 Tokyo Shibaura Electric Co Method of fabricating electric circuit substrate
JPH07106768A (en) * 1993-10-06 1995-04-21 Toshiba Corp Manufacture of three-dimensional printed wiring board
JPH10200217A (en) * 1997-01-07 1998-07-31 Ibiden Co Ltd Flexible substrate for printed wiring board manufacture

Cited By (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005236232A (en) * 2004-02-23 2005-09-02 Hitachi Chem Co Ltd Connection substrate, method for fixing in position, method for manufacturing solid-type multi-layer substrate, press apparatus, and multi-layer
JP4555941B2 (en) * 2004-02-23 2010-10-06 日立化成工業株式会社 Positioning and fixing method and manufacturing method of three-dimensional multilayer substrate
EP1747704A1 (en) * 2004-05-17 2007-01-31 Aspocomp Oy Printed wiring board, manufacturing method and electronic device
EP1747704A4 (en) * 2004-05-17 2011-10-12 Meadville Entpr Hk Ltd Printed wiring board, manufacturing method and electronic device
JP2009288322A (en) * 2008-05-27 2009-12-10 Epson Imaging Devices Corp Electronic device and electronic equipment
JP2011014727A (en) * 2009-07-02 2011-01-20 Mitsui Mining & Smelting Co Ltd Copper foil with composite resin layer, method of manufacturing the same, and method of manufacturing flexible double-sided copper clad laminate and solid molding printed wiring board
US9832889B2 (en) 2013-02-14 2017-11-28 Murata Manufacturing Co., Ltd. Circuit board and method for producing same
WO2014125851A1 (en) * 2013-02-14 2014-08-21 株式会社村田製作所 Circuit substrate, and production method therefor
US9560766B2 (en) 2013-02-14 2017-01-31 Murata Manufacturing Co., Ltd. Circuit board and method for producing same
WO2014125852A1 (en) * 2013-02-14 2014-08-21 株式会社村田製作所 Circuit substrate, and production method therefor
JP2015032691A (en) * 2013-08-02 2015-02-16 株式会社村田製作所 Resin multilayer substrate and method for producing the same
KR20160033527A (en) * 2014-09-18 2016-03-28 삼성전기주식회사 Printed circuit board and method for manufacturing thereof
KR102249661B1 (en) * 2014-09-18 2021-05-10 삼성전기주식회사 Printed circuit board and method for manufacturing thereof
JP2017100401A (en) * 2015-12-03 2017-06-08 日立化成株式会社 Laminate film, laminate and method for producing the same, and method for manufacturing printed wiring board
JPWO2019230524A1 (en) * 2018-05-28 2021-04-22 株式会社村田製作所 Resin multilayer board and electronic equipment
US11406013B2 (en) 2018-05-28 2022-08-02 Murata Manufacturing Co., Ltd. Resin multilayer substrate and electronic device
JP7111157B2 (en) 2018-05-28 2022-08-02 株式会社村田製作所 Resin multilayer substrates and electronic devices
US20230026151A1 (en) * 2021-07-23 2023-01-26 Innolux Corporation Composite layer circuit element and manufacturing method thereof
US11764077B2 (en) * 2021-07-23 2023-09-19 Innolux Corporation Composite layer circuit element and manufacturing method thereof

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