JP2002163149A5 - - Google Patents

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Publication number
JP2002163149A5
JP2002163149A5 JP2001316210A JP2001316210A JP2002163149A5 JP 2002163149 A5 JP2002163149 A5 JP 2002163149A5 JP 2001316210 A JP2001316210 A JP 2001316210A JP 2001316210 A JP2001316210 A JP 2001316210A JP 2002163149 A5 JP2002163149 A5 JP 2002163149A5
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computer system
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JP2001316210A
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JP4008224B2 (ja
JP2002163149A (ja
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Priority claimed from US09/704,176 external-priority patent/US6868481B1/en
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Publication of JP2002163149A5 publication Critical patent/JP2002163149A5/ja
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JP2001316210A 2000-10-31 2001-10-15 マルチプロセッサシステムのキャッシュコヒーレンスプロトコル Expired - Lifetime JP4008224B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/704176 2000-10-31
US09/704,176 US6868481B1 (en) 2000-10-31 2000-10-31 Cache coherence protocol for a multiple bus multiprocessor system

Publications (3)

Publication Number Publication Date
JP2002163149A JP2002163149A (ja) 2002-06-07
JP2002163149A5 true JP2002163149A5 (enExample) 2005-04-07
JP4008224B2 JP4008224B2 (ja) 2007-11-14

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JP2001316210A Expired - Lifetime JP4008224B2 (ja) 2000-10-31 2001-10-15 マルチプロセッサシステムのキャッシュコヒーレンスプロトコル

Country Status (2)

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US (2) US6868481B1 (enExample)
JP (1) JP4008224B2 (enExample)

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US9990292B2 (en) 2016-06-29 2018-06-05 Arm Limited Progressive fine to coarse grain snoop filter
US10042766B1 (en) 2017-02-02 2018-08-07 Arm Limited Data processing apparatus with snoop request address alignment and snoop response time alignment
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