JPS54139436A - Error relief system for buffer control information - Google Patents

Error relief system for buffer control information

Info

Publication number
JPS54139436A
JPS54139436A JP4750878A JP4750878A JPS54139436A JP S54139436 A JPS54139436 A JP S54139436A JP 4750878 A JP4750878 A JP 4750878A JP 4750878 A JP4750878 A JP 4750878A JP S54139436 A JPS54139436 A JP S54139436A
Authority
JP
Japan
Prior art keywords
error
circuits
buffer
register
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4750878A
Other languages
Japanese (ja)
Other versions
JPS5729800B2 (en
Inventor
Akira Hattori
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP4750878A priority Critical patent/JPS54139436A/en
Publication of JPS54139436A publication Critical patent/JPS54139436A/en
Publication of JPS5729800B2 publication Critical patent/JPS5729800B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Detection And Correction Of Errors (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Debugging And Monitoring (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE: To avoid the system down assuredly caused by the disagreeement of the contents between the buffer memories by sending the buffer ineffective address to the all processors in case some error is detected in the copy flag.
CONSTITUTION: Copy flag F read out simultaneously with the address information is stored temporarily in register 10 and then checked at parity check circuit 11 in terms of the presence or absence of the error. In some error is detected in F, circuit 11 generates error signal ER to leas it to AND circuit 12-1, 12-3, 12-5 and 12-7 respectively. While logical input "1" is applied to these circuits 12, and thus output "1" is delivered all at once from circuits 12 to be led via OR circuits 13-1W13- 4 to designation register 14. Accordingly, register 14 sends the buffer ineffective address to all CPU buffer memories regardless of F.
COPYRIGHT: (C)1979,JPO&Japio
JP4750878A 1978-04-21 1978-04-21 Error relief system for buffer control information Granted JPS54139436A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4750878A JPS54139436A (en) 1978-04-21 1978-04-21 Error relief system for buffer control information

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4750878A JPS54139436A (en) 1978-04-21 1978-04-21 Error relief system for buffer control information

Publications (2)

Publication Number Publication Date
JPS54139436A true JPS54139436A (en) 1979-10-29
JPS5729800B2 JPS5729800B2 (en) 1982-06-24

Family

ID=12777044

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4750878A Granted JPS54139436A (en) 1978-04-21 1978-04-21 Error relief system for buffer control information

Country Status (1)

Country Link
JP (1) JPS54139436A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6473433A (en) * 1987-09-16 1989-03-17 Fujitsu Ltd Cache memory control system
JP2002163149A (en) * 2000-10-31 2002-06-07 Hewlett Packard Co <Hp> Cache coherence protocol for multi-processor system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6473433A (en) * 1987-09-16 1989-03-17 Fujitsu Ltd Cache memory control system
JP2002163149A (en) * 2000-10-31 2002-06-07 Hewlett Packard Co <Hp> Cache coherence protocol for multi-processor system

Also Published As

Publication number Publication date
JPS5729800B2 (en) 1982-06-24

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