JPS6473433A - Cache memory control system - Google Patents

Cache memory control system

Info

Publication number
JPS6473433A
JPS6473433A JP62229853A JP22985387A JPS6473433A JP S6473433 A JPS6473433 A JP S6473433A JP 62229853 A JP62229853 A JP 62229853A JP 22985387 A JP22985387 A JP 22985387A JP S6473433 A JPS6473433 A JP S6473433A
Authority
JP
Japan
Prior art keywords
cache
nullification
cache memory
parity error
request signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62229853A
Other languages
Japanese (ja)
Inventor
Masahiro Kawato
Kazuyoshi Okabe
Osamu Katakura
Osamu Moriyama
Hideyuki Sugawara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
PFU Ltd
Original Assignee
Fujitsu Ltd
PFU Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd, PFU Ltd filed Critical Fujitsu Ltd
Priority to JP62229853A priority Critical patent/JPS6473433A/en
Publication of JPS6473433A publication Critical patent/JPS6473433A/en
Pending legal-status Critical Current

Links

Landscapes

  • Techniques For Improving Reliability Of Storages (AREA)
  • Debugging And Monitoring (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Detection And Correction Of Errors (AREA)

Abstract

PURPOSE:To remove overhead by performing all cache nullification processing by a hardware. CONSTITUTION:A parity error inform signal generating means A which detects and informs the parity error of address information, a cache nullification request signal generating means B which outputs according to a parity error inform signal and a cache timing signal to check the use of a cache memory, when both coincide with each other, and a valid bit resetting means C which resets all valid bits according to the cache nullification request signal, are provided. Then, when the parity error is detected in the address information at the time of cache memory access, the nullification processing of the contents of the cache memory is executed by the hardware according to the cache nullification request signal. Thus, the overhead in a case that the nullification processing of the cache memory is executed at the time of the detection of the parity error is removed.
JP62229853A 1987-09-16 1987-09-16 Cache memory control system Pending JPS6473433A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62229853A JPS6473433A (en) 1987-09-16 1987-09-16 Cache memory control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62229853A JPS6473433A (en) 1987-09-16 1987-09-16 Cache memory control system

Publications (1)

Publication Number Publication Date
JPS6473433A true JPS6473433A (en) 1989-03-17

Family

ID=16898709

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62229853A Pending JPS6473433A (en) 1987-09-16 1987-09-16 Cache memory control system

Country Status (1)

Country Link
JP (1) JPS6473433A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015222612A (en) * 2005-07-29 2015-12-10 株式会社半導体エネルギー研究所 Semiconductor device

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54139436A (en) * 1978-04-21 1979-10-29 Fujitsu Ltd Error relief system for buffer control information
JPS56117400A (en) * 1980-02-20 1981-09-14 Fujitsu Ltd Buffer memory control system
JPS57113493A (en) * 1980-12-31 1982-07-14 Fujitsu Ltd Error processing system of tag 2
JPS59167891A (en) * 1983-03-14 1984-09-21 Nec Corp Buffer storage device
JPS617959A (en) * 1984-06-22 1986-01-14 Fujitsu Ltd Control system of tag storage device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54139436A (en) * 1978-04-21 1979-10-29 Fujitsu Ltd Error relief system for buffer control information
JPS56117400A (en) * 1980-02-20 1981-09-14 Fujitsu Ltd Buffer memory control system
JPS57113493A (en) * 1980-12-31 1982-07-14 Fujitsu Ltd Error processing system of tag 2
JPS59167891A (en) * 1983-03-14 1984-09-21 Nec Corp Buffer storage device
JPS617959A (en) * 1984-06-22 1986-01-14 Fujitsu Ltd Control system of tag storage device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015222612A (en) * 2005-07-29 2015-12-10 株式会社半導体エネルギー研究所 Semiconductor device

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