JP2002100596A - Edge protecting device for silicon wafer - Google Patents
Edge protecting device for silicon waferInfo
- Publication number
- JP2002100596A JP2002100596A JP2000289824A JP2000289824A JP2002100596A JP 2002100596 A JP2002100596 A JP 2002100596A JP 2000289824 A JP2000289824 A JP 2000289824A JP 2000289824 A JP2000289824 A JP 2000289824A JP 2002100596 A JP2002100596 A JP 2002100596A
- Authority
- JP
- Japan
- Prior art keywords
- wafer
- protective film
- edge
- silicon wafer
- edge portion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- Mechanical Treatment Of Semiconductor (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、両面研磨時におけ
るウェーハのエッジ部の変形、摩耗及び破損を抑制し得
るシリコンウェーハのエッジ部保護方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for protecting an edge portion of a silicon wafer which can suppress deformation, wear and breakage of the edge portion of the wafer during double-side polishing.
【０００２】[0002]
【従来の技術】高精度の平坦度を有する半導体シリコン
ウェーハは、シリコン単結晶インゴットをスライスして
得られたウェーハを、面取り、機械研磨（ラッピン
グ）、エッチング、機械的化学的研磨（メカノケミカル
ポリッシング）及び洗浄等の各工程を経て製造される。
これらの工程は目的により、その一部の工程の順序が変
更されたり、複数回繰返されたり、或いは熱処理、研削
等他の工程が付加、置換されたりして種々の工程が行わ
れる。高精度の平坦度を有するシリコンウェーハを得る
ために、シリコンウェーハを両面同時に研磨する方法が
行われている。これは、シリコンウェーハを研磨後の厚
さより若干薄いキャリアの中に装填し、両面を同時に研
磨する方法である。2. Description of the Related Art A semiconductor silicon wafer having high precision flatness is obtained by slicing a wafer obtained by slicing a silicon single crystal ingot, chamfering, mechanical polishing (lapping), etching, mechanical chemical polishing (mechanochemical polishing). ) And washing.
Depending on the purpose, various steps are performed by changing the order of some of the steps, repeating the steps a plurality of times, or adding or replacing other steps such as heat treatment and grinding. In order to obtain a silicon wafer having a high degree of flatness, a method of simultaneously polishing both surfaces of a silicon wafer has been used. This is a method in which a silicon wafer is loaded in a carrier slightly thinner than the thickness after polishing, and both surfaces are simultaneously polished.
【０００３】上記方法を用いた両面研磨装置は、例え
ば、図５に示すように、相対する上下の定盤に研磨布を
貼付け、その間にウェーハ１外径より０．５〜２ｍｍ程
度大きい直径のキャリアホール２ａを３〜６個設けた、
キャリア２と称する薄円盤を定盤３全体で４〜５枚セッ
トする。図６に示すように、キャリア２は定盤３の中心
に位置するサンギア３ａと定盤３の外周周囲に位置する
インターナルギア３ｂとそれぞれかみ合って保持され
る。そのキャリアホール２ａにウェーハ１をセットした
後、上定盤と下定盤の間にウェーハを挟んで所定圧力を
加えながら、上下定盤の回転、キャリアの公転及びウェ
ーハ自体の自転という複雑な運動を利用してウェーハの
表裏面の研磨を行うものである。上記両面研磨装置によ
りウェーハの表裏面ともに均一に研磨され、極めて高精
度の平坦度、均一厚みが得られる。In a double-side polishing apparatus using the above method, for example, as shown in FIG. 5, a polishing cloth is attached to upper and lower platens facing each other, and the diameter of the polishing pad is larger than the outer diameter of the wafer 1 by about 0.5 to 2 mm. 3-6 carrier holes 2a are provided,
Four to five thin disks called carriers 2 are set on the entire surface plate 3. As shown in FIG. 6, the carrier 2 is held in engagement with a sun gear 3a located at the center of the surface plate 3 and an internal gear 3b located around the outer periphery of the surface plate 3. After setting the wafer 1 in the carrier hole 2a, while applying a predetermined pressure across the wafer between the upper and lower stools, the complicated movements of rotation of the upper and lower stools, revolving of the carrier, and rotation of the wafer itself are performed. This is used to polish the front and back surfaces of the wafer. Both the front and back surfaces of the wafer are uniformly polished by the double-side polishing apparatus, so that extremely high precision flatness and uniform thickness can be obtained.
【０００４】両面研磨装置による両面研磨方法は、ラッ
ピング及びメカノケミカルポリッシングのそれぞれに用
いることができ、高精度の平坦度が得られるため非常に
有用な方法であるが、ウェーハの厚みバラツキ、上下定
盤の精度などの影響により、研磨加工中のウェーハが自
由に自転せず、ウェーハエッジ部のある一部分だけがキ
ャリアホールと接触して変形及び摩耗する問題があっ
た。この両面研磨装置を用いた上記問題点を解決する方
法として、両面研磨装置のキャリアに改良を施し、キャ
リアホールの形状を多角形にしてウェーハに両面同時研
磨を施す方法が開示されている（特開平７−２３７１２
１）。この方法では、キャリアホールの形状を多角形に
することにより、ウェーハはキャリアホールに２点で支
持され、キャリアの公転に伴う支持方向の変化と、押し
つけられる方向によりキャリアホール内のウェーハが円
滑に自転する。従って、エッジ部のあらゆる部分でキャ
リアホールに接触するため、一部分だけの変形や摩耗を
防止することができる。The double-side polishing method using a double-side polishing apparatus can be used for lapping and mechanochemical polishing, respectively, and is a very useful method because a high-precision flatness can be obtained. Due to the influence of the accuracy of the board, the wafer being polished cannot rotate freely, and there is a problem that only a part of the wafer edge portion comes into contact with the carrier hole and is deformed and worn. As a method of solving the above-mentioned problem using the double-side polishing apparatus, a method of improving the carrier of the double-side polishing apparatus, making the shape of the carrier hole polygonal, and simultaneously polishing the wafer on both sides is disclosed. Kaihei 7-23712
1). In this method, the wafer is supported at two points by the carrier hole by making the shape of the carrier hole into a polygon, and the wafer in the carrier hole is smoothly moved by the change in the supporting direction due to the revolution of the carrier and the pressing direction. Rotate. Therefore, the carrier hole is brought into contact with any part of the edge, so that deformation and wear of only a part can be prevented.
【０００５】[0005]
【発明が解決しようとする課題】しかし、特開平７−２
３７１２１号公報に示される方法でも、研磨時にはウェ
ーハのエッジ部がキャリアホールと接触するため、エッ
ジ部に設けられているオリエンテーションフラットやＶ
字型のオリエンテーションノッチより破損するおそれが
あった。本発明の目的は、両面同時研磨時におけるウェ
ーハエッジ部の変形、摩耗及び破損を抑制し得るシリコ
ンウェーハの製造方法を提供することにある。However, Japanese Patent Application Laid-Open No. Hei 7-2
Also in the method disclosed in Japanese Patent No. 37121, the edge portion of the wafer comes into contact with the carrier hole during polishing, so that the orientation flat or the V
There was a risk of damage from the letter-shaped orientation notch. An object of the present invention is to provide a method of manufacturing a silicon wafer capable of suppressing deformation, abrasion and breakage of a wafer edge portion during simultaneous double-side polishing.
【０００６】[0006]
【課題を解決するための手段】請求項１に係る発明は、
図１に示すように、シリコンウェーハ１１の表裏面及び
エッジ部を保護膜１２で被覆する工程と、ウェーハ１１
のエッジ部に被覆した保護膜１２をマスク材１３で被覆
する工程と、マスク材１３で被覆されていない保護膜１
２を除去してウェーハ１１の表裏面を露出させる工程
と、マスク材１３を除去してエッジ部に保護膜１２を残
留する工程とを含むシリコンウェーハのエッジ部保護方
法である。請求項１に係る発明では、上記工程により、
ウェーハ１１のエッジ部を保護膜１２により被覆したの
で両面研磨時におけるウェーハの自転に伴うキャリアホ
ールとの接触において、保護膜がエッジ部の代わりにキ
ャリアホールと接触するため、エッジ部の変形、摩耗及
び破損を抑制することができる。The invention according to claim 1 is
As shown in FIG. 1, a step of covering the front and back surfaces and edge portions of a silicon wafer 11 with a protective film 12;
Covering the edge portion of the protective film 12 with the mask material 13 and the protective film 1 not covered with the mask material 13.
2 is a method of protecting the edge portion of the silicon wafer including a process of exposing the front and back surfaces of the wafer 11 by removing the mask material 13 and a process of removing the mask material 13 to leave the protective film 12 on the edge portion. In the invention according to claim 1, by the above-described steps,
Since the edge portion of the wafer 11 is covered with the protective film 12, the protective film comes into contact with the carrier hole instead of the edge portion when the double-side polishing is performed. And damage can be suppressed.
【０００７】[0007]
【発明の実施の形態】本発明のシリコンウェーハのエッ
ジ部保護方法は、両面ラッピングや両面メカノケミカル
ポリッシングを施す際に適応できる。本明細書におい
て、エッジ部とは、ウェーハ周辺部を面取り（ベベリン
グ、Bevelling）加工したウェーハの周辺部をいう。BEST MODE FOR CARRYING OUT THE INVENTION The method for protecting an edge portion of a silicon wafer according to the present invention can be applied when performing double-sided lapping or double-sided mechanochemical polishing. In this specification, the edge portion refers to a peripheral portion of a wafer obtained by chamfering (beveling) the peripheral portion of the wafer.
【０００８】本発明の実施の形態を図１に基づいて説明
する。先ずシリコンウェーハ１１を準備し（図１
（ａ））、このウェーハ１１の全面、即ち表裏面及びエ
ッジ部を保護膜１２で被覆する（図１（ｂ））。保護膜
１２には熱酸化膜、窒化膜又は酸窒化膜等が挙げられ
る。熱酸化膜の被覆方法は、ウェーハを高温の酸化雰囲
気に晒すことにより行われる。また窒化膜の被覆方法に
は化学的気相堆積（ＣＶＤ、Chemical Vapor Depositio
n）法によるウェーハ上への堆積やＳｉの直接熱窒化法
が挙げられ、ＣＶＤ法には常圧ＣＶＤ法、減圧熱ＣＶＤ
法、また、窒化膜の低温成長を目的とするプラズマＣＶ
Ｄ法、光ＣＶＤ法などがある。Ｓｉの直接熱窒化法はシ
リコンウェーハを窒素雰囲気中で高温に熱することによ
り窒化膜が得られる。このうち熱ＣＶＤ法やプラズマＣ
ＶＤ法等は窒化膜の堆積速度が速いため、本発明の被覆
に好ましい。酸窒化膜の被覆方法は、ウェーハを高温の
ＡｒガスとＮ2ガス雰囲気下に晒すことにより行われ
る。この際に、系内に残存している酸素及びＡｒ、Ｎ2
ガス中に不純物として含まれる酸素も作用することによ
り酸窒化膜が形成される。保護膜の膜厚は０．０１〜１
０μｍである。好ましくは０．１〜５μｍである。膜厚
が０．０１μｍ未満であると、両面研磨時においてエッ
ジ部が破損するおそれがある。１０μｍを越えると、保
護膜の膜厚の制御上問題があり、保護膜の膜厚にむらが
生じ、両面研磨工程における研磨不良が発生する。膜厚
が０．０１〜１０μｍの範囲であればエッジ部を十分に
保護することができる。An embodiment of the present invention will be described with reference to FIG. First, a silicon wafer 11 is prepared (FIG. 1).
(A)), the entire surface of the wafer 11, that is, the front and back surfaces and edge portions are covered with a protective film 12 (FIG. 1 (b)). The protective film 12 includes a thermal oxide film, a nitride film, an oxynitride film, and the like. The method of coating the thermal oxide film is performed by exposing the wafer to a high-temperature oxidizing atmosphere. In addition, chemical vapor deposition (CVD, Chemical Vapor Depositio
n) methods include deposition on a wafer and direct thermal nitridation of Si.
And plasma CV for low temperature growth of nitride film
D method, photo CVD method and the like. In the direct thermal nitridation method of Si, a nitride film is obtained by heating a silicon wafer to a high temperature in a nitrogen atmosphere. Among them, thermal CVD and plasma C
The VD method or the like is preferable for the coating of the present invention because the deposition rate of the nitride film is high. The method of coating the oxynitride film is performed by exposing the wafer to a high-temperature Ar gas and N 2 gas atmosphere. At this time, oxygen remaining in the system and Ar, N 2
Oxynitride film is formed by the action of oxygen contained as an impurity in the gas. The thickness of the protective film is 0.01 to 1
0 μm. Preferably it is 0.1-5 μm. If the film thickness is less than 0.01 μm, the edge may be damaged during double-side polishing. If the thickness exceeds 10 μm, there is a problem in controlling the thickness of the protective film, the thickness of the protective film becomes uneven, and poor polishing occurs in the double-side polishing step. When the thickness is in the range of 0.01 to 10 μm, the edge portion can be sufficiently protected.
【０００９】次いでウェーハ１１のエッジ部に被覆した
保護膜１２をマスク材１３で被覆する（図１（ｃ））。
マスク材１３には保護膜の除去工程で除去されない材質
からなる接着テープ、ゴムリング、軟質テトラフルオロ
エチレン製ゴムリング、硬質テトラフルオロエチレン製
リング、塩化ビニル製リング、レジスト層が挙げられ
る。マスク材１３として接着テープを用いる場合、エッ
ジ部が被覆されるように、ウェーハ周縁を接着テープで
シールする。マスク材１３としてゴムリングを用いる場
合、図４に示すように、ゴムリング１３ａをウェーハ１
１の周縁に嵌めてエッジ部をカバーする。ゴムリング１
３ａはウェーハのエッジ部が約１ｍｍ程度覆われるよう
に嵌める。図４の破線がウェーハの外周にあたる。ゴム
リング１３ａは外周がキャリアホールの内周より小さい
ものを使用する。マスク材１３として軟質テトラフルオ
ロエチレン製ゴムリング、硬質テトラフルオロエチレン
製リング、塩化ビニル製リングを用いる場合も、上記ゴ
ムリングによる被覆方法と同様にウェーハの周縁に嵌め
てエッジ部をカバーする。マスク材１３としてレジスト
層を用いる場合、ウェーハのエッジ部にのみレジストを
塗布してこの上にレジスト層を形成する。レジスト層の
形成方法としては、ウェーハのエッジ部にのみレジスト
を塗布する方法の他に、図示しないがウェーハの全面、
即ち表裏面及びエッジ部にレジストを塗布してレジスト
層を形成した後、このレジスト層の表面をパターンマス
クで覆って露光及び現像することによりウェーハのエッ
ジ部の保護膜上にのみレジスト層を残留させてもよい。Next, a protective film 12 covering the edge of the wafer 11 is covered with a mask material 13 (FIG. 1C).
Examples of the mask material 13 include an adhesive tape, a rubber ring, a soft tetrafluoroethylene rubber ring, a hard tetrafluoroethylene ring, a vinyl chloride ring, and a resist layer made of a material that is not removed in the step of removing the protective film. When using an adhesive tape as the mask material 13, the peripheral edge of the wafer is sealed with the adhesive tape so that the edge portion is covered. When a rubber ring is used as the mask material 13, as shown in FIG.
1 to cover the edge portion. Rubber ring 1
3a is fitted so that the edge of the wafer is covered by about 1 mm. The broken line in FIG. 4 corresponds to the outer periphery of the wafer. The rubber ring 13a whose outer circumference is smaller than the inner circumference of the carrier hole is used. When using a rubber ring made of a soft tetrafluoroethylene, a ring made of a hard tetrafluoroethylene, or a ring made of vinyl chloride as the mask material 13, the edge portion is covered by fitting to the peripheral edge of the wafer in the same manner as the above-mentioned method of covering with the rubber ring. When a resist layer is used as the mask material 13, a resist is applied only to the edge portion of the wafer, and a resist layer is formed thereon. As a method of forming the resist layer, in addition to the method of applying the resist only to the edge portion of the wafer, not shown, the entire surface of the wafer,
That is, a resist layer is formed by applying a resist on the front and back surfaces and an edge portion, and then the surface of the resist layer is covered with a pattern mask and exposed and developed to leave the resist layer only on the protective film at the edge portion of the wafer. May be.
【００１０】次にマスク材１３で被覆されていない保護
膜１２を除去してウェーハ１１の表裏面を露出させる
（図１（ｄ））。保護膜１２を除去する手段としては、
好ましくはウェーハ１１をフッ化水素酸水溶液若しくは
フッ化水素酸とフッ化アンモニウムとの混合溶液に浸漬
する方法が採用される。最後にマスク材１３を除去して
ウェーハ１１のエッジ部にのみ保護膜１２を残留させる
ことにより、所望のエッジ部に保護膜を被覆したウェー
ハ１１を得る（図１（ｅ））。図２に図１（ｅ）のエッ
ジ部の部分拡大断面図を示す。図３はこの実施の形態に
より製造されたエッジ部に保護膜を被覆したウェーハの
平面図を示す。Next, the protective film 12 not covered with the mask material 13 is removed to expose the front and back surfaces of the wafer 11 (FIG. 1D). As means for removing the protective film 12,
Preferably, a method is used in which the wafer 11 is immersed in a hydrofluoric acid aqueous solution or a mixed solution of hydrofluoric acid and ammonium fluoride. Finally, the mask material 13 is removed and the protective film 12 is left only on the edge of the wafer 11 to obtain the wafer 11 having a desired edge coated with the protective film (FIG. 1E). FIG. 2 is a partially enlarged cross-sectional view of the edge portion of FIG. FIG. 3 shows a plan view of a wafer having an edge portion coated with a protective film manufactured according to this embodiment.
【００１１】上記工程によりエッジ部に保護膜を被覆し
たウェーハを両面研磨工程に用いることにより、保護膜
がエッジ部の代わりにキャリアホールと接触するため、
エッジ部の変形、摩耗及び破損を抑制することができ
る。両面研磨工程を終えたウェーハはエッジ部の保護膜
をそのまま残存させてもよいし、或いはフッ化水素酸を
水で希釈した酸エッチング液により保護膜を除去しても
よい。[0011] By using the wafer having the edge portion coated with the protective film in the above process in the double-side polishing process, the protective film comes into contact with the carrier hole instead of the edge portion.
The deformation, wear and breakage of the edge can be suppressed. The wafer after the double-side polishing step may leave the protective film at the edge portion as it is, or may remove the protective film using an acid etching solution obtained by diluting hydrofluoric acid with water.
【００１２】[0012]
【発明の効果】以上述べたように、本発明によれば、シ
リコンウェーハのエッジ部保護方法は、シリコンウェー
ハの表裏面及びエッジ部を膜厚が０．０１〜１０μｍの
熱酸化膜等からなる保護膜で被覆し、ウェーハのエッジ
部に被覆した保護膜を接着テープ等のマスク材で被覆
し、マスク材で被覆されていない保護膜を除去してウェ
ーハの表裏面を露出させ、マスク材を除去してエッジ部
に保護膜を残留したので、従来のシリコンウェーハに比
べて、両面同時研磨時におけるウェーハエッジ部の変
形、摩耗及び破損を抑制することができる。As described above, according to the present invention, in the method for protecting the edge portion of a silicon wafer, the front and back surfaces and the edge portion of the silicon wafer are formed of a thermal oxide film having a thickness of 0.01 to 10 μm. Cover with a protective film, cover the protective film on the edge of the wafer with a mask material such as adhesive tape, remove the protective film not covered with the mask material, expose the front and back surfaces of the wafer, and remove the mask material. Since the protective film is left on the edge portion after the removal, the deformation, abrasion and breakage of the wafer edge portion during simultaneous double-side polishing can be suppressed as compared with the conventional silicon wafer.
【図１】本発明の実施の形態のシリコンウェーハのエッ
ジ部保護方法を工程順に示す断面図。FIG. 1 is a sectional view showing a method of protecting an edge portion of a silicon wafer according to an embodiment of the present invention in the order of steps.
【図２】本発明の方法により形成されたシリコンウェー
ハのエッジ部周辺の部分拡大断面図。FIG. 2 is a partially enlarged cross-sectional view around the edge of a silicon wafer formed by the method of the present invention.
【図３】本発明の方法により形成されたエッジ部に保護
膜を被覆したシリコンウェーハの平面図。FIG. 3 is a plan view of a silicon wafer in which an edge formed by the method of the present invention is covered with a protective film.
【図４】本実施の形態におけるウェーハ外周にゴムリン
グを嵌着した図。FIG. 4 is a diagram in which a rubber ring is fitted around the wafer in the present embodiment.
【図５】両面研磨装置におけるキャリアの上面説明図。FIG. 5 is an explanatory top view of a carrier in the double-side polishing apparatus.
【図６】両面研磨装置におけるキャリアをセットした定
盤の上面説明図。FIG. 6 is an explanatory top view of a surface plate on which a carrier is set in the double-side polishing apparatus.
１１ シリコンウェーハ １２ 保護膜 １３ マスク材 11 silicon wafer 12 protective film 13 mask material
フロントページの続き (72)発明者 高石 和成 埼玉県大宮市北袋町１丁目297番地 三菱 マテリアル株式会社シリコン研究センター 内Continued on the front page (72) Inventor Kazunari Takaishi 1-297 Kitabukuro-cho, Omiya-shi, Saitama Mitsubishi Materials Corporation Silicon Research Center
Claims (5)
ジ部を保護膜(12)で被覆する工程と、 前記ウェーハ(11)のエッジ部に被覆した保護膜(12)をマ
スク材(13)で被覆する工程と、 前記マスク材(13)で被覆されていない保護膜(12)を除去
して前記ウェーハ(11)の表裏面を露出させる工程と、 前記マスク材(13)を除去してエッジ部に保護膜(12)を残
留する工程とを含むシリコンウェーハのエッジ部保護方
法。A step of coating the front and back surfaces and edges of the silicon wafer with a protective film, and a step of masking the protective film covering the edges of the wafer with a mask material. Removing the protective film (12) not covered with the mask material (13) to expose the front and back surfaces of the wafer (11); removing the mask material (13) Leaving a protective film (12) on the edge portion.
化膜である請求項１記載の保護方法。2. The method according to claim 1, wherein the protective film is a thermal oxide film, a nitride film or an oxynitride film.
である請求項１又は２記載の保護方法。3. The protective film (12) has a thickness of 0.01 to 10 μm.
The protection method according to claim 1 or 2, wherein
1)をフッ化水素酸水溶液若しくはフッ化水素酸とフッ化
アンモニウムとの混合溶液に浸漬することにより行われ
る請求項１ないし３いずれか記載の保護方法。4. The method according to claim 1, wherein the protective film is removed from the silicon wafer.
The protection method according to any one of claims 1 to 3, wherein the method is performed by immersing 1) in a hydrofluoric acid aqueous solution or a mixed solution of hydrofluoric acid and ammonium fluoride.
グ、軟質テトラフルオロエチレン製ゴムリング、硬質テ
トラフルオロエチレン製リング、塩化ビニル製リング又
はレジスト層である請求項１記載の保護方法。5. The method according to claim 1, wherein the mask material is an adhesive tape, a rubber ring, a soft tetrafluoroethylene rubber ring, a hard tetrafluoroethylene ring, a vinyl chloride ring, or a resist layer.
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| JP2000289824A JP3646640B2 (en) | 2000-09-25 | 2000-09-25 | Silicon wafer edge protection method |
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| JP3646640B2 JP3646640B2 (en) | 2005-05-11 |
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008205387A (en) * | 2007-02-22 | 2008-09-04 | Tokyo Ohka Kogyo Co Ltd | Treatment method of support plate |
| DE102007061141B3 (en) * | 2007-12-19 | 2009-06-25 | Austriamicrosystems Ag | Wafer i.e. silicon-wafer, edge protecting method for manufacturing of integrated circuits of semiconductor chip, involves removing mask, and producing local oxide layer by local oxidation in area in which pad-nitride layer is removed |
| JP2011216573A (en) * | 2010-03-31 | 2011-10-27 | Mitsubishi Electric Corp | Method of manufacturing semiconductor device |
| CN102361008A (en) * | 2011-10-28 | 2012-02-22 | 上海华力微电子有限公司 | Method for controlling defects of wafer edge |
| JP2012156553A (en) * | 2012-05-10 | 2012-08-16 | Tokyo Ohka Kogyo Co Ltd | Support plate processing method |
| CN105070645A (en) * | 2015-07-21 | 2015-11-18 | 上海华力微电子有限公司 | Method of avoiding peeling defect source of wafer edge aluminum and device |
| CN107546151A (en) * | 2016-06-24 | 2018-01-05 | 株式会社迪思科 | Diaphragm coating unit and diaphragm method for coating |
| CN110223909A (en) * | 2019-05-29 | 2019-09-10 | 浙江荷清柔性电子技术有限公司 | A kind of crystal round fringes processing method and wafer assembly |
| CN111199872A (en) * | 2020-01-09 | 2020-05-26 | 长江存储科技有限责任公司 | Forming method of wafer edge protection layer, three-dimensional memory and preparation method of three-dimensional memory |
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Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008205387A (en) * | 2007-02-22 | 2008-09-04 | Tokyo Ohka Kogyo Co Ltd | Treatment method of support plate |
| DE102007061141B3 (en) * | 2007-12-19 | 2009-06-25 | Austriamicrosystems Ag | Wafer i.e. silicon-wafer, edge protecting method for manufacturing of integrated circuits of semiconductor chip, involves removing mask, and producing local oxide layer by local oxidation in area in which pad-nitride layer is removed |
| JP2011216573A (en) * | 2010-03-31 | 2011-10-27 | Mitsubishi Electric Corp | Method of manufacturing semiconductor device |
| CN102361008A (en) * | 2011-10-28 | 2012-02-22 | 上海华力微电子有限公司 | Method for controlling defects of wafer edge |
| JP2012156553A (en) * | 2012-05-10 | 2012-08-16 | Tokyo Ohka Kogyo Co Ltd | Support plate processing method |
| CN105070645A (en) * | 2015-07-21 | 2015-11-18 | 上海华力微电子有限公司 | Method of avoiding peeling defect source of wafer edge aluminum and device |
| CN107546151A (en) * | 2016-06-24 | 2018-01-05 | 株式会社迪思科 | Diaphragm coating unit and diaphragm method for coating |
| CN107546151B (en) * | 2016-06-24 | 2022-10-21 | 株式会社迪思科 | Protective film coating device and protective film coating method |
| CN110223909A (en) * | 2019-05-29 | 2019-09-10 | 浙江荷清柔性电子技术有限公司 | A kind of crystal round fringes processing method and wafer assembly |
| CN110223909B (en) * | 2019-05-29 | 2024-03-26 | 浙江荷清柔性电子技术有限公司 | Wafer edge processing method and wafer assembly |
| CN111199872A (en) * | 2020-01-09 | 2020-05-26 | 长江存储科技有限责任公司 | Forming method of wafer edge protection layer, three-dimensional memory and preparation method of three-dimensional memory |
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